1 /* $NetBSD: if_iy.c,v 1.71 2006/04/14 21:49:08 christos Exp $ */ 2 /* #define IYDEBUG */ 3 /* #define IYMEMDEBUG */ 4 5 /*- 6 * Copyright (c) 1996,2001 The NetBSD Foundation, Inc. 7 * All rights reserved. 8 * 9 * This code is derived from software contributed to The NetBSD Foundation 10 * by Ignatios Souvatzis. 11 * 12 * Redistribution and use in source and binary forms, with or without 13 * modification, are permitted provided that the following conditions 14 * are met: 15 * 1. Redistributions of source code must retain the above copyright 16 * notice, this list of conditions and the following disclaimer. 17 * 2. Redistributions in binary form must reproduce the above copyright 18 * notice, this list of conditions and the following disclaimer in the 19 * documentation and/or other materials provided with the distribution. 20 * 3. All advertising materials mentioning features or use of this software 21 * must display the following acknowledgement: 22 * This product includes software developed by the NetBSD 23 * Foundation, Inc. and its contributors. 24 * 4. Neither the name of The NetBSD Foundation nor the names of its 25 * contributors may be used to endorse or promote products derived 26 * from this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 29 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 30 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 31 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 32 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 33 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 34 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 35 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 36 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 37 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 38 * POSSIBILITY OF SUCH DAMAGE. 39 */ 40 41 /* 42 * Supported hardware: 43 * 44 * - Intel EtherExpress Pro/10. 45 * - possibly other boards using the i82595 chip and no special tweaks. 46 */ 47 48 #include <sys/cdefs.h> 49 __KERNEL_RCSID(0, "$NetBSD: if_iy.c,v 1.71 2006/04/14 21:49:08 christos Exp $"); 50 51 #include "opt_inet.h" 52 #include "opt_ns.h" 53 #include "bpfilter.h" 54 #include "rnd.h" 55 56 #include <sys/param.h> 57 #include <sys/systm.h> 58 #include <sys/mbuf.h> 59 #include <sys/buf.h> 60 #include <sys/protosw.h> 61 #include <sys/socket.h> 62 #include <sys/ioctl.h> 63 #include <sys/errno.h> 64 #include <sys/syslog.h> 65 #include <sys/device.h> 66 #include <sys/endian.h> 67 #if NRND > 0 68 #include <sys/rnd.h> 69 #endif 70 71 #include <net/if.h> 72 #include <net/if_types.h> 73 #include <net/if_dl.h> 74 75 #include <net/if_ether.h> 76 77 #if NBPFILTER > 0 78 #include <net/bpf.h> 79 #include <net/bpfdesc.h> 80 #endif 81 82 #ifdef INET 83 #include <netinet/in.h> 84 #include <netinet/in_systm.h> 85 #include <netinet/in_var.h> 86 #include <netinet/ip.h> 87 #include <netinet/if_inarp.h> 88 #endif 89 90 #ifdef NS 91 #include <netns/ns.h> 92 #include <netns/ns_if.h> 93 #endif 94 95 #if defined(SIOCSIFMEDIA) 96 #include <net/if_media.h> 97 #endif 98 99 #include <machine/cpu.h> 100 #include <machine/bus.h> 101 #include <machine/intr.h> 102 103 #include <dev/isa/isareg.h> 104 #include <dev/isa/isavar.h> 105 #include <dev/ic/i82595reg.h> 106 107 /* XXX why isn't this centralized? */ 108 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 109 #define bus_space_write_stream_2 bus_space_write_2 110 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 111 #define bus_space_read_stream_2 bus_space_read_2 112 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 113 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 114 115 /* 116 * Ethernet status, per interface. 117 */ 118 struct iy_softc { 119 struct device sc_dev; 120 void *sc_ih; 121 122 bus_space_tag_t sc_iot; 123 bus_space_handle_t sc_ioh; 124 125 struct ethercom sc_ethercom; 126 127 struct ifmedia iy_ifmedia; 128 int iy_media; 129 130 int mappedirq; 131 132 int hard_vers; 133 134 int promisc; 135 136 int sram, tx_size, rx_size; 137 138 int tx_start, tx_end, tx_last; 139 int rx_start; 140 141 int doing_mc_setup; 142 #ifdef IYDEBUG 143 int sc_debug; 144 #endif 145 146 #if NRND > 0 147 rndsource_element_t rnd_source; 148 #endif 149 }; 150 151 void iywatchdog(struct ifnet *); 152 int iyioctl(struct ifnet *, u_long, caddr_t); 153 int iyintr(void *); 154 void iyinit(struct iy_softc *); 155 void iystop(struct iy_softc *); 156 void iystart(struct ifnet *); 157 158 void iy_intr_rx(struct iy_softc *); 159 void iy_intr_tx(struct iy_softc *); 160 161 void iyreset(struct iy_softc *); 162 void iy_readframe(struct iy_softc *, int); 163 void iy_drop_packet_buffer(struct iy_softc *); 164 void iy_find_mem_size(struct iy_softc *); 165 void iyrint(struct iy_softc *); 166 void iytint(struct iy_softc *); 167 void iyxmit(struct iy_softc *); 168 static void iy_mc_setup(struct iy_softc *); 169 static void iy_mc_reset(struct iy_softc *); 170 void iyget(struct iy_softc *, bus_space_tag_t, bus_space_handle_t, int); 171 void iyprobemem(struct iy_softc *); 172 static inline void eepromwritebit(bus_space_tag_t, bus_space_handle_t, int); 173 static inline int eepromreadbit(bus_space_tag_t, bus_space_handle_t); 174 175 #ifdef IYDEBUGX 176 void print_rbd(volatile struct iy_recv_buf_desc *); 177 178 int in_ifrint = 0; 179 int in_iftint = 0; 180 #endif 181 182 int iy_mediachange(struct ifnet *); 183 void iy_mediastatus(struct ifnet *, struct ifmediareq *); 184 185 int iyprobe(struct device *, struct cfdata *, void *); 186 void iyattach(struct device *, struct device *, void *); 187 188 static u_int16_t eepromread(bus_space_tag_t, bus_space_handle_t, int); 189 190 static int eepromreadall(bus_space_tag_t, bus_space_handle_t, u_int16_t *, 191 int); 192 193 CFATTACH_DECL(iy, sizeof(struct iy_softc), 194 iyprobe, iyattach, NULL, NULL); 195 196 static u_int8_t eepro_irqmap[] = EEPP_INTMAP; 197 static u_int8_t eepro_revirqmap[] = EEPP_RINTMAP; 198 199 int 200 iyprobe(parent, match, aux) 201 struct device *parent; 202 struct cfdata *match; 203 void *aux; 204 { 205 struct isa_attach_args *ia = aux; 206 u_int16_t eaddr[8]; 207 bus_space_tag_t iot; 208 bus_space_handle_t ioh; 209 u_int8_t c, d; 210 int irq; 211 212 if (ia->ia_nio < 1) 213 return (0); 214 if (ia->ia_nirq < 1) 215 return (0); 216 217 if (ISA_DIRECT_CONFIG(ia)) 218 return (0); 219 220 iot = ia->ia_iot; 221 222 if (ia->ia_io[0].ir_addr == ISA_UNKNOWN_PORT) 223 return 0; 224 225 if (bus_space_map(iot, ia->ia_io[0].ir_addr, 16, 0, &ioh)) 226 return 0; 227 228 /* try to find the round robin sig: */ 229 230 c = bus_space_read_1(iot, ioh, ID_REG); 231 if ((c & ID_REG_MASK) != ID_REG_SIG) 232 goto out; 233 234 d = bus_space_read_1(iot, ioh, ID_REG); 235 if ((d & ID_REG_MASK) != ID_REG_SIG) 236 goto out; 237 238 if (((d-c) & R_ROBIN_BITS) != 0x40) 239 goto out; 240 241 d = bus_space_read_1(iot, ioh, ID_REG); 242 if ((d & ID_REG_MASK) != ID_REG_SIG) 243 goto out; 244 245 if (((d-c) & R_ROBIN_BITS) != 0x80) 246 goto out; 247 248 d = bus_space_read_1(iot, ioh, ID_REG); 249 if ((d & ID_REG_MASK) != ID_REG_SIG) 250 goto out; 251 252 if (((d-c) & R_ROBIN_BITS) != 0xC0) 253 goto out; 254 255 d = bus_space_read_1(iot, ioh, ID_REG); 256 if ((d & ID_REG_MASK) != ID_REG_SIG) 257 goto out; 258 259 if (((d-c) & R_ROBIN_BITS) != 0x00) 260 goto out; 261 262 #ifdef IYDEBUG 263 printf("iyprobe verified working ID reg.\n"); 264 #endif 265 266 if (eepromreadall(iot, ioh, eaddr, 8)) 267 goto out; 268 269 if (ia->ia_irq[0].ir_irq == ISA_UNKNOWN_IRQ) 270 irq = eepro_irqmap[eaddr[EEPPW1] & EEPP_Int]; 271 else 272 irq = ia->ia_irq[0].ir_irq; 273 274 if (irq >= sizeof(eepro_revirqmap)) 275 goto out; 276 277 if (eepro_revirqmap[irq] == 0xff) 278 goto out; 279 280 /* now lets reset the chip */ 281 282 bus_space_write_1(iot, ioh, COMMAND_REG, RESET_CMD); 283 delay(200); 284 285 ia->ia_nio = 1; 286 ia->ia_io[0].ir_size = 16; 287 288 ia->ia_nirq = 1; 289 ia->ia_irq[0].ir_irq = irq; 290 291 ia->ia_niomem = 0; 292 ia->ia_ndrq = 0; 293 294 bus_space_unmap(iot, ioh, 16); 295 return 1; /* found */ 296 out: 297 bus_space_unmap(iot, ioh, 16); 298 return 0; 299 } 300 301 void 302 iyattach(parent, self, aux) 303 struct device *parent, *self; 304 void *aux; 305 { 306 struct iy_softc *sc = (void *)self; 307 struct isa_attach_args *ia = aux; 308 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 309 bus_space_tag_t iot; 310 bus_space_handle_t ioh; 311 unsigned temp; 312 u_int16_t eaddr[8]; 313 u_int8_t myaddr[ETHER_ADDR_LEN]; 314 int eirq; 315 316 iot = ia->ia_iot; 317 318 if (bus_space_map(iot, ia->ia_io[0].ir_addr, 16, 0, &ioh)) { 319 printf(": can't map i/o space\n"); 320 return; 321 } 322 323 sc->sc_iot = iot; 324 sc->sc_ioh = ioh; 325 326 sc->mappedirq = eepro_revirqmap[ia->ia_irq[0].ir_irq]; 327 328 /* now let's reset the chip */ 329 330 bus_space_write_1(iot, ioh, COMMAND_REG, RESET_CMD); 331 delay(200); 332 333 iyprobemem(sc); 334 335 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 336 ifp->if_softc = sc; 337 ifp->if_start = iystart; 338 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS 339 | IFF_MULTICAST; 340 341 sc->doing_mc_setup = 0; 342 343 ifp->if_ioctl = iyioctl; 344 ifp->if_watchdog = iywatchdog; 345 346 IFQ_SET_READY(&ifp->if_snd); 347 348 (void)eepromreadall(iot, ioh, eaddr, 8); 349 sc->hard_vers = eaddr[EEPW6] & EEPP_BoardRev; 350 351 #ifdef DIAGNOSTICS 352 if ((eaddr[EEPPEther0] != 353 eepromread(iot, ioh, EEPPEther0a)) && 354 (eaddr[EEPPEther1] != 355 eepromread(iot, ioh, EEPPEther1a)) && 356 (eaddr[EEPPEther2] != 357 eepromread(iot, ioh, EEPPEther2a))) 358 359 printf("EEPROM Ethernet address differs from copy\n"); 360 #endif 361 362 myaddr[1] = eaddr[EEPPEther0] & 0xFF; 363 myaddr[0] = eaddr[EEPPEther0] >> 8; 364 myaddr[3] = eaddr[EEPPEther1] & 0xFF; 365 myaddr[2] = eaddr[EEPPEther1] >> 8; 366 myaddr[5] = eaddr[EEPPEther2] & 0xFF; 367 myaddr[4] = eaddr[EEPPEther2] >> 8; 368 369 ifmedia_init(&sc->iy_ifmedia, 0, iy_mediachange, iy_mediastatus); 370 ifmedia_add(&sc->iy_ifmedia, IFM_ETHER | IFM_10_2, 0, NULL); 371 ifmedia_add(&sc->iy_ifmedia, IFM_ETHER | IFM_10_5, 0, NULL); 372 ifmedia_add(&sc->iy_ifmedia, IFM_ETHER | IFM_10_T, 0, NULL); 373 ifmedia_add(&sc->iy_ifmedia, IFM_ETHER | IFM_AUTO, 0, NULL); 374 ifmedia_set(&sc->iy_ifmedia, IFM_ETHER | IFM_AUTO); 375 /* Attach the interface. */ 376 if_attach(ifp); 377 ether_ifattach(ifp, myaddr); 378 printf(": address %s, rev. %d, %d kB\n", 379 ether_sprintf(myaddr), 380 sc->hard_vers, sc->sram/1024); 381 382 eirq = eepro_irqmap[eaddr[EEPPW1] & EEPP_Int]; 383 if (eirq != ia->ia_irq[0].ir_irq) 384 printf("%s: EEPROM irq setting %d ignored\n", 385 sc->sc_dev.dv_xname, eirq); 386 387 sc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq[0].ir_irq, 388 IST_EDGE, IPL_NET, iyintr, sc); 389 390 #if NRND > 0 391 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 392 RND_TYPE_NET, 0); 393 #endif 394 395 temp = bus_space_read_1(iot, ioh, INT_NO_REG); 396 bus_space_write_1(iot, ioh, INT_NO_REG, (temp & 0xf8) | sc->mappedirq); 397 } 398 399 void 400 iystop(sc) 401 struct iy_softc *sc; 402 { 403 bus_space_tag_t iot; 404 bus_space_handle_t ioh; 405 #ifdef IYDEBUG 406 u_int p, v; 407 #endif 408 409 iot = sc->sc_iot; 410 ioh = sc->sc_ioh; 411 412 bus_space_write_1(iot, ioh, COMMAND_REG, RCV_DISABLE_CMD); 413 414 bus_space_write_1(iot, ioh, INT_MASK_REG, ALL_INTS); 415 bus_space_write_1(iot, ioh, STATUS_REG, ALL_INTS); 416 417 bus_space_write_1(iot, ioh, COMMAND_REG, RESET_CMD); 418 delay(200); 419 #ifdef IYDEBUG 420 printf("%s: dumping tx chain (st 0x%x end 0x%x last 0x%x)\n", 421 sc->sc_dev.dv_xname, sc->tx_start, sc->tx_end, sc->tx_last); 422 p = sc->tx_last; 423 if (!p) 424 p = sc->tx_start; 425 do { 426 char sbuf[128]; 427 428 bus_space_write_2(iot, ioh, HOST_ADDR_REG, p); 429 430 v = le16toh(bus_space_read_stream_2(iot, ioh, MEM_PORT_REG)); 431 bitmask_snprintf(v, "\020\006Ab\010Dn", sbuf, sizeof(sbuf)); 432 printf("0x%04x: %s ", p, sbuf); 433 434 v = le16toh(bus_space_read_stream_2(iot, ioh, MEM_PORT_REG)); 435 bitmask_snprintf(v, "\020\6MAX_COL\7HRT_BEAT\010TX_DEF\011UND_RUN\012JERR\013LST_CRS\014LTCOL\016TX_OK\020COLL", 436 sbuf, sizeof(sbuf)); 437 printf("0x%s", sbuf); 438 439 p = le16toh(bus_space_read_stream_2(iot, ioh, MEM_PORT_REG)); 440 printf(" 0x%04x", p); 441 442 v = le16toh(bus_space_read_stream_2(iot, ioh, MEM_PORT_REG)); 443 bitmask_snprintf(v, "\020\020Ch", sbuf, sizeof(sbuf)); 444 printf(" 0x%s\n", sbuf); 445 446 } while (v & 0x8000); 447 #endif 448 sc->tx_start = sc->tx_end = sc->rx_size; 449 sc->tx_last = 0; 450 sc->sc_ethercom.ec_if.if_flags &= ~(IFF_RUNNING|IFF_OACTIVE); 451 } 452 453 void 454 iyreset(sc) 455 struct iy_softc *sc; 456 { 457 int s; 458 s = splnet(); 459 iystop(sc); 460 iyinit(sc); 461 splx(s); 462 } 463 464 void 465 iyinit(sc) 466 struct iy_softc *sc; 467 { 468 int i; 469 unsigned temp; 470 struct ifnet *ifp; 471 bus_space_tag_t iot; 472 bus_space_handle_t ioh; 473 474 iot = sc->sc_iot; 475 ioh = sc->sc_ioh; 476 477 ifp = &sc->sc_ethercom.ec_if; 478 #ifdef IYDEBUG 479 printf("ifp is %p\n", ifp); 480 #endif 481 482 bus_space_write_1(iot, ioh, 0, BANK_SEL(2)); 483 484 temp = bus_space_read_1(iot, ioh, EEPROM_REG); 485 if (temp & 0x10) 486 bus_space_write_1(iot, ioh, EEPROM_REG, temp & ~0x10); 487 488 for (i=0; i<6; ++i) { 489 bus_space_write_1(iot, ioh, I_ADD(i), LLADDR(ifp->if_sadl)[i]); 490 } 491 492 temp = bus_space_read_1(iot, ioh, REG1); 493 bus_space_write_1(iot, ioh, REG1, 494 temp | /* XMT_CHAIN_INT | XMT_CHAIN_ERRSTOP | */ RCV_DISCARD_BAD); 495 496 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) { 497 temp = MATCH_ALL; 498 } else 499 temp = MATCH_BRDCST; 500 501 bus_space_write_1(iot, ioh, RECV_MODES_REG, temp); 502 503 #ifdef IYDEBUG 504 { 505 char sbuf[128]; 506 507 bitmask_snprintf(temp, "\020\1PRMSC\2NOBRDST\3SEECRC\4LENGTH\5NOSaIns\6MultiIA", 508 sbuf, sizeof(sbuf)); 509 printf("%s: RECV_MODES set to %s\n", sc->sc_dev.dv_xname, sbuf); 510 } 511 #endif 512 /* XXX VOODOO */ 513 temp = bus_space_read_1(iot, ioh, MEDIA_SELECT); 514 bus_space_write_1(iot, ioh, MEDIA_SELECT, temp); 515 /* XXX END OF VOODOO */ 516 517 518 delay(500000); /* for the hardware to test for the connector */ 519 520 temp = bus_space_read_1(iot, ioh, MEDIA_SELECT); 521 #ifdef IYDEBUG 522 { 523 char sbuf[128]; 524 525 bitmask_snprintf(temp, "\020\1LnkInDis\2PolCor\3TPE\4JabberDis\5NoAport\6BNC", 526 sbuf, sizeof(sbuf)); 527 printf("%s: media select was 0x%s ", sc->sc_dev.dv_xname, sbuf); 528 } 529 #endif 530 temp = (temp & TEST_MODE_MASK); 531 532 switch(IFM_SUBTYPE(sc->iy_ifmedia.ifm_media)) { 533 case IFM_10_5: 534 temp &= ~ (BNC_BIT | TPE_BIT); 535 break; 536 537 case IFM_10_2: 538 temp = (temp & ~TPE_BIT) | BNC_BIT; 539 break; 540 541 case IFM_10_T: 542 temp = (temp & ~BNC_BIT) | TPE_BIT; 543 break; 544 default: 545 ; 546 /* nothing; leave as it is */ 547 } 548 switch (temp & (BNC_BIT | TPE_BIT)) { 549 case BNC_BIT: 550 sc->iy_media = IFM_ETHER | IFM_10_2; 551 break; 552 case TPE_BIT: 553 sc->iy_media = IFM_ETHER | IFM_10_T; 554 break; 555 default: 556 sc->iy_media = IFM_ETHER | IFM_10_5; 557 } 558 559 bus_space_write_1(iot, ioh, MEDIA_SELECT, temp); 560 #ifdef IYDEBUG 561 { 562 char sbuf[128]; 563 564 bitmask_snprintf(temp, "\020\1LnkInDis\2PolCor\3TPE\4JabberDis\5NoAport\6BNC", 565 sbuf, sizeof(sbuf)); 566 printf("changed to 0x%s\n", sbuf); 567 } 568 #endif 569 570 bus_space_write_1(iot, ioh, 0, BANK_SEL(0)); 571 bus_space_write_1(iot, ioh, INT_MASK_REG, ALL_INTS); 572 bus_space_write_1(iot, ioh, 0, BANK_SEL(1)); 573 574 temp = bus_space_read_1(iot, ioh, INT_NO_REG); 575 bus_space_write_1(iot, ioh, INT_NO_REG, (temp & 0xf8) | sc->mappedirq); 576 577 #ifdef IYDEBUG 578 { 579 char sbuf[128]; 580 581 bitmask_snprintf(temp, "\020\4bad_irq\010flash/boot present", 582 sbuf, sizeof(sbuf)); 583 printf("%s: int no was %s\n", sc->sc_dev.dv_xname, sbuf); 584 585 temp = bus_space_read_1(iot, ioh, INT_NO_REG); 586 bitmask_snprintf(temp, "\020\4bad_irq\010flash/boot present", 587 sbuf, sizeof(sbuf)); 588 printf("%s: int no now %s\n", sc->sc_dev.dv_xname, sbuf); 589 } 590 #endif 591 592 bus_space_write_1(iot, ioh, RCV_LOWER_LIMIT_REG, 0); 593 bus_space_write_1(iot, ioh, RCV_UPPER_LIMIT_REG, (sc->rx_size -2) >>8); 594 bus_space_write_1(iot, ioh, XMT_LOWER_LIMIT_REG, sc->rx_size >>8); 595 bus_space_write_1(iot, ioh, XMT_UPPER_LIMIT_REG, (sc->sram - 2) >>8); 596 597 temp = bus_space_read_1(iot, ioh, REG1); 598 #ifdef IYDEBUG 599 { 600 char sbuf[128]; 601 602 bitmask_snprintf(temp, "\020\2WORD_WIDTH\010INT_ENABLE", 603 sbuf, sizeof(sbuf)); 604 printf("%s: HW access is %s\n", sc->sc_dev.dv_xname, sbuf); 605 } 606 #endif 607 bus_space_write_1(iot, ioh, REG1, temp | INT_ENABLE); /* XXX what about WORD_WIDTH? */ 608 609 #ifdef IYDEBUG 610 { 611 char sbuf[128]; 612 613 temp = bus_space_read_1(iot, ioh, REG1); 614 bitmask_snprintf(temp, "\020\2WORD_WIDTH\010INT_ENABLE", 615 sbuf, sizeof(sbuf)); 616 printf("%s: HW access is %s\n", sc->sc_dev.dv_xname, sbuf); 617 } 618 #endif 619 620 bus_space_write_1(iot, ioh, 0, BANK_SEL(0)); 621 622 bus_space_write_1(iot, ioh, INT_MASK_REG, ALL_INTS & ~(RX_BIT|TX_BIT)); 623 bus_space_write_1(iot, ioh, STATUS_REG, ALL_INTS); /* clear ints */ 624 625 bus_space_write_1(iot, ioh, RCV_COPY_THRESHOLD, 0); 626 627 bus_space_write_2(iot, ioh, RCV_START_LOW, 0); 628 bus_space_write_2(iot, ioh, RCV_STOP_LOW, sc->rx_size - 2); 629 sc->rx_start = 0; 630 631 bus_space_write_1(iot, ioh, 0, SEL_RESET_CMD); 632 delay(200); 633 634 bus_space_write_2(iot, ioh, XMT_ADDR_REG, sc->rx_size); 635 636 sc->tx_start = sc->tx_end = sc->rx_size; 637 sc->tx_last = 0; 638 639 bus_space_write_1(iot, ioh, 0, RCV_ENABLE_CMD); 640 641 ifp->if_flags |= IFF_RUNNING; 642 ifp->if_flags &= ~IFF_OACTIVE; 643 } 644 645 void 646 iystart(ifp) 647 struct ifnet *ifp; 648 { 649 struct iy_softc *sc; 650 651 652 struct mbuf *m0, *m; 653 u_int len, pad, last, end; 654 u_int llen, residual; 655 int avail; 656 caddr_t data; 657 unsigned temp; 658 u_int16_t resval, stat; 659 bus_space_tag_t iot; 660 bus_space_handle_t ioh; 661 662 #ifdef IYDEBUG 663 printf("iystart called\n"); 664 #endif 665 sc = ifp->if_softc; 666 667 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) != IFF_RUNNING) 668 return; 669 670 iy_intr_tx(sc); 671 672 iot = sc->sc_iot; 673 ioh = sc->sc_ioh; 674 675 for (;;) { 676 IFQ_POLL(&ifp->if_snd, m0); 677 if (m0 == NULL) 678 break; 679 #ifdef IYDEBUG 680 printf("%s: trying to write another packet to the hardware\n", 681 sc->sc_dev.dv_xname); 682 #endif 683 684 /* We need to use m->m_pkthdr.len, so require the header */ 685 if ((m0->m_flags & M_PKTHDR) == 0) 686 panic("iystart: no header mbuf"); 687 688 len = m0->m_pkthdr.len; 689 pad = len & 1; 690 691 #ifdef IYDEBUG 692 printf("%s: length is %d.\n", sc->sc_dev.dv_xname, len); 693 #endif 694 if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) { 695 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 696 } 697 698 if (len + pad > ETHER_MAX_LEN) { 699 /* packet is obviously too large: toss it */ 700 ++ifp->if_oerrors; 701 IFQ_DEQUEUE(&ifp->if_snd, m0); 702 m_freem(m0); 703 continue; 704 } 705 706 #if NBPFILTER > 0 707 if (ifp->if_bpf) 708 bpf_mtap(ifp->if_bpf, m0); 709 #endif 710 711 avail = sc->tx_start - sc->tx_end; 712 if (avail <= 0) 713 avail += sc->tx_size; 714 715 #ifdef IYDEBUG 716 printf("%s: avail is %d.\n", sc->sc_dev.dv_xname, avail); 717 #endif 718 /* 719 * we MUST RUN at splnet here --- 720 * XXX todo: or even turn off the boards ints ??? hm... 721 */ 722 723 /* See if there is room to put another packet in the buffer. */ 724 725 if ((len+pad+2*I595_XMT_HDRLEN) > avail) { 726 #ifdef IYDEBUG 727 printf("%s: len = %d, avail = %d, setting OACTIVE\n", 728 sc->sc_dev.dv_xname, len, avail); 729 #endif 730 /* mark interface as full ... */ 731 ifp->if_flags |= IFF_OACTIVE; 732 733 /* and wait for any transmission result */ 734 bus_space_write_1(iot, ioh, 0, BANK_SEL(2)); 735 736 temp = bus_space_read_1(iot, ioh, REG1); 737 bus_space_write_1(iot, ioh, REG1, 738 temp & ~XMT_CHAIN_INT); 739 740 bus_space_write_1(iot, ioh, 0, BANK_SEL(0)); 741 742 return; 743 } 744 745 /* we know it fits in the hardware now, so dequeue it */ 746 IFQ_DEQUEUE(&ifp->if_snd, m0); 747 748 last = sc->tx_end; 749 end = last + pad + len + I595_XMT_HDRLEN; 750 751 if (end >= sc->sram) { 752 if ((sc->sram - last) <= I595_XMT_HDRLEN) { 753 /* keep header in one piece */ 754 last = sc->rx_size; 755 end = last + pad + len + I595_XMT_HDRLEN; 756 } else 757 end -= sc->tx_size; 758 } 759 760 bus_space_write_2(iot, ioh, HOST_ADDR_REG, last); 761 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 762 htole16(XMT_CMD)); 763 764 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 765 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 766 767 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 768 htole16(len + pad)); 769 770 residual = resval = 0; 771 772 while ((m = m0)!=0) { 773 data = mtod(m, caddr_t); 774 llen = m->m_len; 775 if (residual) { 776 #ifdef IYDEBUG 777 printf("%s: merging residual with next mbuf.\n", 778 sc->sc_dev.dv_xname); 779 #endif 780 resval |= *data << 8; 781 bus_space_write_stream_2(iot, ioh, 782 MEM_PORT_REG, resval); 783 --llen; 784 ++data; 785 } 786 /* 787 * XXX ALIGNMENT LOSSAGE HERE. 788 */ 789 if (llen > 1) 790 bus_space_write_multi_stream_2(iot, ioh, 791 MEM_PORT_REG, (u_int16_t *) data, 792 llen>>1); 793 residual = llen & 1; 794 if (residual) { 795 resval = *(data + llen - 1); 796 #ifdef IYDEBUG 797 printf("%s: got odd mbuf to send.\n", 798 sc->sc_dev.dv_xname); 799 #endif 800 } 801 802 MFREE(m, m0); 803 } 804 805 if (residual) 806 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 807 resval); 808 809 pad >>= 1; 810 while (pad-- > 0) 811 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 0); 812 813 #ifdef IYDEBUG 814 printf("%s: new last = 0x%x, end = 0x%x.\n", 815 sc->sc_dev.dv_xname, last, end); 816 printf("%s: old start = 0x%x, end = 0x%x, last = 0x%x\n", 817 sc->sc_dev.dv_xname, sc->tx_start, sc->tx_end, sc->tx_last); 818 #endif 819 820 if (sc->tx_start != sc->tx_end) { 821 bus_space_write_2(iot, ioh, HOST_ADDR_REG, 822 sc->tx_last + XMT_COUNT); 823 824 /* 825 * XXX We keep stat in le order, to potentially save 826 * a byte swap. 827 */ 828 stat = bus_space_read_stream_2(iot, ioh, MEM_PORT_REG); 829 830 bus_space_write_2(iot, ioh, HOST_ADDR_REG, 831 sc->tx_last + XMT_CHAIN); 832 833 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 834 htole16(last)); 835 836 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, 837 stat | htole16(CHAIN)); 838 #ifdef IYDEBUG 839 printf("%s: setting 0x%x to 0x%x\n", 840 sc->sc_dev.dv_xname, sc->tx_last + XMT_COUNT, 841 le16toh(stat) | CHAIN); 842 #endif 843 } 844 stat = bus_space_read_2(iot, ioh, MEM_PORT_REG); /* dummy read */ 845 846 /* XXX todo: enable ints here if disabled */ 847 848 ++ifp->if_opackets; 849 850 if (sc->tx_start == sc->tx_end) { 851 bus_space_write_2(iot, ioh, XMT_ADDR_REG, last); 852 bus_space_write_1(iot, ioh, 0, XMT_CMD); 853 sc->tx_start = last; 854 #ifdef IYDEBUG 855 printf("%s: writing 0x%x to XAR and giving XCMD\n", 856 sc->sc_dev.dv_xname, last); 857 #endif 858 } else { 859 bus_space_write_1(iot, ioh, 0, RESUME_XMT_CMD); 860 #ifdef IYDEBUG 861 printf("%s: giving RESUME_XCMD\n", 862 sc->sc_dev.dv_xname); 863 #endif 864 } 865 sc->tx_last = last; 866 sc->tx_end = end; 867 } 868 /* and wait only for end of transmission chain */ 869 bus_space_write_1(iot, ioh, 0, BANK_SEL(2)); 870 871 temp = bus_space_read_1(iot, ioh, REG1); 872 bus_space_write_1(iot, ioh, REG1, temp | XMT_CHAIN_INT); 873 874 bus_space_write_1(iot, ioh, 0, BANK_SEL(0)); 875 } 876 877 878 static inline void 879 eepromwritebit(iot, ioh, what) 880 bus_space_tag_t iot; 881 bus_space_handle_t ioh; 882 int what; 883 { 884 bus_space_write_1(iot, ioh, EEPROM_REG, what); 885 delay(1); 886 bus_space_write_1(iot, ioh, EEPROM_REG, what|EESK); 887 delay(1); 888 bus_space_write_1(iot, ioh, EEPROM_REG, what); 889 delay(1); 890 } 891 892 static inline int 893 eepromreadbit(iot, ioh) 894 bus_space_tag_t iot; 895 bus_space_handle_t ioh; 896 { 897 int b; 898 899 bus_space_write_1(iot, ioh, EEPROM_REG, EECS|EESK); 900 delay(1); 901 b = bus_space_read_1(iot, ioh, EEPROM_REG); 902 bus_space_write_1(iot, ioh, EEPROM_REG, EECS); 903 delay(1); 904 905 return ((b & EEDO) != 0); 906 } 907 908 static u_int16_t 909 eepromread(iot, ioh, offset) 910 bus_space_tag_t iot; 911 bus_space_handle_t ioh; 912 int offset; 913 { 914 volatile int i; 915 volatile int j; 916 volatile u_int16_t readval; 917 918 bus_space_write_1(iot, ioh, 0, BANK_SEL(2)); 919 delay(1); 920 bus_space_write_1(iot, ioh, EEPROM_REG, EECS); /* XXXX??? */ 921 delay(1); 922 923 eepromwritebit(iot, ioh, EECS|EEDI); 924 eepromwritebit(iot, ioh, EECS|EEDI); 925 eepromwritebit(iot, ioh, EECS); 926 927 for (j=5; j>=0; --j) { 928 if ((offset>>j) & 1) 929 eepromwritebit(iot, ioh, EECS|EEDI); 930 else 931 eepromwritebit(iot, ioh, EECS); 932 } 933 934 for (readval=0, i=0; i<16; ++i) { 935 readval<<=1; 936 readval |= eepromreadbit(iot, ioh); 937 } 938 939 bus_space_write_1(iot, ioh, EEPROM_REG, 0|EESK); 940 delay(1); 941 bus_space_write_1(iot, ioh, EEPROM_REG, 0); 942 943 bus_space_write_1(iot, ioh, COMMAND_REG, BANK_SEL(0)); 944 945 return readval; 946 } 947 948 /* 949 * Device timeout/watchdog routine. Entered if the device neglects to generate 950 * an interrupt after a transmit has been started on it. 951 */ 952 void 953 iywatchdog(ifp) 954 struct ifnet *ifp; 955 { 956 struct iy_softc *sc = ifp->if_softc; 957 958 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 959 ++sc->sc_ethercom.ec_if.if_oerrors; 960 iyreset(sc); 961 } 962 963 /* 964 * What to do upon receipt of an interrupt. 965 */ 966 int 967 iyintr(arg) 968 void *arg; 969 { 970 struct iy_softc *sc; 971 struct ifnet *ifp; 972 bus_space_tag_t iot; 973 bus_space_handle_t ioh; 974 975 u_short status; 976 977 sc = arg; 978 iot = sc->sc_iot; 979 ioh = sc->sc_ioh; 980 981 ifp = &sc->sc_ethercom.ec_if; 982 983 status = bus_space_read_1(iot, ioh, STATUS_REG); 984 #ifdef IYDEBUG 985 if (status & ALL_INTS) { 986 char sbuf[128]; 987 988 bitmask_snprintf(status, "\020\1RX_STP\2RX\3TX\4EXEC", 989 sbuf, sizeof(sbuf)); 990 printf("%s: got interrupt %s", sc->sc_dev.dv_xname, sbuf); 991 992 if (status & EXEC_INT) { 993 bitmask_snprintf(bus_space_read_1(iot, ioh, 0), 994 "\020\6ABORT", sbuf, sizeof(sbuf)); 995 printf(" event %s\n", sbuf); 996 } else 997 printf("\n"); 998 } 999 #endif 1000 if ((status & (RX_INT | TX_INT)) == 0) 1001 return 0; 1002 1003 if (status & RX_INT) { 1004 iy_intr_rx(sc); 1005 bus_space_write_1(iot, ioh, STATUS_REG, RX_INT); 1006 } 1007 if (status & TX_INT) { 1008 /* Tell feeders we may be able to accept more data... */ 1009 ifp->if_flags &= ~IFF_OACTIVE; 1010 /* and get more data. */ 1011 iystart(ifp); 1012 bus_space_write_1(iot, ioh, STATUS_REG, TX_INT); 1013 } 1014 1015 #if NRND > 0 1016 rnd_add_uint32(&sc->rnd_source, status); 1017 #endif 1018 1019 return 1; 1020 } 1021 1022 void 1023 iyget(sc, iot, ioh, rxlen) 1024 struct iy_softc *sc; 1025 bus_space_tag_t iot; 1026 bus_space_handle_t ioh; 1027 int rxlen; 1028 { 1029 struct mbuf *m, *top, **mp; 1030 struct ifnet *ifp; 1031 int len; 1032 1033 ifp = &sc->sc_ethercom.ec_if; 1034 1035 MGETHDR(m, M_DONTWAIT, MT_DATA); 1036 if (m == 0) 1037 goto dropped; 1038 m->m_pkthdr.rcvif = ifp; 1039 m->m_pkthdr.len = rxlen; 1040 len = MHLEN; 1041 top = 0; 1042 mp = ⊤ 1043 1044 while (rxlen > 0) { 1045 if (top) { 1046 MGET(m, M_DONTWAIT, MT_DATA); 1047 if (m == 0) { 1048 m_freem(top); 1049 goto dropped; 1050 } 1051 len = MLEN; 1052 } 1053 if (rxlen >= MINCLSIZE) { 1054 MCLGET(m, M_DONTWAIT); 1055 if ((m->m_flags & M_EXT) == 0) { 1056 m_free(m); 1057 m_freem(top); 1058 goto dropped; 1059 } 1060 len = MCLBYTES; 1061 } 1062 len = min(rxlen, len); 1063 /* 1064 * XXX ALIGNMENT LOSSAGE HERE. 1065 */ 1066 if (len > 1) { 1067 len &= ~1; 1068 1069 bus_space_read_multi_stream_2(iot, ioh, MEM_PORT_REG, 1070 mtod(m, u_int16_t *), len/2); 1071 } else { 1072 #ifdef IYDEBUG 1073 printf("%s: received odd mbuf\n", sc->sc_dev.dv_xname); 1074 #endif 1075 *(mtod(m, caddr_t)) = bus_space_read_stream_2(iot, ioh, 1076 MEM_PORT_REG); 1077 } 1078 m->m_len = len; 1079 rxlen -= len; 1080 *mp = m; 1081 mp = &m->m_next; 1082 } 1083 1084 if (top == NULL) 1085 return; 1086 1087 /* XXX receive the top here */ 1088 ++ifp->if_ipackets; 1089 1090 1091 #if NBPFILTER > 0 1092 if (ifp->if_bpf) 1093 bpf_mtap(ifp->if_bpf, top); 1094 #endif 1095 (*ifp->if_input)(ifp, top); 1096 return; 1097 1098 dropped: 1099 ++ifp->if_ierrors; 1100 return; 1101 } 1102 1103 void 1104 iy_intr_rx(sc) 1105 struct iy_softc *sc; 1106 { 1107 bus_space_tag_t iot; 1108 bus_space_handle_t ioh; 1109 1110 u_int rxadrs, rxevnt, rxstatus, rxnext, rxlen; 1111 1112 iot = sc->sc_iot; 1113 ioh = sc->sc_ioh; 1114 1115 rxadrs = sc->rx_start; 1116 bus_space_write_2(iot, ioh, HOST_ADDR_REG, rxadrs); 1117 rxevnt = le16toh(bus_space_read_stream_2(iot, ioh, MEM_PORT_REG)); 1118 rxnext = 0; 1119 1120 while (rxevnt == RCV_DONE) { 1121 rxstatus = le16toh(bus_space_read_stream_2(iot, ioh, 1122 MEM_PORT_REG)); 1123 rxnext = le16toh(bus_space_read_stream_2(iot, ioh, 1124 MEM_PORT_REG)); 1125 rxlen = le16toh(bus_space_read_stream_2(iot, ioh, 1126 MEM_PORT_REG)); 1127 #ifdef IYDEBUG 1128 { 1129 char sbuf[128]; 1130 1131 bitmask_snprintf(rxstatus, "\020\1RCLD\2IA_MCH\010SHORT\011OVRN\013ALGERR\014CRCERR\015LENERR\016RCVOK\020TYP", 1132 sbuf, sizeof(sbuf)); 1133 printf("%s: pck at 0x%04x stat %s next 0x%x len 0x%x\n", 1134 sc->sc_dev.dv_xname, rxadrs, sbuf, rxnext, rxlen); 1135 } 1136 #endif 1137 iyget(sc, iot, ioh, rxlen); 1138 1139 /* move stop address */ 1140 bus_space_write_2(iot, ioh, RCV_STOP_LOW, 1141 rxnext == 0 ? sc->rx_size - 2 : rxnext - 2); 1142 1143 bus_space_write_2(iot, ioh, HOST_ADDR_REG, rxnext); 1144 rxadrs = rxnext; 1145 rxevnt = le16toh(bus_space_read_stream_2(iot, ioh, 1146 MEM_PORT_REG)); 1147 } 1148 sc->rx_start = rxnext; 1149 } 1150 1151 void 1152 iy_intr_tx(sc) 1153 struct iy_softc *sc; 1154 { 1155 bus_space_tag_t iot; 1156 bus_space_handle_t ioh; 1157 struct ifnet *ifp; 1158 u_int txstatus, txstat2, txlen, txnext; 1159 1160 ifp = &sc->sc_ethercom.ec_if; 1161 iot = sc->sc_iot; 1162 ioh = sc->sc_ioh; 1163 1164 while (sc->tx_start != sc->tx_end) { 1165 bus_space_write_2(iot, ioh, HOST_ADDR_REG, sc->tx_start); 1166 txstatus = le16toh(bus_space_read_stream_2(iot, ioh, 1167 MEM_PORT_REG)); 1168 1169 if ((txstatus & (TX_DONE|CMD_MASK)) != (TX_DONE|XMT_CMD)) 1170 break; 1171 1172 txstat2 = le16toh(bus_space_read_stream_2(iot, ioh, 1173 MEM_PORT_REG)); 1174 txnext = le16toh(bus_space_read_stream_2(iot, ioh, 1175 MEM_PORT_REG)); 1176 txlen = le16toh(bus_space_read_stream_2(iot, ioh, 1177 MEM_PORT_REG)); 1178 #ifdef IYDEBUG 1179 { 1180 char sbuf[128]; 1181 1182 bitmask_snprintf(txstat2, "\020\6MAX_COL\7HRT_BEAT\010TX_DEF\011UND_RUN\012JERR\013LST_CRS\014LTCOL\016TX_OK\020COLL", 1183 sbuf, sizeof(sbuf)); 1184 printf("txstat 0x%x stat2 0x%s next 0x%x len 0x%x\n", 1185 txstatus, sbuf, txnext, txlen); 1186 } 1187 #endif 1188 if (txlen & CHAIN) 1189 sc->tx_start = txnext; 1190 else 1191 sc->tx_start = sc->tx_end; 1192 ifp->if_flags &= ~IFF_OACTIVE; 1193 1194 if (txstat2 & 0x0020) 1195 ifp->if_collisions += 16; 1196 else 1197 ifp->if_collisions += txstat2 & 0x000f; 1198 1199 if ((txstat2 & 0x2000) == 0) 1200 ++ifp->if_oerrors; 1201 } 1202 } 1203 1204 int 1205 iyioctl(ifp, cmd, data) 1206 struct ifnet *ifp; 1207 u_long cmd; 1208 caddr_t data; 1209 { 1210 struct iy_softc *sc; 1211 struct ifaddr *ifa; 1212 struct ifreq *ifr; 1213 int s, error = 0; 1214 1215 sc = ifp->if_softc; 1216 ifa = (struct ifaddr *)data; 1217 ifr = (struct ifreq *)data; 1218 1219 #ifdef IYDEBUG 1220 printf("iyioctl called with ifp %p (%s) cmd 0x%lx data %p\n", 1221 ifp, ifp->if_xname, cmd, data); 1222 #endif 1223 1224 s = splnet(); 1225 1226 switch (cmd) { 1227 1228 case SIOCSIFADDR: 1229 ifp->if_flags |= IFF_UP; 1230 1231 switch (ifa->ifa_addr->sa_family) { 1232 #ifdef INET 1233 case AF_INET: 1234 iyinit(sc); 1235 arp_ifinit(ifp, ifa); 1236 break; 1237 #endif 1238 #ifdef NS 1239 /* XXX - This code is probably wrong. */ 1240 case AF_NS: 1241 { 1242 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1243 1244 if (ns_nullhost(*ina)) 1245 ina->x_host = *(union ns_host *) 1246 LLADDR(ifp->if_sadl); 1247 else 1248 memcpy(LLADDR(ifp->if_sadl), ina->x_host.c_host, 1249 ETHER_ADDR_LEN); 1250 /* Set new address. */ 1251 iyinit(sc); 1252 break; 1253 } 1254 #endif /* NS */ 1255 default: 1256 iyinit(sc); 1257 break; 1258 } 1259 break; 1260 1261 case SIOCSIFFLAGS: 1262 sc->promisc = ifp->if_flags & (IFF_PROMISC | IFF_ALLMULTI); 1263 if ((ifp->if_flags & IFF_UP) == 0 && 1264 (ifp->if_flags & IFF_RUNNING) != 0) { 1265 /* 1266 * If interface is marked down and it is running, then 1267 * stop it. 1268 */ 1269 iystop(sc); 1270 ifp->if_flags &= ~IFF_RUNNING; 1271 } else if ((ifp->if_flags & IFF_UP) != 0 && 1272 (ifp->if_flags & IFF_RUNNING) == 0) { 1273 /* 1274 * If interface is marked up and it is stopped, then 1275 * start it. 1276 */ 1277 iyinit(sc); 1278 } else { 1279 /* 1280 * Reset the interface to pick up changes in any other 1281 * flags that affect hardware registers. 1282 */ 1283 iystop(sc); 1284 iyinit(sc); 1285 } 1286 #ifdef IYDEBUGX 1287 if (ifp->if_flags & IFF_DEBUG) 1288 sc->sc_debug = IFY_ALL; 1289 else 1290 sc->sc_debug = 0; 1291 #endif 1292 break; 1293 1294 case SIOCADDMULTI: 1295 case SIOCDELMULTI: 1296 error = (cmd == SIOCADDMULTI) ? 1297 ether_addmulti(ifr, &sc->sc_ethercom): 1298 ether_delmulti(ifr, &sc->sc_ethercom); 1299 1300 if (error == ENETRESET) { 1301 /* 1302 * Multicast list has changed; set the hardware filter 1303 * accordingly. 1304 */ 1305 if (ifp->if_flags & IFF_RUNNING) { 1306 /* XXX can't make it work otherwise */ 1307 iyreset(sc); 1308 iy_mc_reset(sc); 1309 } 1310 error = 0; 1311 } 1312 break; 1313 1314 case SIOCSIFMEDIA: 1315 case SIOCGIFMEDIA: 1316 error = ifmedia_ioctl(ifp, ifr, &sc->iy_ifmedia, cmd); 1317 break; 1318 default: 1319 error = EINVAL; 1320 } 1321 splx(s); 1322 return error; 1323 } 1324 1325 int 1326 iy_mediachange(ifp) 1327 struct ifnet *ifp; 1328 { 1329 struct iy_softc *sc = ifp->if_softc; 1330 1331 if (IFM_TYPE(sc->iy_ifmedia.ifm_media) != IFM_ETHER) 1332 return EINVAL; 1333 switch(IFM_SUBTYPE(sc->iy_ifmedia.ifm_media)) { 1334 case IFM_10_5: 1335 case IFM_10_2: 1336 case IFM_10_T: 1337 case IFM_AUTO: 1338 iystop(sc); 1339 iyinit(sc); 1340 return 0; 1341 default: 1342 return EINVAL; 1343 } 1344 } 1345 1346 void 1347 iy_mediastatus(ifp, ifmr) 1348 struct ifnet *ifp; 1349 struct ifmediareq *ifmr; 1350 { 1351 struct iy_softc *sc = ifp->if_softc; 1352 1353 ifmr->ifm_active = sc->iy_media; 1354 ifmr->ifm_status = IFM_AVALID | IFM_ACTIVE; 1355 } 1356 1357 1358 static void 1359 iy_mc_setup(sc) 1360 struct iy_softc *sc; 1361 { 1362 struct ether_multi *enm; 1363 struct ether_multistep step; 1364 struct ethercom *ecp; 1365 struct ifnet *ifp; 1366 bus_space_tag_t iot; 1367 bus_space_handle_t ioh; 1368 int avail, last /*, end*/ , len; 1369 int timeout; 1370 volatile u_int16_t dum; 1371 u_int8_t temp; 1372 1373 1374 ecp = &sc->sc_ethercom; 1375 ifp = &ecp->ec_if; 1376 1377 iot = sc->sc_iot; 1378 ioh = sc->sc_ioh; 1379 1380 len = 6 * ecp->ec_multicnt; 1381 1382 avail = sc->tx_start - sc->tx_end; 1383 if (avail <= 0) 1384 avail += sc->tx_size; 1385 if (ifp->if_flags & IFF_DEBUG) 1386 printf("%s: iy_mc_setup called, %d addresses, " 1387 "%d/%d bytes needed/avail\n", ifp->if_xname, 1388 ecp->ec_multicnt, len + I595_XMT_HDRLEN, avail); 1389 1390 last = sc->rx_size; 1391 1392 bus_space_write_1(iot, ioh, 0, BANK_SEL(2)); 1393 bus_space_write_1(iot, ioh, RECV_MODES_REG, MATCH_BRDCST); 1394 /* XXX VOODOO */ 1395 temp = bus_space_read_1(iot, ioh, MEDIA_SELECT); 1396 bus_space_write_1(iot, ioh, MEDIA_SELECT, temp); 1397 /* XXX END OF VOODOO */ 1398 bus_space_write_1(iot, ioh, 0, BANK_SEL(0)); 1399 bus_space_write_2(iot, ioh, HOST_ADDR_REG, last); 1400 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, htole16(MC_SETUP_CMD)); 1401 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 1402 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 1403 bus_space_write_stream_2(iot, ioh, MEM_PORT_REG, htole16(len)); 1404 1405 ETHER_FIRST_MULTI(step, ecp, enm); 1406 while(enm) { 1407 /* 1408 * XXX ALIGNMENT LOSSAGE HERE? 1409 */ 1410 bus_space_write_multi_stream_2(iot, ioh, MEM_PORT_REG, 1411 (u_int16_t *) enm->enm_addrlo, 3); 1412 1413 ETHER_NEXT_MULTI(step, enm); 1414 } 1415 dum = bus_space_read_2(iot, ioh, MEM_PORT_REG); /* dummy read */ 1416 bus_space_write_2(iot, ioh, XMT_ADDR_REG, last); 1417 bus_space_write_1(iot, ioh, 0, MC_SETUP_CMD); 1418 1419 1420 sc->tx_start = sc->rx_size; 1421 sc->tx_end = sc->rx_size + I595_XMT_HDRLEN + len; 1422 1423 for (timeout=0; timeout<100; timeout++) { 1424 DELAY(2); 1425 if ((bus_space_read_1(iot, ioh, STATUS_REG) & EXEC_INT) == 0) 1426 continue; 1427 1428 temp = bus_space_read_1(iot, ioh, 0); 1429 bus_space_write_1(iot, ioh, STATUS_REG, EXEC_INT); 1430 #ifdef DIAGNOSTIC 1431 if (temp & 0x20) { 1432 printf("%s: mc setup failed, %d usec\n", 1433 sc->sc_dev.dv_xname, timeout * 2); 1434 } else if (((temp & 0x0f) == 0x03) && 1435 (ifp->if_flags & IFF_DEBUG)) { 1436 printf("%s: mc setup done, %d usec\n", 1437 sc->sc_dev.dv_xname, timeout * 2); 1438 } 1439 #endif 1440 break; 1441 } 1442 sc->tx_start = sc->tx_end; 1443 ifp->if_flags &= ~IFF_OACTIVE; 1444 1445 } 1446 1447 static void 1448 iy_mc_reset(sc) 1449 struct iy_softc *sc; 1450 { 1451 struct ether_multi *enm; 1452 struct ether_multistep step; 1453 struct ethercom *ecp; 1454 struct ifnet *ifp; 1455 bus_space_tag_t iot; 1456 bus_space_handle_t ioh; 1457 u_int16_t temp; 1458 1459 ecp = &sc->sc_ethercom; 1460 ifp = &ecp->ec_if; 1461 1462 iot = sc->sc_iot; 1463 ioh = sc->sc_ioh; 1464 1465 if (ecp->ec_multicnt > 63) { 1466 ifp->if_flags |= IFF_ALLMULTI; 1467 1468 } else if (ecp->ec_multicnt > 0) { 1469 /* 1470 * Step through the list of addresses. 1471 */ 1472 ETHER_FIRST_MULTI(step, ecp, enm); 1473 while(enm) { 1474 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 6) != 0) { 1475 ifp->if_flags |= IFF_ALLMULTI; 1476 goto setupmulti; 1477 } 1478 ETHER_NEXT_MULTI(step, enm); 1479 } 1480 /* OK, we really need to do it now: */ 1481 #if 0 1482 if ((ifp->if_flags & (IFF_RUNNING | IFF_OACTIVE)) 1483 != IFF_RUNNING) { 1484 ifp->if_flags |= IFF_OACTIVE; 1485 sc->want_mc_setup = 1; 1486 return; 1487 } 1488 #endif 1489 iy_mc_setup(sc); 1490 } else { 1491 ifp->if_flags &= ~IFF_ALLMULTI; 1492 } 1493 1494 setupmulti: 1495 bus_space_write_1(iot, ioh, 0, BANK_SEL(2)); 1496 if (ifp->if_flags & (IFF_PROMISC|IFF_ALLMULTI)) { 1497 temp = MATCH_ALL; 1498 } else 1499 temp = MATCH_BRDCST; 1500 1501 bus_space_write_1(iot, ioh, RECV_MODES_REG, temp); 1502 /* XXX VOODOO */ 1503 temp = bus_space_read_1(iot, ioh, MEDIA_SELECT); 1504 bus_space_write_1(iot, ioh, MEDIA_SELECT, temp); 1505 /* XXX END OF VOODOO */ 1506 1507 /* XXX TBD: setup hardware for all multicasts */ 1508 bus_space_write_1(iot, ioh, 0, BANK_SEL(0)); 1509 return; 1510 } 1511 1512 #ifdef IYDEBUGX 1513 void 1514 print_rbd(rbd) 1515 volatile struct ie_recv_buf_desc *rbd; 1516 { 1517 printf("RBD at %08lx:\nactual %04x, next %04x, buffer %08x\n" 1518 "length %04x, mbz %04x\n", (u_long)rbd, rbd->ie_rbd_actual, 1519 rbd->ie_rbd_next, rbd->ie_rbd_buffer, rbd->ie_rbd_length, 1520 rbd->mbz); 1521 } 1522 #endif 1523 1524 void 1525 iyprobemem(sc) 1526 struct iy_softc *sc; 1527 { 1528 bus_space_tag_t iot; 1529 bus_space_handle_t ioh; 1530 int testing; 1531 1532 iot = sc->sc_iot; 1533 ioh = sc->sc_ioh; 1534 1535 bus_space_write_1(iot, ioh, COMMAND_REG, BANK_SEL(0)); 1536 delay(1); 1537 bus_space_write_2(iot, ioh, HOST_ADDR_REG, 4096-2); 1538 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 1539 1540 for (testing=65536; testing >= 4096; testing >>= 1) { 1541 bus_space_write_2(iot, ioh, HOST_ADDR_REG, testing-2); 1542 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0xdead); 1543 bus_space_write_2(iot, ioh, HOST_ADDR_REG, testing-2); 1544 if (bus_space_read_2(iot, ioh, MEM_PORT_REG) != 0xdead) { 1545 #ifdef IYMEMDEBUG 1546 printf("%s: Didn't keep 0xdead at 0x%x\n", 1547 sc->sc_dev.dv_xname, testing-2); 1548 #endif 1549 continue; 1550 } 1551 1552 bus_space_write_2(iot, ioh, HOST_ADDR_REG, testing-2); 1553 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0xbeef); 1554 bus_space_write_2(iot, ioh, HOST_ADDR_REG, testing-2); 1555 if (bus_space_read_2(iot, ioh, MEM_PORT_REG) != 0xbeef) { 1556 #ifdef IYMEMDEBUG 1557 printf("%s: Didn't keep 0xbeef at 0x%x\n", 1558 sc->sc_dev.dv_xname, testing-2); 1559 #endif 1560 continue; 1561 } 1562 1563 bus_space_write_2(iot, ioh, HOST_ADDR_REG, 0); 1564 bus_space_write_2(iot, ioh, MEM_PORT_REG, 0); 1565 bus_space_write_2(iot, ioh, HOST_ADDR_REG, testing >> 1); 1566 bus_space_write_2(iot, ioh, MEM_PORT_REG, testing >> 1); 1567 bus_space_write_2(iot, ioh, HOST_ADDR_REG, 0); 1568 if (bus_space_read_2(iot, ioh, MEM_PORT_REG) == (testing >> 1)) { 1569 #ifdef IYMEMDEBUG 1570 printf("%s: 0x%x alias of 0x0\n", 1571 sc->sc_dev.dv_xname, testing >> 1); 1572 #endif 1573 continue; 1574 } 1575 1576 break; 1577 } 1578 1579 sc->sram = testing; 1580 1581 switch(testing) { 1582 case 65536: 1583 /* 4 NFS packets + overhead RX, 2 NFS + overhead TX */ 1584 sc->rx_size = 44*1024; 1585 break; 1586 1587 case 32768: 1588 /* 2 NFS packets + overhead RX, 1 NFS + overhead TX */ 1589 sc->rx_size = 22*1024; 1590 break; 1591 1592 case 16384: 1593 /* 1 NFS packet + overhead RX, 4 big packets TX */ 1594 sc->rx_size = 10*1024; 1595 break; 1596 default: 1597 sc->rx_size = testing/2; 1598 break; 1599 } 1600 sc->tx_size = testing - sc->rx_size; 1601 } 1602 1603 static int 1604 eepromreadall(iot, ioh, wordp, maxi) 1605 bus_space_tag_t iot; 1606 bus_space_handle_t ioh; 1607 u_int16_t *wordp; 1608 int maxi; 1609 { 1610 int i; 1611 u_int16_t checksum, tmp; 1612 1613 checksum = 0; 1614 1615 for (i=0; i<EEPP_LENGTH; ++i) { 1616 tmp = eepromread(iot, ioh, i); 1617 checksum += tmp; 1618 if (i<maxi) 1619 wordp[i] = tmp; 1620 } 1621 1622 if (checksum != EEPP_CHKSUM) { 1623 #ifdef IYDEBUG 1624 printf("wrong EEPROM checksum 0x%x should be 0x%x\n", 1625 checksum, EEPP_CHKSUM); 1626 #endif 1627 return 1; 1628 } 1629 return 0; 1630 } 1631