1 /* $NetBSD: if_ix.c,v 1.35 2016/07/14 04:19:27 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Rafal K. Boni. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: if_ix.c,v 1.35 2016/07/14 04:19:27 msaitoh Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/mbuf.h> 38 #include <sys/errno.h> 39 #include <sys/device.h> 40 #include <sys/protosw.h> 41 #include <sys/socket.h> 42 43 #include <net/if.h> 44 #include <net/if_dl.h> 45 #include <net/if_types.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 49 #include <sys/cpu.h> 50 #include <sys/bus.h> 51 #include <sys/intr.h> 52 53 #include <dev/isa/isareg.h> 54 #include <dev/isa/isavar.h> 55 56 #include <dev/ic/i82586reg.h> 57 #include <dev/ic/i82586var.h> 58 #include <dev/isa/if_ixreg.h> 59 60 #ifdef IX_DEBUG 61 #define DPRINTF(x) printf x 62 #else 63 #define DPRINTF(x) 64 #endif 65 66 int ix_media[] = { 67 IFM_ETHER | IFM_10_5, 68 IFM_ETHER | IFM_10_2, 69 IFM_ETHER | IFM_10_T, 70 }; 71 #define NIX_MEDIA (sizeof(ix_media) / sizeof(ix_media[0])) 72 73 struct ix_softc { 74 struct ie_softc sc_ie; 75 76 bus_space_tag_t sc_regt; /* space tag for registers */ 77 bus_space_handle_t sc_regh; /* space handle for registers */ 78 79 u_int8_t use_pio; /* use PIO rather than shared mem */ 80 u_int16_t irq_encoded; /* encoded IRQ */ 81 void *sc_ih; /* interrupt handle */ 82 }; 83 84 static void ix_reset(struct ie_softc *, int); 85 static void ix_atten(struct ie_softc *, int); 86 static int ix_intrhook(struct ie_softc *, int); 87 88 static void ix_copyin(struct ie_softc *, void *, int, size_t); 89 static void ix_copyout(struct ie_softc *, const void *, int, size_t); 90 91 static void ix_bus_barrier(struct ie_softc *, int, int, int); 92 93 static u_int16_t ix_read_16(struct ie_softc *, int); 94 static void ix_write_16(struct ie_softc *, int, u_int16_t); 95 static void ix_write_24(struct ie_softc *, int, int); 96 static void ix_zeromem (struct ie_softc *, int, int); 97 98 static void ix_mediastatus(struct ie_softc *, struct ifmediareq *); 99 100 static u_int16_t ix_read_eeprom(bus_space_tag_t, bus_space_handle_t, int); 101 static void ix_eeprom_outbits(bus_space_tag_t, bus_space_handle_t, int, 102 int); 103 static int ix_eeprom_inbits (bus_space_tag_t, bus_space_handle_t); 104 static void ix_eeprom_clock (bus_space_tag_t, bus_space_handle_t, int); 105 106 int ix_match(device_t, cfdata_t, void *); 107 void ix_attach(device_t, device_t, void *); 108 109 /* 110 * EtherExpress/16 support routines 111 */ 112 static void 113 ix_reset(struct ie_softc *sc, int why) 114 { 115 struct ix_softc* isc = (struct ix_softc *) sc; 116 117 switch (why) { 118 case CHIP_PROBE: 119 bus_space_write_1(isc->sc_regt, isc->sc_regh, IX_ECTRL, 120 IX_RESET_586); 121 delay(100); 122 bus_space_write_1(isc->sc_regt, isc->sc_regh, IX_ECTRL, 0); 123 delay(100); 124 break; 125 126 case CARD_RESET: 127 break; 128 } 129 } 130 131 static void 132 ix_atten(struct ie_softc *sc, int why) 133 { 134 struct ix_softc* isc = (struct ix_softc *) sc; 135 bus_space_write_1(isc->sc_regt, isc->sc_regh, IX_ATTN, 0); 136 } 137 138 static u_int16_t 139 ix_read_eeprom(bus_space_tag_t iot, bus_space_handle_t ioh, int location) 140 { 141 int ectrl, edata; 142 143 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 144 ectrl &= IX_ECTRL_MASK; 145 ectrl |= IX_ECTRL_EECS; 146 bus_space_write_1(iot, ioh, IX_ECTRL, ectrl); 147 148 ix_eeprom_outbits(iot, ioh, IX_EEPROM_READ, IX_EEPROM_OPSIZE1); 149 ix_eeprom_outbits(iot, ioh, location, IX_EEPROM_ADDR_SIZE); 150 edata = ix_eeprom_inbits(iot, ioh); 151 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 152 ectrl &= ~(IX_RESET_ASIC | IX_ECTRL_EEDI | IX_ECTRL_EECS); 153 bus_space_write_1(iot, ioh, IX_ECTRL, ectrl); 154 ix_eeprom_clock(iot, ioh, 1); 155 ix_eeprom_clock(iot, ioh, 0); 156 return (edata); 157 } 158 159 static void 160 ix_eeprom_outbits(bus_space_tag_t iot, bus_space_handle_t ioh, int edata, 161 int count) 162 { 163 int ectrl, i; 164 165 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 166 ectrl &= ~IX_RESET_ASIC; 167 for (i = count - 1; i >= 0; i--) { 168 ectrl &= ~IX_ECTRL_EEDI; 169 if (edata & (1 << i)) { 170 ectrl |= IX_ECTRL_EEDI; 171 } 172 bus_space_write_1(iot, ioh, IX_ECTRL, ectrl); 173 delay(1); /* eeprom data must be setup for 0.4 uSec */ 174 ix_eeprom_clock(iot, ioh, 1); 175 ix_eeprom_clock(iot, ioh, 0); 176 } 177 ectrl &= ~IX_ECTRL_EEDI; 178 bus_space_write_1(iot, ioh, IX_ECTRL, ectrl); 179 delay(1); /* eeprom data must be held for 0.4 uSec */ 180 } 181 182 static int 183 ix_eeprom_inbits(bus_space_tag_t iot, bus_space_handle_t ioh) 184 { 185 int ectrl, edata, i; 186 187 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 188 ectrl &= ~IX_RESET_ASIC; 189 for (edata = 0, i = 0; i < 16; i++) { 190 edata = edata << 1; 191 ix_eeprom_clock(iot, ioh, 1); 192 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 193 if (ectrl & IX_ECTRL_EEDO) { 194 edata |= 1; 195 } 196 ix_eeprom_clock(iot, ioh, 0); 197 } 198 return (edata); 199 } 200 201 static void 202 ix_eeprom_clock(bus_space_tag_t iot, bus_space_handle_t ioh, int state) 203 { 204 int ectrl; 205 206 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 207 ectrl &= ~(IX_RESET_ASIC | IX_ECTRL_EESK); 208 if (state) { 209 ectrl |= IX_ECTRL_EESK; 210 } 211 bus_space_write_1(iot, ioh, IX_ECTRL, ectrl); 212 delay(9); /* EESK must be stable for 8.38 uSec */ 213 } 214 215 static int 216 ix_intrhook(struct ie_softc *sc, int where) 217 { 218 struct ix_softc* isc = (struct ix_softc *) sc; 219 220 switch (where) { 221 case INTR_ENTER: 222 /* entering ISR: disable card interrupts */ 223 bus_space_write_1(isc->sc_regt, isc->sc_regh, 224 IX_IRQ, isc->irq_encoded); 225 break; 226 227 case INTR_EXIT: 228 /* exiting ISR: re-enable card interrupts */ 229 bus_space_write_1(isc->sc_regt, isc->sc_regh, IX_IRQ, 230 isc->irq_encoded | IX_IRQ_ENABLE); 231 break; 232 } 233 234 return 1; 235 } 236 237 238 static void 239 ix_copyin(struct ie_softc *sc, void *dst, int offset, size_t size) 240 { 241 int i, dribble; 242 u_int8_t* bptr = dst; 243 u_int16_t* wptr = dst; 244 struct ix_softc* isc = (struct ix_softc *) sc; 245 246 if (isc->use_pio) { 247 /* Reset read pointer to the specified offset */ 248 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, 249 BUS_SPACE_BARRIER_READ); 250 bus_space_write_2(sc->bt, sc->bh, IX_READPTR, offset); 251 bus_space_barrier(sc->bt, sc->bh, IX_READPTR, 2, 252 BUS_SPACE_BARRIER_WRITE); 253 } else { 254 bus_space_barrier(sc->bt, sc->bh, offset, size, 255 BUS_SPACE_BARRIER_READ); 256 } 257 258 if (offset % 2) { 259 if (isc->use_pio) 260 *bptr = bus_space_read_1(sc->bt, sc->bh, IX_DATAPORT); 261 else 262 *bptr = bus_space_read_1(sc->bt, sc->bh, offset); 263 offset++; bptr++; size--; 264 } 265 266 dribble = size % 2; 267 wptr = (u_int16_t*) bptr; 268 269 if (isc->use_pio) { 270 for(i = 0; i < size / 2; i++) { 271 *wptr = bus_space_read_2(sc->bt, sc->bh, IX_DATAPORT); 272 wptr++; 273 } 274 } else { 275 bus_space_read_region_2(sc->bt, sc->bh, offset, 276 (u_int16_t *) bptr, size / 2); 277 } 278 279 if (dribble) { 280 bptr += size - 1; 281 offset += size - 1; 282 283 if (isc->use_pio) 284 *bptr = bus_space_read_1(sc->bt, sc->bh, IX_DATAPORT); 285 else 286 *bptr = bus_space_read_1(sc->bt, sc->bh, offset); 287 } 288 } 289 290 static void 291 ix_copyout(struct ie_softc *sc, const void *src, int offset, size_t size) 292 { 293 int i, dribble; 294 int osize = size; 295 int ooffset = offset; 296 const u_int8_t* bptr = src; 297 const u_int16_t* wptr = src; 298 struct ix_softc* isc = (struct ix_softc *) sc; 299 300 if (isc->use_pio) { 301 /* Reset write pointer to the specified offset */ 302 bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); 303 bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, 304 BUS_SPACE_BARRIER_WRITE); 305 } 306 307 if (offset % 2) { 308 if (isc->use_pio) 309 bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, *bptr); 310 else 311 bus_space_write_1(sc->bt, sc->bh, offset, *bptr); 312 offset++; bptr++; size--; 313 } 314 315 dribble = size % 2; 316 wptr = (const u_int16_t*) bptr; 317 318 if (isc->use_pio) { 319 for(i = 0; i < size / 2; i++) { 320 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, *wptr); 321 wptr++; 322 } 323 } else { 324 bus_space_write_region_2(sc->bt, sc->bh, offset, 325 (const u_int16_t *)bptr, size / 2); 326 } 327 328 if (dribble) { 329 bptr += size - 1; 330 offset += size - 1; 331 332 if (isc->use_pio) 333 bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, *bptr); 334 else 335 bus_space_write_1(sc->bt, sc->bh, offset, *bptr); 336 } 337 338 if (isc->use_pio) 339 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, 340 BUS_SPACE_BARRIER_WRITE); 341 else 342 bus_space_barrier(sc->bt, sc->bh, ooffset, osize, 343 BUS_SPACE_BARRIER_WRITE); 344 } 345 346 static void 347 ix_bus_barrier(struct ie_softc *sc, int offset, int length, int flags) 348 { 349 struct ix_softc* isc = (struct ix_softc *) sc; 350 351 if (isc->use_pio) 352 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, flags); 353 else 354 bus_space_barrier(sc->bt, sc->bh, offset, length, flags); 355 } 356 357 static u_int16_t 358 ix_read_16 (struct ie_softc *sc, int offset) 359 { 360 struct ix_softc* isc = (struct ix_softc *) sc; 361 362 if (isc->use_pio) { 363 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, 364 BUS_SPACE_BARRIER_READ); 365 366 /* Reset read pointer to the specified offset */ 367 bus_space_write_2(sc->bt, sc->bh, IX_READPTR, offset); 368 bus_space_barrier(sc->bt, sc->bh, IX_READPTR, 2, 369 BUS_SPACE_BARRIER_WRITE); 370 371 return bus_space_read_2(sc->bt, sc->bh, IX_DATAPORT); 372 } else { 373 bus_space_barrier(sc->bt, sc->bh, offset, 2, 374 BUS_SPACE_BARRIER_READ); 375 return bus_space_read_2(sc->bt, sc->bh, offset); 376 } 377 } 378 379 static void 380 ix_write_16 (struct ie_softc *sc, int offset, u_int16_t value) 381 { 382 struct ix_softc* isc = (struct ix_softc *) sc; 383 384 if (isc->use_pio) { 385 /* Reset write pointer to the specified offset */ 386 bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); 387 bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, 388 BUS_SPACE_BARRIER_WRITE); 389 390 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, value); 391 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, 392 BUS_SPACE_BARRIER_WRITE); 393 } else { 394 bus_space_write_2(sc->bt, sc->bh, offset, value); 395 bus_space_barrier(sc->bt, sc->bh, offset, 2, 396 BUS_SPACE_BARRIER_WRITE); 397 } 398 } 399 400 static void 401 ix_write_24 (struct ie_softc *sc, int offset, int addr) 402 { 403 char* ptr; 404 struct ix_softc* isc = (struct ix_softc *) sc; 405 int val = addr + (u_long) sc->sc_maddr - (u_long) sc->sc_iobase; 406 407 if (isc->use_pio) { 408 /* Reset write pointer to the specified offset */ 409 bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); 410 bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, 411 BUS_SPACE_BARRIER_WRITE); 412 413 ptr = (char*) &val; 414 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, 415 *((u_int16_t *)ptr)); 416 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, 417 *((u_int16_t *)(ptr + 2))); 418 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, 419 BUS_SPACE_BARRIER_WRITE); 420 } else { 421 bus_space_write_4(sc->bt, sc->bh, offset, val); 422 bus_space_barrier(sc->bt, sc->bh, offset, 4, 423 BUS_SPACE_BARRIER_WRITE); 424 } 425 } 426 427 static void 428 ix_zeromem(struct ie_softc *sc, int offset, int count) 429 { 430 int i; 431 int dribble; 432 struct ix_softc* isc = (struct ix_softc *) sc; 433 434 if (isc->use_pio) { 435 /* Reset write pointer to the specified offset */ 436 bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); 437 bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, 438 BUS_SPACE_BARRIER_WRITE); 439 440 if (offset % 2) { 441 bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, 0); 442 count--; 443 } 444 445 dribble = count % 2; 446 for(i = 0; i < count / 2; i++) 447 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, 0); 448 449 if (dribble) 450 bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, 0); 451 452 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, 453 BUS_SPACE_BARRIER_WRITE); 454 } else { 455 bus_space_set_region_1(sc->bt, sc->bh, offset, 0, count); 456 bus_space_barrier(sc->bt, sc->bh, offset, count, 457 BUS_SPACE_BARRIER_WRITE); 458 } 459 } 460 461 static void 462 ix_mediastatus(struct ie_softc *sc, struct ifmediareq *ifmr) 463 { 464 struct ifmedia *ifm = &sc->sc_media; 465 466 /* 467 * The currently selected media is always the active media. 468 */ 469 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 470 } 471 472 int 473 ix_match(device_t parent, cfdata_t cf, void *aux) 474 { 475 int i; 476 int rv = 0; 477 bus_addr_t maddr; 478 bus_size_t msiz; 479 u_short checksum = 0; 480 bus_space_handle_t ioh; 481 bus_space_tag_t iot; 482 u_int8_t val, bart_config; 483 u_short pg, adjust, decode, edecode; 484 u_short board_id, id_var1, id_var2, irq, irq_encoded; 485 struct isa_attach_args * const ia = aux; 486 short irq_translate[] = {0, 0x09, 0x03, 0x04, 0x05, 0x0a, 0x0b, 0}; 487 488 if (ia->ia_nio < 1) 489 return (0); 490 if (ia->ia_niomem < 1) 491 return (0); 492 if (ia->ia_nirq < 1) 493 return (0); 494 495 if (ISA_DIRECT_CONFIG(ia)) 496 return (0); 497 498 iot = ia->ia_iot; 499 500 if (ia->ia_io[0].ir_addr == ISA_UNKNOWN_PORT) 501 return (0); 502 503 if (bus_space_map(iot, ia->ia_io[0].ir_addr, 504 IX_IOSIZE, 0, &ioh) != 0) { 505 DPRINTF(("Can't map io space at 0x%x\n", ia->ia_iobase)); 506 return (0); 507 } 508 509 /* XXX: reset any ee16 at the current iobase */ 510 bus_space_write_1(iot, ioh, IX_ECTRL, IX_RESET_ASIC); 511 bus_space_write_1(iot, ioh, IX_ECTRL, 0); 512 delay(240); 513 514 /* now look for ee16. */ 515 board_id = id_var1 = id_var2 = 0; 516 for (i = 0; i < 4 ; i++) { 517 id_var1 = bus_space_read_1(iot, ioh, IX_ID_PORT); 518 id_var2 = ((id_var1 & 0x03) << 2); 519 board_id |= (( id_var1 >> 4) << id_var2); 520 } 521 522 if (board_id != IX_ID) { 523 DPRINTF(("BART ID mismatch (got 0x%04x, expected 0x%04x)\n", 524 board_id, IX_ID)); 525 goto out; 526 } 527 528 /* 529 * The shared RAM size and location of the EE16 is encoded into 530 * EEPROM location 6. The location of the first set bit tells us 531 * the memory address (0xc0000 + (0x4000 * FSB)), where FSB is the 532 * number of the first set bit. The zeroes are then shifted out, 533 * and the results is the memory size (1 = 16k, 3 = 32k, 7 = 48k, 534 * 0x0f = 64k). 535 * 536 * Examples: 537 * 0x3c -> 64k@0xc8000, 0x70 -> 48k@0xd0000, 0xc0 -> 32k@0xd8000 538 * 0x80 -> 16k@0xdc000. 539 * 540 * Side note: this comes from reading the old driver rather than 541 * from a more definitive source, so it could be out-of-whack 542 * with what the card can do... 543 */ 544 545 val = ix_read_eeprom(iot, ioh, 6) & 0xff; 546 for (pg = 0; pg < 8; pg++) { 547 if (val & 1) 548 break; 549 val >>= 1; 550 } 551 552 maddr = 0xc0000 + (pg * 0x4000); 553 554 switch (val) { 555 case 0x00: 556 maddr = 0; 557 msiz = 0; 558 break; 559 560 case 0x01: 561 msiz = 16 * 1024; 562 break; 563 564 case 0x03: 565 msiz = 32 * 1024; 566 break; 567 568 case 0x07: 569 msiz = 48 * 1024; 570 break; 571 572 case 0x0f: 573 msiz = 64 * 1024; 574 break; 575 576 default: 577 DPRINTF(("invalid memory size %02x\n", val)); 578 goto out; 579 } 580 581 if (ia->ia_iomem[0].ir_addr != ISA_UNKNOWN_IOMEM && 582 ia->ia_iomem[0].ir_addr != maddr) { 583 DPRINTF(( 584 "ix_match: memaddr of board @ 0x%x doesn't match config\n", 585 ia->ia_iobase)); 586 goto out; 587 } 588 589 if (ia->ia_iomem[0].ir_size != ISA_UNKNOWN_IOSIZ && 590 ia->ia_iomem[0].ir_size != msiz) { 591 DPRINTF(( 592 "ix_match: memsize of board @ 0x%x doesn't match config\n", 593 ia->ia_iobase)); 594 goto out; 595 } 596 597 /* need to put the 586 in RESET, and leave it */ 598 bus_space_write_1(iot, ioh, IX_ECTRL, IX_RESET_586); 599 600 /* read the eeprom and checksum it, should == IX_ID */ 601 for(i = 0; i < 0x40; i++) 602 checksum += ix_read_eeprom(iot, ioh, i); 603 604 if (checksum != IX_ID) { 605 DPRINTF(("checksum mismatch (got 0x%04x, expected 0x%04x\n", 606 checksum, IX_ID)); 607 goto out; 608 } 609 610 /* 611 * Only do the following bit if using memory-mapped access. For 612 * boards with no mapped memory, we use PIO. We also use PIO for 613 * boards with 16K of mapped memory, as those setups don't seem 614 * to work otherwise. 615 */ 616 if (msiz != 0 && msiz != 16384) { 617 /* Set board up with memory-mapping info */ 618 adjust = IX_MCTRL_FMCS16 | (pg & 0x3) << 2; 619 decode = ((1 << (ia->ia_iomem[0].ir_size / 16384)) - 1) << pg; 620 edecode = ((~decode >> 4) & 0xF0) | (decode >> 8); 621 622 bus_space_write_1(iot, ioh, IX_MEMDEC, decode & 0xFF); 623 bus_space_write_1(iot, ioh, IX_MCTRL, adjust); 624 bus_space_write_1(iot, ioh, IX_MPCTRL, (~decode & 0xFF)); 625 626 /* XXX disable Exxx */ 627 bus_space_write_1(iot, ioh, IX_MECTRL, edecode); 628 } 629 630 /* 631 * Get the encoded interrupt number from the EEPROM, check it 632 * against the passed in IRQ. Issue a warning if they do not 633 * match, and fail the probe. If irq is 'ISA_UNKNOWN_IRQ' then we 634 * use the EEPROM irq, and continue. 635 */ 636 irq_encoded = ix_read_eeprom(iot, ioh, IX_EEPROM_CONFIG1); 637 irq_encoded = (irq_encoded & IX_EEPROM_IRQ) >> IX_EEPROM_IRQ_SHIFT; 638 irq = irq_translate[irq_encoded]; 639 if (ia->ia_irq[0].ir_irq != ISA_UNKNOWN_IRQ && 640 irq != ia->ia_irq[0].ir_irq) { 641 DPRINTF(("board IRQ %d does not match config\n", irq)); 642 goto out; 643 } 644 645 /* disable the board interrupts */ 646 bus_space_write_1(iot, ioh, IX_IRQ, irq_encoded); 647 648 bart_config = bus_space_read_1(iot, ioh, IX_CONFIG); 649 bart_config |= IX_BART_LOOPBACK; 650 bart_config |= IX_BART_MCS16_TEST; /* inb doesn't get bit! */ 651 bus_space_write_1(iot, ioh, IX_CONFIG, bart_config); 652 bart_config = bus_space_read_1(iot, ioh, IX_CONFIG); 653 654 bus_space_write_1(iot, ioh, IX_ECTRL, 0); 655 delay(100); 656 657 rv = 1; 658 659 ia->ia_nio = 1; 660 ia->ia_io[0].ir_size = IX_IOSIZE; 661 662 ia->ia_niomem = 1; 663 ia->ia_iomem[0].ir_addr = maddr; 664 ia->ia_iomem[0].ir_size = msiz; 665 666 ia->ia_nirq = 1; 667 ia->ia_irq[0].ir_irq = irq; 668 669 DPRINTF(("ix_match: found board @ 0x%x\n", ia->ia_iobase)); 670 671 out: 672 bus_space_unmap(iot, ioh, IX_IOSIZE); 673 return (rv); 674 } 675 676 void 677 ix_attach(device_t parent, device_t self, void *aux) 678 { 679 struct ix_softc *isc = device_private(self); 680 struct ie_softc *sc = &isc->sc_ie; 681 struct isa_attach_args *ia = aux; 682 683 int media; 684 int i, memsize; 685 u_int8_t bart_config; 686 bus_space_tag_t iot; 687 u_int8_t bpat, bval; 688 u_int16_t wpat, wval; 689 bus_space_handle_t ioh, memh; 690 u_short irq_encoded; 691 u_int8_t ethaddr[ETHER_ADDR_LEN]; 692 693 sc->sc_dev = self; 694 iot = ia->ia_iot; 695 696 /* 697 * Shared memory access seems to fail on 16K mapped boards, so 698 * disable shared memory access if the board is in 16K mode. If 699 * no memory is mapped, we have no choice but to use PIO 700 */ 701 isc->use_pio = (ia->ia_iomem[0].ir_size <= (16 * 1024)); 702 703 if (bus_space_map(iot, ia->ia_io[0].ir_addr, 704 ia->ia_io[0].ir_size, 0, &ioh) != 0) { 705 706 DPRINTF(("\n%s: can't map i/o space 0x%x-0x%x\n", 707 device_xname(self), ia->ia_[0].ir_addr, 708 ia->ia_io[0].ir_addr + ia->ia_io[0].ir_size - 1)); 709 return; 710 } 711 712 /* We map memory even if using PIO so something else doesn't grab it */ 713 if (ia->ia_iomem[0].ir_size) { 714 if (bus_space_map(ia->ia_memt, ia->ia_iomem[0].ir_addr, 715 ia->ia_iomem[0].ir_size, 0, &memh) != 0) { 716 DPRINTF(("\n%s: can't map iomem space 0x%x-0x%x\n", 717 device_xname(self), ia->ia_iomem[0].ir_addr, 718 ia->ia_iomem[0].ir_addr + ia->ia_iomem[0].ir_size - 1)); 719 bus_space_unmap(iot, ioh, ia->ia_io[0].ir_size); 720 return; 721 } 722 } 723 724 isc->sc_regt = iot; 725 isc->sc_regh = ioh; 726 727 /* 728 * Get the hardware ethernet address from the EEPROM and 729 * save it in the softc for use by the 586 setup code. 730 */ 731 wval = ix_read_eeprom(iot, ioh, IX_EEPROM_ENET_HIGH); 732 ethaddr[1] = wval & 0xFF; 733 ethaddr[0] = wval >> 8; 734 wval = ix_read_eeprom(iot, ioh, IX_EEPROM_ENET_MID); 735 ethaddr[3] = wval & 0xFF; 736 ethaddr[2] = wval >> 8; 737 wval = ix_read_eeprom(iot, ioh, IX_EEPROM_ENET_LOW); 738 ethaddr[5] = wval & 0xFF; 739 ethaddr[4] = wval >> 8; 740 741 sc->hwinit = NULL; 742 sc->hwreset = ix_reset; 743 sc->chan_attn = ix_atten; 744 sc->intrhook = ix_intrhook; 745 746 sc->memcopyin = ix_copyin; 747 sc->memcopyout = ix_copyout; 748 749 /* If using PIO, make sure to setup single-byte read/write functions */ 750 if (isc->use_pio) { 751 sc->ie_bus_barrier = ix_bus_barrier; 752 } else { 753 sc->ie_bus_barrier = NULL; 754 } 755 756 sc->ie_bus_read16 = ix_read_16; 757 sc->ie_bus_write16 = ix_write_16; 758 sc->ie_bus_write24 = ix_write_24; 759 760 sc->do_xmitnopchain = 0; 761 762 sc->sc_mediachange = NULL; 763 sc->sc_mediastatus = ix_mediastatus; 764 765 if (isc->use_pio) { 766 sc->bt = iot; 767 sc->bh = ioh; 768 769 /* 770 * If using PIO, the memory size is bounded by on-card memory, 771 * not by how much is mapped into the memory-mapped region, so 772 * determine how much total memory we have to play with here. 773 */ 774 for(memsize = 64 * 1024; memsize; memsize -= 16 * 1024) { 775 /* warm up shared memory, the zero it all out */ 776 ix_zeromem(sc, 0, 32); 777 ix_zeromem(sc, 0, memsize); 778 779 /* Reset write pointer to the start of RAM */ 780 bus_space_write_2(iot, ioh, IX_WRITEPTR, 0); 781 bus_space_barrier(iot, ioh, IX_WRITEPTR, 2, 782 BUS_SPACE_BARRIER_WRITE); 783 784 /* write test pattern */ 785 for(i = 0, wpat = 1; i < memsize; i += 2) { 786 bus_space_write_2(iot, ioh, IX_DATAPORT, wpat); 787 wpat += 3; 788 } 789 790 /* Flush all reads & writes to data port */ 791 bus_space_barrier(iot, ioh, IX_DATAPORT, 2, 792 BUS_SPACE_BARRIER_READ | 793 BUS_SPACE_BARRIER_WRITE); 794 795 /* Reset read pointer to beginning of card RAM */ 796 bus_space_write_2(iot, ioh, IX_READPTR, 0); 797 bus_space_barrier(iot, ioh, IX_READPTR, 2, 798 BUS_SPACE_BARRIER_WRITE); 799 800 /* read and verify test pattern */ 801 for(i = 0, wpat = 1; i < memsize; i += 2) { 802 wval = bus_space_read_2(iot, ioh, IX_DATAPORT); 803 804 if (wval != wpat) 805 break; 806 807 wpat += 3; 808 } 809 810 /* If we failed, try next size down */ 811 if (i != memsize) 812 continue; 813 814 /* Now try it all with byte reads/writes */ 815 ix_zeromem(sc, 0, 32); 816 ix_zeromem(sc, 0, memsize); 817 818 /* Reset write pointer to start of card RAM */ 819 bus_space_write_2(iot, ioh, IX_WRITEPTR, 0); 820 bus_space_barrier(iot, ioh, IX_WRITEPTR, 2, 821 BUS_SPACE_BARRIER_WRITE); 822 823 /* write out test pattern */ 824 for(i = 0, bpat = 1; i < memsize; i++) { 825 bus_space_write_1(iot, ioh, IX_DATAPORT, bpat); 826 bpat += 3; 827 } 828 829 /* Flush all reads & writes to data port */ 830 bus_space_barrier(iot, ioh, IX_DATAPORT, 2, 831 BUS_SPACE_BARRIER_READ | 832 BUS_SPACE_BARRIER_WRITE); 833 834 /* Reset read pointer to beginning of card RAM */ 835 bus_space_write_2(iot, ioh, IX_READPTR, 0); 836 bus_space_barrier(iot, ioh, IX_READPTR, 2, 837 BUS_SPACE_BARRIER_WRITE); 838 839 /* read and verify test pattern */ 840 for(i = 0, bpat = 1; i < memsize; i++) { 841 bval = bus_space_read_1(iot, ioh, IX_DATAPORT); 842 843 if (bval != bpat) 844 bpat += 3; 845 } 846 847 /* If we got through all of memory, we're done! */ 848 if (i == memsize) 849 break; 850 } 851 852 /* Memory tests failed, punt... */ 853 if (memsize == 0) { 854 DPRINTF(("\n%s: can't determine size of on-card RAM\n", 855 device_xname(self))); 856 bus_space_unmap(iot, ioh, ia->ia_io[0].ir_size); 857 return; 858 } 859 860 sc->bt = iot; 861 sc->bh = ioh; 862 863 sc->sc_msize = memsize; 864 sc->sc_maddr = (void*) 0; 865 } else { 866 sc->bt = ia->ia_memt; 867 sc->bh = memh; 868 869 sc->sc_msize = ia->ia_iomem[0].ir_size; 870 sc->sc_maddr = (void *)memh; 871 } 872 873 /* Map i/o space. */ 874 sc->sc_iobase = (char *)sc->sc_maddr + sc->sc_msize - (1 << 24); 875 876 /* set up pointers to important on-card control structures */ 877 sc->iscp = 0; 878 sc->scb = IE_ISCP_SZ; 879 sc->scp = sc->sc_msize + IE_SCP_ADDR - (1 << 24); 880 881 sc->buf_area = sc->scb + IE_SCB_SZ; 882 sc->buf_area_sz = sc->sc_msize - IE_ISCP_SZ - IE_SCB_SZ - IE_SCP_SZ; 883 884 /* zero card memory */ 885 ix_zeromem(sc, 0, 32); 886 ix_zeromem(sc, 0, sc->sc_msize); 887 888 /* set card to 16-bit bus mode */ 889 if (isc->use_pio) { 890 bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, 891 IE_SCP_BUS_USE((u_long)sc->scp)); 892 bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, 893 BUS_SPACE_BARRIER_WRITE); 894 895 bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, 896 IE_SYSBUS_16BIT); 897 } else { 898 bus_space_write_1(sc->bt, sc->bh, 899 IE_SCP_BUS_USE((u_long)sc->scp), 900 IE_SYSBUS_16BIT); 901 } 902 903 /* set up pointers to key structures */ 904 ix_write_24(sc, IE_SCP_ISCP((u_long)sc->scp), (u_long) sc->iscp); 905 ix_write_16(sc, IE_ISCP_SCB((u_long)sc->iscp), (u_long) sc->scb); 906 ix_write_24(sc, IE_ISCP_BASE((u_long)sc->iscp), (u_long) sc->iscp); 907 908 /* flush setup of pointers, check if chip answers */ 909 if (isc->use_pio) { 910 bus_space_barrier(sc->bt, sc->bh, 0, IX_IOSIZE, 911 BUS_SPACE_BARRIER_WRITE); 912 } else { 913 bus_space_barrier(sc->bt, sc->bh, 0, sc->sc_msize, 914 BUS_SPACE_BARRIER_WRITE); 915 } 916 917 if (!i82586_proberam(sc)) { 918 DPRINTF(("\n%s: Can't talk to i82586!\n", 919 device_xname(self))); 920 bus_space_unmap(iot, ioh, ia->ia_io[0].ir_size); 921 922 if (ia->ia_iomem[0].ir_size) 923 bus_space_unmap(ia->ia_memt, memh, 924 ia->ia_iomem[0].ir_size); 925 return; 926 } 927 928 /* Figure out which media is being used... */ 929 if (ix_read_eeprom(iot, ioh, IX_EEPROM_CONFIG1) & 930 IX_EEPROM_MEDIA_EXT) { 931 if (ix_read_eeprom(iot, ioh, IX_EEPROM_MEDIA) & 932 IX_EEPROM_MEDIA_TP) 933 media = IFM_ETHER | IFM_10_T; 934 else 935 media = IFM_ETHER | IFM_10_2; 936 } else 937 media = IFM_ETHER | IFM_10_5; 938 939 /* Take the card out of lookback */ 940 bart_config = bus_space_read_1(iot, ioh, IX_CONFIG); 941 bart_config &= ~IX_BART_LOOPBACK; 942 bart_config |= IX_BART_MCS16_TEST; /* inb doesn't get bit! */ 943 bus_space_write_1(iot, ioh, IX_CONFIG, bart_config); 944 bart_config = bus_space_read_1(iot, ioh, IX_CONFIG); 945 946 irq_encoded = ix_read_eeprom(iot, ioh, 947 IX_EEPROM_CONFIG1); 948 irq_encoded = (irq_encoded & IX_EEPROM_IRQ) >> IX_EEPROM_IRQ_SHIFT; 949 950 /* Enable interrupts */ 951 bus_space_write_1(iot, ioh, IX_IRQ, 952 irq_encoded | IX_IRQ_ENABLE); 953 954 /* Flush all writes to registers */ 955 bus_space_barrier(iot, ioh, 0, ia->ia_io[0].ir_size, 956 BUS_SPACE_BARRIER_WRITE); 957 958 isc->irq_encoded = irq_encoded; 959 960 i82586_attach(sc, "EtherExpress/16", ethaddr, 961 ix_media, NIX_MEDIA, media); 962 963 if (isc->use_pio) 964 aprint_error_dev(self, "unsupported memory config, using PIO " 965 "to access %d bytes of memory\n", sc->sc_msize); 966 967 isc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq[0].ir_irq, 968 IST_EDGE, IPL_NET, i82586_intr, sc); 969 if (isc->sc_ih == NULL) { 970 DPRINTF(("\n%s: can't establish interrupt\n", 971 device_xname(self))); 972 } 973 } 974 975 CFATTACH_DECL_NEW(ix, sizeof(struct ix_softc), 976 ix_match, ix_attach, NULL, NULL); 977