1 /* $NetBSD: if_ix.c,v 1.38 2019/04/25 10:08:46 msaitoh Exp $ */ 2 3 /*- 4 * Copyright (c) 1998 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Rafal K. Boni. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #include <sys/cdefs.h> 33 __KERNEL_RCSID(0, "$NetBSD: if_ix.c,v 1.38 2019/04/25 10:08:46 msaitoh Exp $"); 34 35 #include <sys/param.h> 36 #include <sys/systm.h> 37 #include <sys/mbuf.h> 38 #include <sys/errno.h> 39 #include <sys/device.h> 40 #include <sys/protosw.h> 41 #include <sys/socket.h> 42 43 #include <net/if.h> 44 #include <net/if_dl.h> 45 #include <net/if_types.h> 46 #include <net/if_media.h> 47 #include <net/if_ether.h> 48 49 #include <sys/cpu.h> 50 #include <sys/bus.h> 51 #include <sys/intr.h> 52 53 #include <dev/isa/isareg.h> 54 #include <dev/isa/isavar.h> 55 56 #include <dev/ic/i82586reg.h> 57 #include <dev/ic/i82586var.h> 58 #include <dev/isa/if_ixreg.h> 59 60 #ifdef IX_DEBUG 61 #define DPRINTF(x) printf x 62 #else 63 #define DPRINTF(x) 64 #endif 65 66 static int ix_media[] = { 67 IFM_ETHER | IFM_10_5, 68 IFM_ETHER | IFM_10_2, 69 IFM_ETHER | IFM_10_T, 70 }; 71 #define NIX_MEDIA __arraycount(ix_media) 72 73 struct ix_softc { 74 struct ie_softc sc_ie; 75 76 bus_space_tag_t sc_regt; /* space tag for registers */ 77 bus_space_handle_t sc_regh; /* space handle for registers */ 78 79 uint8_t use_pio; /* use PIO rather than shared mem */ 80 uint16_t irq_encoded; /* encoded IRQ */ 81 void *sc_ih; /* interrupt handle */ 82 }; 83 84 static void ix_reset(struct ie_softc *, int); 85 static void ix_atten(struct ie_softc *, int); 86 static int ix_intrhook(struct ie_softc *, int); 87 88 static void ix_copyin(struct ie_softc *, void *, int, size_t); 89 static void ix_copyout(struct ie_softc *, const void *, int, size_t); 90 91 static void ix_bus_barrier(struct ie_softc *, int, int, int); 92 93 static uint16_t ix_read_16(struct ie_softc *, int); 94 static void ix_write_16(struct ie_softc *, int, uint16_t); 95 static void ix_write_24(struct ie_softc *, int, int); 96 static void ix_zeromem(struct ie_softc *, int, int); 97 98 static void ix_mediastatus(struct ie_softc *, struct ifmediareq *); 99 100 static uint16_t ix_read_eeprom(bus_space_tag_t, bus_space_handle_t, int); 101 static void ix_eeprom_outbits(bus_space_tag_t, bus_space_handle_t, int, 102 int); 103 static int ix_eeprom_inbits(bus_space_tag_t, bus_space_handle_t); 104 static void ix_eeprom_clock(bus_space_tag_t, bus_space_handle_t, int); 105 106 static int ix_match(device_t, cfdata_t, void *); 107 static void ix_attach(device_t, device_t, void *); 108 109 /* 110 * EtherExpress/16 support routines 111 */ 112 static void 113 ix_reset(struct ie_softc *sc, int why) 114 { 115 struct ix_softc *isc = (struct ix_softc *)sc; 116 117 switch (why) { 118 case CHIP_PROBE: 119 bus_space_write_1(isc->sc_regt, isc->sc_regh, IX_ECTRL, 120 IX_RESET_586); 121 delay(100); 122 bus_space_write_1(isc->sc_regt, isc->sc_regh, IX_ECTRL, 0); 123 delay(100); 124 break; 125 126 case CARD_RESET: 127 break; 128 } 129 } 130 131 static void 132 ix_atten(struct ie_softc *sc, int why) 133 { 134 struct ix_softc *isc = (struct ix_softc *)sc; 135 136 bus_space_write_1(isc->sc_regt, isc->sc_regh, IX_ATTN, 0); 137 } 138 139 static uint16_t 140 ix_read_eeprom(bus_space_tag_t iot, bus_space_handle_t ioh, int location) 141 { 142 int ectrl, edata; 143 144 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 145 ectrl &= IX_ECTRL_MASK; 146 ectrl |= IX_ECTRL_EECS; 147 bus_space_write_1(iot, ioh, IX_ECTRL, ectrl); 148 149 ix_eeprom_outbits(iot, ioh, IX_EEPROM_READ, IX_EEPROM_OPSIZE1); 150 ix_eeprom_outbits(iot, ioh, location, IX_EEPROM_ADDR_SIZE); 151 edata = ix_eeprom_inbits(iot, ioh); 152 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 153 ectrl &= ~(IX_RESET_ASIC | IX_ECTRL_EEDI | IX_ECTRL_EECS); 154 bus_space_write_1(iot, ioh, IX_ECTRL, ectrl); 155 ix_eeprom_clock(iot, ioh, 1); 156 ix_eeprom_clock(iot, ioh, 0); 157 return edata; 158 } 159 160 static void 161 ix_eeprom_outbits(bus_space_tag_t iot, bus_space_handle_t ioh, int edata, 162 int count) 163 { 164 int ectrl, i; 165 166 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 167 ectrl &= ~IX_RESET_ASIC; 168 for (i = count - 1; i >= 0; i--) { 169 ectrl &= ~IX_ECTRL_EEDI; 170 if (edata & (1 << i)) { 171 ectrl |= IX_ECTRL_EEDI; 172 } 173 bus_space_write_1(iot, ioh, IX_ECTRL, ectrl); 174 delay(1); /* eeprom data must be setup for 0.4 uSec */ 175 ix_eeprom_clock(iot, ioh, 1); 176 ix_eeprom_clock(iot, ioh, 0); 177 } 178 ectrl &= ~IX_ECTRL_EEDI; 179 bus_space_write_1(iot, ioh, IX_ECTRL, ectrl); 180 delay(1); /* eeprom data must be held for 0.4 uSec */ 181 } 182 183 static int 184 ix_eeprom_inbits(bus_space_tag_t iot, bus_space_handle_t ioh) 185 { 186 int ectrl, edata, i; 187 188 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 189 ectrl &= ~IX_RESET_ASIC; 190 for (edata = 0, i = 0; i < 16; i++) { 191 edata = edata << 1; 192 ix_eeprom_clock(iot, ioh, 1); 193 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 194 if (ectrl & IX_ECTRL_EEDO) { 195 edata |= 1; 196 } 197 ix_eeprom_clock(iot, ioh, 0); 198 } 199 return edata; 200 } 201 202 static void 203 ix_eeprom_clock(bus_space_tag_t iot, bus_space_handle_t ioh, int state) 204 { 205 int ectrl; 206 207 ectrl = bus_space_read_1(iot, ioh, IX_ECTRL); 208 ectrl &= ~(IX_RESET_ASIC | IX_ECTRL_EESK); 209 if (state) { 210 ectrl |= IX_ECTRL_EESK; 211 } 212 bus_space_write_1(iot, ioh, IX_ECTRL, ectrl); 213 delay(9); /* EESK must be stable for 8.38 uSec */ 214 } 215 216 static int 217 ix_intrhook(struct ie_softc *sc, int where) 218 { 219 struct ix_softc *isc = (struct ix_softc *)sc; 220 221 switch (where) { 222 case INTR_ENTER: 223 /* Entering ISR: disable card interrupts */ 224 bus_space_write_1(isc->sc_regt, isc->sc_regh, 225 IX_IRQ, isc->irq_encoded); 226 break; 227 228 case INTR_EXIT: 229 /* Exiting ISR: re-enable card interrupts */ 230 bus_space_write_1(isc->sc_regt, isc->sc_regh, IX_IRQ, 231 isc->irq_encoded | IX_IRQ_ENABLE); 232 break; 233 } 234 235 return 1; 236 } 237 238 239 static void 240 ix_copyin(struct ie_softc *sc, void *dst, int offset, size_t size) 241 { 242 int i, dribble; 243 uint8_t *bptr = dst; 244 uint16_t *wptr = dst; 245 struct ix_softc *isc = (struct ix_softc *)sc; 246 247 if (isc->use_pio) { 248 /* Reset read pointer to the specified offset */ 249 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, 250 BUS_SPACE_BARRIER_READ); 251 bus_space_write_2(sc->bt, sc->bh, IX_READPTR, offset); 252 bus_space_barrier(sc->bt, sc->bh, IX_READPTR, 2, 253 BUS_SPACE_BARRIER_WRITE); 254 } else 255 bus_space_barrier(sc->bt, sc->bh, offset, size, 256 BUS_SPACE_BARRIER_READ); 257 258 if (offset % 2) { 259 if (isc->use_pio) 260 *bptr = bus_space_read_1(sc->bt, sc->bh, IX_DATAPORT); 261 else 262 *bptr = bus_space_read_1(sc->bt, sc->bh, offset); 263 offset++; bptr++; size--; 264 } 265 266 dribble = size % 2; 267 wptr = (uint16_t*)bptr; 268 269 if (isc->use_pio) { 270 for (i = 0; i < size / 2; i++) { 271 *wptr = bus_space_read_2(sc->bt, sc->bh, IX_DATAPORT); 272 wptr++; 273 } 274 } else 275 bus_space_read_region_2(sc->bt, sc->bh, offset, 276 (uint16_t *)bptr, size / 2); 277 278 if (dribble) { 279 bptr += size - 1; 280 offset += size - 1; 281 282 if (isc->use_pio) 283 *bptr = bus_space_read_1(sc->bt, sc->bh, IX_DATAPORT); 284 else 285 *bptr = bus_space_read_1(sc->bt, sc->bh, offset); 286 } 287 } 288 289 static void 290 ix_copyout(struct ie_softc *sc, const void *src, int offset, size_t size) 291 { 292 int i, dribble; 293 int osize = size; 294 int ooffset = offset; 295 const uint8_t *bptr = src; 296 const uint16_t *wptr = src; 297 struct ix_softc *isc = (struct ix_softc *)sc; 298 299 if (isc->use_pio) { 300 /* Reset write pointer to the specified offset */ 301 bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); 302 bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, 303 BUS_SPACE_BARRIER_WRITE); 304 } 305 306 if (offset % 2) { 307 if (isc->use_pio) 308 bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, *bptr); 309 else 310 bus_space_write_1(sc->bt, sc->bh, offset, *bptr); 311 offset++; bptr++; size--; 312 } 313 314 dribble = size % 2; 315 wptr = (const uint16_t*)bptr; 316 317 if (isc->use_pio) { 318 for (i = 0; i < size / 2; i++) { 319 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, *wptr); 320 wptr++; 321 } 322 } else 323 bus_space_write_region_2(sc->bt, sc->bh, offset, 324 (const uint16_t *)bptr, size / 2); 325 326 if (dribble) { 327 bptr += size - 1; 328 offset += size - 1; 329 330 if (isc->use_pio) 331 bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, *bptr); 332 else 333 bus_space_write_1(sc->bt, sc->bh, offset, *bptr); 334 } 335 336 if (isc->use_pio) 337 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, 338 BUS_SPACE_BARRIER_WRITE); 339 else 340 bus_space_barrier(sc->bt, sc->bh, ooffset, osize, 341 BUS_SPACE_BARRIER_WRITE); 342 } 343 344 static void 345 ix_bus_barrier(struct ie_softc *sc, int offset, int length, int flags) 346 { 347 struct ix_softc *isc = (struct ix_softc *)sc; 348 349 if (isc->use_pio) 350 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, flags); 351 else 352 bus_space_barrier(sc->bt, sc->bh, offset, length, flags); 353 } 354 355 static uint16_t 356 ix_read_16(struct ie_softc *sc, int offset) 357 { 358 struct ix_softc *isc = (struct ix_softc *)sc; 359 360 if (isc->use_pio) { 361 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, 362 BUS_SPACE_BARRIER_READ); 363 364 /* Reset read pointer to the specified offset */ 365 bus_space_write_2(sc->bt, sc->bh, IX_READPTR, offset); 366 bus_space_barrier(sc->bt, sc->bh, IX_READPTR, 2, 367 BUS_SPACE_BARRIER_WRITE); 368 369 return bus_space_read_2(sc->bt, sc->bh, IX_DATAPORT); 370 } else { 371 bus_space_barrier(sc->bt, sc->bh, offset, 2, 372 BUS_SPACE_BARRIER_READ); 373 return bus_space_read_2(sc->bt, sc->bh, offset); 374 } 375 } 376 377 static void 378 ix_write_16(struct ie_softc *sc, int offset, uint16_t value) 379 { 380 struct ix_softc *isc = (struct ix_softc *)sc; 381 382 if (isc->use_pio) { 383 /* Reset write pointer to the specified offset */ 384 bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); 385 bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, 386 BUS_SPACE_BARRIER_WRITE); 387 388 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, value); 389 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, 390 BUS_SPACE_BARRIER_WRITE); 391 } else { 392 bus_space_write_2(sc->bt, sc->bh, offset, value); 393 bus_space_barrier(sc->bt, sc->bh, offset, 2, 394 BUS_SPACE_BARRIER_WRITE); 395 } 396 } 397 398 static void 399 ix_write_24 (struct ie_softc *sc, int offset, int addr) 400 { 401 char *ptr; 402 struct ix_softc *isc = (struct ix_softc *)sc; 403 int val = addr + (u_long)sc->sc_maddr - (u_long)sc->sc_iobase; 404 405 if (isc->use_pio) { 406 /* Reset write pointer to the specified offset */ 407 bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); 408 bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, 409 BUS_SPACE_BARRIER_WRITE); 410 411 ptr = (char*)&val; 412 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, 413 *((uint16_t *)ptr)); 414 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, 415 *((uint16_t *)(ptr + 2))); 416 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, 417 BUS_SPACE_BARRIER_WRITE); 418 } else { 419 bus_space_write_4(sc->bt, sc->bh, offset, val); 420 bus_space_barrier(sc->bt, sc->bh, offset, 4, 421 BUS_SPACE_BARRIER_WRITE); 422 } 423 } 424 425 static void 426 ix_zeromem(struct ie_softc *sc, int offset, int count) 427 { 428 int i; 429 int dribble; 430 struct ix_softc *isc = (struct ix_softc *)sc; 431 432 if (isc->use_pio) { 433 /* Reset write pointer to the specified offset */ 434 bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, offset); 435 bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, 436 BUS_SPACE_BARRIER_WRITE); 437 438 if (offset % 2) { 439 bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, 0); 440 count--; 441 } 442 443 dribble = count % 2; 444 for (i = 0; i < count / 2; i++) 445 bus_space_write_2(sc->bt, sc->bh, IX_DATAPORT, 0); 446 447 if (dribble) 448 bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, 0); 449 450 bus_space_barrier(sc->bt, sc->bh, IX_DATAPORT, 2, 451 BUS_SPACE_BARRIER_WRITE); 452 } else { 453 bus_space_set_region_1(sc->bt, sc->bh, offset, 0, count); 454 bus_space_barrier(sc->bt, sc->bh, offset, count, 455 BUS_SPACE_BARRIER_WRITE); 456 } 457 } 458 459 static void 460 ix_mediastatus(struct ie_softc *sc, struct ifmediareq *ifmr) 461 { 462 struct ifmedia *ifm = &sc->sc_media; 463 464 /* The currently selected media is always the active media. */ 465 ifmr->ifm_active = ifm->ifm_cur->ifm_media; 466 } 467 468 int 469 ix_match(device_t parent, cfdata_t cf, void *aux) 470 { 471 int i; 472 int rv = 0; 473 bus_addr_t maddr; 474 bus_size_t msiz; 475 u_short checksum = 0; 476 bus_space_handle_t ioh; 477 bus_space_tag_t iot; 478 uint8_t val, bart_config; 479 uint16_t pg, adjust, decode, edecode; 480 uint16_t board_id, id_var1, id_var2, irq, irq_encoded; 481 struct isa_attach_args * const ia = aux; 482 short irq_translate[] = {0, 0x09, 0x03, 0x04, 0x05, 0x0a, 0x0b, 0}; 483 484 if (ia->ia_nio < 1) 485 return 0; 486 if (ia->ia_niomem < 1) 487 return 0; 488 if (ia->ia_nirq < 1) 489 return 0; 490 491 if (ISA_DIRECT_CONFIG(ia)) 492 return 0; 493 494 iot = ia->ia_iot; 495 496 if (ia->ia_io[0].ir_addr == ISA_UNKNOWN_PORT) 497 return 0; 498 499 if (bus_space_map(iot, ia->ia_io[0].ir_addr, 500 IX_IOSIZE, 0, &ioh) != 0) { 501 DPRINTF(("Can't map io space at 0x%x\n", 502 ia->ia_io[0].ir_addr)); 503 return 0; 504 } 505 506 /* XXX: reset any ee16 at the current iobase */ 507 bus_space_write_1(iot, ioh, IX_ECTRL, IX_RESET_ASIC); 508 bus_space_write_1(iot, ioh, IX_ECTRL, 0); 509 delay(240); 510 511 /* Now look for ee16. */ 512 board_id = id_var1 = id_var2 = 0; 513 for (i = 0; i < 4 ; i++) { 514 id_var1 = bus_space_read_1(iot, ioh, IX_ID_PORT); 515 id_var2 = ((id_var1 & 0x03) << 2); 516 board_id |= (( id_var1 >> 4) << id_var2); 517 } 518 519 if (board_id != IX_ID) { 520 DPRINTF(("BART ID mismatch (got 0x%04x, expected 0x%04x)\n", 521 board_id, IX_ID)); 522 goto out; 523 } 524 525 /* 526 * The shared RAM size and location of the EE16 is encoded into 527 * EEPROM location 6. The location of the first set bit tells us 528 * the memory address (0xc0000 + (0x4000 * FSB)), where FSB is the 529 * number of the first set bit. The zeroes are then shifted out, 530 * and the results is the memory size (1 = 16k, 3 = 32k, 7 = 48k, 531 * 0x0f = 64k). 532 * 533 * Examples: 534 * 0x3c -> 64k@0xc8000, 0x70 -> 48k@0xd0000, 0xc0 -> 32k@0xd8000 535 * 0x80 -> 16k@0xdc000. 536 * 537 * Side note: this comes from reading the old driver rather than 538 * from a more definitive source, so it could be out-of-whack 539 * with what the card can do... 540 */ 541 542 val = ix_read_eeprom(iot, ioh, 6) & 0xff; 543 for (pg = 0; pg < 8; pg++) { 544 if (val & 1) 545 break; 546 val >>= 1; 547 } 548 549 maddr = 0xc0000 + (pg * 0x4000); 550 551 switch (val) { 552 case 0x00: 553 maddr = 0; 554 msiz = 0; 555 break; 556 557 case 0x01: 558 msiz = 16 * 1024; 559 break; 560 561 case 0x03: 562 msiz = 32 * 1024; 563 break; 564 565 case 0x07: 566 msiz = 48 * 1024; 567 break; 568 569 case 0x0f: 570 msiz = 64 * 1024; 571 break; 572 573 default: 574 DPRINTF(("invalid memory size %02x\n", val)); 575 goto out; 576 } 577 578 if (ia->ia_iomem[0].ir_addr != ISA_UNKNOWN_IOMEM && 579 ia->ia_iomem[0].ir_addr != maddr) { 580 DPRINTF(( 581 "ix_match: memaddr of board @ 0x%x doesn't match config\n", 582 ia->ia_iomem[0].ir_addr)); 583 goto out; 584 } 585 586 if (ia->ia_iomem[0].ir_size != ISA_UNKNOWN_IOSIZ && 587 ia->ia_iomem[0].ir_size != msiz) { 588 DPRINTF(( 589 "ix_match: memsize of board @ 0x%x doesn't match config\n", 590 ia->ia_iomem[0].ir_addr)); 591 goto out; 592 } 593 594 /* Need to put the 586 in RESET, and leave it */ 595 bus_space_write_1(iot, ioh, IX_ECTRL, IX_RESET_586); 596 597 /* Read the eeprom and checksum it, should == IX_ID */ 598 for (i = 0; i < 0x40; i++) 599 checksum += ix_read_eeprom(iot, ioh, i); 600 601 if (checksum != IX_ID) { 602 DPRINTF(("checksum mismatch (got 0x%04x, expected 0x%04x\n", 603 checksum, IX_ID)); 604 goto out; 605 } 606 607 /* 608 * Only do the following bit if using memory-mapped access. For 609 * boards with no mapped memory, we use PIO. We also use PIO for 610 * boards with 16K of mapped memory, as those setups don't seem 611 * to work otherwise. 612 */ 613 if (msiz != 0 && msiz != 16384) { 614 /* Set board up with memory-mapping info */ 615 adjust = IX_MCTRL_FMCS16 | (pg & 0x3) << 2; 616 decode = ((1 << (ia->ia_iomem[0].ir_size / 16384)) - 1) << pg; 617 edecode = ((~decode >> 4) & 0xF0) | (decode >> 8); 618 619 bus_space_write_1(iot, ioh, IX_MEMDEC, decode & 0xFF); 620 bus_space_write_1(iot, ioh, IX_MCTRL, adjust); 621 bus_space_write_1(iot, ioh, IX_MPCTRL, (~decode & 0xFF)); 622 623 /* XXX disable Exxx */ 624 bus_space_write_1(iot, ioh, IX_MECTRL, edecode); 625 } 626 627 /* 628 * Get the encoded interrupt number from the EEPROM, check it 629 * against the passed in IRQ. Issue a warning if they do not 630 * match, and fail the probe. If irq is 'ISA_UNKNOWN_IRQ' then we 631 * use the EEPROM irq, and continue. 632 */ 633 irq_encoded = ix_read_eeprom(iot, ioh, IX_EEPROM_CONFIG1); 634 irq_encoded = (irq_encoded & IX_EEPROM_IRQ) >> IX_EEPROM_IRQ_SHIFT; 635 irq = irq_translate[irq_encoded]; 636 if (ia->ia_irq[0].ir_irq != ISA_UNKNOWN_IRQ && 637 irq != ia->ia_irq[0].ir_irq) { 638 DPRINTF(("board IRQ %d does not match config\n", irq)); 639 goto out; 640 } 641 642 /* Disable the board interrupts */ 643 bus_space_write_1(iot, ioh, IX_IRQ, irq_encoded); 644 645 bart_config = bus_space_read_1(iot, ioh, IX_CONFIG); 646 bart_config |= IX_BART_LOOPBACK; 647 bart_config |= IX_BART_MCS16_TEST; /* inb doesn't get bit! */ 648 bus_space_write_1(iot, ioh, IX_CONFIG, bart_config); 649 bart_config = bus_space_read_1(iot, ioh, IX_CONFIG); 650 651 bus_space_write_1(iot, ioh, IX_ECTRL, 0); 652 delay(100); 653 654 rv = 1; 655 656 ia->ia_nio = 1; 657 ia->ia_io[0].ir_size = IX_IOSIZE; 658 659 ia->ia_niomem = 1; 660 ia->ia_iomem[0].ir_addr = maddr; 661 ia->ia_iomem[0].ir_size = msiz; 662 663 ia->ia_nirq = 1; 664 ia->ia_irq[0].ir_irq = irq; 665 666 DPRINTF(("ix_match: found board @ 0x%x\n", ia->ia_iomem[0].ir_addr)); 667 668 out: 669 bus_space_unmap(iot, ioh, IX_IOSIZE); 670 return rv; 671 } 672 673 static void 674 ix_attach(device_t parent, device_t self, void *aux) 675 { 676 struct ix_softc *isc = device_private(self); 677 struct ie_softc *sc = &isc->sc_ie; 678 struct isa_attach_args *ia = aux; 679 680 int media; 681 int i, memsize; 682 uint8_t bart_config; 683 bus_space_tag_t iot; 684 uint8_t bpat, bval; 685 uint16_t wpat, wval; 686 bus_space_handle_t ioh, memh; 687 uint16_t irq_encoded; 688 uint8_t ethaddr[ETHER_ADDR_LEN]; 689 690 sc->sc_dev = self; 691 iot = ia->ia_iot; 692 693 /* 694 * Shared memory access seems to fail on 16K mapped boards, so 695 * disable shared memory access if the board is in 16K mode. If 696 * no memory is mapped, we have no choice but to use PIO 697 */ 698 isc->use_pio = (ia->ia_iomem[0].ir_size <= (16 * 1024)); 699 700 if (bus_space_map(iot, ia->ia_io[0].ir_addr, 701 ia->ia_io[0].ir_size, 0, &ioh) != 0) { 702 703 DPRINTF(("\n%s: can't map i/o space 0x%x-0x%x\n", 704 device_xname(self), ia->ia_io[0].ir_addr, 705 ia->ia_io[0].ir_addr + ia->ia_io[0].ir_size - 1)); 706 return; 707 } 708 709 /* We map memory even if using PIO so something else doesn't grab it */ 710 if (ia->ia_iomem[0].ir_size) { 711 if (bus_space_map(ia->ia_memt, ia->ia_iomem[0].ir_addr, 712 ia->ia_iomem[0].ir_size, 0, &memh) != 0) { 713 DPRINTF(("\n%s: can't map iomem space 0x%x-0x%x\n", 714 device_xname(self), ia->ia_iomem[0].ir_addr, 715 ia->ia_iomem[0].ir_addr 716 + ia->ia_iomem[0].ir_size - 1)); 717 bus_space_unmap(iot, ioh, ia->ia_io[0].ir_size); 718 return; 719 } 720 } 721 722 isc->sc_regt = iot; 723 isc->sc_regh = ioh; 724 725 /* 726 * Get the hardware ethernet address from the EEPROM and 727 * save it in the softc for use by the 586 setup code. 728 */ 729 wval = ix_read_eeprom(iot, ioh, IX_EEPROM_ENET_HIGH); 730 ethaddr[1] = wval & 0xFF; 731 ethaddr[0] = wval >> 8; 732 wval = ix_read_eeprom(iot, ioh, IX_EEPROM_ENET_MID); 733 ethaddr[3] = wval & 0xFF; 734 ethaddr[2] = wval >> 8; 735 wval = ix_read_eeprom(iot, ioh, IX_EEPROM_ENET_LOW); 736 ethaddr[5] = wval & 0xFF; 737 ethaddr[4] = wval >> 8; 738 739 sc->hwinit = NULL; 740 sc->hwreset = ix_reset; 741 sc->chan_attn = ix_atten; 742 sc->intrhook = ix_intrhook; 743 744 sc->memcopyin = ix_copyin; 745 sc->memcopyout = ix_copyout; 746 747 /* If using PIO, make sure to setup single-byte read/write functions */ 748 if (isc->use_pio) { 749 sc->ie_bus_barrier = ix_bus_barrier; 750 } else { 751 sc->ie_bus_barrier = NULL; 752 } 753 754 sc->ie_bus_read16 = ix_read_16; 755 sc->ie_bus_write16 = ix_write_16; 756 sc->ie_bus_write24 = ix_write_24; 757 758 sc->do_xmitnopchain = 0; 759 760 sc->sc_mediachange = NULL; 761 sc->sc_mediastatus = ix_mediastatus; 762 763 if (isc->use_pio) { 764 sc->bt = iot; 765 sc->bh = ioh; 766 767 /* 768 * If using PIO, the memory size is bounded by on-card memory, 769 * not by how much is mapped into the memory-mapped region, so 770 * determine how much total memory we have to play with here. 771 */ 772 for (memsize = 64 * 1024; memsize; memsize -= 16 * 1024) { 773 /* warm up shared memory, the zero it all out */ 774 ix_zeromem(sc, 0, 32); 775 ix_zeromem(sc, 0, memsize); 776 777 /* Reset write pointer to the start of RAM */ 778 bus_space_write_2(iot, ioh, IX_WRITEPTR, 0); 779 bus_space_barrier(iot, ioh, IX_WRITEPTR, 2, 780 BUS_SPACE_BARRIER_WRITE); 781 782 /* Write test pattern */ 783 for (i = 0, wpat = 1; i < memsize; i += 2) { 784 bus_space_write_2(iot, ioh, IX_DATAPORT, wpat); 785 wpat += 3; 786 } 787 788 /* Flush all reads & writes to data port */ 789 bus_space_barrier(iot, ioh, IX_DATAPORT, 2, 790 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 791 792 /* Reset read pointer to beginning of card RAM */ 793 bus_space_write_2(iot, ioh, IX_READPTR, 0); 794 bus_space_barrier(iot, ioh, IX_READPTR, 2, 795 BUS_SPACE_BARRIER_WRITE); 796 797 /* Read and verify test pattern */ 798 for (i = 0, wpat = 1; i < memsize; i += 2) { 799 wval = bus_space_read_2(iot, ioh, IX_DATAPORT); 800 801 if (wval != wpat) 802 break; 803 804 wpat += 3; 805 } 806 807 /* If we failed, try next size down */ 808 if (i != memsize) 809 continue; 810 811 /* Now try it all with byte reads/writes */ 812 ix_zeromem(sc, 0, 32); 813 ix_zeromem(sc, 0, memsize); 814 815 /* Reset write pointer to start of card RAM */ 816 bus_space_write_2(iot, ioh, IX_WRITEPTR, 0); 817 bus_space_barrier(iot, ioh, IX_WRITEPTR, 2, 818 BUS_SPACE_BARRIER_WRITE); 819 820 /* Write out test pattern */ 821 for (i = 0, bpat = 1; i < memsize; i++) { 822 bus_space_write_1(iot, ioh, IX_DATAPORT, bpat); 823 bpat += 3; 824 } 825 826 /* Flush all reads & writes to data port */ 827 bus_space_barrier(iot, ioh, IX_DATAPORT, 2, 828 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 829 830 /* Reset read pointer to beginning of card RAM */ 831 bus_space_write_2(iot, ioh, IX_READPTR, 0); 832 bus_space_barrier(iot, ioh, IX_READPTR, 2, 833 BUS_SPACE_BARRIER_WRITE); 834 835 /* Read and verify test pattern */ 836 for (i = 0, bpat = 1; i < memsize; i++) { 837 bval = bus_space_read_1(iot, ioh, IX_DATAPORT); 838 839 if (bval != bpat) 840 bpat += 3; 841 } 842 843 /* If we got through all of memory, we're done! */ 844 if (i == memsize) 845 break; 846 } 847 848 /* Memory tests failed, punt... */ 849 if (memsize == 0) { 850 DPRINTF(("\n%s: can't determine size of on-card RAM\n", 851 device_xname(self))); 852 bus_space_unmap(iot, ioh, ia->ia_io[0].ir_size); 853 return; 854 } 855 856 sc->bt = iot; 857 sc->bh = ioh; 858 859 sc->sc_msize = memsize; 860 sc->sc_maddr = (void*)0; 861 } else { 862 sc->bt = ia->ia_memt; 863 sc->bh = memh; 864 865 sc->sc_msize = ia->ia_iomem[0].ir_size; 866 sc->sc_maddr = (void *)memh; 867 } 868 869 /* Map i/o space. */ 870 sc->sc_iobase = (char *)sc->sc_maddr + sc->sc_msize - (1 << 24); 871 872 /* Set up pointers to important on-card control structures */ 873 sc->iscp = 0; 874 sc->scb = IE_ISCP_SZ; 875 sc->scp = sc->sc_msize + IE_SCP_ADDR - (1 << 24); 876 877 sc->buf_area = sc->scb + IE_SCB_SZ; 878 sc->buf_area_sz = sc->sc_msize - IE_ISCP_SZ - IE_SCB_SZ - IE_SCP_SZ; 879 880 /* Zero card memory */ 881 ix_zeromem(sc, 0, 32); 882 ix_zeromem(sc, 0, sc->sc_msize); 883 884 /* Set card to 16-bit bus mode */ 885 if (isc->use_pio) { 886 bus_space_write_2(sc->bt, sc->bh, IX_WRITEPTR, 887 IE_SCP_BUS_USE((u_long)sc->scp)); 888 bus_space_barrier(sc->bt, sc->bh, IX_WRITEPTR, 2, 889 BUS_SPACE_BARRIER_WRITE); 890 891 bus_space_write_1(sc->bt, sc->bh, IX_DATAPORT, 892 IE_SYSBUS_16BIT); 893 } else 894 bus_space_write_1(sc->bt, sc->bh, 895 IE_SCP_BUS_USE((u_long)sc->scp), IE_SYSBUS_16BIT); 896 897 /* Set up pointers to key structures */ 898 ix_write_24(sc, IE_SCP_ISCP((u_long)sc->scp), (u_long)sc->iscp); 899 ix_write_16(sc, IE_ISCP_SCB((u_long)sc->iscp), (u_long)sc->scb); 900 ix_write_24(sc, IE_ISCP_BASE((u_long)sc->iscp), (u_long)sc->iscp); 901 902 /* Flush setup of pointers, check if chip answers */ 903 if (isc->use_pio) { 904 bus_space_barrier(sc->bt, sc->bh, 0, IX_IOSIZE, 905 BUS_SPACE_BARRIER_WRITE); 906 } else 907 bus_space_barrier(sc->bt, sc->bh, 0, sc->sc_msize, 908 BUS_SPACE_BARRIER_WRITE); 909 910 if (!i82586_proberam(sc)) { 911 DPRINTF(("\n%s: Can't talk to i82586!\n", 912 device_xname(self))); 913 bus_space_unmap(iot, ioh, ia->ia_io[0].ir_size); 914 915 if (ia->ia_iomem[0].ir_size) 916 bus_space_unmap(ia->ia_memt, memh, 917 ia->ia_iomem[0].ir_size); 918 return; 919 } 920 921 /* Figure out which media is being used... */ 922 if (ix_read_eeprom(iot, ioh, IX_EEPROM_CONFIG1) & 923 IX_EEPROM_MEDIA_EXT) { 924 if (ix_read_eeprom(iot, ioh, IX_EEPROM_MEDIA) & 925 IX_EEPROM_MEDIA_TP) 926 media = IFM_ETHER | IFM_10_T; 927 else 928 media = IFM_ETHER | IFM_10_2; 929 } else 930 media = IFM_ETHER | IFM_10_5; 931 932 /* Take the card out of lookback */ 933 bart_config = bus_space_read_1(iot, ioh, IX_CONFIG); 934 bart_config &= ~IX_BART_LOOPBACK; 935 bart_config |= IX_BART_MCS16_TEST; /* inb doesn't get bit! */ 936 bus_space_write_1(iot, ioh, IX_CONFIG, bart_config); 937 bart_config = bus_space_read_1(iot, ioh, IX_CONFIG); 938 939 irq_encoded = ix_read_eeprom(iot, ioh, IX_EEPROM_CONFIG1); 940 irq_encoded = (irq_encoded & IX_EEPROM_IRQ) >> IX_EEPROM_IRQ_SHIFT; 941 942 /* Enable interrupts */ 943 bus_space_write_1(iot, ioh, IX_IRQ, irq_encoded | IX_IRQ_ENABLE); 944 945 /* Flush all writes to registers */ 946 bus_space_barrier(iot, ioh, 0, ia->ia_io[0].ir_size, 947 BUS_SPACE_BARRIER_WRITE); 948 949 isc->irq_encoded = irq_encoded; 950 951 i82586_attach(sc, "EtherExpress/16", ethaddr, 952 ix_media, NIX_MEDIA, media); 953 954 if (isc->use_pio) 955 aprint_error_dev(self, "unsupported memory config, using PIO " 956 "to access %d bytes of memory\n", sc->sc_msize); 957 958 isc->sc_ih = isa_intr_establish(ia->ia_ic, ia->ia_irq[0].ir_irq, 959 IST_EDGE, IPL_NET, i82586_intr, sc); 960 if (isc->sc_ih == NULL) { 961 DPRINTF(("\n%s: can't establish interrupt\n", 962 device_xname(self))); 963 } 964 } 965 966 CFATTACH_DECL_NEW(ix, sizeof(struct ix_softc), 967 ix_match, ix_attach, NULL, NULL); 968