1 /* $NetBSD: i82365_isasubr.c,v 1.48 2012/10/27 17:18:24 chs Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Christian E. Hopps. All rights reserved. 5 * Copyright (c) 1998 Bill Sommerfeld. All rights reserved. 6 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Marc Horowitz. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: i82365_isasubr.c,v 1.48 2012/10/27 17:18:24 chs Exp $"); 36 37 #define PCICISADEBUG 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <sys/extent.h> 43 #include <sys/malloc.h> 44 45 #include <sys/bus.h> 46 #include <sys/intr.h> 47 48 #include <dev/isa/isareg.h> 49 #include <dev/isa/isavar.h> 50 51 #include <dev/pcmcia/pcmciareg.h> 52 #include <dev/pcmcia/pcmciavar.h> 53 #include <dev/pcmcia/pcmciachip.h> 54 55 #include <dev/ic/i82365reg.h> 56 #include <dev/ic/i82365var.h> 57 #include <dev/isa/i82365_isavar.h> 58 59 /***************************************************************************** 60 * Configurable parameters. 61 *****************************************************************************/ 62 63 #include "opt_pcic_isa_alloc_iobase.h" 64 #include "opt_pcic_isa_alloc_iosize.h" 65 #include "opt_pcic_isa_intr_alloc_mask.h" 66 67 /* 68 * Default I/O allocation range. If both are set to non-zero, these 69 * values will be used instead. Otherwise, the code attempts to probe 70 * the bus width. Systems with 10 address bits should use 0x300 and 0xff. 71 * Systems with 12 address bits (most) should use 0x400 and 0xbff. 72 */ 73 74 #ifndef PCIC_ISA_ALLOC_IOBASE 75 #define PCIC_ISA_ALLOC_IOBASE 0 76 #endif 77 78 #ifndef PCIC_ISA_ALLOC_IOSIZE 79 #define PCIC_ISA_ALLOC_IOSIZE 0 80 #endif 81 82 int pcic_isa_alloc_iobase = PCIC_ISA_ALLOC_IOBASE; 83 int pcic_isa_alloc_iosize = PCIC_ISA_ALLOC_IOSIZE; 84 85 86 /* 87 * Default IRQ allocation bitmask. This defines the range of allowable 88 * IRQs for PCMCIA slots. Useful if order of probing would screw up other 89 * devices, or if PCIC hardware/cards have trouble with certain interrupt 90 * lines. 91 */ 92 93 #ifndef PCIC_ISA_INTR_ALLOC_MASK 94 #define PCIC_ISA_INTR_ALLOC_MASK 0xffff 95 #endif 96 97 int pcic_isa_intr_alloc_mask = PCIC_ISA_INTR_ALLOC_MASK; 98 99 #ifndef PCIC_IRQ_PROBE 100 #ifdef hpcmips 101 /* 102 * The irq probing doesn't work with current vrisab implementation. 103 * The irq is just an key to find matching GPIO port to use and is fixed. 104 */ 105 #define PCIC_IRQ_PROBE 0 106 #else 107 #define PCIC_IRQ_PROBE 1 108 #endif 109 #endif 110 111 int pcic_irq_probe = PCIC_IRQ_PROBE; 112 113 /***************************************************************************** 114 * End of configurable parameters. 115 *****************************************************************************/ 116 117 #ifdef PCICISADEBUG 118 int pcicsubr_debug = 0; 119 #define DPRINTF(arg) do { if (pcicsubr_debug) printf arg ; } while (0) 120 #else 121 #define DPRINTF(arg) 122 #endif 123 124 /* 125 * count the interrupt if we have a status set 126 * just use socket 0 127 */ 128 129 void pcic_isa_probe_interrupts(struct pcic_isa_softc *, struct pcic_handle *); 130 static int pcic_isa_count_intr(void *); 131 132 static int 133 pcic_isa_count_intr(void *arg) 134 { 135 struct pcic_softc *sc; 136 struct pcic_isa_softc *isc; 137 struct pcic_handle *h; 138 int cscreg; 139 140 h = arg; 141 isc = device_private(h->ph_parent); 142 sc = &isc->sc_pcic; 143 144 cscreg = pcic_read(h, PCIC_CSC); 145 if (cscreg & PCIC_CSC_CD) { 146 if ((++sc->intr_detect % 20) == 0) 147 printf("."); 148 else 149 DPRINTF((".")); 150 return 1; 151 } 152 153 /* 154 * make sure we don't get stuck in a loop due to 155 * unhandled level interrupts 156 */ 157 if (++sc->intr_false > 40) { 158 pcic_write(h, PCIC_CSC_INTR, 0); 159 delay(10); 160 } 161 162 #ifdef PCICISADEBUG 163 if (cscreg) 164 DPRINTF(("o")); 165 else 166 DPRINTF(("X")); 167 #endif 168 return cscreg ? 1 : 0; 169 } 170 171 /* 172 * use soft interrupt card detect to find out which irqs are available 173 * for this controller 174 */ 175 void 176 pcic_isa_probe_interrupts(struct pcic_isa_softc *isc, struct pcic_handle *h) 177 { 178 struct pcic_softc *sc = &isc->sc_pcic; 179 isa_chipset_tag_t ic; 180 int i, j, mask, irq; 181 int cd, cscintr, intr, csc; 182 183 ic = isc->sc_ic; 184 185 printf("%s: controller %d detecting irqs with mask 0x%04x:", 186 device_xname(sc->dev), h->chip, sc->intr_mask[h->chip]); 187 DPRINTF(("\n")); 188 189 /* clear any current interrupt */ 190 pcic_read(h, PCIC_CSC); 191 192 /* first disable the status irq, card detect is enabled later */ 193 pcic_write(h, PCIC_CSC_INTR, 0); 194 195 /* steer the interrupt to isa and disable ring and interrupt */ 196 intr = pcic_read(h, PCIC_INTR); 197 DPRINTF(("pcic: old intr 0x%x\n", intr)); 198 intr &= ~(PCIC_INTR_RI_ENABLE | PCIC_INTR_ENABLE | PCIC_INTR_IRQ_MASK); 199 pcic_write(h, PCIC_INTR, intr); 200 201 202 /* clear any current interrupt */ 203 pcic_read(h, PCIC_CSC); 204 205 cd = pcic_read(h, PCIC_CARD_DETECT); 206 cd |= PCIC_CARD_DETECT_SW_INTR; 207 208 mask = 0; 209 for (i = 0; i < 16; i++) { 210 /* honor configured limitations */ 211 if ((sc->intr_mask[h->chip] & (1 << i)) == 0) 212 continue; 213 214 DPRINTF(("probing irq %d: ", i)); 215 216 /* ask for a pulse interrupt so we don't share */ 217 if (isa_intr_alloc(ic, (1 << i), IST_PULSE, &irq)) { 218 DPRINTF(("currently allocated\n")); 219 continue; 220 } 221 222 cscintr = PCIC_CSC_INTR_CD_ENABLE; 223 cscintr |= (irq << PCIC_CSC_INTR_IRQ_SHIFT); 224 pcic_write(h, PCIC_CSC_INTR, cscintr); 225 delay(10); 226 227 /* Clear any pending interrupt. */ 228 (void) pcic_read(h, PCIC_CSC); 229 230 if ((sc->ih = isa_intr_establish(ic, irq, IST_EDGE, IPL_TTY, 231 pcic_isa_count_intr, h)) == NULL) 232 panic("cant get interrupt"); 233 234 /* interrupt 40 times */ 235 sc->intr_detect = 0; 236 for (j = 0; j < 40 && sc->ih; j++) { 237 sc->intr_false = 0; 238 pcic_write(h, PCIC_CARD_DETECT, cd); 239 delay(100); 240 csc = pcic_read(h, PCIC_CSC); 241 DPRINTF(("%s", csc ? "-" : "")); 242 } 243 DPRINTF((" total %d\n", sc->intr_detect)); 244 /* allow for misses */ 245 if (sc->intr_detect > 37 && sc->intr_detect <= 40) { 246 printf("%d", i); 247 DPRINTF((" succeded\n")); 248 mask |= (1 << i); 249 } 250 251 if (sc->ih != NULL) { 252 isa_intr_disestablish(ic, sc->ih); 253 sc->ih = NULL; 254 255 pcic_write(h, PCIC_CSC_INTR, 0); 256 delay(10); 257 } 258 } 259 sc->intr_mask[h->chip] = mask; 260 261 printf("%s\n", sc->intr_mask[h->chip] ? "" : " none"); 262 } 263 264 /* 265 * called with interrupts enabled, light up the irqs to find out 266 * which irq lines are actually hooked up to our pcic 267 */ 268 void 269 pcic_isa_config_interrupts(device_t self) 270 { 271 struct pcic_softc *sc; 272 struct pcic_isa_softc *isc; 273 struct pcic_handle *h; 274 isa_chipset_tag_t ic; 275 int s, i, chipmask, chipuniq; 276 277 isc = device_private(self); 278 sc = &isc->sc_pcic; 279 ic = isc->sc_ic; 280 281 /* probe each controller */ 282 chipmask = 0xffff; 283 for (i = 0; i < PCIC_NSLOTS; i += 2) { 284 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 285 h = &sc->handle[i]; 286 else if (sc->handle[i + 1].flags & PCIC_FLAG_SOCKETP) 287 h = &sc->handle[i + 1]; 288 else 289 continue; 290 291 sc->intr_mask[h->chip] = 292 PCIC_INTR_IRQ_VALIDMASK & pcic_isa_intr_alloc_mask; 293 294 /* the cirrus chips lack support for the soft interrupt */ 295 if (pcic_irq_probe != 0 && 296 h->vendor != PCIC_VENDOR_CIRRUS_PD67XX) 297 pcic_isa_probe_interrupts(isc, h); 298 299 chipmask &= sc->intr_mask[h->chip]; 300 } 301 /* now see if there is at least one irq per chip not shared by all */ 302 chipuniq = 1; 303 for (i = 0; i < PCIC_NSLOTS; i += 2) { 304 if ((sc->handle[i].flags & PCIC_FLAG_SOCKETP) == 0 && 305 (sc->handle[i + 1].flags & PCIC_FLAG_SOCKETP) == 0) 306 continue; 307 if ((sc->intr_mask[i / 2] & ~chipmask) == 0) { 308 chipuniq = 0; 309 break; 310 } 311 } 312 /* 313 * the rest of the following code used to run at config time with 314 * no interrupts and gets unhappy if this is violated so... 315 */ 316 s = splhigh(); 317 318 /* 319 * allocate our irq. it will be used by both controllers. I could 320 * use two different interrupts, but interrupts are relatively 321 * scarce, shareable, and for PCIC controllers, very infrequent. 322 */ 323 if ((device_cfdata(self)->cf_flags & 1) == 0) { 324 if (sc->irq != ISA_UNKNOWN_IRQ) { 325 if ((chipmask & (1 << sc->irq)) == 0) 326 printf("%s: warning: configured irq %d not " 327 "detected as available\n", 328 device_xname(self), sc->irq); 329 } else if (chipmask == 0 || 330 isa_intr_alloc(ic, chipmask, IST_EDGE, &sc->irq)) { 331 aprint_error_dev(self, "no available irq; "); 332 sc->irq = ISA_UNKNOWN_IRQ; 333 } else if ((chipmask & ~(1 << sc->irq)) == 0 && chipuniq == 0) { 334 aprint_error_dev(self, "can't share irq with cards; "); 335 sc->irq = ISA_UNKNOWN_IRQ; 336 } 337 } else { 338 printf("%s: ", device_xname(self)); 339 sc->irq = ISA_UNKNOWN_IRQ; 340 } 341 342 if (sc->irq != ISA_UNKNOWN_IRQ) { 343 sc->ih = isa_intr_establish(ic, sc->irq, IST_EDGE, IPL_TTY, 344 pcic_intr, sc); 345 if (sc->ih == NULL) { 346 aprint_error_dev(self, "can't establish interrupt"); 347 sc->irq = ISA_UNKNOWN_IRQ; 348 } 349 } 350 if (sc->irq == ISA_UNKNOWN_IRQ) 351 printf("polling for socket events\n"); 352 else 353 printf("%s: using irq %d for socket events\n", 354 device_xname(self), sc->irq); 355 356 pcic_attach_sockets_finish(sc); 357 358 splx(s); 359 } 360 361 /* 362 * XXX This routine does not deal with the aliasing issue that its 363 * trying to. 364 * 365 * Any isa device may be decoding only 10 bits of address including 366 * the pcic. This routine only detects if the pcic is doing 10 bits. 367 * 368 * What should be done is detect the pcic's idea of the bus width, 369 * and then within those limits allocate a sparse map, where the 370 * each sub region is offset by 0x400. 371 */ 372 void pcic_isa_bus_width_probe(struct pcic_softc *sc, bus_space_tag_t iot, 373 bus_space_handle_t ioh, bus_addr_t base, uint32_t length) 374 { 375 bus_space_handle_t ioh_high; 376 int i, iobuswidth, tmp1, tmp2; 377 378 /* 379 * figure out how wide the isa bus is. Do this by checking if the 380 * pcic controller is mirrored 0x400 above where we expect it to be. 381 */ 382 383 iobuswidth = 12; 384 385 /* Map i/o space. */ 386 if (bus_space_map(iot, base + 0x400, length, 0, &ioh_high)) { 387 aprint_error_dev(sc->dev, "can't map high i/o space\n"); 388 return; 389 } 390 391 for (i = 0; i < PCIC_NSLOTS; i++) { 392 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) { 393 /* 394 * read the ident flags from the normal space and 395 * from the mirror, and compare them 396 */ 397 398 bus_space_write_1(iot, ioh, PCIC_REG_INDEX, 399 sc->handle[i].sock + PCIC_IDENT); 400 tmp1 = bus_space_read_1(iot, ioh, PCIC_REG_DATA); 401 402 bus_space_write_1(iot, ioh_high, PCIC_REG_INDEX, 403 sc->handle[i].sock + PCIC_IDENT); 404 tmp2 = bus_space_read_1(iot, ioh_high, PCIC_REG_DATA); 405 406 if (tmp1 == tmp2) 407 iobuswidth = 10; 408 } 409 } 410 411 bus_space_free(iot, ioh_high, length); 412 413 /* 414 * XXX some hardware doesn't seem to grok addresses in 0x400 range-- 415 * apparently missing a bit or more of address lines. (e.g. 416 * CIRRUS_PD672X with Linksys EthernetCard ne2000 clone in TI 417 * TravelMate 5000--not clear which is at fault) 418 * 419 * Add a kludge to detect 10 bit wide buses and deal with them, 420 * and also a config file option to override the probe. 421 */ 422 423 if (iobuswidth == 10) { 424 sc->iobase = 0x300; 425 sc->iosize = 0x0ff; 426 } else { 427 sc->iobase = 0x400; 428 sc->iosize = 0xbff; 429 } 430 431 DPRINTF(("%s: bus_space_alloc range 0x%04lx-0x%04lx (probed)\n", 432 device_xname(sc->dev), (long) sc->iobase, 433 (long)(sc->iobase + sc->iosize))); 434 435 if (pcic_isa_alloc_iobase && pcic_isa_alloc_iosize) { 436 sc->iobase = pcic_isa_alloc_iobase; 437 sc->iosize = pcic_isa_alloc_iosize; 438 439 DPRINTF(("%s: bus_space_alloc range 0x%04lx-0x%04lx " 440 "(config override)\n", device_xname(sc->dev), 441 (long) sc->iobase, (long)(sc->iobase + sc->iosize))); 442 } 443 } 444 445 void * 446 pcic_isa_chip_intr_establish(pcmcia_chipset_handle_t pch, 447 struct pcmcia_function *pf, int ipl, int (*fct)(void *), void *arg) 448 { 449 struct pcic_handle *h = (struct pcic_handle *) pch; 450 struct pcic_isa_softc *isc = device_private(h->ph_parent); 451 struct pcic_softc *sc = &isc->sc_pcic; 452 isa_chipset_tag_t ic = isc->sc_ic; 453 int irq, ist; 454 void *ih; 455 int reg; 456 457 /* 458 * PLEASE NOTE: 459 * The IRQLEVEL bit has no bearing on what happens on the host side of 460 * the PCMCIA controller. ISA interrupts are defined to be edge- 461 * triggered, and as this attachment is for ISA devices, the interrupt 462 * *must* be configured for edge-trigger. If you think you should 463 * change this to use IST_LEVEL, you are *wrong*. You should figure 464 * out what your real problem is and leave this code alone rather than 465 * breaking everyone else's systems. - mycroft 466 */ 467 if (pf->cfe->flags & PCMCIA_CFE_IRQLEVEL) 468 ist = IST_EDGE; /* SEE COMMENT ABOVE */ 469 else if (pf->cfe->flags & PCMCIA_CFE_IRQPULSE) 470 ist = IST_PULSE; /* SEE COMMENT ABOVE */ 471 else 472 ist = IST_EDGE; /* SEE COMMENT ABOVE */ 473 474 if (isa_intr_alloc(ic, sc->intr_mask[h->chip], ist, &irq)) 475 return NULL; 476 477 h->ih_irq = irq; 478 if (h->flags & PCIC_FLAG_ENABLED) { 479 reg = pcic_read(h, PCIC_INTR); 480 reg &= ~PCIC_INTR_IRQ_MASK; 481 pcic_write(h, PCIC_INTR, reg | irq); 482 } 483 484 if ((ih = isa_intr_establish(ic, irq, ist, ipl, fct, arg)) == NULL) 485 return NULL; 486 487 printf("%s: card irq %d\n", device_xname(h->pcmcia), irq); 488 489 return ih; 490 } 491 492 void 493 pcic_isa_chip_intr_disestablish(pcmcia_chipset_handle_t pch, void *ih) 494 { 495 struct pcic_handle *h = (struct pcic_handle *) pch; 496 struct pcic_isa_softc *isc = device_private(h->ph_parent); 497 isa_chipset_tag_t ic = isc->sc_ic; 498 int reg; 499 500 isa_intr_disestablish(ic, ih); 501 502 h->ih_irq = 0; 503 if (h->flags & PCIC_FLAG_ENABLED) { 504 reg = pcic_read(h, PCIC_INTR); 505 reg &= ~PCIC_INTR_IRQ_MASK; 506 pcic_write(h, PCIC_INTR, reg); 507 } 508 } 509