1 /* $NetBSD: i82365_isasubr.c,v 1.39 2007/10/19 12:00:17 ad Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Christian E. Hopps. All rights reserved. 5 * Copyright (c) 1998 Bill Sommerfeld. All rights reserved. 6 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Marc Horowitz. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: i82365_isasubr.c,v 1.39 2007/10/19 12:00:17 ad Exp $"); 36 37 #define PCICISADEBUG 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <sys/extent.h> 43 #include <sys/malloc.h> 44 45 #include <sys/bus.h> 46 #include <sys/intr.h> 47 48 #include <dev/isa/isareg.h> 49 #include <dev/isa/isavar.h> 50 51 #include <dev/pcmcia/pcmciareg.h> 52 #include <dev/pcmcia/pcmciavar.h> 53 #include <dev/pcmcia/pcmciachip.h> 54 55 #include <dev/ic/i82365reg.h> 56 #include <dev/ic/i82365var.h> 57 #include <dev/isa/i82365_isavar.h> 58 59 /***************************************************************************** 60 * Configurable parameters. 61 *****************************************************************************/ 62 63 #include "opt_pcic_isa_alloc_iobase.h" 64 #include "opt_pcic_isa_alloc_iosize.h" 65 #include "opt_pcic_isa_intr_alloc_mask.h" 66 67 /* 68 * Default I/O allocation range. If both are set to non-zero, these 69 * values will be used instead. Otherwise, the code attempts to probe 70 * the bus width. Systems with 10 address bits should use 0x300 and 0xff. 71 * Systems with 12 address bits (most) should use 0x400 and 0xbff. 72 */ 73 74 #ifndef PCIC_ISA_ALLOC_IOBASE 75 #define PCIC_ISA_ALLOC_IOBASE 0 76 #endif 77 78 #ifndef PCIC_ISA_ALLOC_IOSIZE 79 #define PCIC_ISA_ALLOC_IOSIZE 0 80 #endif 81 82 int pcic_isa_alloc_iobase = PCIC_ISA_ALLOC_IOBASE; 83 int pcic_isa_alloc_iosize = PCIC_ISA_ALLOC_IOSIZE; 84 85 86 /* 87 * Default IRQ allocation bitmask. This defines the range of allowable 88 * IRQs for PCMCIA slots. Useful if order of probing would screw up other 89 * devices, or if PCIC hardware/cards have trouble with certain interrupt 90 * lines. 91 */ 92 93 #ifndef PCIC_ISA_INTR_ALLOC_MASK 94 #define PCIC_ISA_INTR_ALLOC_MASK 0xffff 95 #endif 96 97 int pcic_isa_intr_alloc_mask = PCIC_ISA_INTR_ALLOC_MASK; 98 99 #ifndef PCIC_IRQ_PROBE 100 #ifdef hpcmips 101 /* 102 * The irq probing doesn't work with current vrisab implementation. 103 * The irq is just an key to find matching GPIO port to use and is fixed. 104 */ 105 #define PCIC_IRQ_PROBE 0 106 #else 107 #define PCIC_IRQ_PROBE 1 108 #endif 109 #endif 110 111 int pcic_irq_probe = PCIC_IRQ_PROBE; 112 113 /***************************************************************************** 114 * End of configurable parameters. 115 *****************************************************************************/ 116 117 #ifdef PCICISADEBUG 118 int pcicsubr_debug = 0; 119 #define DPRINTF(arg) do { if (pcicsubr_debug) printf arg ; } while (0) 120 #else 121 #define DPRINTF(arg) 122 #endif 123 124 /* 125 * count the interrupt if we have a status set 126 * just use socket 0 127 */ 128 129 void pcic_isa_probe_interrupts(struct pcic_softc *, struct pcic_handle *); 130 static int pcic_isa_count_intr(void *); 131 132 static int 133 pcic_isa_count_intr(arg) 134 void *arg; 135 { 136 struct pcic_softc *sc; 137 struct pcic_isa_softc *isc; 138 struct pcic_handle *h; 139 int cscreg; 140 141 h = arg; 142 sc = (struct pcic_softc *)h->ph_parent; 143 isc = (struct pcic_isa_softc *)h->ph_parent; 144 145 cscreg = pcic_read(h, PCIC_CSC); 146 if (cscreg & PCIC_CSC_CD) { 147 if ((++sc->intr_detect % 20) == 0) 148 printf("."); 149 else 150 DPRINTF((".")); 151 return (1); 152 } 153 154 /* 155 * make sure we don't get stuck in a loop due to 156 * unhandled level interrupts 157 */ 158 if (++sc->intr_false > 40) { 159 isa_intr_disestablish(isc->sc_ic, sc->ih); 160 sc->ih = 0; 161 162 pcic_write(h, PCIC_CSC_INTR, 0); 163 delay(10); 164 } 165 166 #ifdef PCICISADEBUG 167 if (cscreg) 168 DPRINTF(("o")); 169 else 170 DPRINTF(("X")); 171 #endif 172 return (cscreg ? 1 : 0); 173 } 174 175 /* 176 * use soft interrupt card detect to find out which irqs are available 177 * for this controller 178 */ 179 void 180 pcic_isa_probe_interrupts(sc, h) 181 struct pcic_softc *sc; 182 struct pcic_handle *h; 183 { 184 struct pcic_isa_softc *isc = (void *) sc; 185 isa_chipset_tag_t ic; 186 int i, j, mask, irq; 187 int cd, cscintr, intr, csc; 188 189 ic = isc->sc_ic; 190 191 printf("%s: controller %d detecting irqs with mask 0x%04x:", 192 sc->dev.dv_xname, h->chip, sc->intr_mask[h->chip]); 193 DPRINTF(("\n")); 194 195 /* clear any current interrupt */ 196 pcic_read(h, PCIC_CSC); 197 198 /* first disable the status irq, card detect is enabled later */ 199 pcic_write(h, PCIC_CSC_INTR, 0); 200 201 /* steer the interrupt to isa and disable ring and interrupt */ 202 intr = pcic_read(h, PCIC_INTR); 203 DPRINTF(("pcic: old intr 0x%x\n", intr)); 204 intr &= ~(PCIC_INTR_RI_ENABLE | PCIC_INTR_ENABLE | PCIC_INTR_IRQ_MASK); 205 pcic_write(h, PCIC_INTR, intr); 206 207 208 /* clear any current interrupt */ 209 pcic_read(h, PCIC_CSC); 210 211 cd = pcic_read(h, PCIC_CARD_DETECT); 212 cd |= PCIC_CARD_DETECT_SW_INTR; 213 214 mask = 0; 215 for (i = 0; i < 16; i++) { 216 /* honor configured limitations */ 217 if ((sc->intr_mask[h->chip] & (1 << i)) == 0) 218 continue; 219 220 DPRINTF(("probing irq %d: ", i)); 221 222 /* ask for a pulse interrupt so we don't share */ 223 if (isa_intr_alloc(ic, (1 << i), IST_PULSE, &irq)) { 224 DPRINTF(("currently allocated\n")); 225 continue; 226 } 227 228 cscintr = PCIC_CSC_INTR_CD_ENABLE; 229 cscintr |= (irq << PCIC_CSC_INTR_IRQ_SHIFT); 230 pcic_write(h, PCIC_CSC_INTR, cscintr); 231 delay(10); 232 233 /* Clear any pending interrupt. */ 234 (void) pcic_read(h, PCIC_CSC); 235 236 if ((sc->ih = isa_intr_establish(ic, irq, IST_EDGE, IPL_TTY, 237 pcic_isa_count_intr, h)) == NULL) 238 panic("cant get interrupt"); 239 240 /* interrupt 40 times */ 241 sc->intr_detect = 0; 242 for (j = 0; j < 40 && sc->ih; j++) { 243 sc->intr_false = 0; 244 pcic_write(h, PCIC_CARD_DETECT, cd); 245 delay(100); 246 csc = pcic_read(h, PCIC_CSC); 247 DPRINTF(("%s", csc ? "-" : "")); 248 } 249 DPRINTF((" total %d\n", sc->intr_detect)); 250 /* allow for misses */ 251 if (sc->intr_detect > 37 && sc->intr_detect <= 40) { 252 printf("%d", i); 253 DPRINTF((" succeded\n")); 254 mask |= (1 << i); 255 } 256 257 if (sc->ih) { 258 isa_intr_disestablish(ic, sc->ih); 259 sc->ih = 0; 260 261 pcic_write(h, PCIC_CSC_INTR, 0); 262 delay(10); 263 } 264 } 265 sc->intr_mask[h->chip] = mask; 266 267 printf("%s\n", sc->intr_mask[h->chip] ? "" : " none"); 268 } 269 270 /* 271 * called with interrupts enabled, light up the irqs to find out 272 * which irq lines are actually hooked up to our pcic 273 */ 274 void 275 pcic_isa_config_interrupts(self) 276 struct device *self; 277 { 278 struct pcic_softc *sc; 279 struct pcic_isa_softc *isc; 280 struct pcic_handle *h; 281 isa_chipset_tag_t ic; 282 int s, i, chipmask, chipuniq; 283 284 sc = (struct pcic_softc *) self; 285 isc = (struct pcic_isa_softc *) self; 286 ic = isc->sc_ic; 287 288 /* probe each controller */ 289 chipmask = 0xffff; 290 for (i = 0; i < PCIC_NSLOTS; i += 2) { 291 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 292 h = &sc->handle[i]; 293 else if (sc->handle[i + 1].flags & PCIC_FLAG_SOCKETP) 294 h = &sc->handle[i + 1]; 295 else 296 continue; 297 298 sc->intr_mask[h->chip] = 299 PCIC_INTR_IRQ_VALIDMASK & pcic_isa_intr_alloc_mask; 300 301 /* the cirrus chips lack support for the soft interrupt */ 302 if (pcic_irq_probe != 0 && 303 h->vendor != PCIC_VENDOR_CIRRUS_PD67XX) 304 pcic_isa_probe_interrupts(sc, h); 305 306 chipmask &= sc->intr_mask[h->chip]; 307 } 308 /* now see if there is at least one irq per chip not shared by all */ 309 chipuniq = 1; 310 for (i = 0; i < PCIC_NSLOTS; i += 2) { 311 if ((sc->handle[i].flags & PCIC_FLAG_SOCKETP) == 0 && 312 (sc->handle[i + 1].flags & PCIC_FLAG_SOCKETP) == 0) 313 continue; 314 if ((sc->intr_mask[i / 2] & ~chipmask) == 0) { 315 chipuniq = 0; 316 break; 317 } 318 } 319 /* 320 * the rest of the following code used to run at config time with 321 * no interrupts and gets unhappy if this is violated so... 322 */ 323 s = splhigh(); 324 325 /* 326 * allocate our irq. it will be used by both controllers. I could 327 * use two different interrupts, but interrupts are relatively 328 * scarce, shareable, and for PCIC controllers, very infrequent. 329 */ 330 if ((device_cfdata(self)->cf_flags & 1) == 0) { 331 if (sc->irq != ISA_UNKNOWN_IRQ) { 332 if ((chipmask & (1 << sc->irq)) == 0) 333 printf("%s: warning: configured irq %d not " 334 "detected as available\n", 335 sc->dev.dv_xname, sc->irq); 336 } else if (chipmask == 0 || 337 isa_intr_alloc(ic, chipmask, IST_EDGE, &sc->irq)) { 338 printf("%s: no available irq; ", sc->dev.dv_xname); 339 sc->irq = ISA_UNKNOWN_IRQ; 340 } else if ((chipmask & ~(1 << sc->irq)) == 0 && chipuniq == 0) { 341 printf("%s: can't share irq with cards; ", 342 sc->dev.dv_xname); 343 sc->irq = ISA_UNKNOWN_IRQ; 344 } 345 } else { 346 printf("%s: ", sc->dev.dv_xname); 347 sc->irq = ISA_UNKNOWN_IRQ; 348 } 349 350 if (sc->irq != ISA_UNKNOWN_IRQ) { 351 sc->ih = isa_intr_establish(ic, sc->irq, IST_EDGE, IPL_TTY, 352 pcic_intr, sc); 353 if (sc->ih == NULL) { 354 printf("%s: can't establish interrupt", 355 sc->dev.dv_xname); 356 sc->irq = ISA_UNKNOWN_IRQ; 357 } 358 } 359 if (sc->irq == ISA_UNKNOWN_IRQ) 360 printf("polling for socket events\n"); 361 else 362 printf("%s: using irq %d for socket events\n", sc->dev.dv_xname, 363 sc->irq); 364 365 pcic_attach_sockets_finish(sc); 366 367 splx(s); 368 } 369 370 /* 371 * XXX This routine does not deal with the aliasing issue that its 372 * trying to. 373 * 374 * Any isa device may be decoding only 10 bits of address including 375 * the pcic. This routine only detects if the pcic is doing 10 bits. 376 * 377 * What should be done is detect the pcic's idea of the bus width, 378 * and then within those limits allocate a sparse map, where the 379 * each sub region is offset by 0x400. 380 */ 381 void pcic_isa_bus_width_probe (sc, iot, ioh, base, length) 382 struct pcic_softc *sc; 383 bus_space_tag_t iot; 384 bus_space_handle_t ioh; 385 bus_addr_t base; 386 u_int32_t length; 387 { 388 bus_space_handle_t ioh_high; 389 int i, iobuswidth, tmp1, tmp2; 390 391 /* 392 * figure out how wide the isa bus is. Do this by checking if the 393 * pcic controller is mirrored 0x400 above where we expect it to be. 394 */ 395 396 iobuswidth = 12; 397 398 /* Map i/o space. */ 399 if (bus_space_map(iot, base + 0x400, length, 0, &ioh_high)) { 400 printf("%s: can't map high i/o space\n", sc->dev.dv_xname); 401 return; 402 } 403 404 for (i = 0; i < PCIC_NSLOTS; i++) { 405 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) { 406 /* 407 * read the ident flags from the normal space and 408 * from the mirror, and compare them 409 */ 410 411 bus_space_write_1(iot, ioh, PCIC_REG_INDEX, 412 sc->handle[i].sock + PCIC_IDENT); 413 tmp1 = bus_space_read_1(iot, ioh, PCIC_REG_DATA); 414 415 bus_space_write_1(iot, ioh_high, PCIC_REG_INDEX, 416 sc->handle[i].sock + PCIC_IDENT); 417 tmp2 = bus_space_read_1(iot, ioh_high, PCIC_REG_DATA); 418 419 if (tmp1 == tmp2) 420 iobuswidth = 10; 421 } 422 } 423 424 bus_space_free(iot, ioh_high, length); 425 426 /* 427 * XXX some hardware doesn't seem to grok addresses in 0x400 range-- 428 * apparently missing a bit or more of address lines. (e.g. 429 * CIRRUS_PD672X with Linksys EthernetCard ne2000 clone in TI 430 * TravelMate 5000--not clear which is at fault) 431 * 432 * Add a kludge to detect 10 bit wide buses and deal with them, 433 * and also a config file option to override the probe. 434 */ 435 436 if (iobuswidth == 10) { 437 sc->iobase = 0x300; 438 sc->iosize = 0x0ff; 439 } else { 440 sc->iobase = 0x400; 441 sc->iosize = 0xbff; 442 } 443 444 DPRINTF(("%s: bus_space_alloc range 0x%04lx-0x%04lx (probed)\n", 445 sc->dev.dv_xname, (long) sc->iobase, 446 447 (long) sc->iobase + sc->iosize)); 448 449 if (pcic_isa_alloc_iobase && pcic_isa_alloc_iosize) { 450 sc->iobase = pcic_isa_alloc_iobase; 451 sc->iosize = pcic_isa_alloc_iosize; 452 453 DPRINTF(("%s: bus_space_alloc range 0x%04lx-0x%04lx " 454 "(config override)\n", sc->dev.dv_xname, (long) sc->iobase, 455 (long) sc->iobase + sc->iosize)); 456 } 457 } 458 459 void * 460 pcic_isa_chip_intr_establish(pch, pf, ipl, fct, arg) 461 pcmcia_chipset_handle_t pch; 462 struct pcmcia_function *pf; 463 int ipl; 464 int (*fct)(void *); 465 void *arg; 466 { 467 struct pcic_handle *h = (struct pcic_handle *) pch; 468 struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent); 469 struct pcic_isa_softc *isc = (struct pcic_isa_softc *)(h->ph_parent); 470 isa_chipset_tag_t ic = isc->sc_ic; 471 int irq, ist; 472 void *ih; 473 int reg; 474 475 /* 476 * PLEASE NOTE: 477 * The IRQLEVEL bit has no bearing on what happens on the host side of 478 * the PCMCIA controller. ISA interrupts are defined to be edge- 479 * triggered, and as this attachment is for ISA devices, the interrupt 480 * *must* be configured for edge-trigger. If you think you should 481 * change this to use IST_LEVEL, you are *wrong*. You should figure 482 * out what your real problem is and leave this code alone rather than 483 * breaking everyone else's systems. - mycroft 484 */ 485 if (pf->cfe->flags & PCMCIA_CFE_IRQLEVEL) 486 ist = IST_EDGE; /* SEE COMMENT ABOVE */ 487 else if (pf->cfe->flags & PCMCIA_CFE_IRQPULSE) 488 ist = IST_PULSE; /* SEE COMMENT ABOVE */ 489 else 490 ist = IST_EDGE; /* SEE COMMENT ABOVE */ 491 492 if (isa_intr_alloc(ic, sc->intr_mask[h->chip], ist, &irq)) 493 return (NULL); 494 495 h->ih_irq = irq; 496 if (h->flags & PCIC_FLAG_ENABLED) { 497 reg = pcic_read(h, PCIC_INTR); 498 reg &= ~PCIC_INTR_IRQ_MASK; 499 pcic_write(h, PCIC_INTR, reg | irq); 500 } 501 502 if ((ih = isa_intr_establish(ic, irq, ist, ipl, fct, arg)) == NULL) 503 return (NULL); 504 505 printf("%s: card irq %d\n", h->pcmcia->dv_xname, irq); 506 507 return (ih); 508 } 509 510 void 511 pcic_isa_chip_intr_disestablish(pch, ih) 512 pcmcia_chipset_handle_t pch; 513 void *ih; 514 { 515 struct pcic_handle *h = (struct pcic_handle *) pch; 516 struct pcic_isa_softc *isc = (struct pcic_isa_softc *)(h->ph_parent); 517 isa_chipset_tag_t ic = isc->sc_ic; 518 int reg; 519 520 isa_intr_disestablish(ic, ih); 521 522 h->ih_irq = 0; 523 if (h->flags & PCIC_FLAG_ENABLED) { 524 reg = pcic_read(h, PCIC_INTR); 525 reg &= ~PCIC_INTR_IRQ_MASK; 526 pcic_write(h, PCIC_INTR, reg); 527 } 528 } 529