1 /* $NetBSD: i82365_isasubr.c,v 1.30 2001/11/15 09:48:09 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Christian E. Hopps. All rights reserved. 5 * Copyright (c) 1998 Bill Sommerfeld. All rights reserved. 6 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 7 * 8 * Redistribution and use in source and binary forms, with or without 9 * modification, are permitted provided that the following conditions 10 * are met: 11 * 1. Redistributions of source code must retain the above copyright 12 * notice, this list of conditions and the following disclaimer. 13 * 2. Redistributions in binary form must reproduce the above copyright 14 * notice, this list of conditions and the following disclaimer in the 15 * documentation and/or other materials provided with the distribution. 16 * 3. All advertising materials mentioning features or use of this software 17 * must display the following acknowledgement: 18 * This product includes software developed by Marc Horowitz. 19 * 4. The name of the author may not be used to endorse or promote products 20 * derived from this software without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34 #include <sys/cdefs.h> 35 __KERNEL_RCSID(0, "$NetBSD: i82365_isasubr.c,v 1.30 2001/11/15 09:48:09 lukem Exp $"); 36 37 #define PCICISADEBUG 38 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <sys/extent.h> 43 #include <sys/malloc.h> 44 45 #include <machine/bus.h> 46 #include <machine/intr.h> 47 48 #include <dev/isa/isareg.h> 49 #include <dev/isa/isavar.h> 50 51 #include <dev/pcmcia/pcmciareg.h> 52 #include <dev/pcmcia/pcmciavar.h> 53 #include <dev/pcmcia/pcmciachip.h> 54 55 #include <dev/ic/i82365reg.h> 56 #include <dev/ic/i82365var.h> 57 #include <dev/isa/i82365_isavar.h> 58 59 /***************************************************************************** 60 * Configurable parameters. 61 *****************************************************************************/ 62 63 #include "opt_pcic_isa_alloc_iobase.h" 64 #include "opt_pcic_isa_alloc_iosize.h" 65 #include "opt_pcic_isa_intr_alloc_mask.h" 66 67 /* 68 * Default I/O allocation range. If both are set to non-zero, these 69 * values will be used instead. Otherwise, the code attempts to probe 70 * the bus width. Systems with 10 address bits should use 0x300 and 0xff. 71 * Systems with 12 address bits (most) should use 0x400 and 0xbff. 72 */ 73 74 #ifndef PCIC_ISA_ALLOC_IOBASE 75 #define PCIC_ISA_ALLOC_IOBASE 0 76 #endif 77 78 #ifndef PCIC_ISA_ALLOC_IOSIZE 79 #define PCIC_ISA_ALLOC_IOSIZE 0 80 #endif 81 82 int pcic_isa_alloc_iobase = PCIC_ISA_ALLOC_IOBASE; 83 int pcic_isa_alloc_iosize = PCIC_ISA_ALLOC_IOSIZE; 84 85 86 /* 87 * Default IRQ allocation bitmask. This defines the range of allowable 88 * IRQs for PCMCIA slots. Useful if order of probing would screw up other 89 * devices, or if PCIC hardware/cards have trouble with certain interrupt 90 * lines. 91 */ 92 93 #ifndef PCIC_ISA_INTR_ALLOC_MASK 94 #define PCIC_ISA_INTR_ALLOC_MASK 0xffff 95 #endif 96 97 int pcic_isa_intr_alloc_mask = PCIC_ISA_INTR_ALLOC_MASK; 98 99 #ifndef PCIC_IRQ_PROBE 100 #ifdef hpcmips 101 /* 102 * The irq probing doesn't work with current vrisab implementation. 103 * The irq is just an key to find matching GPIO port to use and is fixed. 104 */ 105 #define PCIC_IRQ_PROBE 0 106 #else 107 #define PCIC_IRQ_PROBE 1 108 #endif 109 #endif 110 111 int pcic_irq_probe = PCIC_IRQ_PROBE; 112 113 /***************************************************************************** 114 * End of configurable parameters. 115 *****************************************************************************/ 116 117 #ifdef PCICISADEBUG 118 int pcicsubr_debug = 0; 119 #define DPRINTF(arg) do { if (pcicsubr_debug) printf arg ; } while (0) 120 #else 121 #define DPRINTF(arg) 122 #endif 123 124 /* 125 * count the interrupt if we have a status set 126 * just use socket 0 127 */ 128 129 void pcic_isa_probe_interrupts __P((struct pcic_softc *, struct pcic_handle *)); 130 static int pcic_isa_count_intr __P((void *)); 131 132 static int 133 pcic_isa_count_intr(arg) 134 void *arg; 135 { 136 struct pcic_softc *sc; 137 struct pcic_isa_softc *isc; 138 struct pcic_handle *h; 139 int cscreg; 140 141 h = arg; 142 sc = (struct pcic_softc *)h->ph_parent; 143 isc = (struct pcic_isa_softc *)h->ph_parent; 144 145 cscreg = pcic_read(h, PCIC_CSC); 146 if (cscreg & PCIC_CSC_CD) { 147 if ((++sc->intr_detect % 20) == 0) 148 printf("."); 149 else 150 DPRINTF((".")); 151 return (1); 152 } 153 154 /* 155 * make sure we don't get stuck in a loop due to 156 * unhandled level interupts 157 */ 158 if (++sc->intr_false > 40) { 159 isa_intr_disestablish(isc->sc_ic, sc->ih); 160 sc->ih = 0; 161 162 pcic_write(h, PCIC_CSC_INTR, 0); 163 delay(10); 164 } 165 166 #ifdef PCICISADEBUG 167 if (cscreg) 168 DPRINTF(("o")); 169 else 170 DPRINTF(("X")); 171 #endif 172 return (cscreg ? 1 : 0); 173 } 174 175 /* 176 * use soft interrupt card detect to find out which irqs are available 177 * for this controller 178 */ 179 void 180 pcic_isa_probe_interrupts(sc, h) 181 struct pcic_softc *sc; 182 struct pcic_handle *h; 183 { 184 struct pcic_isa_softc *isc = (void *) sc; 185 isa_chipset_tag_t ic; 186 int i, j, mask, irq; 187 int cd, cscintr, intr, csc; 188 189 ic = isc->sc_ic; 190 191 printf("%s: controller %d detecting irqs with mask 0x%04x:", 192 sc->dev.dv_xname, h->chip, sc->intr_mask[h->chip]); 193 DPRINTF(("\n")); 194 195 /* clear any current interrupt */ 196 pcic_read(h, PCIC_CSC); 197 198 /* first disable the status irq, card detect is enabled later */ 199 pcic_write(h, PCIC_CSC_INTR, 0); 200 201 /* steer the interrupt to isa and disable ring and interrupt */ 202 intr = pcic_read(h, PCIC_INTR); 203 DPRINTF(("pcic: old intr 0x%x\n", intr)); 204 intr &= ~(PCIC_INTR_RI_ENABLE | PCIC_INTR_ENABLE | PCIC_INTR_IRQ_MASK); 205 pcic_write(h, PCIC_INTR, intr); 206 207 208 /* clear any current interrupt */ 209 pcic_read(h, PCIC_CSC); 210 211 cd = pcic_read(h, PCIC_CARD_DETECT); 212 cd |= PCIC_CARD_DETECT_SW_INTR; 213 214 mask = 0; 215 for (i = 0; i < 16; i++) { 216 /* honor configured limitations */ 217 if ((sc->intr_mask[h->chip] & (1 << i)) == 0) 218 continue; 219 220 DPRINTF(("probing irq %d: ", i)); 221 222 /* ask for a pulse interrupt so we don't share */ 223 if (isa_intr_alloc(ic, (1 << i), IST_PULSE, &irq)) { 224 DPRINTF(("currently allocated\n")); 225 continue; 226 } 227 228 cscintr = PCIC_CSC_INTR_CD_ENABLE; 229 cscintr |= (irq << PCIC_CSC_INTR_IRQ_SHIFT); 230 pcic_write(h, PCIC_CSC_INTR, cscintr); 231 delay(10); 232 233 /* Clear any pending interrupt. */ 234 (void) pcic_read(h, PCIC_CSC); 235 236 if ((sc->ih = isa_intr_establish(ic, irq, IST_EDGE, IPL_TTY, 237 pcic_isa_count_intr, h)) == NULL) 238 panic("cant get interrupt"); 239 240 /* interrupt 40 times */ 241 sc->intr_detect = 0; 242 for (j = 0; j < 40 && sc->ih; j++) { 243 sc->intr_false = 0; 244 pcic_write(h, PCIC_CARD_DETECT, cd); 245 delay(100); 246 csc = pcic_read(h, PCIC_CSC); 247 DPRINTF(("%s", csc ? "-" : "")); 248 } 249 DPRINTF((" total %d\n", sc->intr_detect)); 250 /* allow for misses */ 251 if (sc->intr_detect > 37 && sc->intr_detect <= 40) { 252 printf("%d", i); 253 DPRINTF((" succeded\n")); 254 mask |= (1 << i); 255 } 256 257 if (sc->ih) { 258 isa_intr_disestablish(ic, sc->ih); 259 sc->ih = 0; 260 261 pcic_write(h, PCIC_CSC_INTR, 0); 262 delay(10); 263 } 264 } 265 sc->intr_mask[h->chip] = mask; 266 267 printf("%s\n", sc->intr_mask[h->chip] ? "" : " none"); 268 } 269 270 /* 271 * called with interrupts enabled, light up the irqs to find out 272 * which irq lines are actually hooked up to our pcic 273 */ 274 void 275 pcic_isa_config_interrupts(self) 276 struct device *self; 277 { 278 struct pcic_softc *sc; 279 struct pcic_isa_softc *isc; 280 struct pcic_handle *h; 281 isa_chipset_tag_t ic; 282 int s, i, chipmask, chipuniq; 283 284 sc = (struct pcic_softc *) self; 285 isc = (struct pcic_isa_softc *) self; 286 ic = isc->sc_ic; 287 288 /* probe each controller */ 289 chipmask = 0xffff; 290 for (i = 0; i < PCIC_NSLOTS; i += 2) { 291 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) 292 h = &sc->handle[i]; 293 else if (sc->handle[i + 1].flags & PCIC_FLAG_SOCKETP) 294 h = &sc->handle[i + 1]; 295 else 296 continue; 297 298 sc->intr_mask[h->chip] = 299 PCIC_INTR_IRQ_VALIDMASK & pcic_isa_intr_alloc_mask; 300 301 /* the cirrus chips lack support for the soft interrupt */ 302 if (pcic_irq_probe != 0 && 303 h->vendor != PCIC_VENDOR_CIRRUS_PD6710 && 304 h->vendor != PCIC_VENDOR_CIRRUS_PD672X) 305 pcic_isa_probe_interrupts(sc, h); 306 307 chipmask &= sc->intr_mask[h->chip]; 308 } 309 /* now see if there is at least one irq per chip not shared by all */ 310 chipuniq = 1; 311 for (i = 0; i < PCIC_NSLOTS; i += 2) { 312 if ((sc->handle[i].flags & PCIC_FLAG_SOCKETP) == 0 && 313 (sc->handle[i + 1].flags & PCIC_FLAG_SOCKETP) == 0) 314 continue; 315 if ((sc->intr_mask[i / 2] & ~chipmask) == 0) { 316 chipuniq = 0; 317 break; 318 } 319 } 320 /* 321 * the rest of the following code used to run at config time with 322 * no interrupts and gets unhappy if this is violated so... 323 */ 324 s = splhigh(); 325 326 /* 327 * allocate our irq. it will be used by both controllers. I could 328 * use two different interrupts, but interrupts are relatively 329 * scarce, shareable, and for PCIC controllers, very infrequent. 330 */ 331 if ((self->dv_cfdata->cf_flags & 1) == 0) { 332 if (sc->irq != ISACF_IRQ_DEFAULT) { 333 if ((chipmask & (1 << sc->irq)) == 0) 334 printf("%s: warning: configured irq %d not " 335 "detected as available\n", 336 sc->dev.dv_xname, sc->irq); 337 } else if (chipmask == 0 || 338 isa_intr_alloc(ic, chipmask, IST_EDGE, &sc->irq)) { 339 printf("%s: no available irq; ", sc->dev.dv_xname); 340 sc->irq = ISACF_IRQ_DEFAULT; 341 } else if ((chipmask & ~(1 << sc->irq)) == 0 && chipuniq == 0) { 342 printf("%s: can't share irq with cards; ", 343 sc->dev.dv_xname); 344 sc->irq = ISACF_IRQ_DEFAULT; 345 } 346 } else { 347 printf("%s: ", sc->dev.dv_xname); 348 sc->irq = ISACF_IRQ_DEFAULT; 349 } 350 351 if (sc->irq != ISACF_IRQ_DEFAULT) { 352 sc->ih = isa_intr_establish(ic, sc->irq, IST_EDGE, IPL_TTY, 353 pcic_intr, sc); 354 if (sc->ih == NULL) { 355 printf("%s: can't establish interrupt", 356 sc->dev.dv_xname); 357 sc->irq = ISACF_IRQ_DEFAULT; 358 } 359 } 360 if (sc->irq == ISACF_IRQ_DEFAULT) 361 printf("polling for socket events\n"); 362 else 363 printf("%s: using irq %d for socket events\n", sc->dev.dv_xname, 364 sc->irq); 365 366 pcic_attach_sockets_finish(sc); 367 368 splx(s); 369 } 370 371 /* 372 * XXX This routine does not deal with the aliasing issue that its 373 * trying to. 374 * 375 * Any isa device may be decoding only 10 bits of address including 376 * the pcic. This routine only detects if the pcic is doing 10 bits. 377 * 378 * What should be done is detect the pcic's idea of the bus width, 379 * and then within those limits allocate a sparse map, where the 380 * each sub region is offset by 0x400. 381 */ 382 void pcic_isa_bus_width_probe (sc, iot, ioh, base, length) 383 struct pcic_softc *sc; 384 bus_space_tag_t iot; 385 bus_space_handle_t ioh; 386 bus_addr_t base; 387 u_int32_t length; 388 { 389 bus_space_handle_t ioh_high; 390 int i, iobuswidth, tmp1, tmp2; 391 392 /* 393 * figure out how wide the isa bus is. Do this by checking if the 394 * pcic controller is mirrored 0x400 above where we expect it to be. 395 */ 396 397 iobuswidth = 12; 398 399 /* Map i/o space. */ 400 if (bus_space_map(iot, base + 0x400, length, 0, &ioh_high)) { 401 printf("%s: can't map high i/o space\n", sc->dev.dv_xname); 402 return; 403 } 404 405 for (i = 0; i < PCIC_NSLOTS; i++) { 406 if (sc->handle[i].flags & PCIC_FLAG_SOCKETP) { 407 /* 408 * read the ident flags from the normal space and 409 * from the mirror, and compare them 410 */ 411 412 bus_space_write_1(iot, ioh, PCIC_REG_INDEX, 413 sc->handle[i].sock + PCIC_IDENT); 414 tmp1 = bus_space_read_1(iot, ioh, PCIC_REG_DATA); 415 416 bus_space_write_1(iot, ioh_high, PCIC_REG_INDEX, 417 sc->handle[i].sock + PCIC_IDENT); 418 tmp2 = bus_space_read_1(iot, ioh_high, PCIC_REG_DATA); 419 420 if (tmp1 == tmp2) 421 iobuswidth = 10; 422 } 423 } 424 425 bus_space_free(iot, ioh_high, length); 426 427 /* 428 * XXX some hardware doesn't seem to grok addresses in 0x400 range-- 429 * apparently missing a bit or more of address lines. (e.g. 430 * CIRRUS_PD672X with Linksys EthernetCard ne2000 clone in TI 431 * TravelMate 5000--not clear which is at fault) 432 * 433 * Add a kludge to detect 10 bit wide buses and deal with them, 434 * and also a config file option to override the probe. 435 */ 436 437 if (iobuswidth == 10) { 438 sc->iobase = 0x300; 439 sc->iosize = 0x0ff; 440 } else { 441 sc->iobase = 0x400; 442 sc->iosize = 0xbff; 443 } 444 445 DPRINTF(("%s: bus_space_alloc range 0x%04lx-0x%04lx (probed)\n", 446 sc->dev.dv_xname, (long) sc->iobase, 447 448 (long) sc->iobase + sc->iosize)); 449 450 if (pcic_isa_alloc_iobase && pcic_isa_alloc_iosize) { 451 sc->iobase = pcic_isa_alloc_iobase; 452 sc->iosize = pcic_isa_alloc_iosize; 453 454 DPRINTF(("%s: bus_space_alloc range 0x%04lx-0x%04lx " 455 "(config override)\n", sc->dev.dv_xname, (long) sc->iobase, 456 (long) sc->iobase + sc->iosize)); 457 } 458 } 459 460 void * 461 pcic_isa_chip_intr_establish(pch, pf, ipl, fct, arg) 462 pcmcia_chipset_handle_t pch; 463 struct pcmcia_function *pf; 464 int ipl; 465 int (*fct) __P((void *)); 466 void *arg; 467 { 468 struct pcic_handle *h = (struct pcic_handle *) pch; 469 struct pcic_softc *sc = (struct pcic_softc *)(h->ph_parent); 470 struct pcic_isa_softc *isc = (struct pcic_isa_softc *)(h->ph_parent); 471 isa_chipset_tag_t ic = isc->sc_ic; 472 int irq, ist; 473 void *ih; 474 int reg; 475 476 /* 477 * PLEASE NOTE: 478 * The IRQLEVEL bit has no bearing on what happens on the host side of 479 * the PCMCIA controller. ISA interrupts are defined to be edge- 480 * triggered, and as this attachment is for ISA devices, the interrupt 481 * *must* be configured for edge-trigger. If you think you should 482 * change this to use IST_LEVEL, you are *wrong*. You should figure 483 * out what your real problem is and leave this code alone rather than 484 * breaking everyone else's systems. - mycroft 485 */ 486 if (pf->cfe->flags & PCMCIA_CFE_IRQLEVEL) 487 ist = IST_EDGE; /* SEE COMMENT ABOVE */ 488 else if (pf->cfe->flags & PCMCIA_CFE_IRQPULSE) 489 ist = IST_PULSE; /* SEE COMMENT ABOVE */ 490 else 491 ist = IST_EDGE; /* SEE COMMENT ABOVE */ 492 493 if (isa_intr_alloc(ic, sc->intr_mask[h->chip], ist, &irq)) 494 return (NULL); 495 496 h->ih_irq = irq; 497 if (h->flags & PCIC_FLAG_ENABLED) { 498 reg = pcic_read(h, PCIC_INTR); 499 reg &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE); 500 pcic_write(h, PCIC_INTR, reg | irq); 501 } 502 503 if ((ih = isa_intr_establish(ic, irq, ist, ipl, fct, arg)) == NULL) 504 return (NULL); 505 506 printf("%s: card irq %d\n", h->pcmcia->dv_xname, irq); 507 508 return (ih); 509 } 510 511 void 512 pcic_isa_chip_intr_disestablish(pch, ih) 513 pcmcia_chipset_handle_t pch; 514 void *ih; 515 { 516 struct pcic_handle *h = (struct pcic_handle *) pch; 517 struct pcic_isa_softc *isc = (struct pcic_isa_softc *)(h->ph_parent); 518 isa_chipset_tag_t ic = isc->sc_ic; 519 int reg; 520 521 isa_intr_disestablish(ic, ih); 522 523 h->ih_irq = 0; 524 if (h->flags & PCIC_FLAG_ENABLED) { 525 reg = pcic_read(h, PCIC_INTR); 526 reg &= ~(PCIC_INTR_IRQ_MASK | PCIC_INTR_ENABLE); 527 pcic_write(h, PCIC_INTR, reg); 528 } 529 } 530