xref: /netbsd-src/sys/dev/isa/cmsreg.h (revision 8b0f9554ff8762542c4defc4f70e1eb76fb508fa)
1 /* $NetBSD: cmsreg.h,v 1.3 2005/12/11 12:22:02 christos Exp $ */
2 
3 /*
4  * Copyright (c) 2000 The NetBSD Foundation, Inc.
5  * All rights reserved.
6  *
7  * Redistribution and use in source and binary forms, with or without
8  * modification, are permitted provided that the following conditions
9  * are met:
10  * 1. Redistributions of source code must retain the above copyright
11  *    notice, this list of conditions and the following disclaimer.
12  * 2. Redistributions in binary form must reproduce the above copyright
13  *    notice, this list of conditions and the following disclaimer in the
14  *    documentation and/or other materials provided with the distribution.
15  * 3. All advertising materials mentioning features or use of this software
16  *    must display the following acknowledgement:
17  *        This product includes software developed by the NetBSD
18  *        Foundation, Inc. and its contributors.
19  * 4. Neither the name of The NetBSD Foundation nor the names of its
20  *    contributors may be used to endorse or promote products derived
21  *    from this software without specific prior written permission.
22  *
23  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
24  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
25  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
26  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
27  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
28  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
29  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
30  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
31  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
32  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
33  * POSSIBILITY OF SUCH DAMAGE.
34  */
35 
36 #define CMS_NVOICES 12
37 #define CMS_FIRST_NOTE 30
38 
39 /* direct registers */
40 
41 #define CMS_DATA0 0x00 /* for chip 0, voices 0-5 */
42 #define CMS_ADDR0 0x01
43 
44 #define CMS_DATA1 0x02 /* for chip 1, voices 6-11 */
45 #define CMS_ADDR1 0x03
46 
47 #define CMS_MREG  0x04 /* always returns 0x7f */
48 #define CMS_WREG  0x07 /* writable register */
49 #define CMS_RREG  0x0b /* readable register */
50 
51 #define CMS_IOSIZE 16
52 
53 /*
54  * Note that for each register, if ports CMS_DATA1/CMS_ADDR1 are used
55  * then the first voice is modified.  If ports CMS_DATA2/CMS_ADDR2 are
56  * used then the second voice is modified.
57  */
58 
59 /*
60  * Each voice can have a volume between 0 and 15 on both left and
61  * right channels.  The high-order nibble is the right channel volume,
62  * and the low-order nibble is the left channel volume.
63  */
64 
65 #define CMS_IREG_VOL0 0x00
66 #define CMS_IREG_VOL1 0x01
67 #define CMS_IREG_VOL2 0x02
68 #define CMS_IREG_VOL3 0x03
69 #define CMS_IREG_VOL4 0x04
70 #define CMS_IREG_VOL5 0x05
71 
72 /* Frequency registers */
73 #define CMS_IREG_FREQ0 0x08
74 #define CMS_IREG_FREQ1 0x09
75 #define CMS_IREG_FREQ2 0x0a
76 #define CMS_IREG_FREQ3 0x0b
77 #define CMS_IREG_FREQ4 0x0c
78 #define CMS_IREG_FREQ5 0x0d
79 
80 /*
81  * Octave Registers: To get tones in higher octaves the octave
82  * register for the voice must be set.  Each octave register stores
83  * the octave number for two voices.  The high-order nibble is for
84  * first voice and the low-order nibble is for the second voice.
85  */
86 
87 #define CMS_IREG_OCTAVE_1_0 0x10
88 #define CMS_IREG_OCTAVE_3_2 0x11
89 #define CMS_IREG_OCTAVE_5_4 0x12
90 
91 #define CMS_IREG_FREQ_CTL 0x14 /* voice frequencies */
92 #define CMS_IREG_FREQ_ENBL0 0x01 /* setting the bit enables the voice */
93 #define CMS_IREG_FREQ_ENBL1 0x02 /* clearing the bit disables the voice */
94 #define CMS_IREG_FREQ_ENBL2 0x04
95 #define CMS_IREG_FREQ_ENBL3 0x08
96 #define CMS_IREG_FREQ_ENBL4 0x10
97 #define CMS_IREG_FREQ_ENBL5 0x20
98 
99 /*
100  * There are 4 noise generators, each noise generator can be connected
101  * up to any of three voices:
102  *
103  * Noise generator 0: connected to voices 0,1,2
104  *                 1: connected to voices 3,4,5
105  *                 2: connected to voices 6,7,8
106  *                 3: connected to voices 0,10,11
107  *
108  * CMS_DATA1/CMS_ADDR1 access noise generators 0 and 1.  Each noise
109  * generator has two bits which control the noise generator rate.
110  */
111 
112 #define CMS_IREG_NOISE_CTL 0x15 /* noises */
113 #define CMS_IREG_NOISE_ENBL0 0x01
114 #define CMS_IREG_NOISE_ENBL1 0x02
115 #define CMS_IREG_NOISE_ENBL2 0x04
116 #define CMS_IREG_NOISE_ENBL3 0x08
117 #define CMS_IREG_NOISE_ENBL4 0x10
118 #define CMS_IREG_NOISE_ENBL5 0x20
119 
120 #define CMS_IREG_NOISE_BW 0x16
121 #define CMS_IREG_NOISE_MASK0 0x03 /* bits for noise generator 0 */
122 #define CMS_IREG_NOISE_MASK1 0x30 /* bits for noise generator 1 */
123 /* the bits in the mask have the following meaning */
124 #define CMS_IREG_NOISE_MASK_28k 0 /* 28kHz */
125 #define CMS_IREG_NOISE_MASK_14k 1 /* 14kHz */
126 #define CMS_IREG_NOISE_MASK_7k  2 /* 6.8kHz */
127 
128 #define CMS_IREG_SYS_CTL 0x1c
129 #define CMS_IREG_SYS_ENBL  0x01 /* enable all channels */
130 #define CMS_IREG_SYS_RESET 0x02 /* reset and synchronise generators */
131 
132 
133 /*
134  * Some useful macros
135  */
136 
137 #define CMS_WRITE(sc, chip, reg, val)					\
138 do {									\
139 	(sc)->sc_shadowregs[((chip)<<5) + (reg)] = val;			\
140 	bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh,			\
141 		CMS_ADDR0 + ((chip)<<1), (reg));			\
142 	bus_space_write_1((sc)->sc_iot, (sc)->sc_ioh,			\
143 		CMS_DATA0 + ((chip)<<1), (val));			\
144 } while (0)
145 
146 #define CMS_READ(sc, chip, reg) ((sc)->sc_shadowregs[((chip)<<5) + (reg)])
147 
148 #define CHAN_TO_CHIP(chan) ((chan)>5)
149 #define CHAN_TO_VOICE(chan) ((chan)%6)
150 #define OCTAVE_OFFSET(voice) ((voice)>>1)
151 #define OCTAVE_SHIFT(voice) (((voice)&1)<<2)
152