1 /* $NetBSD: z8530sc.c,v 1.18 2003/01/28 12:35:39 pk Exp $ */ 2 3 /* 4 * Copyright (c) 1994 Gordon W. Ross 5 * Copyright (c) 1992, 1993 6 * The Regents of the University of California. All rights reserved. 7 * 8 * This software was developed by the Computer Systems Engineering group 9 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 10 * contributed to Berkeley. 11 * 12 * All advertising materials mentioning features or use of this software 13 * must display the following acknowledgement: 14 * This product includes software developed by the University of 15 * California, Lawrence Berkeley Laboratory. 16 * 17 * Redistribution and use in source and binary forms, with or without 18 * modification, are permitted provided that the following conditions 19 * are met: 20 * 1. Redistributions of source code must retain the above copyright 21 * notice, this list of conditions and the following disclaimer. 22 * 2. Redistributions in binary form must reproduce the above copyright 23 * notice, this list of conditions and the following disclaimer in the 24 * documentation and/or other materials provided with the distribution. 25 * 3. All advertising materials mentioning features or use of this software 26 * must display the following acknowledgement: 27 * This product includes software developed by the University of 28 * California, Berkeley and its contributors. 29 * 4. Neither the name of the University nor the names of its contributors 30 * may be used to endorse or promote products derived from this software 31 * without specific prior written permission. 32 * 33 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 34 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 35 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 36 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 37 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 38 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 39 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 40 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 41 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 42 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 43 * SUCH DAMAGE. 44 * 45 * @(#)zs.c 8.1 (Berkeley) 7/19/93 46 */ 47 48 /* 49 * Zilog Z8530 Dual UART driver (common part) 50 * 51 * This file contains the machine-independent parts of the 52 * driver common to tty and keyboard/mouse sub-drivers. 53 */ 54 55 #include <sys/cdefs.h> 56 __KERNEL_RCSID(0, "$NetBSD: z8530sc.c,v 1.18 2003/01/28 12:35:39 pk Exp $"); 57 58 #include <sys/param.h> 59 #include <sys/systm.h> 60 #include <sys/proc.h> 61 #include <sys/device.h> 62 #include <sys/conf.h> 63 #include <sys/file.h> 64 #include <sys/ioctl.h> 65 #include <sys/tty.h> 66 #include <sys/time.h> 67 #include <sys/kernel.h> 68 #include <sys/syslog.h> 69 70 #include <dev/ic/z8530reg.h> 71 #include <machine/z8530var.h> 72 73 void 74 zs_break(cs, set) 75 struct zs_chanstate *cs; 76 int set; 77 { 78 79 if (set) { 80 cs->cs_preg[5] |= ZSWR5_BREAK; 81 cs->cs_creg[5] |= ZSWR5_BREAK; 82 } else { 83 cs->cs_preg[5] &= ~ZSWR5_BREAK; 84 cs->cs_creg[5] &= ~ZSWR5_BREAK; 85 } 86 zs_write_reg(cs, 5, cs->cs_creg[5]); 87 } 88 89 90 /* 91 * drain on-chip fifo 92 */ 93 void 94 zs_iflush(cs) 95 struct zs_chanstate *cs; 96 { 97 u_char c, rr0, rr1; 98 int i; 99 100 /* 101 * Count how many times we loop. Some systems, such as some 102 * Apple PowerBooks, claim to have SCC's which they really don't. 103 */ 104 for (i = 0; i < 32; i++) { 105 /* Is there input available? */ 106 rr0 = zs_read_csr(cs); 107 if ((rr0 & ZSRR0_RX_READY) == 0) 108 break; 109 110 /* 111 * First read the status, because reading the data 112 * destroys the status of this char. 113 */ 114 rr1 = zs_read_reg(cs, 1); 115 c = zs_read_data(cs); 116 117 if (rr1 & (ZSRR1_FE | ZSRR1_DO | ZSRR1_PE)) { 118 /* Clear the receive error. */ 119 zs_write_csr(cs, ZSWR0_RESET_ERRORS); 120 } 121 } 122 } 123 124 125 /* 126 * Write the given register set to the given zs channel in the proper order. 127 * The channel must not be transmitting at the time. The receiver will 128 * be disabled for the time it takes to write all the registers. 129 * Call this with interrupts disabled. 130 */ 131 void 132 zs_loadchannelregs(cs) 133 struct zs_chanstate *cs; 134 { 135 u_char *reg, v; 136 137 zs_write_csr(cs, ZSM_RESET_ERR); /* XXX: reset error condition */ 138 139 #if 1 140 /* 141 * XXX: Is this really a good idea? 142 * XXX: Should go elsewhere! -gwr 143 */ 144 zs_iflush(cs); /* XXX */ 145 #endif 146 147 if (cs->cs_ctl_chan != NULL) 148 v = ((cs->cs_ctl_chan->cs_creg[5] & (ZSWR5_RTS | ZSWR5_DTR)) != 149 (cs->cs_ctl_chan->cs_preg[5] & (ZSWR5_RTS | ZSWR5_DTR))); 150 else 151 v = 0; 152 153 if (memcmp((caddr_t)cs->cs_preg, (caddr_t)cs->cs_creg, 16) == 0 && !v) 154 return; /* only change if values are different */ 155 156 /* Copy "pending" regs to "current" */ 157 memcpy((caddr_t)cs->cs_creg, (caddr_t)cs->cs_preg, 16); 158 reg = cs->cs_creg; /* current regs */ 159 160 /* disable interrupts */ 161 zs_write_reg(cs, 1, reg[1] & ~ZSWR1_IMASK); 162 163 /* baud clock divisor, stop bits, parity */ 164 zs_write_reg(cs, 4, reg[4]); 165 166 /* misc. TX/RX control bits */ 167 zs_write_reg(cs, 10, reg[10]); 168 169 /* char size, enable (RX/TX) */ 170 zs_write_reg(cs, 3, reg[3] & ~ZSWR3_RX_ENABLE); 171 zs_write_reg(cs, 5, reg[5] & ~ZSWR5_TX_ENABLE); 172 173 /* synchronous mode stuff */ 174 zs_write_reg(cs, 6, reg[6]); 175 zs_write_reg(cs, 7, reg[7]); 176 177 #if 0 178 /* 179 * Registers 2 and 9 are special because they are 180 * actually common to both channels, but must be 181 * programmed through channel A. The "zsc" attach 182 * function takes care of setting these registers 183 * and they should not be touched thereafter. 184 */ 185 /* interrupt vector */ 186 zs_write_reg(cs, 2, reg[2]); 187 /* master interrupt control */ 188 zs_write_reg(cs, 9, reg[9]); 189 #endif 190 191 /* Shut down the BRG */ 192 zs_write_reg(cs, 14, reg[14] & ~ZSWR14_BAUD_ENA); 193 194 #ifdef ZS_MD_SETCLK 195 /* Let the MD code setup any external clock. */ 196 ZS_MD_SETCLK(cs); 197 #endif /* ZS_MD_SETCLK */ 198 199 /* clock mode control */ 200 zs_write_reg(cs, 11, reg[11]); 201 202 /* baud rate (lo/hi) */ 203 zs_write_reg(cs, 12, reg[12]); 204 zs_write_reg(cs, 13, reg[13]); 205 206 /* Misc. control bits */ 207 zs_write_reg(cs, 14, reg[14]); 208 209 /* which lines cause status interrupts */ 210 zs_write_reg(cs, 15, reg[15]); 211 212 /* 213 * Zilog docs recommend resetting external status twice at this 214 * point. Mainly as the status bits are latched, and the first 215 * interrupt clear might unlatch them to new values, generating 216 * a second interrupt request. 217 */ 218 zs_write_csr(cs, ZSM_RESET_STINT); 219 zs_write_csr(cs, ZSM_RESET_STINT); 220 221 /* char size, enable (RX/TX)*/ 222 zs_write_reg(cs, 3, reg[3]); 223 zs_write_reg(cs, 5, reg[5]); 224 225 /* Write the status bits on the alternate channel also. */ 226 if (cs->cs_ctl_chan != NULL) { 227 v = cs->cs_ctl_chan->cs_preg[5]; 228 cs->cs_ctl_chan->cs_creg[5] = v; 229 zs_write_reg(cs->cs_ctl_chan, 5, v); 230 } 231 232 /* interrupt enables: RX, TX, STATUS */ 233 zs_write_reg(cs, 1, reg[1]); 234 } 235 236 237 /* 238 * ZS hardware interrupt. Scan all ZS channels. NB: we know here that 239 * channels are kept in (A,B) pairs. 240 * 241 * Do just a little, then get out; set a software interrupt if more 242 * work is needed. 243 * 244 * We deliberately ignore the vectoring Zilog gives us, and match up 245 * only the number of `reset interrupt under service' operations, not 246 * the order. 247 */ 248 int 249 zsc_intr_hard(arg) 250 void *arg; 251 { 252 struct zsc_softc *zsc = arg; 253 struct zs_chanstate *cs; 254 u_char rr3; 255 256 /* First look at channel A. */ 257 cs = zsc->zsc_cs[0]; 258 259 /* Lock both channels */ 260 simple_lock(&cs->cs_lock); 261 simple_lock(&zsc->zsc_cs[1]->cs_lock); 262 /* Note: only channel A has an RR3 */ 263 rr3 = zs_read_reg(cs, 3); 264 265 /* 266 * Clear interrupt first to avoid a race condition. 267 * If a new interrupt condition happens while we are 268 * servicing this one, we will get another interrupt 269 * shortly. We can NOT just sit here in a loop, or 270 * we will cause horrible latency for other devices 271 * on this interrupt level (i.e. sun3x floppy disk). 272 */ 273 if (rr3 & (ZSRR3_IP_A_RX | ZSRR3_IP_A_TX | ZSRR3_IP_A_STAT)) { 274 zs_write_csr(cs, ZSWR0_CLR_INTR); 275 if (rr3 & ZSRR3_IP_A_RX) 276 (*cs->cs_ops->zsop_rxint)(cs); 277 if (rr3 & ZSRR3_IP_A_STAT) 278 (*cs->cs_ops->zsop_stint)(cs, 0); 279 if (rr3 & ZSRR3_IP_A_TX) 280 (*cs->cs_ops->zsop_txint)(cs); 281 } 282 283 /* Done with channel A */ 284 simple_unlock(&cs->cs_lock); 285 286 /* Now look at channel B. */ 287 cs = zsc->zsc_cs[1]; 288 if (rr3 & (ZSRR3_IP_B_RX | ZSRR3_IP_B_TX | ZSRR3_IP_B_STAT)) { 289 zs_write_csr(cs, ZSWR0_CLR_INTR); 290 if (rr3 & ZSRR3_IP_B_RX) 291 (*cs->cs_ops->zsop_rxint)(cs); 292 if (rr3 & ZSRR3_IP_B_STAT) 293 (*cs->cs_ops->zsop_stint)(cs, 0); 294 if (rr3 & ZSRR3_IP_B_TX) 295 (*cs->cs_ops->zsop_txint)(cs); 296 } 297 298 simple_unlock(&cs->cs_lock); 299 300 /* Note: caller will check cs_x->cs_softreq and DTRT. */ 301 return (rr3); 302 } 303 304 305 /* 306 * ZS software interrupt. Scan all channels for deferred interrupts. 307 */ 308 int 309 zsc_intr_soft(arg) 310 void *arg; 311 { 312 struct zsc_softc *zsc = arg; 313 struct zs_chanstate *cs; 314 int rval, chan; 315 316 rval = 0; 317 for (chan = 0; chan < 2; chan++) { 318 cs = zsc->zsc_cs[chan]; 319 320 /* 321 * The softint flag can be safely cleared once 322 * we have decided to call the softint routine. 323 * (No need to do splzs() first.) 324 */ 325 if (cs->cs_softreq) { 326 cs->cs_softreq = 0; 327 (*cs->cs_ops->zsop_softint)(cs); 328 rval++; 329 } 330 } 331 return (rval); 332 } 333 334 /* 335 * Provide a null zs "ops" vector. 336 */ 337 338 static void zsnull_rxint __P((struct zs_chanstate *)); 339 static void zsnull_stint __P((struct zs_chanstate *, int)); 340 static void zsnull_txint __P((struct zs_chanstate *)); 341 static void zsnull_softint __P((struct zs_chanstate *)); 342 343 static void 344 zsnull_rxint(cs) 345 struct zs_chanstate *cs; 346 { 347 /* Ask for softint() call. */ 348 cs->cs_softreq = 1; 349 } 350 351 static void 352 zsnull_stint(cs, force) 353 struct zs_chanstate *cs; 354 int force; 355 { 356 /* Ask for softint() call. */ 357 cs->cs_softreq = 1; 358 } 359 360 static void 361 zsnull_txint(cs) 362 struct zs_chanstate *cs; 363 { 364 /* Ask for softint() call. */ 365 cs->cs_softreq = 1; 366 } 367 368 static void 369 zsnull_softint(cs) 370 struct zs_chanstate *cs; 371 { 372 zs_write_reg(cs, 1, 0); 373 zs_write_reg(cs, 15, 0); 374 } 375 376 struct zsops zsops_null = { 377 zsnull_rxint, /* receive char available */ 378 zsnull_stint, /* external/status */ 379 zsnull_txint, /* xmit buffer empty */ 380 zsnull_softint, /* process software interrupt */ 381 }; 382