1 /* $NetBSD: wdc.c,v 1.288 2017/10/20 07:06:07 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 2001, 2003 Manuel Bouyer. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 */ 26 27 /*- 28 * Copyright (c) 1998, 2003, 2004 The NetBSD Foundation, Inc. 29 * All rights reserved. 30 * 31 * This code is derived from software contributed to The NetBSD Foundation 32 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 33 * 34 * Redistribution and use in source and binary forms, with or without 35 * modification, are permitted provided that the following conditions 36 * are met: 37 * 1. Redistributions of source code must retain the above copyright 38 * notice, this list of conditions and the following disclaimer. 39 * 2. Redistributions in binary form must reproduce the above copyright 40 * notice, this list of conditions and the following disclaimer in the 41 * documentation and/or other materials provided with the distribution. 42 * 43 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 44 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 45 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 46 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 47 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 48 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 49 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 50 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 51 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 52 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 53 * POSSIBILITY OF SUCH DAMAGE. 54 */ 55 56 /* 57 * CODE UNTESTED IN THE CURRENT REVISION: 58 */ 59 60 #include <sys/cdefs.h> 61 __KERNEL_RCSID(0, "$NetBSD: wdc.c,v 1.288 2017/10/20 07:06:07 jdolecek Exp $"); 62 63 #include "opt_ata.h" 64 #include "opt_wdc.h" 65 66 #include <sys/param.h> 67 #include <sys/systm.h> 68 #include <sys/kernel.h> 69 #include <sys/conf.h> 70 #include <sys/buf.h> 71 #include <sys/device.h> 72 #include <sys/malloc.h> 73 #include <sys/syslog.h> 74 #include <sys/proc.h> 75 76 #include <sys/intr.h> 77 #include <sys/bus.h> 78 79 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 80 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 81 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 82 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 83 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 84 #define bus_space_read_stream_2 bus_space_read_2 85 #define bus_space_read_stream_4 bus_space_read_4 86 #define bus_space_write_stream_2 bus_space_write_2 87 #define bus_space_write_stream_4 bus_space_write_4 88 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 89 90 #include <dev/ata/atavar.h> 91 #include <dev/ata/atareg.h> 92 #include <dev/ata/satareg.h> 93 #include <dev/ata/satavar.h> 94 #include <dev/ic/wdcreg.h> 95 #include <dev/ic/wdcvar.h> 96 97 #include "locators.h" 98 99 #include "atapibus.h" 100 #include "wd.h" 101 #include "sata.h" 102 103 #define WDCDELAY 100 /* 100 microseconds */ 104 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 105 #if 0 106 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 107 #define WDCNDELAY_DEBUG 50 108 #endif 109 110 /* When polling wait that much and then kpause for 1/hz seconds */ 111 #define WDCDELAY_POLL 1 /* ms */ 112 113 /* timeout for the control commands */ 114 #define WDC_CTRL_DELAY 10000 /* 10s, for the recall command */ 115 116 /* 117 * timeout when waiting for BSY to deassert when probing. 118 * set to 5s. From the standards this could be up to 31, but we can't 119 * wait that much at boot time, and 5s seems to be enough. 120 */ 121 #define WDC_PROBE_WAIT 5 122 123 124 #if NWD > 0 125 extern const struct ata_bustype wdc_ata_bustype; /* in ata_wdc.c */ 126 #else 127 /* A fake one, the autoconfig will print "wd at foo ... not configured */ 128 const struct ata_bustype wdc_ata_bustype = { 129 SCSIPI_BUSTYPE_ATA, 130 NULL, /* wdc_ata_bio */ 131 NULL, /* wdc_reset_drive */ 132 wdc_reset_channel, 133 wdc_exec_command, 134 NULL, /* ata_get_params */ 135 NULL, /* wdc_ata_addref */ 136 NULL, /* wdc_ata_delref */ 137 NULL /* ata_kill_pending */ 138 }; 139 #endif 140 141 /* Flags to wdcreset(). */ 142 #define RESET_POLL 1 143 #define RESET_SLEEP 0 /* wdcreset() will use kpause() */ 144 145 static int wdcprobe1(struct ata_channel *, int); 146 static int wdcreset(struct ata_channel *, int); 147 static void __wdcerror(struct ata_channel *, const char *); 148 static int __wdcwait_reset(struct ata_channel *, int, int); 149 static void __wdccommand_done(struct ata_channel *, struct ata_xfer *); 150 static void __wdccommand_poll(struct ata_channel *, struct ata_xfer *); 151 static void __wdccommand_done_end(struct ata_channel *, struct ata_xfer *); 152 static void __wdccommand_kill_xfer(struct ata_channel *, 153 struct ata_xfer *, int); 154 static int __wdccommand_start(struct ata_channel *, struct ata_xfer *); 155 static int __wdccommand_intr(struct ata_channel *, struct ata_xfer *, int); 156 static int __wdcwait(struct ata_channel *, int, int, int, int *); 157 158 static void wdc_datain_pio(struct ata_channel *, int, void *, size_t); 159 static void wdc_dataout_pio(struct ata_channel *, int, void *, size_t); 160 #define DEBUG_INTR 0x01 161 #define DEBUG_XFERS 0x02 162 #define DEBUG_STATUS 0x04 163 #define DEBUG_FUNCS 0x08 164 #define DEBUG_PROBE 0x10 165 #define DEBUG_DETACH 0x20 166 #define DEBUG_DELAY 0x40 167 #ifdef ATADEBUG 168 extern int atadebug_mask; /* init'ed in ata.c */ 169 int wdc_nxfer = 0; 170 #define ATADEBUG_PRINT(args, level) if (atadebug_mask & (level)) printf args 171 #else 172 #define ATADEBUG_PRINT(args, level) 173 #endif 174 175 /* 176 * Initialize the "shadow register" handles for a standard wdc controller. 177 */ 178 void 179 wdc_init_shadow_regs(struct wdc_regs *wdr) 180 { 181 wdr->cmd_iohs[wd_status] = wdr->cmd_iohs[wd_command]; 182 wdr->cmd_iohs[wd_features] = wdr->cmd_iohs[wd_error]; 183 } 184 185 /* 186 * Allocate a wdc_regs array, based on the number of channels. 187 */ 188 void 189 wdc_allocate_regs(struct wdc_softc *wdc) 190 { 191 192 wdc->regs = malloc(wdc->sc_atac.atac_nchannels * 193 sizeof(struct wdc_regs), M_DEVBUF, M_WAITOK); 194 } 195 196 #if NSATA > 0 197 /* 198 * probe drives on SATA controllers with standard SATA registers: 199 * bring the PHYs online, read the drive signature and set drive flags 200 * appropriately. 201 */ 202 void 203 wdc_sataprobe(struct ata_channel *chp) 204 { 205 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 206 uint8_t st = 0, sc __unused, sn __unused, cl, ch; 207 int i; 208 209 KASSERT(chp->ch_ndrives == 0 || chp->ch_drive != NULL); 210 211 /* do this before we take lock */ 212 213 ata_channel_lock(chp); 214 215 /* reset the PHY and bring online */ 216 switch (sata_reset_interface(chp, wdr->sata_iot, wdr->sata_control, 217 wdr->sata_status, AT_WAIT)) { 218 case SStatus_DET_DEV: 219 /* wait 5s for BSY to clear */ 220 for (i = 0; i < WDC_PROBE_WAIT * hz; i++) { 221 bus_space_write_1(wdr->cmd_iot, 222 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 223 delay(10); /* 400ns delay */ 224 st = bus_space_read_1(wdr->cmd_iot, 225 wdr->cmd_iohs[wd_status], 0); 226 if ((st & WDCS_BSY) == 0) 227 break; 228 ata_delay(chp, 1, "sataprb", AT_WAIT); 229 } 230 if (i == WDC_PROBE_WAIT * hz) 231 aprint_error_dev(chp->ch_atac->atac_dev, 232 "BSY never cleared, status 0x%02x\n", st); 233 sc = bus_space_read_1(wdr->cmd_iot, 234 wdr->cmd_iohs[wd_seccnt], 0); 235 sn = bus_space_read_1(wdr->cmd_iot, 236 wdr->cmd_iohs[wd_sector], 0); 237 cl = bus_space_read_1(wdr->cmd_iot, 238 wdr->cmd_iohs[wd_cyl_lo], 0); 239 ch = bus_space_read_1(wdr->cmd_iot, 240 wdr->cmd_iohs[wd_cyl_hi], 0); 241 ATADEBUG_PRINT(("%s: port %d: sc=0x%x sn=0x%x " 242 "cl=0x%x ch=0x%x\n", 243 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 244 sc, sn, cl, ch), DEBUG_PROBE); 245 if (atabus_alloc_drives(chp, 1) != 0) 246 return; 247 /* 248 * sc and sn are supposed to be 0x1 for ATAPI, but in some 249 * cases we get wrong values here, so ignore it. 250 */ 251 if (cl == 0x14 && ch == 0xeb) 252 chp->ch_drive[0].drive_type = ATA_DRIVET_ATAPI; 253 else 254 chp->ch_drive[0].drive_type = ATA_DRIVET_ATA; 255 256 /* 257 * issue a reset in case only the interface part of the drive 258 * is up 259 */ 260 if (wdcreset(chp, RESET_SLEEP) != 0) 261 chp->ch_drive[0].drive_type = ATA_DRIVET_NONE; 262 break; 263 264 default: 265 break; 266 } 267 268 ata_channel_unlock(chp); 269 } 270 #endif /* NSATA > 0 */ 271 272 273 /* Test to see controller with at last one attached drive is there. 274 * Returns a bit for each possible drive found (0x01 for drive 0, 275 * 0x02 for drive 1). 276 * Logic: 277 * - If a status register is at 0xff, assume there is no drive here 278 * (ISA has pull-up resistors). Similarly if the status register has 279 * the value we last wrote to the bus (for IDE interfaces without pullups). 280 * If no drive at all -> return. 281 * - reset the controller, wait for it to complete (may take up to 31s !). 282 * If timeout -> return. 283 * - test ATA/ATAPI signatures. If at last one drive found -> return. 284 * - try an ATA command on the master. 285 */ 286 287 void 288 wdc_drvprobe(struct ata_channel *chp) 289 { 290 struct ataparams params; /* XXX: large struct */ 291 struct atac_softc *atac = chp->ch_atac; 292 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 293 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 294 u_int8_t st0 = 0, st1 = 0; 295 int i, j, error, tfd; 296 297 if (atabus_alloc_drives(chp, wdc->wdc_maxdrives) != 0) 298 return; 299 if (wdcprobe1(chp, 0) == 0) { 300 /* No drives, abort the attach here. */ 301 atabus_free_drives(chp); 302 return; 303 } 304 305 ata_channel_lock(chp); 306 /* for ATA/OLD drives, wait for DRDY, 3s timeout */ 307 for (i = 0; i < mstohz(3000); i++) { 308 /* 309 * select drive 1 first, so that master is selected on 310 * exit from the loop 311 */ 312 if (chp->ch_ndrives > 1 && 313 chp->ch_drive[1].drive_type == ATA_DRIVET_ATA) { 314 if (wdc->select) 315 wdc->select(chp,1); 316 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 317 0, WDSD_IBM | 0x10); 318 delay(10); /* 400ns delay */ 319 st1 = bus_space_read_1(wdr->cmd_iot, 320 wdr->cmd_iohs[wd_status], 0); 321 } 322 if (chp->ch_drive[0].drive_type == ATA_DRIVET_ATA) { 323 if (wdc->select) 324 wdc->select(chp,0); 325 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 326 0, WDSD_IBM); 327 delay(10); /* 400ns delay */ 328 st0 = bus_space_read_1(wdr->cmd_iot, 329 wdr->cmd_iohs[wd_status], 0); 330 } 331 332 333 if ((chp->ch_drive[0].drive_type != ATA_DRIVET_ATA || 334 (st0 & WDCS_DRDY)) && 335 (chp->ch_ndrives < 2 || 336 chp->ch_drive[1].drive_type != ATA_DRIVET_ATA || 337 (st1 & WDCS_DRDY))) 338 break; 339 #ifdef WDC_NO_IDS 340 /* cannot kpause here (can't enable IPL_BIO interrups), 341 * delay instead 342 */ 343 delay(1000000 / hz); 344 #else 345 ata_delay(chp, 1, "atadrdy", AT_WAIT); 346 #endif 347 } 348 if ((st0 & WDCS_DRDY) == 0 && 349 chp->ch_drive[0].drive_type != ATA_DRIVET_ATAPI) 350 chp->ch_drive[0].drive_type = ATA_DRIVET_NONE; 351 if (chp->ch_ndrives > 1 && (st1 & WDCS_DRDY) == 0 && 352 chp->ch_drive[1].drive_type != ATA_DRIVET_ATAPI) 353 chp->ch_drive[1].drive_type = ATA_DRIVET_NONE; 354 ata_channel_unlock(chp); 355 356 ATADEBUG_PRINT(("%s:%d: wait DRDY st0 0x%x st1 0x%x\n", 357 device_xname(atac->atac_dev), 358 chp->ch_channel, st0, st1), DEBUG_PROBE); 359 360 /* Wait a bit, some devices are weird just after a reset. */ 361 delay(5000); 362 363 for (i = 0; i < chp->ch_ndrives; i++) { 364 #if NATA_DMA 365 /* 366 * Init error counter so that an error within the first xfers 367 * will trigger a downgrade 368 */ 369 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 370 #endif 371 372 /* If controller can't do 16bit flag the drives as 32bit */ 373 if ((atac->atac_cap & 374 (ATAC_CAP_DATA16 | ATAC_CAP_DATA32)) == ATAC_CAP_DATA32) { 375 ata_channel_lock(chp); 376 chp->ch_drive[i].drive_flags |= ATA_DRIVE_CAP32; 377 ata_channel_unlock(chp); 378 } 379 if (chp->ch_drive[i].drive_type == ATA_DRIVET_NONE) 380 continue; 381 382 /* Shortcut in case we've been shutdown */ 383 if (chp->ch_flags & ATACH_SHUTDOWN) 384 return; 385 386 /* 387 * Issue an identify, to try to detect ghosts. 388 * Note that we can't use interrupts here, because if there 389 * is no devices, we will get a command aborted without 390 * interrupts. 391 */ 392 error = ata_get_params(&chp->ch_drive[i], 393 AT_WAIT | AT_POLL, ¶ms); 394 if (error != CMD_OK) { 395 ata_channel_lock(chp); 396 ata_delay(chp, 1000, "atacnf", AT_WAIT); 397 ata_channel_unlock(chp); 398 399 /* Shortcut in case we've been shutdown */ 400 if (chp->ch_flags & ATACH_SHUTDOWN) 401 return; 402 403 error = ata_get_params(&chp->ch_drive[i], 404 AT_WAIT | AT_POLL, ¶ms); 405 } 406 if (error != CMD_OK) { 407 ATADEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 408 device_xname(atac->atac_dev), 409 chp->ch_channel, i, error), DEBUG_PROBE); 410 ata_channel_lock(chp); 411 if (chp->ch_drive[i].drive_type != ATA_DRIVET_ATA || 412 (wdc->cap & WDC_CAPABILITY_PREATA) == 0) { 413 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 414 ata_channel_unlock(chp); 415 continue; 416 } 417 /* 418 * Pre-ATA drive ? 419 * Test registers writability (Error register not 420 * writable, but cyllo is), then try an ATA command. 421 */ 422 if (wdc->select) 423 wdc->select(chp,i); 424 bus_space_write_1(wdr->cmd_iot, 425 wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM | (i << 4)); 426 delay(10); /* 400ns delay */ 427 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 428 0, 0x58); 429 bus_space_write_1(wdr->cmd_iot, 430 wdr->cmd_iohs[wd_cyl_lo], 0, 0xa5); 431 if (bus_space_read_1(wdr->cmd_iot, 432 wdr->cmd_iohs[wd_error], 0) == 0x58 || 433 bus_space_read_1(wdr->cmd_iot, 434 wdr->cmd_iohs[wd_cyl_lo], 0) != 0xa5) { 435 ATADEBUG_PRINT(("%s:%d:%d: register " 436 "writability failed\n", 437 device_xname(atac->atac_dev), 438 chp->ch_channel, i), DEBUG_PROBE); 439 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 440 ata_channel_unlock(chp); 441 continue; 442 } 443 if (wdc_wait_for_ready(chp, 10000, 0, &tfd) == 444 WDCWAIT_TOUT) { 445 ATADEBUG_PRINT(("%s:%d:%d: not ready\n", 446 device_xname(atac->atac_dev), 447 chp->ch_channel, i), DEBUG_PROBE); 448 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 449 ata_channel_unlock(chp); 450 continue; 451 } 452 bus_space_write_1(wdr->cmd_iot, 453 wdr->cmd_iohs[wd_command], 0, WDCC_RECAL); 454 delay(10); /* 400ns delay */ 455 if (wdc_wait_for_ready(chp, 10000, 0, &tfd) == 456 WDCWAIT_TOUT) { 457 ATADEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 458 device_xname(atac->atac_dev), 459 chp->ch_channel, i), DEBUG_PROBE); 460 chp->ch_drive[i].drive_type = ATA_DRIVET_NONE; 461 ata_channel_unlock(chp); 462 } else { 463 for (j = 0; j < chp->ch_ndrives; j++) { 464 if (chp->ch_drive[i].drive_type != 465 ATA_DRIVET_NONE) { 466 chp->ch_drive[j].drive_type = 467 ATA_DRIVET_OLD; 468 } 469 } 470 ata_channel_unlock(chp); 471 } 472 } 473 } 474 } 475 476 int 477 wdcprobe(struct wdc_regs *wdr) 478 { 479 struct wdc_softc wdc; 480 struct ata_channel ch; 481 int rv; 482 483 memset(&wdc, 0, sizeof(wdc)); 484 memset(&ch, 0, sizeof(ch)); 485 ata_channel_init(&ch); 486 ch.ch_atac = &wdc.sc_atac; 487 wdc.regs = wdr; 488 489 /* default reset method */ 490 if (wdc.reset == NULL) 491 wdc.reset = wdc_do_reset; 492 493 rv = wdcprobe1(&ch, 1); 494 495 ata_channel_destroy(&ch); 496 497 return rv; 498 } 499 500 static int 501 wdcprobe1(struct ata_channel *chp, int poll) 502 { 503 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 504 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 505 u_int8_t st0 = 0, st1 = 0, sc __unused, sn __unused, cl, ch; 506 u_int8_t ret_value = 0x03; 507 u_int8_t drive; 508 /* XXX if poll, wdc_probe_count is 0. */ 509 int wdc_probe_count = 510 poll ? (WDC_PROBE_WAIT / WDCDELAY) 511 : (WDC_PROBE_WAIT * hz); 512 513 /* 514 * Sanity check to see if the wdc channel responds at all. 515 */ 516 517 ata_channel_lock(chp); 518 if ((wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 519 while (wdc_probe_count-- > 0) { 520 if (wdc->select) 521 wdc->select(chp,0); 522 523 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 524 0, WDSD_IBM); 525 delay(10); /* 400ns delay */ 526 st0 = bus_space_read_1(wdr->cmd_iot, 527 wdr->cmd_iohs[wd_status], 0); 528 529 if (wdc->select) 530 wdc->select(chp,1); 531 532 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 533 0, WDSD_IBM | 0x10); 534 delay(10); /* 400ns delay */ 535 st1 = bus_space_read_1(wdr->cmd_iot, 536 wdr->cmd_iohs[wd_status], 0); 537 if ((st0 & WDCS_BSY) == 0) 538 break; 539 } 540 541 ATADEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 542 __func__, chp->ch_channel, st0, st1), DEBUG_PROBE); 543 544 if (st0 == 0xff || st0 == WDSD_IBM) 545 ret_value &= ~0x01; 546 if (st1 == 0xff || st1 == (WDSD_IBM | 0x10)) 547 ret_value &= ~0x02; 548 /* Register writability test, drive 0. */ 549 if (ret_value & 0x01) { 550 if (wdc->select) 551 wdc->select(chp,0); 552 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 553 0, WDSD_IBM); 554 bus_space_write_1(wdr->cmd_iot, 555 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 556 cl = bus_space_read_1(wdr->cmd_iot, 557 wdr->cmd_iohs[wd_cyl_lo], 0); 558 if (cl != 0x02) { 559 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 560 "got 0x%x != 0x02\n", 561 __func__, chp->ch_channel, cl), 562 DEBUG_PROBE); 563 ret_value &= ~0x01; 564 } 565 bus_space_write_1(wdr->cmd_iot, 566 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 567 cl = bus_space_read_1(wdr->cmd_iot, 568 wdr->cmd_iohs[wd_cyl_lo], 0); 569 if (cl != 0x01) { 570 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo: " 571 "got 0x%x != 0x01\n", 572 __func__, chp->ch_channel, cl), 573 DEBUG_PROBE); 574 ret_value &= ~0x01; 575 } 576 bus_space_write_1(wdr->cmd_iot, 577 wdr->cmd_iohs[wd_sector], 0, 0x01); 578 cl = bus_space_read_1(wdr->cmd_iot, 579 wdr->cmd_iohs[wd_sector], 0); 580 if (cl != 0x01) { 581 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 582 "got 0x%x != 0x01\n", 583 __func__, chp->ch_channel, cl), 584 DEBUG_PROBE); 585 ret_value &= ~0x01; 586 } 587 bus_space_write_1(wdr->cmd_iot, 588 wdr->cmd_iohs[wd_sector], 0, 0x02); 589 cl = bus_space_read_1(wdr->cmd_iot, 590 wdr->cmd_iohs[wd_sector], 0); 591 if (cl != 0x02) { 592 ATADEBUG_PRINT(("%s:%d drive 0 wd_sector: " 593 "got 0x%x != 0x02\n", 594 __func__, chp->ch_channel, cl), 595 DEBUG_PROBE); 596 ret_value &= ~0x01; 597 } 598 cl = bus_space_read_1(wdr->cmd_iot, 599 wdr->cmd_iohs[wd_cyl_lo], 0); 600 if (cl != 0x01) { 601 ATADEBUG_PRINT(("%s:%d drive 0 wd_cyl_lo(2): " 602 "got 0x%x != 0x01\n", 603 __func__, chp->ch_channel, cl), 604 DEBUG_PROBE); 605 ret_value &= ~0x01; 606 } 607 } 608 /* Register writability test, drive 1. */ 609 if (ret_value & 0x02) { 610 if (wdc->select) 611 wdc->select(chp,1); 612 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 613 0, WDSD_IBM | 0x10); 614 bus_space_write_1(wdr->cmd_iot, 615 wdr->cmd_iohs[wd_cyl_lo], 0, 0x02); 616 cl = bus_space_read_1(wdr->cmd_iot, 617 wdr->cmd_iohs[wd_cyl_lo], 0); 618 if (cl != 0x02) { 619 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 620 "got 0x%x != 0x02\n", 621 __func__, chp->ch_channel, cl), 622 DEBUG_PROBE); 623 ret_value &= ~0x02; 624 } 625 bus_space_write_1(wdr->cmd_iot, 626 wdr->cmd_iohs[wd_cyl_lo], 0, 0x01); 627 cl = bus_space_read_1(wdr->cmd_iot, 628 wdr->cmd_iohs[wd_cyl_lo], 0); 629 if (cl != 0x01) { 630 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo: " 631 "got 0x%x != 0x01\n", 632 __func__, chp->ch_channel, cl), 633 DEBUG_PROBE); 634 ret_value &= ~0x02; 635 } 636 bus_space_write_1(wdr->cmd_iot, 637 wdr->cmd_iohs[wd_sector], 0, 0x01); 638 cl = bus_space_read_1(wdr->cmd_iot, 639 wdr->cmd_iohs[wd_sector], 0); 640 if (cl != 0x01) { 641 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 642 "got 0x%x != 0x01\n", 643 __func__, chp->ch_channel, cl), 644 DEBUG_PROBE); 645 ret_value &= ~0x02; 646 } 647 bus_space_write_1(wdr->cmd_iot, 648 wdr->cmd_iohs[wd_sector], 0, 0x02); 649 cl = bus_space_read_1(wdr->cmd_iot, 650 wdr->cmd_iohs[wd_sector], 0); 651 if (cl != 0x02) { 652 ATADEBUG_PRINT(("%s:%d drive 1 wd_sector: " 653 "got 0x%x != 0x02\n", 654 __func__, chp->ch_channel, cl), 655 DEBUG_PROBE); 656 ret_value &= ~0x02; 657 } 658 cl = bus_space_read_1(wdr->cmd_iot, 659 wdr->cmd_iohs[wd_cyl_lo], 0); 660 if (cl != 0x01) { 661 ATADEBUG_PRINT(("%s:%d drive 1 wd_cyl_lo(2): " 662 "got 0x%x != 0x01\n", 663 __func__, chp->ch_channel, cl), 664 DEBUG_PROBE); 665 ret_value &= ~0x02; 666 } 667 } 668 669 if (ret_value == 0) { 670 ata_channel_unlock(chp); 671 return 0; 672 } 673 } 674 675 #if 0 /* XXX this break some ATA or ATAPI devices */ 676 /* 677 * reset bus. Also send an ATAPI_RESET to devices, in case there are 678 * ATAPI device out there which don't react to the bus reset 679 */ 680 if (ret_value & 0x01) { 681 if (wdc->select) 682 wdc->select(chp,0); 683 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 684 0, WDSD_IBM); 685 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 686 ATAPI_SOFT_RESET); 687 } 688 if (ret_value & 0x02) { 689 if (wdc->select) 690 wdc->select(chp,0); 691 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 692 0, WDSD_IBM | 0x10); 693 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, 694 ATAPI_SOFT_RESET); 695 } 696 697 delay(5000); 698 #endif 699 700 wdc->reset(chp, RESET_POLL); 701 DELAY(2000); 702 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 703 704 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 705 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 706 WDCTL_4BIT); 707 708 #ifdef WDC_NO_IDS 709 ret_value = __wdcwait_reset(chp, ret_value, RESET_POLL); 710 #else 711 ret_value = __wdcwait_reset(chp, ret_value, poll); 712 #endif 713 ATADEBUG_PRINT(("%s:%d: after reset, ret_value=%#x\n", 714 __func__, chp->ch_channel, ret_value), DEBUG_PROBE); 715 716 /* if reset failed, there's nothing here */ 717 if (ret_value == 0) { 718 ata_channel_unlock(chp); 719 return 0; 720 } 721 722 /* 723 * Test presence of drives. First test register signatures looking 724 * for ATAPI devices. If it's not an ATAPI and reset said there may 725 * be something here assume it's ATA or OLD. Ghost will be killed 726 * later in attach routine. 727 */ 728 for (drive = 0; drive < wdc->wdc_maxdrives; drive++) { 729 if ((ret_value & (0x01 << drive)) == 0) 730 continue; 731 if (wdc->select) 732 wdc->select(chp,drive); 733 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 734 WDSD_IBM | (drive << 4)); 735 delay(10); /* 400ns delay */ 736 /* Save registers contents */ 737 sc = bus_space_read_1(wdr->cmd_iot, 738 wdr->cmd_iohs[wd_seccnt], 0); 739 sn = bus_space_read_1(wdr->cmd_iot, 740 wdr->cmd_iohs[wd_sector], 0); 741 cl = bus_space_read_1(wdr->cmd_iot, 742 wdr->cmd_iohs[wd_cyl_lo], 0); 743 ch = bus_space_read_1(wdr->cmd_iot, 744 wdr->cmd_iohs[wd_cyl_hi], 0); 745 746 ATADEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 747 "cl=0x%x ch=0x%x\n", __func__, chp->ch_channel, drive, sc, 748 sn, cl, ch), DEBUG_PROBE); 749 /* 750 * sc & sn are supposed to be 0x1 for ATAPI but in some cases 751 * we get wrong values here, so ignore it. 752 */ 753 if (chp->ch_drive != NULL) { 754 if (cl == 0x14 && ch == 0xeb) { 755 chp->ch_drive[drive].drive_type = ATA_DRIVET_ATAPI; 756 } else { 757 chp->ch_drive[drive].drive_type = ATA_DRIVET_ATA; 758 } 759 } 760 } 761 /* 762 * Select an existing drive before lowering spl, some WDC_NO_IDS 763 * devices incorrectly assert IRQ on nonexistent slave 764 */ 765 if (ret_value & 0x01) { 766 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 767 WDSD_IBM); 768 (void)bus_space_read_1(wdr->cmd_iot, 769 wdr->cmd_iohs[wd_status], 0); 770 } 771 ata_channel_unlock(chp); 772 return (ret_value); 773 } 774 775 void 776 wdcattach(struct ata_channel *chp) 777 { 778 struct atac_softc *atac = chp->ch_atac; 779 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 780 781 KASSERT(wdc->wdc_maxdrives > 0 && wdc->wdc_maxdrives <= WDC_MAXDRIVES); 782 783 /* default data transfer methods */ 784 if (wdc->datain_pio == NULL) 785 wdc->datain_pio = wdc_datain_pio; 786 if (wdc->dataout_pio == NULL) 787 wdc->dataout_pio = wdc_dataout_pio; 788 /* default reset method */ 789 if (wdc->reset == NULL) 790 wdc->reset = wdc_do_reset; 791 792 /* initialise global data */ 793 if (atac->atac_bustype_ata == NULL) 794 atac->atac_bustype_ata = &wdc_ata_bustype; 795 if (atac->atac_probe == NULL) 796 atac->atac_probe = wdc_drvprobe; 797 #if NATAPIBUS > 0 798 if (atac->atac_atapibus_attach == NULL) 799 atac->atac_atapibus_attach = wdc_atapibus_attach; 800 #endif 801 802 ata_channel_attach(chp); 803 } 804 805 void 806 wdc_childdetached(device_t self, device_t child) 807 { 808 struct atac_softc *atac = device_private(self); 809 struct ata_channel *chp; 810 int i; 811 812 for (i = 0; i < atac->atac_nchannels; i++) { 813 chp = atac->atac_channels[i]; 814 if (child == chp->atabus) { 815 chp->atabus = NULL; 816 return; 817 } 818 } 819 } 820 821 int 822 wdcdetach(device_t self, int flags) 823 { 824 struct atac_softc *atac = device_private(self); 825 struct ata_channel *chp; 826 struct scsipi_adapter *adapt = &atac->atac_atapi_adapter._generic; 827 int i, error = 0; 828 829 for (i = 0; i < atac->atac_nchannels; i++) { 830 chp = atac->atac_channels[i]; 831 if (chp->atabus == NULL) 832 continue; 833 ATADEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 834 device_xname(atac->atac_dev), device_xname(chp->atabus)), 835 DEBUG_DETACH); 836 if ((error = config_detach(chp->atabus, flags)) != 0) 837 return error; 838 ata_channel_detach(chp); 839 } 840 if (adapt->adapt_refcnt != 0) 841 return EBUSY; 842 return 0; 843 } 844 845 /* restart an interrupted I/O */ 846 void 847 wdcrestart(void *v) 848 { 849 struct ata_channel *chp = v; 850 int s; 851 852 s = splbio(); 853 atastart(chp); 854 splx(s); 855 } 856 857 858 /* 859 * Interrupt routine for the controller. Acknowledge the interrupt, check for 860 * errors on the current operation, mark it done if necessary, and start the 861 * next request. Also check for a partially done transfer, and continue with 862 * the next chunk if so. 863 */ 864 int 865 wdcintr(void *arg) 866 { 867 struct ata_channel *chp = arg; 868 struct atac_softc *atac = chp->ch_atac; 869 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 870 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 871 struct ata_xfer *xfer; 872 int ret; 873 874 if (!device_is_active(atac->atac_dev)) { 875 ATADEBUG_PRINT(("wdcintr: deactivated controller\n"), 876 DEBUG_INTR); 877 return (0); 878 } 879 880 if ((chp->ch_flags & ATACH_IRQ_WAIT) == 0) { 881 ATADEBUG_PRINT(("wdcintr: irq not expected\n"), DEBUG_INTR); 882 goto ignore; 883 } 884 885 xfer = ata_queue_get_active_xfer(chp); 886 if (xfer == NULL) { 887 ATADEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 888 ignore: 889 /* try to clear the pending interrupt anyway */ 890 (void)bus_space_read_1(wdr->cmd_iot, 891 wdr->cmd_iohs[wd_status], 0); 892 return (0); 893 } 894 895 /* 896 * On some controllers (e.g. some PCI-IDE) setting the WDCTL_IDS bit 897 * actually has no effect, and interrupt is triggered regardless. 898 * Ignore polled commands here, they are processed separately. 899 */ 900 if (ISSET(xfer->c_flags, C_POLL)) { 901 ATADEBUG_PRINT(("%s: polled xfer ignored\n", __func__), 902 DEBUG_INTR); 903 goto ignore; 904 } 905 906 ATADEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 907 KASSERT(xfer != NULL); 908 909 #if NATA_DMA || NATA_PIOBM 910 if (chp->ch_flags & ATACH_DMA_WAIT) { 911 wdc->dma_status = 912 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 913 xfer->c_drive, WDC_DMAEND_END); 914 if (wdc->dma_status & WDC_DMAST_NOIRQ) { 915 /* IRQ not for us, not detected by DMA engine */ 916 return 0; 917 } 918 chp->ch_flags &= ~ATACH_DMA_WAIT; 919 } 920 #endif 921 chp->ch_flags &= ~ATACH_IRQ_WAIT; 922 KASSERT(xfer->c_intr != NULL); 923 ret = xfer->c_intr(chp, xfer, 1); 924 if (ret == 0) /* irq was not for us, still waiting for irq */ 925 chp->ch_flags |= ATACH_IRQ_WAIT; 926 return (ret); 927 } 928 929 /* Put all disk in RESET state */ 930 void 931 wdc_reset_drive(struct ata_drive_datas *drvp, int flags, uint32_t *sigp) 932 { 933 struct ata_channel *chp = drvp->chnl_softc; 934 935 KASSERT(sigp == NULL); 936 937 ATADEBUG_PRINT(("wdc_reset_drive %s:%d for drive %d\n", 938 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 939 drvp->drive), DEBUG_FUNCS); 940 941 ata_reset_channel(chp, flags); 942 } 943 944 void 945 wdc_reset_channel(struct ata_channel *chp, int flags) 946 { 947 struct ata_xfer *xfer; 948 #if NATA_DMA || NATA_PIOBM 949 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 950 #endif 951 952 chp->ch_flags &= ~ATACH_IRQ_WAIT; 953 954 /* 955 * if the current command is on an ATAPI device, issue a 956 * ATAPI_SOFT_RESET 957 */ 958 xfer = ata_queue_get_active_xfer(chp); 959 960 ata_channel_lock(chp); 961 962 if (xfer && xfer->c_chp == chp && (xfer->c_flags & C_ATAPI)) { 963 wdccommandshort(chp, xfer->c_drive, ATAPI_SOFT_RESET); 964 ata_delay(chp, 1000, "atardl", flags); 965 } 966 967 /* reset the channel */ 968 if (flags & AT_WAIT) 969 (void) wdcreset(chp, RESET_SLEEP); 970 else 971 (void) wdcreset(chp, RESET_POLL); 972 973 /* 974 * wait a bit after reset; in case the DMA engines needs some time 975 * to recover. 976 */ 977 ata_delay(chp, 1000, "atardl", flags); 978 979 /* 980 * Look for pending xfers. If we have a shared queue, we'll also reset 981 * the other channel if the current xfer is running on it. 982 * Then we'll kill the eventual active transfer explicitely, so that 983 * it is queued for retry immediatelly without waiting for I/O timeout. 984 */ 985 if (xfer) { 986 if (xfer->c_chp != chp) { 987 ata_channel_unlock(chp); 988 ata_reset_channel(xfer->c_chp, flags); 989 ata_channel_lock(chp); 990 } else { 991 #if NATA_DMA || NATA_PIOBM 992 /* 993 * If we're waiting for DMA, stop the 994 * DMA engine 995 */ 996 if (chp->ch_flags & ATACH_DMA_WAIT) { 997 (*wdc->dma_finish)(wdc->dma_arg, 998 chp->ch_channel, xfer->c_drive, 999 WDC_DMAEND_ABRT_QUIET); 1000 chp->ch_flags &= ~ATACH_DMA_WAIT; 1001 } 1002 #endif 1003 } 1004 } 1005 1006 ata_kill_active(chp, KILL_RESET, flags); 1007 1008 ata_channel_unlock(chp); 1009 } 1010 1011 static int 1012 wdcreset(struct ata_channel *chp, int poll) 1013 { 1014 struct atac_softc *atac = chp->ch_atac; 1015 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1016 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1017 int drv_mask1, drv_mask2; 1018 1019 ata_channel_lock_owned(chp); 1020 1021 #ifdef WDC_NO_IDS 1022 poll = RESET_POLL; 1023 #endif 1024 wdc->reset(chp, poll); 1025 1026 drv_mask1 = (chp->ch_drive[0].drive_type != ATA_DRIVET_NONE) 1027 ? 0x01 : 0x00; 1028 if (chp->ch_ndrives > 1) 1029 drv_mask1 |= (chp->ch_drive[1].drive_type != ATA_DRIVET_NONE) 1030 ? 0x02 : 0x00; 1031 drv_mask2 = __wdcwait_reset(chp, drv_mask1, 1032 (poll == RESET_SLEEP) ? 0 : 1); 1033 if (drv_mask2 != drv_mask1) { 1034 aprint_error("%s channel %d: reset failed for", 1035 device_xname(atac->atac_dev), chp->ch_channel); 1036 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 1037 aprint_normal(" drive 0"); 1038 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 1039 aprint_normal(" drive 1"); 1040 aprint_normal("\n"); 1041 } 1042 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1043 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1044 WDCTL_4BIT); 1045 1046 return (drv_mask1 != drv_mask2) ? 1 : 0; 1047 } 1048 1049 void 1050 wdc_do_reset(struct ata_channel *chp, int poll) 1051 { 1052 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1053 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1054 int s = 0; 1055 1056 if (poll != RESET_SLEEP) 1057 s = splbio(); 1058 if (wdc->select) 1059 wdc->select(chp,0); 1060 /* master */ 1061 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, WDSD_IBM); 1062 delay(10); /* 400ns delay */ 1063 /* assert SRST, wait for reset to complete */ 1064 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1065 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1066 WDCTL_RST | WDCTL_IDS | WDCTL_4BIT); 1067 delay(2000); 1068 } 1069 (void) bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_error], 0); 1070 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1071 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, wd_aux_ctlr, 1072 WDCTL_4BIT | WDCTL_IDS); 1073 delay(10); /* 400ns delay */ 1074 if (poll != RESET_SLEEP) { 1075 /* ACK interrupt in case there is one pending left */ 1076 if (wdc->irqack) 1077 wdc->irqack(chp); 1078 splx(s); 1079 } 1080 } 1081 1082 static int 1083 __wdcwait_reset(struct ata_channel *chp, int drv_mask, int poll) 1084 { 1085 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1086 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1087 int timeout, nloop; 1088 int wflags = poll ? AT_POLL : AT_WAIT; 1089 u_int8_t st0 = 0, st1 = 0; 1090 #ifdef ATADEBUG 1091 u_int8_t sc0 = 0, sn0 = 0, cl0 = 0, ch0 = 0; 1092 u_int8_t sc1 = 0, sn1 = 0, cl1 = 0, ch1 = 0; 1093 #endif 1094 if (poll) 1095 nloop = WDCNDELAY_RST; 1096 else 1097 nloop = WDC_RESET_WAIT * hz / 1000; 1098 /* wait for BSY to deassert */ 1099 for (timeout = 0; timeout < nloop; timeout++) { 1100 if ((drv_mask & 0x01) != 0) { 1101 if (wdc->select) 1102 wdc->select(chp,0); 1103 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1104 0, WDSD_IBM); /* master */ 1105 delay(10); 1106 st0 = bus_space_read_1(wdr->cmd_iot, 1107 wdr->cmd_iohs[wd_status], 0); 1108 #ifdef ATADEBUG 1109 sc0 = bus_space_read_1(wdr->cmd_iot, 1110 wdr->cmd_iohs[wd_seccnt], 0); 1111 sn0 = bus_space_read_1(wdr->cmd_iot, 1112 wdr->cmd_iohs[wd_sector], 0); 1113 cl0 = bus_space_read_1(wdr->cmd_iot, 1114 wdr->cmd_iohs[wd_cyl_lo], 0); 1115 ch0 = bus_space_read_1(wdr->cmd_iot, 1116 wdr->cmd_iohs[wd_cyl_hi], 0); 1117 #endif 1118 } 1119 if ((drv_mask & 0x02) != 0) { 1120 if (wdc->select) 1121 wdc->select(chp,1); 1122 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 1123 0, WDSD_IBM | 0x10); /* slave */ 1124 delay(10); 1125 st1 = bus_space_read_1(wdr->cmd_iot, 1126 wdr->cmd_iohs[wd_status], 0); 1127 #ifdef ATADEBUG 1128 sc1 = bus_space_read_1(wdr->cmd_iot, 1129 wdr->cmd_iohs[wd_seccnt], 0); 1130 sn1 = bus_space_read_1(wdr->cmd_iot, 1131 wdr->cmd_iohs[wd_sector], 0); 1132 cl1 = bus_space_read_1(wdr->cmd_iot, 1133 wdr->cmd_iohs[wd_cyl_lo], 0); 1134 ch1 = bus_space_read_1(wdr->cmd_iot, 1135 wdr->cmd_iohs[wd_cyl_hi], 0); 1136 #endif 1137 } 1138 1139 if ((drv_mask & 0x01) == 0) { 1140 /* no master */ 1141 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 1142 /* No master, slave is ready, it's done */ 1143 goto end; 1144 } 1145 if ((drv_mask & 0x02) == 0) { 1146 /* No master, no slave: it's done */ 1147 goto end; 1148 } 1149 } else if ((drv_mask & 0x02) == 0) { 1150 /* no slave */ 1151 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 1152 /* No slave, master is ready, it's done */ 1153 goto end; 1154 } 1155 } else { 1156 /* Wait for both master and slave to be ready */ 1157 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 1158 goto end; 1159 } 1160 } 1161 ata_delay(chp, WDCDELAY, "atarst", wflags); 1162 } 1163 /* Reset timed out. Maybe it's because drv_mask was not right */ 1164 if (st0 & WDCS_BSY) 1165 drv_mask &= ~0x01; 1166 if (st1 & WDCS_BSY) 1167 drv_mask &= ~0x02; 1168 end: 1169 ATADEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 1170 "cl=0x%x ch=0x%x\n", 1171 device_xname(chp->ch_atac->atac_dev), 1172 chp->ch_channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 1173 ATADEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 1174 "cl=0x%x ch=0x%x\n", 1175 device_xname(chp->ch_atac->atac_dev), 1176 chp->ch_channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 1177 1178 ATADEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x st1=0x%x\n", 1179 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1180 st0, st1), DEBUG_PROBE); 1181 1182 return drv_mask; 1183 } 1184 1185 /* 1186 * Wait for a drive to be !BSY, and have mask in its status register. 1187 * return -1 for a timeout after "timeout" ms. 1188 */ 1189 static int 1190 __wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int *tfd) 1191 { 1192 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1193 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1194 u_char status, error = 0; 1195 int xtime = 0; 1196 int rv; 1197 1198 ATADEBUG_PRINT(("__wdcwait %s:%d\n", 1199 device_xname(chp->ch_atac->atac_dev), 1200 chp->ch_channel), DEBUG_STATUS); 1201 *tfd = 0; 1202 1203 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 1204 1205 for (;;) { 1206 status = 1207 bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_status], 0); 1208 if ((status & (WDCS_BSY | mask)) == bits) 1209 break; 1210 if (++xtime > timeout) { 1211 ATADEBUG_PRINT(("__wdcwait: timeout (time=%d), " 1212 "status %x error %x (mask 0x%x bits 0x%x)\n", 1213 xtime, status, 1214 bus_space_read_1(wdr->cmd_iot, 1215 wdr->cmd_iohs[wd_error], 0), mask, bits), 1216 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 1217 rv = WDCWAIT_TOUT; 1218 goto out; 1219 } 1220 delay(WDCDELAY); 1221 } 1222 #ifdef ATADEBUG 1223 if (xtime > 0 && (atadebug_mask & DEBUG_DELAY)) 1224 printf("__wdcwait: did busy-wait, time=%d\n", xtime); 1225 #endif 1226 if (status & WDCS_ERR) 1227 error = bus_space_read_1(wdr->cmd_iot, 1228 wdr->cmd_iohs[wd_error], 0); 1229 #ifdef WDCNDELAY_DEBUG 1230 /* After autoconfig, there should be no long delays. */ 1231 if (!cold && xtime > WDCNDELAY_DEBUG) { 1232 struct ata_xfer *xfer; 1233 1234 xfer = ata_queue_get_active_xfer(chp); 1235 if (xfer == NULL) 1236 printf("%s channel %d: warning: busy-wait took %dus\n", 1237 device_xname(chp->ch_atac->atac_dev), 1238 chp->ch_channel, WDCDELAY * xtime); 1239 else 1240 printf("%s:%d:%d: warning: busy-wait took %dus\n", 1241 device_xname(chp->ch_atac->atac_dev), 1242 chp->ch_channel, xfer->c_drive, 1243 WDCDELAY * xtime); 1244 } 1245 #endif 1246 rv = WDCWAIT_OK; 1247 1248 out: 1249 *tfd = ATACH_ERR_ST(error, status); 1250 return rv; 1251 } 1252 1253 /* 1254 * Call __wdcwait(), polling using kpause() or waking up the kernel 1255 * thread if possible 1256 */ 1257 int 1258 wdcwait(struct ata_channel *chp, int mask, int bits, int timeout, int flags, 1259 int *tfd) 1260 { 1261 int error, i, timeout_hz = mstohz(timeout); 1262 1263 ata_channel_lock_owned(chp); 1264 1265 if (timeout_hz == 0 || 1266 (flags & (AT_WAIT | AT_POLL)) == AT_POLL) 1267 error = __wdcwait(chp, mask, bits, timeout, tfd); 1268 else { 1269 error = __wdcwait(chp, mask, bits, WDCDELAY_POLL, tfd); 1270 if (error != 0) { 1271 if ((chp->ch_flags & ATACH_TH_RUN) || 1272 (flags & AT_WAIT)) { 1273 /* 1274 * we're running in the channel thread 1275 * or some userland thread context 1276 */ 1277 for (i = 0; i < timeout_hz; i++) { 1278 if (__wdcwait(chp, mask, bits, 1279 WDCDELAY_POLL, tfd) == 0) { 1280 error = 0; 1281 break; 1282 } 1283 kpause("atapoll", true, 1, 1284 &chp->ch_lock); 1285 } 1286 } else { 1287 /* 1288 * we're probably in interrupt context, 1289 * caller must ask the thread to come back here 1290 */ 1291 return(WDCWAIT_THR); 1292 } 1293 } 1294 } 1295 return (error); 1296 } 1297 1298 1299 #if NATA_DMA 1300 /* 1301 * Busy-wait for DMA to complete 1302 */ 1303 int 1304 wdc_dmawait(struct ata_channel *chp, struct ata_xfer *xfer, int timeout) 1305 { 1306 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1307 int xtime; 1308 1309 for (xtime = 0; xtime < timeout * 1000 / WDCDELAY; xtime++) { 1310 wdc->dma_status = 1311 (*wdc->dma_finish)(wdc->dma_arg, 1312 chp->ch_channel, xfer->c_drive, WDC_DMAEND_END); 1313 if ((wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 1314 return 0; 1315 delay(WDCDELAY); 1316 } 1317 /* timeout, force a DMA halt */ 1318 wdc->dma_status = (*wdc->dma_finish)(wdc->dma_arg, 1319 chp->ch_channel, xfer->c_drive, WDC_DMAEND_ABRT); 1320 return 1; 1321 } 1322 #endif 1323 1324 void 1325 wdctimeout(void *arg) 1326 { 1327 struct ata_xfer *xfer = arg; 1328 struct ata_channel *chp = xfer->c_chp; 1329 #if NATA_DMA || NATA_PIOBM 1330 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1331 #endif 1332 int s; 1333 1334 ATADEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 1335 1336 s = splbio(); 1337 KASSERT(xfer != NULL); 1338 1339 if (ata_timo_xfer_check(xfer)) { 1340 /* Already logged */ 1341 goto out; 1342 } 1343 1344 __wdcerror(chp, "lost interrupt"); 1345 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 1346 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 1347 xfer->c_bcount, xfer->c_skip); 1348 #if NATA_DMA || NATA_PIOBM 1349 if (chp->ch_flags & ATACH_DMA_WAIT) { 1350 wdc->dma_status = 1351 (*wdc->dma_finish)(wdc->dma_arg, chp->ch_channel, 1352 xfer->c_drive, WDC_DMAEND_ABRT); 1353 chp->ch_flags &= ~ATACH_DMA_WAIT; 1354 } 1355 #endif 1356 /* 1357 * Call the interrupt routine. If we just missed an interrupt, 1358 * it will do what's needed. Else, it will take the needed 1359 * action (reset the device). 1360 * Before that we need to reinstall the timeout callback, 1361 * in case it will miss another irq while in this transfer 1362 * We arbitray chose it to be 1s 1363 */ 1364 callout_reset(&xfer->c_timo_callout, hz, wdctimeout, xfer); 1365 xfer->c_flags |= C_TIMEOU; 1366 KASSERT(xfer->c_intr != NULL); 1367 xfer->c_intr(chp, xfer, 1); 1368 1369 out: 1370 splx(s); 1371 } 1372 1373 int 1374 wdc_exec_command(struct ata_drive_datas *drvp, struct ata_xfer *xfer) 1375 { 1376 struct ata_channel *chp = drvp->chnl_softc; 1377 struct ata_command *ata_c = &xfer->c_ata_c; 1378 int s, ret; 1379 1380 ATADEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1381 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1382 drvp->drive), DEBUG_FUNCS); 1383 1384 /* set up an xfer and queue. Wait for completion */ 1385 if (chp->ch_atac->atac_cap & ATAC_CAP_NOIRQ) 1386 ata_c->flags |= AT_POLL; 1387 if (ata_c->flags & AT_POLL) 1388 xfer->c_flags |= C_POLL; 1389 if (ata_c->flags & AT_WAIT) 1390 xfer->c_flags |= C_WAIT; 1391 xfer->c_drive = drvp->drive; 1392 xfer->c_databuf = ata_c->data; 1393 xfer->c_bcount = ata_c->bcount; 1394 xfer->c_start = __wdccommand_start; 1395 xfer->c_poll = __wdccommand_poll; 1396 xfer->c_abort = __wdccommand_done; 1397 xfer->c_intr = __wdccommand_intr; 1398 xfer->c_kill_xfer = __wdccommand_kill_xfer; 1399 1400 s = splbio(); 1401 ata_exec_xfer(chp, xfer); 1402 #ifdef DIAGNOSTIC 1403 if ((ata_c->flags & AT_POLL) != 0 && 1404 (ata_c->flags & AT_DONE) == 0) 1405 panic("wdc_exec_command: polled command not done"); 1406 #endif 1407 if (ata_c->flags & AT_DONE) { 1408 ret = ATACMD_COMPLETE; 1409 } else { 1410 if (ata_c->flags & AT_WAIT) { 1411 ata_channel_lock(chp); 1412 if ((ata_c->flags & AT_DONE) == 0) { 1413 ata_wait_xfer(chp, xfer); 1414 KASSERT((ata_c->flags & AT_DONE) != 0); 1415 } 1416 ata_channel_unlock(chp); 1417 ret = ATACMD_COMPLETE; 1418 } else { 1419 ret = ATACMD_QUEUED; 1420 } 1421 } 1422 splx(s); 1423 return ret; 1424 } 1425 1426 static int 1427 __wdccommand_start(struct ata_channel *chp, struct ata_xfer *xfer) 1428 { 1429 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1430 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1431 int drive = xfer->c_drive; 1432 int wait_flags = (xfer->c_flags & C_POLL) ? AT_POLL : 0; 1433 struct ata_command *ata_c = &xfer->c_ata_c; 1434 int tfd; 1435 1436 ATADEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1437 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1438 xfer->c_drive), DEBUG_FUNCS); 1439 1440 if (wdc->select) 1441 wdc->select(chp,drive); 1442 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1443 WDSD_IBM | (drive << 4)); 1444 switch(wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1445 ata_c->r_st_bmask, ata_c->timeout, wait_flags, &tfd)) { 1446 case WDCWAIT_OK: 1447 break; 1448 case WDCWAIT_TOUT: 1449 ata_c->flags |= AT_TIMEOU; 1450 return ATASTART_ABORT; 1451 case WDCWAIT_THR: 1452 return ATASTART_TH; 1453 } 1454 if (ata_c->flags & AT_POLL) { 1455 /* polled command, disable interrupts */ 1456 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1457 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 1458 wd_aux_ctlr, WDCTL_4BIT | WDCTL_IDS); 1459 } 1460 if ((ata_c->flags & AT_LBA48) != 0) { 1461 wdccommandext(chp, drive, ata_c->r_command, 1462 ata_c->r_lba, ata_c->r_count, ata_c->r_features, 1463 ata_c->r_device & ~0x10); 1464 } else { 1465 wdccommand(chp, drive, ata_c->r_command, 1466 (ata_c->r_lba >> 8) & 0xffff, 1467 WDSD_IBM | (drive << 4) | 1468 (((ata_c->flags & AT_LBA) != 0) ? WDSD_LBA : 0) | 1469 ((ata_c->r_lba >> 24) & 0x0f), 1470 ata_c->r_lba & 0xff, 1471 ata_c->r_count & 0xff, 1472 ata_c->r_features & 0xff); 1473 } 1474 1475 if ((ata_c->flags & AT_POLL) == 0) { 1476 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1477 callout_reset(&xfer->c_timo_callout, ata_c->timeout / 1000 * hz, 1478 wdctimeout, xfer); 1479 return ATASTART_STARTED; 1480 } 1481 1482 /* 1483 * Polled command. Wait for drive ready or drq. Done in intr(). 1484 * Wait for at last 400ns for status bit to be valid. 1485 */ 1486 delay(10); /* 400ns delay */ 1487 return ATASTART_POLL; 1488 } 1489 1490 static void 1491 __wdccommand_poll(struct ata_channel *chp, struct ata_xfer *xfer) 1492 { 1493 __wdccommand_intr(chp, xfer, 0); 1494 } 1495 1496 static int 1497 __wdccommand_intr(struct ata_channel *chp, struct ata_xfer *xfer, int irq) 1498 { 1499 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1500 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1501 struct ata_command *ata_c = &xfer->c_ata_c; 1502 int bcount = ata_c->bcount; 1503 char *data = ata_c->data; 1504 int wflags, tfd; 1505 int drive_flags; 1506 1507 if (ata_c->r_command == WDCC_IDENTIFY || 1508 ata_c->r_command == ATAPI_IDENTIFY_DEVICE) { 1509 /* 1510 * The IDENTIFY data has been designed as an array of 1511 * u_int16_t, so we can byteswap it on the fly. 1512 * Historically it's what we have always done so keeping it 1513 * here ensure binary backward compatibility. 1514 */ 1515 drive_flags = ATA_DRIVE_NOSTREAM | 1516 chp->ch_drive[xfer->c_drive].drive_flags; 1517 } else { 1518 /* 1519 * Other data structure are opaque and should be transfered 1520 * as is. 1521 */ 1522 drive_flags = chp->ch_drive[xfer->c_drive].drive_flags; 1523 } 1524 1525 #ifdef WDC_NO_IDS 1526 wflags = AT_POLL; 1527 #else 1528 if ((ata_c->flags & (AT_WAIT | AT_POLL)) == (AT_WAIT | AT_POLL)) { 1529 /* both wait and poll, we can kpause here */ 1530 wflags = AT_WAIT | AT_POLL; 1531 } else { 1532 wflags = AT_POLL; 1533 } 1534 #endif 1535 1536 ata_channel_lock(chp); 1537 1538 again: 1539 ATADEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1540 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, 1541 xfer->c_drive), DEBUG_INTR); 1542 /* 1543 * after a ATAPI_SOFT_RESET, the device will have released the bus. 1544 * Reselect again, it doesn't hurt for others commands, and the time 1545 * penalty for the extra register write is acceptable, 1546 * wdc_exec_command() isn't called often (mostly for autoconfig) 1547 */ 1548 if ((xfer->c_flags & C_ATAPI) != 0) { 1549 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1550 WDSD_IBM | (xfer->c_drive << 4)); 1551 } 1552 if ((ata_c->flags & AT_XFDONE) != 0) { 1553 /* 1554 * We have completed a data xfer. The drive should now be 1555 * in its initial state 1556 */ 1557 if (wdcwait(chp, ata_c->r_st_bmask | WDCS_DRQ, 1558 ata_c->r_st_bmask, (irq == 0) ? ata_c->timeout : 0, 1559 wflags, &tfd) == WDCWAIT_TOUT) { 1560 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1561 ata_channel_unlock(chp); 1562 return 0; /* IRQ was not for us */ 1563 } 1564 ata_c->flags |= AT_TIMEOU; 1565 } 1566 goto out; 1567 } 1568 if (wdcwait(chp, ata_c->r_st_pmask, ata_c->r_st_pmask, 1569 (irq == 0) ? ata_c->timeout : 0, wflags, &tfd) == WDCWAIT_TOUT) { 1570 if (irq && (xfer->c_flags & C_TIMEOU) == 0) { 1571 ata_channel_unlock(chp); 1572 return 0; /* IRQ was not for us */ 1573 } 1574 ata_c->flags |= AT_TIMEOU; 1575 goto out; 1576 } 1577 if (wdc->irqack) 1578 wdc->irqack(chp); 1579 if (ata_c->flags & AT_READ) { 1580 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1581 ata_c->flags |= AT_TIMEOU; 1582 goto out; 1583 } 1584 wdc->datain_pio(chp, drive_flags, data, bcount); 1585 /* at this point the drive should be in its initial state */ 1586 ata_c->flags |= AT_XFDONE; 1587 /* 1588 * XXX checking the status register again here cause some 1589 * hardware to timeout. 1590 */ 1591 } else if (ata_c->flags & AT_WRITE) { 1592 if ((ATACH_ST(tfd) & WDCS_DRQ) == 0) { 1593 ata_c->flags |= AT_TIMEOU; 1594 goto out; 1595 } 1596 wdc->dataout_pio(chp, drive_flags, data, bcount); 1597 ata_c->flags |= AT_XFDONE; 1598 if ((ata_c->flags & AT_POLL) == 0) { 1599 chp->ch_flags |= ATACH_IRQ_WAIT; /* wait for interrupt */ 1600 callout_reset(&xfer->c_timo_callout, 1601 mstohz(ata_c->timeout), wdctimeout, xfer); 1602 ata_channel_unlock(chp); 1603 return 1; 1604 } else { 1605 goto again; 1606 } 1607 } 1608 out: 1609 if (ATACH_ST(tfd) & WDCS_DWF) 1610 ata_c->flags |= AT_DF; 1611 if (ATACH_ST(tfd) & WDCS_ERR) { 1612 ata_c->flags |= AT_ERROR; 1613 ata_c->r_error = ATACH_ST(tfd); 1614 } 1615 1616 ata_channel_unlock(chp); 1617 1618 __wdccommand_done(chp, xfer); 1619 return 1; 1620 } 1621 1622 static void 1623 __wdccommand_done(struct ata_channel *chp, struct ata_xfer *xfer) 1624 { 1625 struct atac_softc *atac = chp->ch_atac; 1626 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1627 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1628 struct ata_command *ata_c = &xfer->c_ata_c; 1629 bool start = true; 1630 1631 ATADEBUG_PRINT(("__wdccommand_done %s:%d:%d flags 0x%x\n", 1632 device_xname(atac->atac_dev), chp->ch_channel, xfer->c_drive, 1633 ata_c->flags), DEBUG_FUNCS); 1634 1635 if (ata_waitdrain_xfer_check(chp, xfer)) { 1636 start = false; 1637 goto out; 1638 } 1639 1640 if ((ata_c->flags & AT_READREG) != 0 && 1641 device_is_active(atac->atac_dev) && 1642 (ata_c->flags & (AT_ERROR | AT_DF)) == 0) { 1643 ata_c->r_status = bus_space_read_1(wdr->cmd_iot, 1644 wdr->cmd_iohs[wd_status], 0); 1645 ata_c->r_error = bus_space_read_1(wdr->cmd_iot, 1646 wdr->cmd_iohs[wd_error], 0); 1647 ata_c->r_count = bus_space_read_1(wdr->cmd_iot, 1648 wdr->cmd_iohs[wd_seccnt], 0); 1649 ata_c->r_lba = (uint64_t)bus_space_read_1(wdr->cmd_iot, 1650 wdr->cmd_iohs[wd_sector], 0) << 0; 1651 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1652 wdr->cmd_iohs[wd_cyl_lo], 0) << 8; 1653 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1654 wdr->cmd_iohs[wd_cyl_hi], 0) << 16; 1655 ata_c->r_device = bus_space_read_1(wdr->cmd_iot, 1656 wdr->cmd_iohs[wd_sdh], 0); 1657 1658 if ((ata_c->flags & AT_LBA48) != 0) { 1659 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1660 if ((ata_c->flags & AT_POLL) != 0) 1661 bus_space_write_1(wdr->ctl_iot, 1662 wdr->ctl_ioh, wd_aux_ctlr, 1663 WDCTL_HOB|WDCTL_4BIT|WDCTL_IDS); 1664 else 1665 bus_space_write_1(wdr->ctl_iot, 1666 wdr->ctl_ioh, wd_aux_ctlr, 1667 WDCTL_HOB|WDCTL_4BIT); 1668 } 1669 ata_c->r_count |= bus_space_read_1(wdr->cmd_iot, 1670 wdr->cmd_iohs[wd_seccnt], 0) << 8; 1671 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1672 wdr->cmd_iohs[wd_sector], 0) << 24; 1673 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1674 wdr->cmd_iohs[wd_cyl_lo], 0) << 32; 1675 ata_c->r_lba |= (uint64_t)bus_space_read_1(wdr->cmd_iot, 1676 wdr->cmd_iohs[wd_cyl_hi], 0) << 40; 1677 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) { 1678 if ((ata_c->flags & AT_POLL) != 0) 1679 bus_space_write_1(wdr->ctl_iot, 1680 wdr->ctl_ioh, wd_aux_ctlr, 1681 WDCTL_4BIT|WDCTL_IDS); 1682 else 1683 bus_space_write_1(wdr->ctl_iot, 1684 wdr->ctl_ioh, wd_aux_ctlr, 1685 WDCTL_4BIT); 1686 } 1687 } else { 1688 ata_c->r_lba |= 1689 (uint64_t)(ata_c->r_device & 0x0f) << 24; 1690 } 1691 ata_c->r_device &= 0xf0; 1692 } 1693 1694 ata_deactivate_xfer(chp, xfer); 1695 1696 __wdccommand_done_end(chp, xfer); 1697 1698 out: 1699 if (ata_c->flags & AT_POLL) { 1700 /* enable interrupts */ 1701 if (! (wdc->cap & WDC_CAPABILITY_NO_AUXCTL)) 1702 bus_space_write_1(wdr->ctl_iot, wdr->ctl_ioh, 1703 wd_aux_ctlr, WDCTL_4BIT); 1704 delay(10); /* some drives need a little delay here */ 1705 } 1706 1707 if (start) 1708 atastart(chp); 1709 } 1710 1711 static void 1712 __wdccommand_done_end(struct ata_channel *chp, struct ata_xfer *xfer) 1713 { 1714 struct ata_command *ata_c = &xfer->c_ata_c; 1715 1716 ata_channel_lock(chp); 1717 ata_c->flags |= AT_DONE; 1718 if (ata_c->flags & AT_WAIT) 1719 ata_wake_xfer(chp, xfer); 1720 ata_channel_unlock(chp); 1721 } 1722 1723 static void 1724 __wdccommand_kill_xfer(struct ata_channel *chp, struct ata_xfer *xfer, 1725 int reason) 1726 { 1727 struct ata_command *ata_c = &xfer->c_ata_c; 1728 bool deactivate = true; 1729 1730 switch (reason) { 1731 case KILL_GONE_INACTIVE: 1732 deactivate = false; 1733 /* FALLTHROUGH */ 1734 case KILL_GONE: 1735 ata_c->flags |= AT_GONE; 1736 break; 1737 case KILL_RESET: 1738 ata_c->flags |= AT_RESET; 1739 break; 1740 default: 1741 printf("__wdccommand_kill_xfer: unknown reason %d\n", 1742 reason); 1743 panic("__wdccommand_kill_xfer"); 1744 } 1745 1746 if (deactivate) 1747 ata_deactivate_xfer(chp, xfer); 1748 1749 __wdccommand_done_end(chp, xfer); 1750 } 1751 1752 /* 1753 * Send a command. The drive should be ready. 1754 * Assumes interrupts are blocked. 1755 */ 1756 void 1757 wdccommand(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1758 u_int16_t cylin, u_int8_t head, u_int8_t sector, u_int8_t count, 1759 u_int8_t features) 1760 { 1761 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1762 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1763 1764 ATADEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1765 "sector=%d count=%d features=%d\n", 1766 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1767 command, cylin, head, sector, count, features), DEBUG_FUNCS); 1768 1769 if (wdc->select) 1770 wdc->select(chp,drive); 1771 1772 /* Select drive, head, and addressing mode. */ 1773 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1774 WDSD_IBM | (drive << 4) | head); 1775 /* Load parameters into the wd_features register. */ 1776 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 0, 1777 features); 1778 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 0, count); 1779 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sector], 0, sector); 1780 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_lo], 0, cylin); 1781 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_cyl_hi], 1782 0, cylin >> 8); 1783 1784 /* Send command. */ 1785 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1786 return; 1787 } 1788 1789 /* 1790 * Send a 48-bit addressing command. The drive should be ready. 1791 * Assumes interrupts are blocked. 1792 */ 1793 void 1794 wdccommandext(struct ata_channel *chp, u_int8_t drive, u_int8_t command, 1795 u_int64_t blkno, u_int16_t count, u_int16_t features, u_int8_t device) 1796 { 1797 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1798 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1799 1800 ATADEBUG_PRINT(("wdccommandext %s:%d:%d: command=0x%02x " 1801 "blkno=0x%012"PRIx64" count=0x%04x features=0x%04x " 1802 "device=0x%02x\n", device_xname(chp->ch_atac->atac_dev), 1803 chp->ch_channel, drive, command, blkno, count, features, device), 1804 DEBUG_FUNCS); 1805 1806 KASSERT(drive < wdc->wdc_maxdrives); 1807 1808 if (wdc->select) 1809 wdc->select(chp,drive); 1810 1811 /* Select drive, head, and addressing mode. */ 1812 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1813 (drive << 4) | device); 1814 1815 if (wdc->cap & WDC_CAPABILITY_WIDEREGS) { 1816 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1817 0, features); 1818 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1819 0, count); 1820 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1821 0, (((blkno >> 16) & 0xff00) | (blkno & 0x00ff))); 1822 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1823 0, (((blkno >> 24) & 0xff00) | ((blkno >> 8) & 0x00ff))); 1824 bus_space_write_2(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1825 0, (((blkno >> 32) & 0xff00) | ((blkno >> 16) & 0x00ff))); 1826 } else { 1827 /* previous */ 1828 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1829 0, features >> 8); 1830 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1831 0, count >> 8); 1832 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1833 0, blkno >> 24); 1834 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1835 0, blkno >> 32); 1836 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1837 0, blkno >> 40); 1838 1839 /* current */ 1840 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_features], 1841 0, features); 1842 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_seccnt], 1843 0, count); 1844 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_lo], 1845 0, blkno); 1846 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_mi], 1847 0, blkno >> 8); 1848 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_lba_hi], 1849 0, blkno >> 16); 1850 } 1851 1852 /* Send command. */ 1853 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1854 return; 1855 } 1856 1857 /* 1858 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1859 * tested by the caller. 1860 */ 1861 void 1862 wdccommandshort(struct ata_channel *chp, int drive, int command) 1863 { 1864 struct wdc_softc *wdc = CHAN_TO_WDC(chp); 1865 struct wdc_regs *wdr = &wdc->regs[chp->ch_channel]; 1866 1867 ATADEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1868 device_xname(chp->ch_atac->atac_dev), chp->ch_channel, drive, 1869 command), DEBUG_FUNCS); 1870 1871 if (wdc->select) 1872 wdc->select(chp,drive); 1873 1874 /* Select drive. */ 1875 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_sdh], 0, 1876 WDSD_IBM | (drive << 4)); 1877 1878 bus_space_write_1(wdr->cmd_iot, wdr->cmd_iohs[wd_command], 0, command); 1879 } 1880 1881 static void 1882 __wdcerror(struct ata_channel *chp, const char *msg) 1883 { 1884 struct atac_softc *atac = chp->ch_atac; 1885 struct ata_xfer *xfer = ata_queue_get_active_xfer(chp); 1886 1887 if (xfer == NULL) 1888 aprint_error("%s:%d: %s\n", device_xname(atac->atac_dev), 1889 chp->ch_channel, msg); 1890 else 1891 aprint_error("%s:%d:%d: %s\n", device_xname(atac->atac_dev), 1892 chp->ch_channel, xfer->c_drive, msg); 1893 } 1894 1895 /* 1896 * the bit bucket 1897 */ 1898 void 1899 wdcbit_bucket(struct ata_channel *chp, int size) 1900 { 1901 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1902 1903 for (; size >= 2; size -= 2) 1904 (void)bus_space_read_2(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1905 if (size) 1906 (void)bus_space_read_1(wdr->cmd_iot, wdr->cmd_iohs[wd_data], 0); 1907 } 1908 1909 static void 1910 wdc_datain_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 1911 { 1912 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 1913 1914 #ifndef __NO_STRICT_ALIGNMENT 1915 if ((uintptr_t)bf & 1) 1916 goto unaligned; 1917 if ((flags & ATA_DRIVE_CAP32) && ((uintptr_t)bf & 3)) 1918 goto unaligned; 1919 #endif 1920 1921 if (flags & ATA_DRIVE_NOSTREAM) { 1922 if ((flags & ATA_DRIVE_CAP32) && len > 3) { 1923 bus_space_read_multi_4(wdr->data32iot, 1924 wdr->data32ioh, 0, bf, len >> 2); 1925 bf = (char *)bf + (len & ~3); 1926 len &= 3; 1927 } 1928 if (len > 1) { 1929 bus_space_read_multi_2(wdr->cmd_iot, 1930 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1931 bf = (char *)bf + (len & ~1); 1932 len &= 1; 1933 } 1934 } else { 1935 if ((flags & ATA_DRIVE_CAP32) && len > 3) { 1936 bus_space_read_multi_stream_4(wdr->data32iot, 1937 wdr->data32ioh, 0, bf, len >> 2); 1938 bf = (char *)bf + (len & ~3); 1939 len &= 3; 1940 } 1941 if (len > 1) { 1942 bus_space_read_multi_stream_2(wdr->cmd_iot, 1943 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 1944 bf = (char *)bf + (len & ~1); 1945 len &= 1; 1946 } 1947 } 1948 if (len) 1949 *((uint8_t *)bf) = bus_space_read_1(wdr->cmd_iot, 1950 wdr->cmd_iohs[wd_data], 0); 1951 return; 1952 1953 #ifndef __NO_STRICT_ALIGNMENT 1954 unaligned: 1955 if (flags & ATA_DRIVE_NOSTREAM) { 1956 if (flags & ATA_DRIVE_CAP32) { 1957 while (len > 3) { 1958 uint32_t val; 1959 1960 val = bus_space_read_4(wdr->data32iot, 1961 wdr->data32ioh, 0); 1962 memcpy(bf, &val, 4); 1963 bf = (char *)bf + 4; 1964 len -= 4; 1965 } 1966 } 1967 while (len > 1) { 1968 uint16_t val; 1969 1970 val = bus_space_read_2(wdr->cmd_iot, 1971 wdr->cmd_iohs[wd_data], 0); 1972 memcpy(bf, &val, 2); 1973 bf = (char *)bf + 2; 1974 len -= 2; 1975 } 1976 } else { 1977 if (flags & ATA_DRIVE_CAP32) { 1978 while (len > 3) { 1979 uint32_t val; 1980 1981 val = bus_space_read_stream_4(wdr->data32iot, 1982 wdr->data32ioh, 0); 1983 memcpy(bf, &val, 4); 1984 bf = (char *)bf + 4; 1985 len -= 4; 1986 } 1987 } 1988 while (len > 1) { 1989 uint16_t val; 1990 1991 val = bus_space_read_stream_2(wdr->cmd_iot, 1992 wdr->cmd_iohs[wd_data], 0); 1993 memcpy(bf, &val, 2); 1994 bf = (char *)bf + 2; 1995 len -= 2; 1996 } 1997 } 1998 #endif 1999 } 2000 2001 static void 2002 wdc_dataout_pio(struct ata_channel *chp, int flags, void *bf, size_t len) 2003 { 2004 struct wdc_regs *wdr = CHAN_TO_WDC_REGS(chp); 2005 2006 #ifndef __NO_STRICT_ALIGNMENT 2007 if ((uintptr_t)bf & 1) 2008 goto unaligned; 2009 if ((flags & ATA_DRIVE_CAP32) && ((uintptr_t)bf & 3)) 2010 goto unaligned; 2011 #endif 2012 2013 if (flags & ATA_DRIVE_NOSTREAM) { 2014 if (flags & ATA_DRIVE_CAP32) { 2015 bus_space_write_multi_4(wdr->data32iot, 2016 wdr->data32ioh, 0, bf, len >> 2); 2017 bf = (char *)bf + (len & ~3); 2018 len &= 3; 2019 } 2020 if (len) { 2021 bus_space_write_multi_2(wdr->cmd_iot, 2022 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 2023 } 2024 } else { 2025 if (flags & ATA_DRIVE_CAP32) { 2026 bus_space_write_multi_stream_4(wdr->data32iot, 2027 wdr->data32ioh, 0, bf, len >> 2); 2028 bf = (char *)bf + (len & ~3); 2029 len &= 3; 2030 } 2031 if (len) { 2032 bus_space_write_multi_stream_2(wdr->cmd_iot, 2033 wdr->cmd_iohs[wd_data], 0, bf, len >> 1); 2034 } 2035 } 2036 return; 2037 2038 #ifndef __NO_STRICT_ALIGNMENT 2039 unaligned: 2040 if (flags & ATA_DRIVE_NOSTREAM) { 2041 if (flags & ATA_DRIVE_CAP32) { 2042 while (len > 3) { 2043 uint32_t val; 2044 2045 memcpy(&val, bf, 4); 2046 bus_space_write_4(wdr->data32iot, 2047 wdr->data32ioh, 0, val); 2048 bf = (char *)bf + 4; 2049 len -= 4; 2050 } 2051 } 2052 while (len > 1) { 2053 uint16_t val; 2054 2055 memcpy(&val, bf, 2); 2056 bus_space_write_2(wdr->cmd_iot, 2057 wdr->cmd_iohs[wd_data], 0, val); 2058 bf = (char *)bf + 2; 2059 len -= 2; 2060 } 2061 } else { 2062 if (flags & ATA_DRIVE_CAP32) { 2063 while (len > 3) { 2064 uint32_t val; 2065 2066 memcpy(&val, bf, 4); 2067 bus_space_write_stream_4(wdr->data32iot, 2068 wdr->data32ioh, 0, val); 2069 bf = (char *)bf + 4; 2070 len -= 4; 2071 } 2072 } 2073 while (len > 1) { 2074 uint16_t val; 2075 2076 memcpy(&val, bf, 2); 2077 bus_space_write_stream_2(wdr->cmd_iot, 2078 wdr->cmd_iohs[wd_data], 0, val); 2079 bf = (char *)bf + 2; 2080 len -= 2; 2081 } 2082 } 2083 #endif 2084 } 2085