1 /* $NetBSD: wdc.c,v 1.92 2000/06/28 17:13:06 mrg Exp $ */ 2 3 4 /* 5 * Copyright (c) 1998 Manuel Bouyer. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Manuel Bouyer. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /*- 34 * Copyright (c) 1998 The NetBSD Foundation, Inc. 35 * All rights reserved. 36 * 37 * This code is derived from software contributed to The NetBSD Foundation 38 * by Charles M. Hannum, by Onno van der Linden and by Manuel Bouyer. 39 * 40 * Redistribution and use in source and binary forms, with or without 41 * modification, are permitted provided that the following conditions 42 * are met: 43 * 1. Redistributions of source code must retain the above copyright 44 * notice, this list of conditions and the following disclaimer. 45 * 2. Redistributions in binary form must reproduce the above copyright 46 * notice, this list of conditions and the following disclaimer in the 47 * documentation and/or other materials provided with the distribution. 48 * 3. All advertising materials mentioning features or use of this software 49 * must display the following acknowledgement: 50 * This product includes software developed by the NetBSD 51 * Foundation, Inc. and its contributors. 52 * 4. Neither the name of The NetBSD Foundation nor the names of its 53 * contributors may be used to endorse or promote products derived 54 * from this software without specific prior written permission. 55 * 56 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 57 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 58 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 59 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 60 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 61 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 62 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 63 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 64 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 65 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 66 * POSSIBILITY OF SUCH DAMAGE. 67 */ 68 69 /* 70 * CODE UNTESTED IN THE CURRENT REVISION: 71 * 72 */ 73 74 #ifndef WDCDEBUG 75 #define WDCDEBUG 76 #endif /* WDCDEBUG */ 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/kernel.h> 81 #include <sys/conf.h> 82 #include <sys/buf.h> 83 #include <sys/device.h> 84 #include <sys/malloc.h> 85 #include <sys/pool.h> 86 #include <sys/syslog.h> 87 #include <sys/proc.h> 88 89 #include <machine/intr.h> 90 #include <machine/bus.h> 91 92 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 93 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 94 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 95 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 96 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 97 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 98 99 #include <dev/ata/atavar.h> 100 #include <dev/ata/atareg.h> 101 #include <dev/ic/wdcreg.h> 102 #include <dev/ic/wdcvar.h> 103 104 #include "atapibus.h" 105 106 #define WDCDELAY 100 /* 100 microseconds */ 107 #define WDCNDELAY_RST (WDC_RESET_WAIT * 1000 / WDCDELAY) 108 #if 0 109 /* If you enable this, it will report any delays more than WDCDELAY * N long. */ 110 #define WDCNDELAY_DEBUG 50 111 #endif 112 113 struct pool wdc_xfer_pool; 114 115 static void __wdcerror __P((struct channel_softc*, char *)); 116 static int __wdcwait_reset __P((struct channel_softc *, int)); 117 void __wdccommand_done __P((struct channel_softc *, struct wdc_xfer *)); 118 void __wdccommand_start __P((struct channel_softc *, struct wdc_xfer *)); 119 int __wdccommand_intr __P((struct channel_softc *, struct wdc_xfer *, int)); 120 int wdprint __P((void *, const char *)); 121 122 123 #define DEBUG_INTR 0x01 124 #define DEBUG_XFERS 0x02 125 #define DEBUG_STATUS 0x04 126 #define DEBUG_FUNCS 0x08 127 #define DEBUG_PROBE 0x10 128 #define DEBUG_DETACH 0x20 129 #define DEBUG_DELAY 0x40 130 #ifdef WDCDEBUG 131 int wdcdebug_mask = 0; 132 int wdc_nxfer = 0; 133 #define WDCDEBUG_PRINT(args, level) if (wdcdebug_mask & (level)) printf args 134 #else 135 #define WDCDEBUG_PRINT(args, level) 136 #endif 137 138 int 139 wdprint(aux, pnp) 140 void *aux; 141 const char *pnp; 142 { 143 struct ata_atapi_attach *aa_link = aux; 144 if (pnp) 145 printf("drive at %s", pnp); 146 printf(" channel %d drive %d", aa_link->aa_channel, 147 aa_link->aa_drv_data->drive); 148 return (UNCONF); 149 } 150 151 int 152 atapi_print(aux, pnp) 153 void *aux; 154 const char *pnp; 155 { 156 struct ata_atapi_attach *aa_link = aux; 157 if (pnp) 158 printf("atapibus at %s", pnp); 159 printf(" channel %d", aa_link->aa_channel); 160 return (UNCONF); 161 } 162 163 /* Test to see controller with at last one attached drive is there. 164 * Returns a bit for each possible drive found (0x01 for drive 0, 165 * 0x02 for drive 1). 166 * Logic: 167 * - If a status register is at 0xff, assume there is no drive here 168 * (ISA has pull-up resistors). If no drive at all -> return. 169 * - reset the controller, wait for it to complete (may take up to 31s !). 170 * If timeout -> return. 171 * - test ATA/ATAPI signatures. If at last one drive found -> return. 172 * - try an ATA command on the master. 173 */ 174 175 int 176 wdcprobe(chp) 177 struct channel_softc *chp; 178 { 179 u_int8_t st0, st1, sc, sn, cl, ch; 180 u_int8_t ret_value = 0x03; 181 u_int8_t drive; 182 183 /* 184 * Sanity check to see if the wdc channel responds at all. 185 */ 186 187 if (chp->wdc == NULL || 188 (chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 189 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 190 WDSD_IBM); 191 delay(10); 192 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 193 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 194 WDSD_IBM | 0x10); 195 delay(10); 196 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 197 198 WDCDEBUG_PRINT(("%s:%d: before reset, st0=0x%x, st1=0x%x\n", 199 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 200 chp->channel, st0, st1), DEBUG_PROBE); 201 202 if (st0 == 0xff) 203 ret_value &= ~0x01; 204 if (st1 == 0xff) 205 ret_value &= ~0x02; 206 if (ret_value == 0) 207 return 0; 208 } 209 210 /* assert SRST, wait for reset to complete */ 211 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 212 WDSD_IBM); 213 delay(10); 214 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 215 WDCTL_RST | WDCTL_IDS); 216 DELAY(1000); 217 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 218 WDCTL_IDS); 219 delay(1000); 220 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 221 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, WDCTL_4BIT); 222 delay(10); 223 224 ret_value = __wdcwait_reset(chp, ret_value); 225 WDCDEBUG_PRINT(("%s:%d: after reset, ret_value=0x%d\n", 226 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 227 ret_value), DEBUG_PROBE); 228 229 /* if reset failed, there's nothing here */ 230 if (ret_value == 0) 231 return 0; 232 233 /* 234 * Test presence of drives. First test register signatures looking for 235 * ATAPI devices. If it's not an ATAPI and reset said there may be 236 * something here assume it's ATA or OLD. Ghost will be killed later in 237 * attach routine. 238 */ 239 for (drive = 0; drive < 2; drive++) { 240 if ((ret_value & (0x01 << drive)) == 0) 241 continue; 242 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 243 WDSD_IBM | (drive << 4)); 244 delay(10); 245 /* Save registers contents */ 246 sc = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 247 sn = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 248 cl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 249 ch = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 250 251 WDCDEBUG_PRINT(("%s:%d:%d: after reset, sc=0x%x sn=0x%x " 252 "cl=0x%x ch=0x%x\n", 253 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 254 chp->channel, drive, sc, sn, cl, ch), DEBUG_PROBE); 255 /* 256 * sc & sn are supposted to be 0x1 for ATAPI but in some cases 257 * we get wrong values here, so ignore it. 258 */ 259 if (cl == 0x14 && ch == 0xeb) { 260 chp->ch_drive[drive].drive_flags |= DRIVE_ATAPI; 261 } else { 262 chp->ch_drive[drive].drive_flags |= DRIVE_ATA; 263 if (chp->wdc == NULL || 264 (chp->wdc->cap & WDC_CAPABILITY_PREATA) != 0) 265 chp->ch_drive[drive].drive_flags |= DRIVE_OLD; 266 } 267 } 268 return (ret_value); 269 } 270 271 void 272 wdcattach(chp) 273 struct channel_softc *chp; 274 { 275 int channel_flags, ctrl_flags, i, error; 276 struct ata_atapi_attach aa_link; 277 struct ataparams params; 278 static int inited = 0; 279 280 callout_init(&chp->ch_callout); 281 282 if ((error = wdc_addref(chp)) != 0) { 283 printf("%s: unable to enable controller\n", 284 chp->wdc->sc_dev.dv_xname); 285 return; 286 } 287 288 if (wdcprobe(chp) == 0) 289 /* If no drives, abort attach here. */ 290 goto out; 291 292 /* initialise global data */ 293 if (inited == 0) { 294 /* Initialize the wdc_xfer pool. */ 295 pool_init(&wdc_xfer_pool, sizeof(struct wdc_xfer), 0, 296 0, 0, "wdcspl", 0, NULL, NULL, M_DEVBUF); 297 inited++; 298 } 299 TAILQ_INIT(&chp->ch_queue->sc_xfer); 300 301 for (i = 0; i < 2; i++) { 302 chp->ch_drive[i].chnl_softc = chp; 303 chp->ch_drive[i].drive = i; 304 /* 305 * Init error counter so that an error withing the first xfers 306 * will trigger a downgrade 307 */ 308 chp->ch_drive[i].n_dmaerrs = NERRS_MAX-1; 309 310 /* If controller can't do 16bit flag the drives as 32bit */ 311 if ((chp->wdc->cap & 312 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 313 WDC_CAPABILITY_DATA32) 314 chp->ch_drive[i].drive_flags |= DRIVE_CAP32; 315 if ((chp->ch_drive[i].drive_flags & DRIVE) == 0) 316 continue; 317 318 /* 319 * Wait a bit, some devices are weird just after a reset. 320 * Then issue a IDENTIFY command, to try to detect slave ghost 321 */ 322 delay(100); 323 error = ata_get_params(&chp->ch_drive[i], AT_POLL, ¶ms); 324 if (error != CMD_OK) { 325 delay(1000000); 326 error = ata_get_params(&chp->ch_drive[i], AT_POLL, 327 ¶ms); 328 } 329 if (error == CMD_OK) { 330 /* If IDENTIFY succeded, this is not an OLD ctrl */ 331 chp->ch_drive[0].drive_flags &= ~DRIVE_OLD; 332 chp->ch_drive[1].drive_flags &= ~DRIVE_OLD; 333 } else { 334 chp->ch_drive[i].drive_flags &= 335 ~(DRIVE_ATA | DRIVE_ATAPI); 336 WDCDEBUG_PRINT(("%s:%d:%d: IDENTIFY failed (%d)\n", 337 chp->wdc->sc_dev.dv_xname, 338 chp->channel, i, error), DEBUG_PROBE); 339 if ((chp->ch_drive[i].drive_flags & DRIVE_OLD) == 0) 340 continue; 341 /* 342 * Pre-ATA drive ? 343 * Test registers writability (Error register not 344 * writable, but cyllo is), then try an ATA command. 345 */ 346 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 347 WDSD_IBM | (i << 4)); 348 delay(10); 349 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 350 wd_error, 0x58); 351 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 352 wd_cyl_lo, 0xa5); 353 if (bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 354 wd_error == 0x58) || 355 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 356 wd_cyl_lo) != 0xa5) { 357 WDCDEBUG_PRINT(("%s:%d:%d: register " 358 "writability failed\n", 359 chp->wdc->sc_dev.dv_xname, 360 chp->channel, i), DEBUG_PROBE); 361 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 362 } 363 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 364 WDSD_IBM | (i << 4)); 365 delay(100); 366 if (wait_for_ready(chp, 10000) != 0) { 367 WDCDEBUG_PRINT(("%s:%d:%d: not ready\n", 368 chp->wdc->sc_dev.dv_xname, 369 chp->channel, i), DEBUG_PROBE); 370 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 371 continue; 372 } 373 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 374 wd_command, WDCC_RECAL); 375 if (wait_for_ready(chp, 10000) != 0) { 376 WDCDEBUG_PRINT(("%s:%d:%d: WDCC_RECAL failed\n", 377 chp->wdc->sc_dev.dv_xname, 378 chp->channel, i), DEBUG_PROBE); 379 chp->ch_drive[i].drive_flags &= ~DRIVE_OLD; 380 } 381 } 382 } 383 ctrl_flags = chp->wdc->sc_dev.dv_cfdata->cf_flags; 384 channel_flags = (ctrl_flags >> (NBBY * chp->channel)) & 0xff; 385 386 WDCDEBUG_PRINT(("wdcattach: ch_drive_flags 0x%x 0x%x\n", 387 chp->ch_drive[0].drive_flags, chp->ch_drive[1].drive_flags), 388 DEBUG_PROBE); 389 390 /* If no drives, abort here */ 391 if ((chp->ch_drive[0].drive_flags & DRIVE) == 0 && 392 (chp->ch_drive[1].drive_flags & DRIVE) == 0) 393 goto out; 394 395 /* 396 * Attach an ATAPI bus, if needed. 397 */ 398 if ((chp->ch_drive[0].drive_flags & DRIVE_ATAPI) || 399 (chp->ch_drive[1].drive_flags & DRIVE_ATAPI)) { 400 #if NATAPIBUS > 0 401 wdc_atapibus_attach(chp); 402 #else 403 /* 404 * Fills in a fake aa_link and call config_found, so that 405 * the config machinery will print 406 * "atapibus at xxx not configured" 407 */ 408 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 409 aa_link.aa_type = T_ATAPI; 410 aa_link.aa_channel = chp->channel; 411 aa_link.aa_openings = 1; 412 aa_link.aa_drv_data = 0; 413 aa_link.aa_bus_private = NULL; 414 chp->atapibus = config_found(&chp->wdc->sc_dev, 415 (void *)&aa_link, atapi_print); 416 #endif 417 } 418 419 for (i = 0; i < 2; i++) { 420 if ((chp->ch_drive[i].drive_flags & 421 (DRIVE_ATA | DRIVE_OLD)) == 0) { 422 continue; 423 } 424 memset(&aa_link, 0, sizeof(struct ata_atapi_attach)); 425 aa_link.aa_type = T_ATA; 426 aa_link.aa_channel = chp->channel; 427 aa_link.aa_openings = 1; 428 aa_link.aa_drv_data = &chp->ch_drive[i]; 429 if (config_found(&chp->wdc->sc_dev, (void *)&aa_link, wdprint)) 430 wdc_probe_caps(&chp->ch_drive[i]); 431 } 432 433 /* 434 * reset drive_flags for unnatached devices, reset state for attached 435 * ones 436 */ 437 for (i = 0; i < 2; i++) { 438 if (chp->ch_drive[i].drv_softc == NULL) 439 chp->ch_drive[i].drive_flags = 0; 440 else 441 chp->ch_drive[i].state = 0; 442 } 443 444 /* 445 * Reset channel. The probe, with some combinations of ATA/ATAPI 446 * devices keep it in a mostly working, but strange state (with busy 447 * led on) 448 */ 449 if ((chp->wdc->cap & WDC_CAPABILITY_NO_EXTRA_RESETS) == 0) { 450 wdcreset(chp, VERBOSE); 451 /* 452 * Read status registers to avoid spurious interrupts. 453 */ 454 for (i = 1; i >= 0; i--) { 455 if (chp->ch_drive[i].drive_flags & DRIVE) { 456 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, 457 wd_sdh, WDSD_IBM | (i << 4)); 458 if (wait_for_unbusy(chp, 10000) < 0) 459 printf("%s:%d:%d: device busy\n", 460 chp->wdc->sc_dev.dv_xname, 461 chp->channel, i); 462 } 463 } 464 } 465 466 out: 467 wdc_delref(chp); 468 } 469 470 /* 471 * Call activate routine of underlying devices. 472 */ 473 int 474 wdcactivate(self, act) 475 struct device *self; 476 enum devact act; 477 { 478 struct wdc_softc *wdc = (struct wdc_softc *)self; 479 struct channel_softc *chp; 480 struct device *sc = 0; 481 int s, i, j, error = 0; 482 483 s = splbio(); 484 switch (act) { 485 case DVACT_ACTIVATE: 486 error = EOPNOTSUPP; 487 break; 488 489 case DVACT_DEACTIVATE: 490 for (i = 0; i < wdc->nchannels; i++) { 491 chp = wdc->channels[i]; 492 493 /* 494 * We might call deactivate routine for 495 * the children of atapibus twice (once via 496 * atapibus, once directly), but since 497 * config_deactivate maintains DVF_ACTIVE flag, 498 * it's safe. 499 */ 500 sc = chp->atapibus; 501 if (sc != NULL) { 502 error = config_deactivate(sc); 503 if (error != 0) 504 goto out; 505 } 506 507 for (j = 0; j < 2; j++) { 508 sc = chp->ch_drive[j].drv_softc; 509 WDCDEBUG_PRINT(("wdcactivate: %s:" 510 " deactivating %s\n", wdc->sc_dev.dv_xname, 511 sc == NULL ? "nodrv" : sc->dv_xname), 512 DEBUG_DETACH); 513 if (sc != NULL) { 514 error = config_deactivate(sc); 515 if (error != 0) 516 goto out; 517 } 518 } 519 } 520 break; 521 } 522 523 out: 524 splx(s); 525 526 #ifdef WDCDEBUG 527 if (sc && error != 0) 528 WDCDEBUG_PRINT(("wdcactivate: %s: error %d deactivating %s\n", 529 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 530 #endif 531 return (error); 532 } 533 534 int 535 wdcdetach(self, flags) 536 struct device *self; 537 int flags; 538 { 539 struct wdc_softc *wdc = (struct wdc_softc *)self; 540 struct channel_softc *chp; 541 struct device *sc = 0; 542 int i, j, error = 0; 543 544 for (i = 0; i < wdc->nchannels; i++) { 545 chp = wdc->channels[i]; 546 547 /* 548 * Detach atapibus and its children. 549 */ 550 sc = chp->atapibus; 551 if (sc != NULL) { 552 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 553 wdc->sc_dev.dv_xname, sc->dv_xname), DEBUG_DETACH); 554 error = config_detach(sc, flags); 555 if (error != 0) 556 goto out; 557 } 558 559 /* 560 * Detach our other children. 561 */ 562 for (j = 0; j < 2; j++) { 563 sc = chp->ch_drive[j].drv_softc; 564 WDCDEBUG_PRINT(("wdcdetach: %s: detaching %s\n", 565 wdc->sc_dev.dv_xname, 566 sc == NULL ? "nodrv" : sc->dv_xname), 567 DEBUG_DETACH); 568 if (sc != NULL) { 569 error = config_detach(sc, flags); 570 if (error != 0) 571 goto out; 572 } 573 } 574 575 wdc_kill_pending(chp); 576 } 577 578 out: 579 #ifdef WDCDEBUG 580 if (sc && error != 0) 581 WDCDEBUG_PRINT(("wdcdetach: %s: error %d detaching %s\n", 582 wdc->sc_dev.dv_xname, error, sc->dv_xname), DEBUG_DETACH); 583 #endif 584 return (error); 585 } 586 587 /* 588 * Start I/O on a controller, for the given channel. 589 * The first xfer may be not for our channel if the channel queues 590 * are shared. 591 */ 592 void 593 wdcstart(chp) 594 struct channel_softc *chp; 595 { 596 struct wdc_xfer *xfer; 597 598 #ifdef WDC_DIAGNOSTIC 599 int spl1, spl2; 600 601 spl1 = splbio(); 602 spl2 = splbio(); 603 if (spl2 != spl1) { 604 printf("wdcstart: not at splbio()\n"); 605 panic("wdcstart"); 606 } 607 splx(spl2); 608 splx(spl1); 609 #endif /* WDC_DIAGNOSTIC */ 610 611 /* is there a xfer ? */ 612 if ((xfer = chp->ch_queue->sc_xfer.tqh_first) == NULL) 613 return; 614 615 /* adjust chp, in case we have a shared queue */ 616 chp = xfer->chp; 617 618 if ((chp->ch_flags & WDCF_ACTIVE) != 0 ) { 619 return; /* channel aleady active */ 620 } 621 #ifdef DIAGNOSTIC 622 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) 623 panic("wdcstart: channel waiting for irq\n"); 624 #endif 625 if (chp->wdc->cap & WDC_CAPABILITY_HWLOCK) 626 if (!(*chp->wdc->claim_hw)(chp, 0)) 627 return; 628 629 WDCDEBUG_PRINT(("wdcstart: xfer %p channel %d drive %d\n", xfer, 630 chp->channel, xfer->drive), DEBUG_XFERS); 631 chp->ch_flags |= WDCF_ACTIVE; 632 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_RESET) { 633 chp->ch_drive[xfer->drive].drive_flags &= ~DRIVE_RESET; 634 chp->ch_drive[xfer->drive].state = 0; 635 } 636 xfer->c_start(chp, xfer); 637 } 638 639 /* restart an interrupted I/O */ 640 void 641 wdcrestart(v) 642 void *v; 643 { 644 struct channel_softc *chp = v; 645 int s; 646 647 s = splbio(); 648 wdcstart(chp); 649 splx(s); 650 } 651 652 653 /* 654 * Interrupt routine for the controller. Acknowledge the interrupt, check for 655 * errors on the current operation, mark it done if necessary, and start the 656 * next request. Also check for a partially done transfer, and continue with 657 * the next chunk if so. 658 */ 659 int 660 wdcintr(arg) 661 void *arg; 662 { 663 struct channel_softc *chp = arg; 664 struct wdc_xfer *xfer; 665 int ret; 666 667 if ((chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) == 0) { 668 WDCDEBUG_PRINT(("wdcintr: deactivated controller\n"), 669 DEBUG_INTR); 670 return (0); 671 } 672 if ((chp->ch_flags & WDCF_IRQ_WAIT) == 0) { 673 WDCDEBUG_PRINT(("wdcintr: inactive controller\n"), DEBUG_INTR); 674 return (0); 675 } 676 677 WDCDEBUG_PRINT(("wdcintr\n"), DEBUG_INTR); 678 xfer = chp->ch_queue->sc_xfer.tqh_first; 679 if (chp->ch_flags & WDCF_DMA_WAIT) { 680 chp->wdc->dma_status = 681 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, chp->channel, 682 xfer->drive, 0); 683 if (chp->wdc->dma_status & WDC_DMAST_NOIRQ) { 684 /* IRQ not for us, not detected by DMA engine */ 685 return 0; 686 } 687 chp->ch_flags &= ~WDCF_DMA_WAIT; 688 } 689 chp->ch_flags &= ~WDCF_IRQ_WAIT; 690 ret = xfer->c_intr(chp, xfer, 1); 691 if (ret == 0) /* irq was not for us, still waiting for irq */ 692 chp->ch_flags |= WDCF_IRQ_WAIT; 693 return (ret); 694 } 695 696 /* Put all disk in RESET state */ 697 void wdc_reset_channel(drvp) 698 struct ata_drive_datas *drvp; 699 { 700 struct channel_softc *chp = drvp->chnl_softc; 701 int drive; 702 WDCDEBUG_PRINT(("ata_reset_channel %s:%d for drive %d\n", 703 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 704 DEBUG_FUNCS); 705 (void) wdcreset(chp, VERBOSE); 706 for (drive = 0; drive < 2; drive++) { 707 chp->ch_drive[drive].state = 0; 708 } 709 } 710 711 int 712 wdcreset(chp, verb) 713 struct channel_softc *chp; 714 int verb; 715 { 716 int drv_mask1, drv_mask2; 717 718 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 719 WDSD_IBM); /* master */ 720 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 721 WDCTL_RST | WDCTL_IDS); 722 delay(1000); 723 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 724 WDCTL_IDS); 725 delay(1000); 726 (void) bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_error); 727 bus_space_write_1(chp->ctl_iot, chp->ctl_ioh, wd_aux_ctlr, 728 WDCTL_4BIT); 729 730 drv_mask1 = (chp->ch_drive[0].drive_flags & DRIVE) ? 0x01:0x00; 731 drv_mask1 |= (chp->ch_drive[1].drive_flags & DRIVE) ? 0x02:0x00; 732 drv_mask2 = __wdcwait_reset(chp, drv_mask1); 733 if (verb && drv_mask2 != drv_mask1) { 734 printf("%s channel %d: reset failed for", 735 chp->wdc->sc_dev.dv_xname, chp->channel); 736 if ((drv_mask1 & 0x01) != 0 && (drv_mask2 & 0x01) == 0) 737 printf(" drive 0"); 738 if ((drv_mask1 & 0x02) != 0 && (drv_mask2 & 0x02) == 0) 739 printf(" drive 1"); 740 printf("\n"); 741 } 742 return (drv_mask1 != drv_mask2) ? 1 : 0; 743 } 744 745 static int 746 __wdcwait_reset(chp, drv_mask) 747 struct channel_softc *chp; 748 int drv_mask; 749 { 750 int timeout; 751 u_int8_t st0, st1; 752 #ifdef WDCDEBUG 753 u_int8_t sc0, sn0, cl0, ch0; 754 u_int8_t sc1, sn1, cl1, ch1; 755 #endif 756 /* wait for BSY to deassert */ 757 for (timeout = 0; timeout < WDCNDELAY_RST;timeout++) { 758 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 759 WDSD_IBM); /* master */ 760 delay(10); 761 st0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 762 #ifdef WDCDEBUG 763 sc0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 764 sn0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 765 cl0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 766 ch0 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 767 #endif 768 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 769 WDSD_IBM | 0x10); /* slave */ 770 delay(10); 771 st1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 772 #ifdef WDCDEBUG 773 sc1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt); 774 sn1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_sector); 775 cl1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo); 776 ch1 = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi); 777 #endif 778 779 if ((drv_mask & 0x01) == 0) { 780 /* no master */ 781 if ((drv_mask & 0x02) != 0 && (st1 & WDCS_BSY) == 0) { 782 /* No master, slave is ready, it's done */ 783 goto end; 784 } 785 } else if ((drv_mask & 0x02) == 0) { 786 /* no slave */ 787 if ((drv_mask & 0x01) != 0 && (st0 & WDCS_BSY) == 0) { 788 /* No slave, master is ready, it's done */ 789 goto end; 790 } 791 } else { 792 /* Wait for both master and slave to be ready */ 793 if ((st0 & WDCS_BSY) == 0 && (st1 & WDCS_BSY) == 0) { 794 goto end; 795 } 796 } 797 delay(WDCDELAY); 798 } 799 /* Reset timed out. Maybe it's because drv_mask was not rigth */ 800 if (st0 & WDCS_BSY) 801 drv_mask &= ~0x01; 802 if (st1 & WDCS_BSY) 803 drv_mask &= ~0x02; 804 end: 805 WDCDEBUG_PRINT(("%s:%d:0: after reset, sc=0x%x sn=0x%x " 806 "cl=0x%x ch=0x%x\n", 807 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 808 chp->channel, sc0, sn0, cl0, ch0), DEBUG_PROBE); 809 WDCDEBUG_PRINT(("%s:%d:1: after reset, sc=0x%x sn=0x%x " 810 "cl=0x%x ch=0x%x\n", 811 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", 812 chp->channel, sc1, sn1, cl1, ch1), DEBUG_PROBE); 813 814 WDCDEBUG_PRINT(("%s:%d: wdcwait_reset() end, st0=0x%x, st1=0x%x\n", 815 chp->wdc ? chp->wdc->sc_dev.dv_xname : "wdcprobe", chp->channel, 816 st0, st1), DEBUG_PROBE); 817 818 return drv_mask; 819 } 820 821 /* 822 * Wait for a drive to be !BSY, and have mask in its status register. 823 * return -1 for a timeout after "timeout" ms. 824 */ 825 int 826 wdcwait(chp, mask, bits, timeout) 827 struct channel_softc *chp; 828 int mask, bits, timeout; 829 { 830 u_char status; 831 int time = 0; 832 #ifdef WDCNDELAY_DEBUG 833 extern int cold; 834 #endif 835 836 WDCDEBUG_PRINT(("wdcwait %s:%d\n", chp->wdc ?chp->wdc->sc_dev.dv_xname 837 :"none", chp->channel), DEBUG_STATUS); 838 chp->ch_error = 0; 839 840 timeout = timeout * 1000 / WDCDELAY; /* delay uses microseconds */ 841 842 for (;;) { 843 chp->ch_status = status = 844 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_status); 845 if ((status & WDCS_BSY) == 0 && (status & mask) == bits) 846 break; 847 if (++time > timeout) { 848 WDCDEBUG_PRINT(("wdcwait: timeout (time=%d), " 849 "status %x error %x (mask 0x%x bits 0x%x)\n", 850 time, status, 851 bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 852 wd_error), mask, bits), 853 DEBUG_STATUS | DEBUG_PROBE | DEBUG_DELAY); 854 return -1; 855 } 856 delay(WDCDELAY); 857 } 858 #ifdef WDCDEBUG 859 if (time > 0 && (wdcdebug_mask & DEBUG_DELAY)) 860 printf("wdcwait: did busy-wait, time=%d\n", time); 861 #endif 862 if (status & WDCS_ERR) 863 chp->ch_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 864 wd_error); 865 #ifdef WDCNDELAY_DEBUG 866 /* After autoconfig, there should be no long delays. */ 867 if (!cold && time > WDCNDELAY_DEBUG) { 868 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 869 if (xfer == NULL) 870 printf("%s channel %d: warning: busy-wait took %dus\n", 871 chp->wdc->sc_dev.dv_xname, chp->channel, 872 WDCDELAY * time); 873 else 874 printf("%s:%d:%d: warning: busy-wait took %dus\n", 875 chp->wdc->sc_dev.dv_xname, chp->channel, 876 xfer->drive, 877 WDCDELAY * time); 878 } 879 #endif 880 return 0; 881 } 882 883 /* 884 * Busy-wait for DMA to complete 885 */ 886 int 887 wdc_dmawait(chp, xfer, timeout) 888 struct channel_softc *chp; 889 struct wdc_xfer *xfer; 890 int timeout; 891 { 892 int time; 893 for (time = 0; time < timeout * 1000 / WDCDELAY; time++) { 894 chp->wdc->dma_status = 895 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 896 chp->channel, xfer->drive, 0); 897 if ((chp->wdc->dma_status & WDC_DMAST_NOIRQ) == 0) 898 return 0; 899 delay(WDCDELAY); 900 } 901 /* timeout, force a DMA halt */ 902 chp->wdc->dma_status = (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 903 chp->channel, xfer->drive, 1); 904 return 1; 905 } 906 907 void 908 wdctimeout(arg) 909 void *arg; 910 { 911 struct channel_softc *chp = (struct channel_softc *)arg; 912 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 913 int s; 914 915 WDCDEBUG_PRINT(("wdctimeout\n"), DEBUG_FUNCS); 916 917 s = splbio(); 918 if ((chp->ch_flags & WDCF_IRQ_WAIT) != 0) { 919 __wdcerror(chp, "lost interrupt"); 920 printf("\ttype: %s tc_bcount: %d tc_skip: %d\n", 921 (xfer->c_flags & C_ATAPI) ? "atapi" : "ata", 922 xfer->c_bcount, 923 xfer->c_skip); 924 if (chp->ch_flags & WDCF_DMA_WAIT) { 925 chp->wdc->dma_status = 926 (*chp->wdc->dma_finish)(chp->wdc->dma_arg, 927 chp->channel, xfer->drive, 1); 928 chp->ch_flags &= ~WDCF_DMA_WAIT; 929 } 930 /* 931 * Call the interrupt routine. If we just missed and interrupt, 932 * it will do what's needed. Else, it will take the needed 933 * action (reset the device). 934 * Before that we need to reinstall the timeout callback, 935 * in case it will miss another irq while in this transfer 936 * We arbitray chose it to be 1s 937 */ 938 callout_reset(&chp->ch_callout, hz, wdctimeout, chp); 939 xfer->c_flags |= C_TIMEOU; 940 chp->ch_flags &= ~WDCF_IRQ_WAIT; 941 xfer->c_intr(chp, xfer, 1); 942 } else 943 __wdcerror(chp, "missing untimeout"); 944 splx(s); 945 } 946 947 /* 948 * Probe drive's capabilites, for use by the controller later 949 * Assumes drvp points to an existing drive. 950 * XXX this should be a controller-indep function 951 */ 952 void 953 wdc_probe_caps(drvp) 954 struct ata_drive_datas *drvp; 955 { 956 struct ataparams params, params2; 957 struct channel_softc *chp = drvp->chnl_softc; 958 struct device *drv_dev = drvp->drv_softc; 959 struct wdc_softc *wdc = chp->wdc; 960 int i, printed; 961 char *sep = ""; 962 int cf_flags; 963 964 if (ata_get_params(drvp, AT_POLL, ¶ms) != CMD_OK) { 965 /* IDENTIFY failed. Can't tell more about the device */ 966 return; 967 } 968 if ((wdc->cap & (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) == 969 (WDC_CAPABILITY_DATA16 | WDC_CAPABILITY_DATA32)) { 970 /* 971 * Controller claims 16 and 32 bit transfers. 972 * Re-do an IDENTIFY with 32-bit transfers, 973 * and compare results. 974 */ 975 drvp->drive_flags |= DRIVE_CAP32; 976 ata_get_params(drvp, AT_POLL, ¶ms2); 977 if (memcmp(¶ms, ¶ms2, sizeof(struct ataparams)) != 0) { 978 /* Not good. fall back to 16bits */ 979 drvp->drive_flags &= ~DRIVE_CAP32; 980 } else { 981 printf("%s: 32-bit data port", drv_dev->dv_xname); 982 } 983 } 984 #if 0 /* Some ultra-DMA drives claims to only support ATA-3. sigh */ 985 if (params.atap_ata_major > 0x01 && 986 params.atap_ata_major != 0xffff) { 987 for (i = 14; i > 0; i--) { 988 if (params.atap_ata_major & (1 << i)) { 989 if ((drvp->drive_flags & DRIVE_CAP32) == 0) 990 printf("%s: ", drv_dev->dv_xname); 991 else 992 printf(", "); 993 printf("ATA version %d\n", i); 994 drvp->ata_vers = i; 995 break; 996 } 997 } 998 } else 999 #endif 1000 if (drvp->drive_flags & DRIVE_CAP32) 1001 printf("\n"); 1002 1003 /* An ATAPI device is at last PIO mode 3 */ 1004 if (drvp->drive_flags & DRIVE_ATAPI) 1005 drvp->PIO_mode = 3; 1006 1007 /* 1008 * It's not in the specs, but it seems that some drive 1009 * returns 0xffff in atap_extensions when this field is invalid 1010 */ 1011 if (params.atap_extensions != 0xffff && 1012 (params.atap_extensions & WDC_EXT_MODES)) { 1013 printed = 0; 1014 /* 1015 * XXX some drives report something wrong here (they claim to 1016 * support PIO mode 8 !). As mode is coded on 3 bits in 1017 * SET FEATURE, limit it to 7 (so limit i to 4). 1018 * If higther mode than 7 is found, abort. 1019 */ 1020 for (i = 7; i >= 0; i--) { 1021 if ((params.atap_piomode_supp & (1 << i)) == 0) 1022 continue; 1023 if (i > 4) 1024 return; 1025 /* 1026 * See if mode is accepted. 1027 * If the controller can't set its PIO mode, 1028 * assume the defaults are good, so don't try 1029 * to set it 1030 */ 1031 if ((wdc->cap & WDC_CAPABILITY_MODE) != 0) 1032 if (ata_set_mode(drvp, 0x08 | (i + 3), 1033 AT_POLL) != CMD_OK) 1034 continue; 1035 if (!printed) { 1036 printf("%s: drive supports PIO mode %d", 1037 drv_dev->dv_xname, i + 3); 1038 sep = ","; 1039 printed = 1; 1040 } 1041 /* 1042 * If controller's driver can't set its PIO mode, 1043 * get the highter one for the drive. 1044 */ 1045 if ((wdc->cap & WDC_CAPABILITY_MODE) == 0 || 1046 wdc->PIO_cap >= i + 3) { 1047 drvp->PIO_mode = i + 3; 1048 drvp->PIO_cap = i + 3; 1049 break; 1050 } 1051 } 1052 if (!printed) { 1053 /* 1054 * We didn't find a valid PIO mode. 1055 * Assume the values returned for DMA are buggy too 1056 */ 1057 return; 1058 } 1059 drvp->drive_flags |= DRIVE_MODE; 1060 printed = 0; 1061 for (i = 7; i >= 0; i--) { 1062 if ((params.atap_dmamode_supp & (1 << i)) == 0) 1063 continue; 1064 if ((wdc->cap & WDC_CAPABILITY_DMA) && 1065 (wdc->cap & WDC_CAPABILITY_MODE)) 1066 if (ata_set_mode(drvp, 0x20 | i, AT_POLL) 1067 != CMD_OK) 1068 continue; 1069 if (!printed) { 1070 printf("%s DMA mode %d", sep, i); 1071 sep = ","; 1072 printed = 1; 1073 } 1074 if (wdc->cap & WDC_CAPABILITY_DMA) { 1075 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1076 wdc->DMA_cap < i) 1077 continue; 1078 drvp->DMA_mode = i; 1079 drvp->DMA_cap = i; 1080 drvp->drive_flags |= DRIVE_DMA; 1081 } 1082 break; 1083 } 1084 if (params.atap_extensions & WDC_EXT_UDMA_MODES) { 1085 printed = 0; 1086 for (i = 7; i >= 0; i--) { 1087 if ((params.atap_udmamode_supp & (1 << i)) 1088 == 0) 1089 continue; 1090 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1091 (wdc->cap & WDC_CAPABILITY_UDMA)) 1092 if (ata_set_mode(drvp, 0x40 | i, 1093 AT_POLL) != CMD_OK) 1094 continue; 1095 if (!printed) { 1096 printf("%s Ultra-DMA mode %d", sep, i); 1097 sep = ","; 1098 printed = 1; 1099 } 1100 if (wdc->cap & WDC_CAPABILITY_UDMA) { 1101 if ((wdc->cap & WDC_CAPABILITY_MODE) && 1102 wdc->UDMA_cap < i) 1103 continue; 1104 drvp->UDMA_mode = i; 1105 drvp->UDMA_cap = i; 1106 drvp->drive_flags |= DRIVE_UDMA; 1107 } 1108 break; 1109 } 1110 } 1111 printf("\n"); 1112 } 1113 1114 /* Try to guess ATA version here, if it didn't get reported */ 1115 if (drvp->ata_vers == 0) { 1116 if (drvp->drive_flags & DRIVE_UDMA) 1117 drvp->ata_vers = 4; /* should be at last ATA-4 */ 1118 else if (drvp->PIO_cap > 2) 1119 drvp->ata_vers = 2; /* should be at last ATA-2 */ 1120 } 1121 cf_flags = drv_dev->dv_cfdata->cf_flags; 1122 if (cf_flags & ATA_CONFIG_PIO_SET) { 1123 drvp->PIO_mode = 1124 (cf_flags & ATA_CONFIG_PIO_MODES) >> ATA_CONFIG_PIO_OFF; 1125 drvp->drive_flags |= DRIVE_MODE; 1126 } 1127 if ((wdc->cap & WDC_CAPABILITY_DMA) == 0) { 1128 /* don't care about DMA modes */ 1129 return; 1130 } 1131 if (cf_flags & ATA_CONFIG_DMA_SET) { 1132 if ((cf_flags & ATA_CONFIG_DMA_MODES) == 1133 ATA_CONFIG_DMA_DISABLE) { 1134 drvp->drive_flags &= ~DRIVE_DMA; 1135 } else { 1136 drvp->DMA_mode = (cf_flags & ATA_CONFIG_DMA_MODES) >> 1137 ATA_CONFIG_DMA_OFF; 1138 drvp->drive_flags |= DRIVE_DMA | DRIVE_MODE; 1139 } 1140 } 1141 if (cf_flags & ATA_CONFIG_UDMA_SET) { 1142 if ((cf_flags & ATA_CONFIG_UDMA_MODES) == 1143 ATA_CONFIG_UDMA_DISABLE) { 1144 drvp->drive_flags &= ~DRIVE_UDMA; 1145 } else { 1146 drvp->UDMA_mode = (cf_flags & ATA_CONFIG_UDMA_MODES) >> 1147 ATA_CONFIG_UDMA_OFF; 1148 drvp->drive_flags |= DRIVE_UDMA | DRIVE_MODE; 1149 } 1150 } 1151 } 1152 1153 /* 1154 * downgrade the transfer mode of a drive after an error. return 1 if 1155 * downgrade was possible, 0 otherwise. 1156 */ 1157 int 1158 wdc_downgrade_mode(drvp) 1159 struct ata_drive_datas *drvp; 1160 { 1161 struct channel_softc *chp = drvp->chnl_softc; 1162 struct device *drv_dev = drvp->drv_softc; 1163 struct wdc_softc *wdc = chp->wdc; 1164 int cf_flags = drv_dev->dv_cfdata->cf_flags; 1165 1166 /* if drive or controller don't know its mode, we can't do much */ 1167 if ((drvp->drive_flags & DRIVE_MODE) == 0 || 1168 (wdc->cap & WDC_CAPABILITY_MODE) == 0) 1169 return 0; 1170 /* current drive mode was set by a config flag, let it this way */ 1171 if ((cf_flags & ATA_CONFIG_PIO_SET) || 1172 (cf_flags & ATA_CONFIG_DMA_SET) || 1173 (cf_flags & ATA_CONFIG_UDMA_SET)) 1174 return 0; 1175 1176 /* 1177 * If we were using Ultra-DMA mode > 2, downgrade to mode 2 first. 1178 * Maybe we didn't properly notice the cable type 1179 * If we were using Ultra-DMA mode 2, downgrade to mode 1 first. 1180 * It helps in some cases. 1181 */ 1182 if ((drvp->drive_flags & DRIVE_UDMA) && drvp->UDMA_mode >= 2) { 1183 drvp->UDMA_mode = (drvp->UDMA_mode == 2) ? 1 : 2; 1184 printf("%s: transfer error, downgrading to Ultra-DMA mode %d\n", 1185 drv_dev->dv_xname, drvp->UDMA_mode); 1186 } 1187 1188 /* 1189 * If we were using ultra-DMA, don't downgrade to multiword DMA 1190 * if we noticed a CRC error. It has been noticed that CRC errors 1191 * in ultra-DMA lead to silent data corruption in multiword DMA. 1192 * Data corruption is less likely to occur in PIO mode. 1193 */ 1194 else if ((drvp->drive_flags & DRIVE_UDMA) && 1195 (drvp->drive_flags & DRIVE_DMAERR) == 0) { 1196 drvp->drive_flags &= ~DRIVE_UDMA; 1197 drvp->drive_flags |= DRIVE_DMA; 1198 drvp->DMA_mode = drvp->DMA_cap; 1199 printf("%s: transfer error, downgrading to DMA mode %d\n", 1200 drv_dev->dv_xname, drvp->DMA_mode); 1201 } else if (drvp->drive_flags & (DRIVE_DMA | DRIVE_UDMA)) { 1202 drvp->drive_flags &= ~(DRIVE_DMA | DRIVE_UDMA); 1203 drvp->PIO_mode = drvp->PIO_cap; 1204 printf("%s: transfer error, downgrading to PIO mode %d\n", 1205 drv_dev->dv_xname, drvp->PIO_mode); 1206 } else /* already using PIO, can't downgrade */ 1207 return 0; 1208 1209 wdc->set_modes(chp); 1210 /* reset the channel, which will shedule all drives for setup */ 1211 wdc_reset_channel(drvp); 1212 return 1; 1213 } 1214 1215 int 1216 wdc_exec_command(drvp, wdc_c) 1217 struct ata_drive_datas *drvp; 1218 struct wdc_command *wdc_c; 1219 { 1220 struct channel_softc *chp = drvp->chnl_softc; 1221 struct wdc_xfer *xfer; 1222 int s, ret; 1223 1224 WDCDEBUG_PRINT(("wdc_exec_command %s:%d:%d\n", 1225 chp->wdc->sc_dev.dv_xname, chp->channel, drvp->drive), 1226 DEBUG_FUNCS); 1227 1228 /* set up an xfer and queue. Wait for completion */ 1229 xfer = wdc_get_xfer(wdc_c->flags & AT_WAIT ? WDC_CANSLEEP : 1230 WDC_NOSLEEP); 1231 if (xfer == NULL) { 1232 return WDC_TRY_AGAIN; 1233 } 1234 1235 if (wdc_c->flags & AT_POLL) 1236 xfer->c_flags |= C_POLL; 1237 xfer->drive = drvp->drive; 1238 xfer->databuf = wdc_c->data; 1239 xfer->c_bcount = wdc_c->bcount; 1240 xfer->cmd = wdc_c; 1241 xfer->c_start = __wdccommand_start; 1242 xfer->c_intr = __wdccommand_intr; 1243 xfer->c_kill_xfer = __wdccommand_done; 1244 1245 s = splbio(); 1246 wdc_exec_xfer(chp, xfer); 1247 #ifdef DIAGNOSTIC 1248 if ((wdc_c->flags & AT_POLL) != 0 && 1249 (wdc_c->flags & AT_DONE) == 0) 1250 panic("wdc_exec_command: polled command not done\n"); 1251 #endif 1252 if (wdc_c->flags & AT_DONE) { 1253 ret = WDC_COMPLETE; 1254 } else { 1255 if (wdc_c->flags & AT_WAIT) { 1256 while ((wdc_c->flags & AT_DONE) == 0) { 1257 tsleep(wdc_c, PRIBIO, "wdccmd", 0); 1258 } 1259 ret = WDC_COMPLETE; 1260 } else { 1261 ret = WDC_QUEUED; 1262 } 1263 } 1264 splx(s); 1265 return ret; 1266 } 1267 1268 void 1269 __wdccommand_start(chp, xfer) 1270 struct channel_softc *chp; 1271 struct wdc_xfer *xfer; 1272 { 1273 int drive = xfer->drive; 1274 struct wdc_command *wdc_c = xfer->cmd; 1275 1276 WDCDEBUG_PRINT(("__wdccommand_start %s:%d:%d\n", 1277 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), 1278 DEBUG_FUNCS); 1279 1280 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1281 WDSD_IBM | (drive << 4)); 1282 if (wdcwait(chp, wdc_c->r_st_bmask | WDCS_DRQ, wdc_c->r_st_bmask, 1283 wdc_c->timeout) != 0) { 1284 wdc_c->flags |= AT_TIMEOU; 1285 __wdccommand_done(chp, xfer); 1286 return; 1287 } 1288 wdccommand(chp, drive, wdc_c->r_command, wdc_c->r_cyl, wdc_c->r_head, 1289 wdc_c->r_sector, wdc_c->r_count, wdc_c->r_precomp); 1290 if ((wdc_c->flags & AT_POLL) == 0) { 1291 chp->ch_flags |= WDCF_IRQ_WAIT; /* wait for interrupt */ 1292 callout_reset(&chp->ch_callout, wdc_c->timeout / 1000 * hz, 1293 wdctimeout, chp); 1294 return; 1295 } 1296 /* 1297 * Polled command. Wait for drive ready or drq. Done in intr(). 1298 * Wait for at last 400ns for status bit to be valid. 1299 */ 1300 delay(10); 1301 __wdccommand_intr(chp, xfer, 0); 1302 } 1303 1304 int 1305 __wdccommand_intr(chp, xfer, irq) 1306 struct channel_softc *chp; 1307 struct wdc_xfer *xfer; 1308 int irq; 1309 { 1310 struct wdc_command *wdc_c = xfer->cmd; 1311 int bcount = wdc_c->bcount; 1312 char *data = wdc_c->data; 1313 1314 WDCDEBUG_PRINT(("__wdccommand_intr %s:%d:%d\n", 1315 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_INTR); 1316 if (wdcwait(chp, wdc_c->r_st_pmask, wdc_c->r_st_pmask, 1317 (irq == 0) ? wdc_c->timeout : 0)) { 1318 if (irq && (xfer->c_flags & C_TIMEOU) == 0) 1319 return 0; /* IRQ was not for us */ 1320 wdc_c->flags |= AT_TIMEOU; 1321 __wdccommand_done(chp, xfer); 1322 return 1; 1323 } 1324 if (chp->wdc->cap & WDC_CAPABILITY_IRQACK) 1325 chp->wdc->irqack(chp); 1326 if (wdc_c->flags & AT_READ) { 1327 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1328 bus_space_read_multi_4(chp->data32iot, chp->data32ioh, 1329 0, (u_int32_t*)data, bcount >> 2); 1330 data += bcount & 0xfffffffc; 1331 bcount = bcount & 0x03; 1332 } 1333 if (bcount > 0) 1334 bus_space_read_multi_2(chp->cmd_iot, chp->cmd_ioh, 1335 wd_data, (u_int16_t *)data, bcount >> 1); 1336 } else if (wdc_c->flags & AT_WRITE) { 1337 if (chp->ch_drive[xfer->drive].drive_flags & DRIVE_CAP32) { 1338 bus_space_write_multi_4(chp->data32iot, chp->data32ioh, 1339 0, (u_int32_t*)data, bcount >> 2); 1340 data += bcount & 0xfffffffc; 1341 bcount = bcount & 0x03; 1342 } 1343 if (bcount > 0) 1344 bus_space_write_multi_2(chp->cmd_iot, chp->cmd_ioh, 1345 wd_data, (u_int16_t *)data, bcount >> 1); 1346 } 1347 __wdccommand_done(chp, xfer); 1348 return 1; 1349 } 1350 1351 void 1352 __wdccommand_done(chp, xfer) 1353 struct channel_softc *chp; 1354 struct wdc_xfer *xfer; 1355 { 1356 struct wdc_command *wdc_c = xfer->cmd; 1357 1358 WDCDEBUG_PRINT(("__wdccommand_done %s:%d:%d\n", 1359 chp->wdc->sc_dev.dv_xname, chp->channel, xfer->drive), DEBUG_FUNCS); 1360 1361 callout_stop(&chp->ch_callout); 1362 1363 if (chp->ch_status & WDCS_DWF) 1364 wdc_c->flags |= AT_DF; 1365 if (chp->ch_status & WDCS_ERR) { 1366 wdc_c->flags |= AT_ERROR; 1367 wdc_c->r_error = chp->ch_error; 1368 } 1369 wdc_c->flags |= AT_DONE; 1370 if ((wdc_c->flags & AT_READREG) != 0 && 1371 (chp->wdc->sc_dev.dv_flags & DVF_ACTIVE) != 0 && 1372 (wdc_c->flags & (AT_ERROR | AT_DF)) == 0) { 1373 wdc_c->r_head = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1374 wd_sdh); 1375 wdc_c->r_cyl = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1376 wd_cyl_hi) << 8; 1377 wdc_c->r_cyl |= bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1378 wd_cyl_lo); 1379 wdc_c->r_sector = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1380 wd_sector); 1381 wdc_c->r_count = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1382 wd_seccnt); 1383 wdc_c->r_error = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1384 wd_error); 1385 wdc_c->r_precomp = bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, 1386 wd_precomp); 1387 } 1388 wdc_free_xfer(chp, xfer); 1389 if (wdc_c->flags & AT_WAIT) 1390 wakeup(wdc_c); 1391 else if (wdc_c->callback) 1392 wdc_c->callback(wdc_c->callback_arg); 1393 wdcstart(chp); 1394 return; 1395 } 1396 1397 /* 1398 * Send a command. The drive should be ready. 1399 * Assumes interrupts are blocked. 1400 */ 1401 void 1402 wdccommand(chp, drive, command, cylin, head, sector, count, precomp) 1403 struct channel_softc *chp; 1404 u_int8_t drive; 1405 u_int8_t command; 1406 u_int16_t cylin; 1407 u_int8_t head, sector, count, precomp; 1408 { 1409 WDCDEBUG_PRINT(("wdccommand %s:%d:%d: command=0x%x cylin=%d head=%d " 1410 "sector=%d count=%d precomp=%d\n", chp->wdc->sc_dev.dv_xname, 1411 chp->channel, drive, command, cylin, head, sector, count, precomp), 1412 DEBUG_FUNCS); 1413 1414 /* Select drive, head, and addressing mode. */ 1415 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1416 WDSD_IBM | (drive << 4) | head); 1417 /* Load parameters. wd_features(ATA/ATAPI) = wd_precomp(ST506) */ 1418 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_precomp, 1419 precomp); 1420 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_lo, cylin); 1421 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_cyl_hi, cylin >> 8); 1422 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sector, sector); 1423 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_seccnt, count); 1424 1425 /* Send command. */ 1426 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1427 return; 1428 } 1429 1430 /* 1431 * Simplified version of wdccommand(). Unbusy/ready/drq must be 1432 * tested by the caller. 1433 */ 1434 void 1435 wdccommandshort(chp, drive, command) 1436 struct channel_softc *chp; 1437 int drive; 1438 int command; 1439 { 1440 1441 WDCDEBUG_PRINT(("wdccommandshort %s:%d:%d command 0x%x\n", 1442 chp->wdc->sc_dev.dv_xname, chp->channel, drive, command), 1443 DEBUG_FUNCS); 1444 1445 /* Select drive. */ 1446 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_sdh, 1447 WDSD_IBM | (drive << 4)); 1448 1449 bus_space_write_1(chp->cmd_iot, chp->cmd_ioh, wd_command, command); 1450 } 1451 1452 /* Add a command to the queue and start controller. Must be called at splbio */ 1453 1454 void 1455 wdc_exec_xfer(chp, xfer) 1456 struct channel_softc *chp; 1457 struct wdc_xfer *xfer; 1458 { 1459 WDCDEBUG_PRINT(("wdc_exec_xfer %p channel %d drive %d\n", xfer, 1460 chp->channel, xfer->drive), DEBUG_XFERS); 1461 1462 /* complete xfer setup */ 1463 xfer->chp = chp; 1464 1465 /* 1466 * If we are a polled command, and the list is not empty, 1467 * we are doing a dump. Drop the list to allow the polled command 1468 * to complete, we're going to reboot soon anyway. 1469 */ 1470 if ((xfer->c_flags & C_POLL) != 0 && 1471 chp->ch_queue->sc_xfer.tqh_first != NULL) { 1472 TAILQ_INIT(&chp->ch_queue->sc_xfer); 1473 } 1474 /* insert at the end of command list */ 1475 TAILQ_INSERT_TAIL(&chp->ch_queue->sc_xfer,xfer , c_xferchain); 1476 WDCDEBUG_PRINT(("wdcstart from wdc_exec_xfer, flags 0x%x\n", 1477 chp->ch_flags), DEBUG_XFERS); 1478 wdcstart(chp); 1479 } 1480 1481 struct wdc_xfer * 1482 wdc_get_xfer(flags) 1483 int flags; 1484 { 1485 struct wdc_xfer *xfer; 1486 int s; 1487 1488 s = splbio(); 1489 xfer = pool_get(&wdc_xfer_pool, 1490 ((flags & WDC_NOSLEEP) != 0 ? PR_NOWAIT : PR_WAITOK)); 1491 splx(s); 1492 memset(xfer, 0, sizeof(struct wdc_xfer)); 1493 return xfer; 1494 } 1495 1496 void 1497 wdc_free_xfer(chp, xfer) 1498 struct channel_softc *chp; 1499 struct wdc_xfer *xfer; 1500 { 1501 struct wdc_softc *wdc = chp->wdc; 1502 int s; 1503 1504 if (wdc->cap & WDC_CAPABILITY_HWLOCK) 1505 (*wdc->free_hw)(chp); 1506 s = splbio(); 1507 chp->ch_flags &= ~WDCF_ACTIVE; 1508 TAILQ_REMOVE(&chp->ch_queue->sc_xfer, xfer, c_xferchain); 1509 pool_put(&wdc_xfer_pool, xfer); 1510 splx(s); 1511 } 1512 1513 /* 1514 * Kill off all pending xfers for a channel_softc. 1515 * 1516 * Must be called at splbio(). 1517 */ 1518 void 1519 wdc_kill_pending(chp) 1520 struct channel_softc *chp; 1521 { 1522 struct wdc_xfer *xfer; 1523 1524 while ((xfer = TAILQ_FIRST(&chp->ch_queue->sc_xfer)) != NULL) { 1525 chp = xfer->chp; 1526 (*xfer->c_kill_xfer)(chp, xfer); 1527 } 1528 } 1529 1530 static void 1531 __wdcerror(chp, msg) 1532 struct channel_softc *chp; 1533 char *msg; 1534 { 1535 struct wdc_xfer *xfer = chp->ch_queue->sc_xfer.tqh_first; 1536 1537 if (xfer == NULL) 1538 printf("%s:%d: %s\n", chp->wdc->sc_dev.dv_xname, chp->channel, 1539 msg); 1540 else 1541 printf("%s:%d:%d: %s\n", chp->wdc->sc_dev.dv_xname, 1542 chp->channel, xfer->drive, msg); 1543 } 1544 1545 /* 1546 * the bit bucket 1547 */ 1548 void 1549 wdcbit_bucket(chp, size) 1550 struct channel_softc *chp; 1551 int size; 1552 { 1553 1554 for (; size >= 2; size -= 2) 1555 (void)bus_space_read_2(chp->cmd_iot, chp->cmd_ioh, wd_data); 1556 if (size) 1557 (void)bus_space_read_1(chp->cmd_iot, chp->cmd_ioh, wd_data); 1558 } 1559 1560 int 1561 wdc_addref(chp) 1562 struct channel_softc *chp; 1563 { 1564 struct wdc_softc *wdc = chp->wdc; 1565 struct atapi_adapter *adapter = &wdc->sc_atapi_adapter; 1566 int s, error = 0; 1567 1568 s = splbio(); 1569 if (adapter->_generic.scsipi_refcnt++ == 0 && 1570 adapter->_generic.scsipi_enable != NULL) { 1571 error = (*adapter->_generic.scsipi_enable)(wdc, 1); 1572 if (error) 1573 adapter->_generic.scsipi_refcnt--; 1574 } 1575 splx(s); 1576 return (error); 1577 } 1578 1579 void 1580 wdc_delref(chp) 1581 struct channel_softc *chp; 1582 { 1583 struct wdc_softc *wdc = chp->wdc; 1584 struct atapi_adapter *adapter = &wdc->sc_atapi_adapter; 1585 int s; 1586 1587 s = splbio(); 1588 if (adapter->_generic.scsipi_refcnt-- == 1 && 1589 adapter->_generic.scsipi_enable != NULL) 1590 (void) (*adapter->_generic.scsipi_enable)(wdc, 0); 1591 splx(s); 1592 } 1593