1 /* $NetBSD: wd33c93.c,v 1.33 2024/02/09 22:08:34 andvar Exp $ */
2
3 /*
4 * Copyright (c) 1990 The Regents of the University of California.
5 * All rights reserved.
6 *
7 * This code is derived from software contributed to Berkeley by
8 * Van Jacobson of Lawrence Berkeley Laboratory.
9 *
10 * Redistribution and use in source and binary forms, with or without
11 * modification, are permitted provided that the following conditions
12 * are met:
13 * 1. Redistributions of source code must retain the above copyright
14 * notice, this list of conditions and the following disclaimer.
15 * 2. Redistributions in binary form must reproduce the above copyright
16 * notice, this list of conditions and the following disclaimer in the
17 * documentation and/or other materials provided with the distribution.
18 * 3. Neither the name of the University nor the names of its contributors
19 * may be used to endorse or promote products derived from this software
20 * without specific prior written permission.
21 *
22 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
25 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
26 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
27 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
28 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
29 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
30 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
31 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
32 * SUCH DAMAGE.
33 *
34 * @(#)scsi.c 7.5 (Berkeley) 5/4/91
35 */
36
37 /*
38 * Changes Copyright (c) 2001 Wayne Knowles
39 * Changes Copyright (c) 1996 Steve Woodford
40 * Original Copyright (c) 1994 Christian E. Hopps
41 *
42 * This code is derived from software contributed to Berkeley by
43 * Van Jacobson of Lawrence Berkeley Laboratory.
44 *
45 * Redistribution and use in source and binary forms, with or without
46 * modification, are permitted provided that the following conditions
47 * are met:
48 * 1. Redistributions of source code must retain the above copyright
49 * notice, this list of conditions and the following disclaimer.
50 * 2. Redistributions in binary form must reproduce the above copyright
51 * notice, this list of conditions and the following disclaimer in the
52 * documentation and/or other materials provided with the distribution.
53 * 3. All advertising materials mentioning features or use of this software
54 * must display the following acknowledgement:
55 * This product includes software developed by the University of
56 * California, Berkeley and its contributors.
57 * 4. Neither the name of the University nor the names of its contributors
58 * may be used to endorse or promote products derived from this software
59 * without specific prior written permission.
60 *
61 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
62 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
63 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
64 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
65 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
66 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
67 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
68 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
69 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
70 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
71 * SUCH DAMAGE.
72 *
73 * @(#)scsi.c 7.5 (Berkeley) 5/4/91
74 */
75
76 /*
77 * This version of the driver is pretty well generic, so should work with
78 * any flavour of WD33C93 chip.
79 */
80
81 #include <sys/cdefs.h>
82 __KERNEL_RCSID(0, "$NetBSD: wd33c93.c,v 1.33 2024/02/09 22:08:34 andvar Exp $");
83
84 #include "opt_ddb.h"
85
86 #include <sys/param.h>
87 #include <sys/systm.h>
88 #include <sys/device.h>
89 #include <sys/kernel.h> /* For hz */
90 #include <sys/disklabel.h>
91 #include <sys/buf.h>
92
93 #include <dev/scsipi/scsi_all.h>
94 #include <dev/scsipi/scsipi_all.h>
95 #include <dev/scsipi/scsiconf.h>
96 #include <dev/scsipi/scsi_message.h>
97
98 #include <sys/bus.h>
99
100 #include <dev/ic/wd33c93reg.h>
101 #include <dev/ic/wd33c93var.h>
102
103 /*
104 * SCSI delays
105 * In u-seconds, primarily for state changes on the SPC.
106 */
107 #define SBIC_CMD_WAIT 50000 /* wait per step of 'immediate' cmds */
108 #define SBIC_DATA_WAIT 50000 /* wait per data in/out step */
109 #define SBIC_INIT_WAIT 50000 /* wait per step (both) during init */
110
111 #define STATUS_UNKNOWN 0xff /* uninitialized status */
112
113 /*
114 * Convenience macro for waiting for a particular wd33c93 event
115 */
116 #define SBIC_WAIT(regs, until, timeo) wd33c93_wait(regs, until, timeo, __LINE__)
117
118 void wd33c93_init (struct wd33c93_softc *);
119 void wd33c93_reset (struct wd33c93_softc *);
120 int wd33c93_go (struct wd33c93_softc *, struct wd33c93_acb *);
121 int wd33c93_dmaok (struct wd33c93_softc *, struct scsipi_xfer *);
122 int wd33c93_wait (struct wd33c93_softc *, u_char, int , int);
123 u_char wd33c93_selectbus (struct wd33c93_softc *, struct wd33c93_acb *);
124 int wd33c93_xfout (struct wd33c93_softc *, int, void *);
125 int wd33c93_xfin (struct wd33c93_softc *, int, void *);
126 int wd33c93_poll (struct wd33c93_softc *, struct wd33c93_acb *);
127 int wd33c93_nextstate (struct wd33c93_softc *, struct wd33c93_acb *,
128 u_char, u_char);
129 int wd33c93_abort (struct wd33c93_softc *, struct wd33c93_acb *,
130 const char *);
131 void wd33c93_xferdone (struct wd33c93_softc *);
132 void wd33c93_error (struct wd33c93_softc *, struct wd33c93_acb *);
133 void wd33c93_scsidone (struct wd33c93_softc *, struct wd33c93_acb *, int);
134 void wd33c93_sched (struct wd33c93_softc *);
135 void wd33c93_dequeue (struct wd33c93_softc *, struct wd33c93_acb *);
136 void wd33c93_dma_stop (struct wd33c93_softc *);
137 void wd33c93_dma_setup (struct wd33c93_softc *, int);
138 int wd33c93_msgin_phase (struct wd33c93_softc *, int);
139 void wd33c93_msgin (struct wd33c93_softc *, u_char *, int);
140 void wd33c93_reselect (struct wd33c93_softc *, int, int, int, int);
141 void wd33c93_sched_msgout (struct wd33c93_softc *, u_short);
142 void wd33c93_msgout (struct wd33c93_softc *);
143 void wd33c93_timeout (void *arg);
144 void wd33c93_watchdog (void *arg);
145 u_char wd33c93_stp2syn (struct wd33c93_softc *, struct wd33c93_tinfo *);
146 void wd33c93_setsync (struct wd33c93_softc *, struct wd33c93_tinfo *);
147 void wd33c93_update_xfer_mode (struct wd33c93_softc *, int);
148
149 static struct pool wd33c93_pool; /* Adapter Control Blocks */
150 static int wd33c93_pool_initialized = 0;
151
152 /*
153 * Timeouts
154 */
155 int wd33c93_cmd_wait = SBIC_CMD_WAIT;
156 int wd33c93_data_wait = SBIC_DATA_WAIT;
157 int wd33c93_init_wait = SBIC_INIT_WAIT;
158
159 int wd33c93_nodma = 0; /* Use polled IO transfers */
160 int wd33c93_nodisc = 0; /* Allow command queues */
161 int wd33c93_notags = 0; /* No Tags */
162
163 /*
164 * Some useful stuff for debugging purposes
165 */
166 #ifdef DEBUG
167
168 #define QPRINTF(a) SBIC_DEBUG(MISC, a)
169
170 int wd33c93_debug = 0; /* Debug flags */
171
172 void wd33c93_print_csr (u_char);
173 void wd33c93_hexdump (u_char *, int);
174
175 #else
176 #define QPRINTF(a) /* */
177 #endif
178
179 static const char *wd33c93_chip_names[] = SBIC_CHIP_LIST;
180
181 /*
182 * Attach instance of driver and probe for sub devices
183 */
184 void
wd33c93_attach(struct wd33c93_softc * sc)185 wd33c93_attach(struct wd33c93_softc *sc)
186 {
187 struct scsipi_adapter *adapt = &sc->sc_adapter;
188 struct scsipi_channel *chan = &sc->sc_channel;
189
190 adapt->adapt_dev = sc->sc_dev;
191 adapt->adapt_nchannels = 1;
192 adapt->adapt_openings = 256;
193 adapt->adapt_max_periph = 256; /* Max tags per device */
194 adapt->adapt_ioctl = NULL;
195 /* adapt_request initialized by MD interface */
196 /* adapt_minphys initialized by MD interface */
197
198 memset(chan, 0, sizeof(*chan));
199 chan->chan_adapter = &sc->sc_adapter;
200 chan->chan_bustype = &scsi_bustype;
201 chan->chan_channel = 0;
202 chan->chan_ntargets = SBIC_NTARG;
203 chan->chan_nluns = SBIC_NLUN;
204 chan->chan_id = sc->sc_id;
205
206 callout_init(&sc->sc_watchdog, 0);
207
208 /*
209 * Add reference to adapter so that we drop the reference after
210 * config_found() to make sure the adapter is disabled.
211 */
212 if (scsipi_adapter_addref(&sc->sc_adapter) != 0) {
213 aprint_error_dev(sc->sc_dev, "unable to enable controller\n");
214 return;
215 }
216
217 sc->sc_cfflags = device_cfdata(sc->sc_dev)->cf_flags;
218 wd33c93_init(sc);
219
220 aprint_normal(": %s (%d.%d MHz clock, %s, SCSI ID %d)\n",
221 wd33c93_chip_names[sc->sc_chip],
222 sc->sc_clkfreq / 10, sc->sc_clkfreq % 10,
223 (sc->sc_dmamode == SBIC_CTL_DMA) ? "DMA" :
224 (sc->sc_dmamode == SBIC_CTL_DBA_DMA) ? "DBA" :
225 (sc->sc_dmamode == SBIC_CTL_BURST_DMA) ? "BURST DMA" : "PIO",
226 sc->sc_channel.chan_id);
227 if (sc->sc_chip == SBIC_CHIP_WD33C93B) {
228 aprint_normal_dev(sc->sc_dev, "microcode revision 0x%02x",
229 sc->sc_rev);
230 if (sc->sc_minsyncperiod < 50)
231 aprint_normal(", Fast SCSI");
232 aprint_normal("\n");
233 }
234
235 sc->sc_child = config_found(sc->sc_dev, &sc->sc_channel,
236 scsiprint, CFARGS_NONE);
237 scsipi_adapter_delref(&sc->sc_adapter);
238 }
239
240 /*
241 * Initialize driver-private structures
242 */
243 void
wd33c93_init(struct wd33c93_softc * sc)244 wd33c93_init(struct wd33c93_softc *sc)
245 {
246 u_int i;
247
248 if (!wd33c93_pool_initialized) {
249 /* All instances share the same pool */
250 pool_init(&wd33c93_pool, sizeof(struct wd33c93_acb), 0, 0, 0,
251 "wd33c93_acb", NULL, IPL_BIO);
252 ++wd33c93_pool_initialized;
253 }
254
255 if (sc->sc_state == 0) {
256 TAILQ_INIT(&sc->ready_list);
257
258 sc->sc_nexus = NULL;
259 sc->sc_disc = 0;
260 memset(sc->sc_tinfo, 0, sizeof(sc->sc_tinfo));
261
262 callout_reset(&sc->sc_watchdog, 60 * hz, wd33c93_watchdog, sc);
263 } else
264 panic("wd33c93: reinitializing driver!");
265
266 sc->sc_flags = 0;
267 sc->sc_state = SBIC_IDLE;
268 wd33c93_reset(sc);
269
270 for (i = 0; i < 8; i++) {
271 struct wd33c93_tinfo *ti = &sc->sc_tinfo[i];
272 /*
273 * cf_flags = 0xTTSSRR
274 *
275 * TT = Bitmask to disable Tagged Queues
276 * SS = Bitmask to disable Sync negotiation
277 * RR = Bitmask to disable disconnect/reselect
278 */
279 ti->flags = T_NEED_RESET;
280 if (CFFLAGS_NOSYNC(sc->sc_cfflags, i))
281 ti->flags |= T_NOSYNC;
282 if (CFFLAGS_NODISC(sc->sc_cfflags, i) || wd33c93_nodisc)
283 ti->flags |= T_NODISC;
284 ti->period = sc->sc_minsyncperiod;
285 ti->offset = 0;
286 }
287 }
288
289 void
wd33c93_reset(struct wd33c93_softc * sc)290 wd33c93_reset(struct wd33c93_softc *sc)
291 {
292 u_int my_id, s, div, i;
293 u_char csr, reg;
294
295 SET_SBIC_cmd(sc, SBIC_CMD_ABORT);
296 WAIT_CIP(sc);
297
298 s = splbio();
299
300 if (sc->sc_reset != NULL)
301 (*sc->sc_reset)(sc);
302
303 my_id = sc->sc_channel.chan_id & SBIC_ID_MASK;
304
305 /* Enable advanced features and really(!) advanced features */
306 #if 1
307 my_id |= (SBIC_ID_EAF | SBIC_ID_RAF); /* XXX - MD Layer */
308 #endif
309
310 SET_SBIC_myid(sc, my_id);
311
312 /* Reset the chip */
313 SET_SBIC_cmd(sc, SBIC_CMD_RESET);
314 DELAY(25);
315 SBIC_WAIT(sc, SBIC_ASR_INT, 0);
316
317 /* Set up various chip parameters */
318 SET_SBIC_control(sc, SBIC_CTL_EDI | SBIC_CTL_IDI);
319
320 GET_SBIC_csr(sc, csr); /* clears interrupt also */
321 GET_SBIC_cdb1(sc, sc->sc_rev); /* valid with RAF on wd33c93b */
322
323 switch (csr) {
324 case SBIC_CSR_RESET:
325 sc->sc_chip = SBIC_CHIP_WD33C93;
326 break;
327 case SBIC_CSR_RESET_AM:
328 SET_SBIC_queue_tag(sc, 0x55);
329 GET_SBIC_queue_tag(sc, reg);
330 sc->sc_chip = (reg == 0x55) ?
331 SBIC_CHIP_WD33C93B : SBIC_CHIP_WD33C93A;
332 SET_SBIC_queue_tag(sc, 0x0);
333 break;
334 default:
335 sc->sc_chip = SBIC_CHIP_UNKNOWN;
336 }
337
338 /*
339 * Choose a suitable clock divisor and work out the resulting
340 * sync transfer periods in 4ns units.
341 */
342 if (sc->sc_clkfreq < 110) {
343 my_id |= SBIC_ID_FS_8_10;
344 div = 2;
345 } else if (sc->sc_clkfreq < 160) {
346 my_id |= SBIC_ID_FS_12_15;
347 div = 3;
348 } else if (sc->sc_clkfreq < 210) {
349 my_id |= SBIC_ID_FS_16_20;
350 div = 4;
351 } else
352 panic("wd33c93: invalid clock speed %d", sc->sc_clkfreq);
353
354 for (i = 0; i < 7; i++)
355 sc->sc_syncperiods[i] =
356 (i + 2) * div * 1250 / sc->sc_clkfreq;
357 sc->sc_minsyncperiod = sc->sc_syncperiods[0];
358 SBIC_DEBUG(SYNC, ("available sync periods: %d %d %d %d %d %d %d\n",
359 sc->sc_syncperiods[0], sc->sc_syncperiods[1],
360 sc->sc_syncperiods[2], sc->sc_syncperiods[3],
361 sc->sc_syncperiods[4], sc->sc_syncperiods[5],
362 sc->sc_syncperiods[6]));
363
364 if (sc->sc_clkfreq >= 160 && sc->sc_chip == SBIC_CHIP_WD33C93B) {
365 for (i = 0; i < 3; i++)
366 sc->sc_fsyncperiods[i] =
367 (i + 2) * 2 * 1250 / sc->sc_clkfreq;
368 SBIC_DEBUG(SYNC, ("available fast sync periods: %d %d %d\n",
369 sc->sc_fsyncperiods[0], sc->sc_fsyncperiods[1],
370 sc->sc_fsyncperiods[2]));
371 sc->sc_minsyncperiod = sc->sc_fsyncperiods[0];
372 }
373
374 /* Max Sync Offset */
375 if (sc->sc_chip == SBIC_CHIP_WD33C93A ||
376 sc->sc_chip == SBIC_CHIP_WD33C93B)
377 sc->sc_maxoffset = SBIC_SYN_93AB_MAX_OFFSET;
378 else
379 sc->sc_maxoffset = SBIC_SYN_93_MAX_OFFSET;
380
381 /*
382 * don't allow Selection (SBIC_RID_ES)
383 * until we can handle target mode!!
384 */
385 SET_SBIC_rselid(sc, SBIC_RID_ER);
386
387 /* Asynchronous for now */
388 SET_SBIC_syn(sc, 0);
389
390 sc->sc_flags = 0;
391 sc->sc_state = SBIC_IDLE;
392
393 splx(s);
394 }
395
396 void
wd33c93_error(struct wd33c93_softc * sc,struct wd33c93_acb * acb)397 wd33c93_error(struct wd33c93_softc *sc, struct wd33c93_acb *acb)
398 {
399 struct scsipi_xfer *xs = acb->xs;
400
401 KASSERT(xs);
402
403 if (xs->xs_control & XS_CTL_SILENT)
404 return;
405
406 scsipi_printaddr(xs->xs_periph);
407 printf("SCSI Error\n");
408 }
409
410 /*
411 * Determine an appropriate value for the synchronous transfer register
412 * given the period and offset values in *ti.
413 */
414 u_char
wd33c93_stp2syn(struct wd33c93_softc * sc,struct wd33c93_tinfo * ti)415 wd33c93_stp2syn(struct wd33c93_softc *sc, struct wd33c93_tinfo *ti)
416 {
417 unsigned i;
418
419 /* see if we can handle fast scsi (100-200ns) first */
420 if (ti->period < 50 && sc->sc_minsyncperiod < 50) {
421 for (i = 0; i < 3; i++)
422 if (sc->sc_fsyncperiods[i] >= ti->period)
423 return (SBIC_SYN(ti->offset, i + 2, 1));
424 }
425
426 for (i = 0; i < 7; i++) {
427 if (sc->sc_syncperiods[i] >= ti->period) {
428 if (i == 6)
429 return (SBIC_SYN(0, 0, 0));
430 else
431 return (SBIC_SYN(ti->offset, i + 2, 0));
432 }
433 }
434
435 /* XXX - can't handle it; do async */
436 return (SBIC_SYN(0, 0, 0));
437 }
438
439 /*
440 * Setup sync mode for given target
441 */
442 void
wd33c93_setsync(struct wd33c93_softc * sc,struct wd33c93_tinfo * ti)443 wd33c93_setsync(struct wd33c93_softc *sc, struct wd33c93_tinfo *ti)
444 {
445 u_char syncreg;
446
447 if (ti->flags & T_SYNCMODE)
448 syncreg = wd33c93_stp2syn(sc, ti);
449 else
450 syncreg = SBIC_SYN(0, 0, 0);
451
452 SBIC_DEBUG(SYNC, ("wd33c93_setsync: sync reg = 0x%02x\n", syncreg));
453 SET_SBIC_syn(sc, syncreg);
454 }
455
456 /*
457 * Check if current operation can be done using DMA
458 *
459 * returns 1 if DMA OK, 0 for polled I/O transfer
460 */
461 int
wd33c93_dmaok(struct wd33c93_softc * sc,struct scsipi_xfer * xs)462 wd33c93_dmaok(struct wd33c93_softc *sc, struct scsipi_xfer *xs)
463 {
464 if (wd33c93_nodma || sc->sc_dmamode == SBIC_CTL_NO_DMA ||
465 (xs->xs_control & XS_CTL_POLL) || xs->datalen == 0)
466 return (0);
467 return(1);
468 }
469
470 /*
471 * Setup for DMA transfer
472 */
473 void
wd33c93_dma_setup(struct wd33c93_softc * sc,int datain)474 wd33c93_dma_setup(struct wd33c93_softc *sc, int datain)
475 {
476 struct wd33c93_acb *acb = sc->sc_nexus;
477 int s;
478
479 sc->sc_daddr = acb->daddr;
480 sc->sc_dleft = acb->dleft;
481
482 s = splbio();
483 /* Indicate that we're in DMA mode */
484 if (sc->sc_dleft) {
485 sc->sc_dmasetup(sc, &sc->sc_daddr, &sc->sc_dleft,
486 datain, &sc->sc_dleft);
487 }
488 splx(s);
489 return;
490 }
491
492
493 /*
494 * Save DMA pointers. Take into account partial transfer. Shut down DMA.
495 */
496 void
wd33c93_dma_stop(struct wd33c93_softc * sc)497 wd33c93_dma_stop(struct wd33c93_softc *sc)
498 {
499 size_t count;
500 int asr;
501
502 /* Wait until WD chip is idle */
503 do {
504 GET_SBIC_asr(sc, asr); /* XXX */
505 if (asr & SBIC_ASR_DBR) {
506 printf("wd33c93_dma_stop: asr %02x canceled!\n", asr);
507 break;
508 }
509 } while (asr & (SBIC_ASR_BSY|SBIC_ASR_CIP));
510
511 /* Only need to save pointers if DMA was active */
512 if (sc->sc_flags & SBICF_INDMA) {
513 int s = splbio();
514
515 /* Shut down DMA and flush FIFO's */
516 sc->sc_dmastop(sc);
517
518 /* Fetch the residual count */
519 SBIC_TC_GET(sc, count);
520
521 /* Work out how many bytes were actually transferred */
522 count = sc->sc_tcnt - count;
523
524 if (sc->sc_dleft < count)
525 printf("xfer too large: dleft=%zu resid=%zu\n",
526 sc->sc_dleft, count);
527
528 /* Fixup partial xfers */
529 sc->sc_daddr = (char *)sc->sc_daddr + count;
530 sc->sc_dleft -= count;
531 sc->sc_tcnt = 0;
532 sc->sc_flags &= ~SBICF_INDMA;
533 splx(s);
534 SBIC_DEBUG(DMA, ("dma_stop\n"));
535 }
536 /*
537 * Ensure the WD chip is back in polled I/O mode, with nothing to
538 * transfer.
539 */
540 SBIC_TC_PUT(sc, 0);
541 SET_SBIC_control(sc, SBIC_CTL_EDI | SBIC_CTL_IDI);
542 }
543
544
545 /*
546 * Handle new request from scsipi layer
547 */
548 void
wd33c93_scsi_request(struct scsipi_channel * chan,scsipi_adapter_req_t req,void * arg)549 wd33c93_scsi_request(struct scsipi_channel *chan, scsipi_adapter_req_t req, void *arg)
550 {
551 struct wd33c93_softc *sc =
552 device_private(chan->chan_adapter->adapt_dev);
553 struct scsipi_xfer *xs;
554 struct scsipi_periph *periph;
555 struct wd33c93_acb *acb;
556 int flags, s;
557
558 SBIC_DEBUG(MISC, ("wd33c93_scsi_request: req 0x%x\n", (int)req));
559
560 switch (req) {
561 case ADAPTER_REQ_RUN_XFER:
562 xs = arg;
563 periph = xs->xs_periph;
564 flags = xs->xs_control;
565
566 if (flags & XS_CTL_DATA_UIO)
567 panic("wd33c93: scsi data uio requested");
568
569 if (sc->sc_nexus && (flags & XS_CTL_POLL))
570 panic("wd33c93_scsicmd: busy");
571
572 s = splbio();
573 acb = pool_get(&wd33c93_pool, PR_NOWAIT);
574 splx(s);
575
576 if (acb == NULL) {
577 scsipi_printaddr(periph);
578 printf("cannot allocate acb\n");
579 xs->error = XS_RESOURCE_SHORTAGE;
580 scsipi_done(xs);
581 return;
582 }
583
584 acb->flags = ACB_ACTIVE;
585 acb->xs = xs;
586 acb->clen = xs->cmdlen;
587 acb->daddr = xs->data;
588 acb->dleft = xs->datalen;
589 acb->timeout = xs->timeout;
590 memcpy(&acb->cmd, xs->cmd, xs->cmdlen);
591
592 if (flags & XS_CTL_POLL) {
593 /*
594 * Complete currently active command(s) before
595 * issuing an immediate command
596 */
597 while (sc->sc_nexus)
598 wd33c93_poll(sc, sc->sc_nexus);
599 }
600
601 s = splbio();
602 TAILQ_INSERT_TAIL(&sc->ready_list, acb, chain);
603 acb->flags |= ACB_READY;
604
605 /* If nothing is active, try to start it now. */
606 if (sc->sc_state == SBIC_IDLE)
607 wd33c93_sched(sc);
608 splx(s);
609
610 if ((flags & XS_CTL_POLL) == 0)
611 return;
612
613 if (wd33c93_poll(sc, acb)) {
614 wd33c93_timeout(acb);
615 if (wd33c93_poll(sc, acb)) /* 2nd retry for ABORT */
616 wd33c93_timeout(acb);
617 }
618 return;
619
620 case ADAPTER_REQ_GROW_RESOURCES:
621 /* XXX Not supported. */
622 return;
623
624 case ADAPTER_REQ_SET_XFER_MODE:
625 {
626 struct wd33c93_tinfo *ti;
627 struct scsipi_xfer_mode *xm = arg;
628
629 ti = &sc->sc_tinfo[xm->xm_target];
630 ti->flags &= ~T_WANTSYNC;
631
632 if ((CFFLAGS_NOTAGS(sc->sc_cfflags, xm->xm_target) == 0) &&
633 (xm->xm_mode & PERIPH_CAP_TQING) && !wd33c93_notags)
634 ti->flags |= T_TAG;
635 else
636 ti->flags &= ~T_TAG;
637
638 SBIC_DEBUG(SYNC, ("wd33c93_scsi_request: "
639 "target %d: scsipi requested %s\n", xm->xm_target,
640 (xm->xm_mode & PERIPH_CAP_SYNC) ? "sync" : "async"));
641
642 if ((xm->xm_mode & PERIPH_CAP_SYNC) != 0 &&
643 (ti->flags & T_NOSYNC) == 0)
644 ti->flags |= T_WANTSYNC;
645 /*
646 * If we're not going to negotiate, send the notification
647 * now, since it won't happen later.
648 */
649 if (!(ti->flags & T_WANTSYNC) == !(ti->flags & T_SYNCMODE))
650 wd33c93_update_xfer_mode(sc, xm->xm_target);
651 else
652 ti->flags |= T_NEGOTIATE;
653 return;
654 }
655
656 }
657 }
658
659 /*
660 * attempt to start the next available command
661 */
662 void
wd33c93_sched(struct wd33c93_softc * sc)663 wd33c93_sched(struct wd33c93_softc *sc)
664 {
665 struct scsipi_periph *periph = NULL; /* Gag the compiler */
666 struct wd33c93_acb *acb;
667 struct wd33c93_tinfo *ti;
668 struct wd33c93_linfo *li;
669 int lun, tag, flags;
670
671 if (sc->sc_state != SBIC_IDLE)
672 return;
673
674 KASSERT(sc->sc_nexus == NULL);
675
676 /* Loop through the ready list looking for work to do... */
677 TAILQ_FOREACH(acb, &sc->ready_list, chain) {
678 periph = acb->xs->xs_periph;
679 lun = periph->periph_lun;
680 ti = &sc->sc_tinfo[periph->periph_target];
681 li = TINFO_LUN(ti, lun);
682
683 KASSERT(acb->flags & ACB_READY);
684
685 /* Select type of tag for this command */
686 if ((ti->flags & T_NODISC) != 0)
687 tag = 0;
688 else if ((ti->flags & T_TAG) == 0)
689 tag = 0;
690 else if ((acb->flags & ACB_SENSE) != 0)
691 tag = 0;
692 else if (acb->xs->xs_control & XS_CTL_POLL)
693 tag = 0; /* No tags for polled commands */
694 else
695 tag = acb->xs->xs_tag_type;
696
697 if (li == NULL) {
698 /* Initialize LUN info and add to list. */
699 li = malloc(sizeof(*li), M_DEVBUF, M_NOWAIT);
700 if (li == NULL)
701 continue;
702 memset(li, 0, sizeof(*li));
703 li->lun = lun;
704 if (lun < SBIC_NLUN)
705 ti->lun[lun] = li;
706 }
707 li->last_used = time_second;
708
709 /*
710 * We've found a potential command, but is the target/lun busy?
711 */
712
713 if (tag == 0 && li->untagged == NULL)
714 li->untagged = acb; /* Issue untagged */
715
716 if (li->untagged != NULL) {
717 tag = 0;
718 if ((li->state != L_STATE_BUSY) && li->used == 0) {
719 /* Issue this untagged command now */
720 acb = li->untagged;
721 periph = acb->xs->xs_periph;
722 } else /* Not ready yet */
723 continue;
724 }
725
726 acb->tag_type = tag;
727 if (tag != 0) {
728 if (li->queued[acb->xs->xs_tag_id])
729 printf("queueing to active tag\n");
730 li->queued[acb->xs->xs_tag_id] = acb;
731 acb->tag_id = acb->xs->xs_tag_id;
732 li->used++;
733 break;
734 }
735 if (li->untagged != NULL && (li->state != L_STATE_BUSY)) {
736 li->state = L_STATE_BUSY;
737 break;
738 }
739 if (li->untagged == NULL && tag != 0) {
740 break;
741 } else
742 printf("%d:%d busy\n", periph->periph_target,
743 periph->periph_lun);
744 }
745
746 if (acb == NULL) {
747 SBIC_DEBUG(ACBS, ("wd33c93sched: no work\n"));
748 return; /* did not find an available command */
749 }
750
751 SBIC_DEBUG(ACBS, ("wd33c93_sched(%d,%d)\n", periph->periph_target,
752 periph->periph_lun));
753
754 TAILQ_REMOVE(&sc->ready_list, acb, chain);
755 acb->flags &= ~ACB_READY;
756
757 flags = acb->xs->xs_control;
758 if (flags & XS_CTL_RESET)
759 wd33c93_reset(sc);
760
761 /* XXX - Implicitly call scsidone on select timeout */
762 if (wd33c93_go(sc, acb) != 0 || acb->xs->error == XS_SELTIMEOUT) {
763 acb->dleft = sc->sc_dleft;
764 wd33c93_scsidone(sc, acb, sc->sc_status);
765 return;
766 }
767
768 return;
769 }
770
771 void
wd33c93_scsidone(struct wd33c93_softc * sc,struct wd33c93_acb * acb,int status)772 wd33c93_scsidone(struct wd33c93_softc *sc, struct wd33c93_acb *acb, int status)
773 {
774 struct scsipi_xfer *xs = acb->xs;
775 struct wd33c93_tinfo *ti;
776 struct wd33c93_linfo *li;
777 int s;
778
779 #ifdef DIAGNOSTIC
780 KASSERT(sc->target == xs->xs_periph->periph_target);
781 KASSERT(sc->lun == xs->xs_periph->periph_lun);
782 if (acb == NULL || xs == NULL) {
783 panic("wd33c93_scsidone -- (%d,%d) no scsipi_xfer",
784 sc->target, sc->lun);
785 }
786 KASSERT(acb->flags != ACB_FREE);
787 #endif
788
789 SBIC_DEBUG(ACBS, ("scsidone: (%d,%d)->(%d,%d)%02x\n",
790 xs->xs_periph->periph_target, xs->xs_periph->periph_lun,
791 sc->target, sc->lun, status));
792 callout_stop(&xs->xs_callout);
793
794 xs->status = status & SCSI_STATUS_MASK;
795 xs->resid = acb->dleft;
796
797 if (xs->error == XS_NOERROR) {
798 switch (xs->status) {
799 case SCSI_CHECK:
800 case SCSI_TERMINATED:
801 /* XXX Need to read sense - return busy for now */
802 /*FALLTHROUGH*/
803 case SCSI_QUEUE_FULL:
804 case SCSI_BUSY:
805 xs->error = XS_BUSY;
806 break;
807 }
808 }
809
810 ti = &sc->sc_tinfo[sc->target];
811 li = TINFO_LUN(ti, sc->lun);
812 ti->cmds++;
813 if (xs->error == XS_SELTIMEOUT) {
814 /* Selection timeout -- discard this LUN if empty */
815 if (li->untagged == NULL && li->used == 0) {
816 if (sc->lun < SBIC_NLUN)
817 ti->lun[sc->lun] = NULL;
818 free(li, M_DEVBUF);
819 }
820 }
821
822 wd33c93_dequeue(sc, acb);
823 if (sc->sc_nexus == acb) {
824 sc->sc_state = SBIC_IDLE;
825 sc->sc_nexus = NULL;
826 sc->sc_flags = 0;
827
828 if (!TAILQ_EMPTY(&sc->ready_list))
829 wd33c93_sched(sc);
830 }
831
832 /* place control block back on free list. */
833 s = splbio();
834 acb->flags = ACB_FREE;
835 pool_put(&wd33c93_pool, acb);
836 splx(s);
837
838 scsipi_done(xs);
839 }
840
841 void
wd33c93_dequeue(struct wd33c93_softc * sc,struct wd33c93_acb * acb)842 wd33c93_dequeue(struct wd33c93_softc *sc, struct wd33c93_acb *acb)
843 {
844 struct wd33c93_tinfo *ti = &sc->sc_tinfo[acb->xs->xs_periph->periph_target];
845 struct wd33c93_linfo *li;
846 int lun = acb->xs->xs_periph->periph_lun;
847
848 li = TINFO_LUN(ti, lun);
849 #ifdef DIAGNOSTIC
850 if (li == NULL || li->lun != lun)
851 panic("wd33c93_dequeue: lun %d for ecb %p does not exist",
852 lun, acb);
853 #endif
854 if (li->untagged == acb) {
855 li->state = L_STATE_IDLE;
856 li->untagged = NULL;
857 }
858 if (acb->tag_type && li->queued[acb->tag_id] != NULL) {
859 #ifdef DIAGNOSTIC
860 if (li->queued[acb->tag_id] != NULL &&
861 (li->queued[acb->tag_id] != acb))
862 panic("wd33c93_dequeue: slot %d for lun %d has %p "
863 "instead of acb %p\n", acb->tag_id,
864 lun, li->queued[acb->tag_id], acb);
865 #endif
866 li->queued[acb->tag_id] = NULL;
867 li->used--;
868 }
869 }
870
871
872 int
wd33c93_wait(struct wd33c93_softc * sc,u_char until,int timeo,int line)873 wd33c93_wait(struct wd33c93_softc *sc, u_char until, int timeo, int line)
874 {
875 u_char val;
876
877 if (timeo == 0)
878 timeo = 1000000; /* some large value.. */
879 GET_SBIC_asr(sc, val);
880 while ((val & until) == 0) {
881 if (timeo-- == 0) {
882 int csr;
883 GET_SBIC_csr(sc, csr);
884 printf("wd33c93_wait: TIMEO @%d with asr=x%x csr=x%x\n",
885 line, val, csr);
886 #if defined(DDB) && defined(DEBUG)
887 Debugger();
888 #endif
889 return(val); /* Maybe I should abort */
890 break;
891 }
892 DELAY(1);
893 GET_SBIC_asr(sc, val);
894 }
895 return(val);
896 }
897
898 int
wd33c93_abort(struct wd33c93_softc * sc,struct wd33c93_acb * acb,const char * where)899 wd33c93_abort(struct wd33c93_softc *sc, struct wd33c93_acb *acb,
900 const char *where)
901 {
902 u_char csr, asr;
903
904 GET_SBIC_asr(sc, asr);
905 GET_SBIC_csr(sc, csr);
906
907 scsipi_printaddr(acb->xs->xs_periph);
908 printf ("ABORT in %s: csr=0x%02x, asr=0x%02x\n", where, csr, asr);
909
910 acb->timeout = SBIC_ABORT_TIMEOUT;
911 acb->flags |= ACB_ABORT;
912
913 /*
914 * Clean up chip itself
915 */
916 if (sc->sc_nexus == acb) {
917 /* Reschedule timeout. */
918 callout_reset(&acb->xs->xs_callout, mstohz(acb->timeout),
919 wd33c93_timeout, acb);
920
921 while (asr & SBIC_ASR_DBR) {
922 /*
923 * wd33c93 is jammed w/data. need to clear it
924 * But we don't know what direction it needs to go
925 */
926 GET_SBIC_data(sc, asr);
927 printf("abort %s: clearing data buffer 0x%02x\n",
928 where, asr);
929 GET_SBIC_asr(sc, asr);
930 if (asr & SBIC_ASR_DBR) /* Not the read direction */
931 SET_SBIC_data(sc, asr);
932 GET_SBIC_asr(sc, asr);
933 }
934
935 scsipi_printaddr(acb->xs->xs_periph);
936 printf("sending ABORT command\n");
937
938 WAIT_CIP(sc);
939 SET_SBIC_cmd(sc, SBIC_CMD_ABORT);
940 WAIT_CIP(sc);
941
942 GET_SBIC_asr(sc, asr);
943
944 scsipi_printaddr(acb->xs->xs_periph);
945 if (asr & (SBIC_ASR_BSY|SBIC_ASR_LCI)) {
946 /*
947 * ok, get more drastic..
948 */
949 printf("Resetting bus\n");
950 wd33c93_reset(sc);
951 } else {
952 printf("sending DISCONNECT to target\n");
953 SET_SBIC_cmd(sc, SBIC_CMD_DISC);
954 WAIT_CIP(sc);
955
956 do {
957 SBIC_WAIT (sc, SBIC_ASR_INT, 0);
958 GET_SBIC_asr(sc, asr);
959 GET_SBIC_csr(sc, csr);
960 SBIC_DEBUG(MISC, ("csr: 0x%02x, asr: 0x%02x\n",
961 csr, asr));
962 } while ((csr != SBIC_CSR_DISC) &&
963 (csr != SBIC_CSR_DISC_1) &&
964 (csr != SBIC_CSR_CMD_INVALID));
965 }
966 sc->sc_state = SBIC_ERROR;
967 sc->sc_flags = 0;
968 }
969 return SBIC_STATE_ERROR;
970 }
971
972
973 /*
974 * select the bus, return when selected or error.
975 *
976 * Returns the current CSR following selection and optionally MSG out phase.
977 * i.e. the returned CSR *should* indicate CMD phase...
978 * If the return value is 0, some error happened.
979 */
980 u_char
wd33c93_selectbus(struct wd33c93_softc * sc,struct wd33c93_acb * acb)981 wd33c93_selectbus(struct wd33c93_softc *sc, struct wd33c93_acb *acb)
982 {
983 struct scsipi_xfer *xs = acb->xs;
984 struct wd33c93_tinfo *ti;
985 u_char target, lun, asr, csr, id;
986
987 KASSERT(sc->sc_state == SBIC_IDLE);
988
989 target = xs->xs_periph->periph_target;
990 lun = xs->xs_periph->periph_lun;
991 ti = &sc->sc_tinfo[target];
992
993 sc->sc_state = SBIC_SELECTING;
994 sc->target = target;
995 sc->lun = lun;
996
997 SBIC_DEBUG(PHASE, ("wd33c93_selectbus %d: ", target));
998
999 if ((xs->xs_control & XS_CTL_POLL) == 0)
1000 callout_reset(&xs->xs_callout, mstohz(acb->timeout),
1001 wd33c93_timeout, acb);
1002
1003 /*
1004 * issue select
1005 */
1006 SBIC_TC_PUT(sc, 0);
1007 SET_SBIC_selid(sc, target);
1008 SET_SBIC_timeo(sc, SBIC_TIMEOUT(250, sc->sc_clkfreq));
1009
1010 GET_SBIC_asr(sc, asr);
1011 if (asr & (SBIC_ASR_INT|SBIC_ASR_BSY)) {
1012 /* This means we got ourselves reselected upon */
1013 SBIC_DEBUG(PHASE, ("WD busy (reselect?) ASR=%02x\n", asr));
1014 return 0;
1015 }
1016
1017 SET_SBIC_cmd(sc, SBIC_CMD_SEL_ATN);
1018 WAIT_CIP(sc);
1019
1020 /*
1021 * wait for select (merged from separate function may need
1022 * cleanup)
1023 */
1024 do {
1025 asr = SBIC_WAIT(sc, SBIC_ASR_INT | SBIC_ASR_LCI, 0);
1026 if (asr & SBIC_ASR_LCI) {
1027 QPRINTF(("late LCI: asr %02x\n", asr));
1028 return 0;
1029 }
1030
1031 /* Clear interrupt */
1032 GET_SBIC_csr (sc, csr);
1033
1034 /* Reselected from under our feet? */
1035 if (csr == SBIC_CSR_RSLT_NI || csr == SBIC_CSR_RSLT_IFY) {
1036 SBIC_DEBUG(PHASE, ("got reselected, asr %02x\n", asr));
1037 /*
1038 * We need to handle this now so we don't lock up later
1039 */
1040 wd33c93_nextstate(sc, acb, csr, asr);
1041 return 0;
1042 }
1043
1044 /* Whoops! */
1045 if (csr == SBIC_CSR_SLT || csr == SBIC_CSR_SLT_ATN) {
1046 panic("wd33c93_selectbus: target issued select!");
1047 return 0;
1048 }
1049
1050 } while (csr != (SBIC_CSR_MIS_2 | MESG_OUT_PHASE) &&
1051 csr != (SBIC_CSR_MIS_2 | CMD_PHASE) &&
1052 csr != SBIC_CSR_SEL_TIMEO);
1053
1054 /* Anyone at home? */
1055 if (csr == SBIC_CSR_SEL_TIMEO) {
1056 xs->error = XS_SELTIMEOUT;
1057 SBIC_DEBUG(PHASE, ("-- Selection Timeout\n"));
1058 return 0;
1059 }
1060
1061 SBIC_DEBUG(PHASE, ("Selection Complete\n"));
1062
1063 /* Assume we're now selected */
1064 GET_SBIC_selid(sc, id);
1065 if (id != target) {
1066 /* Something went wrong - wrong target was select */
1067 printf("wd33c93_selectbus: wrong target selected;"
1068 " WANTED %d GOT %d", target, id);
1069 return 0; /* XXX: Need to call nexstate to handle? */
1070 }
1071
1072 sc->sc_flags |= SBICF_SELECTED;
1073 sc->sc_state = SBIC_CONNECTED;
1074
1075 /* setup correct sync mode for this target */
1076 wd33c93_setsync(sc, ti);
1077
1078 if (ti->flags & T_NODISC && sc->sc_disc == 0)
1079 SET_SBIC_rselid (sc, 0); /* Not expecting a reselect */
1080 else
1081 SET_SBIC_rselid (sc, SBIC_RID_ER);
1082
1083 /*
1084 * We only really need to do anything when the target goes to MSG out
1085 * If the device ignored ATN, it's probably old and brain-dead,
1086 * but we'll try to support it anyhow.
1087 * If it doesn't support message out, it definitely doesn't
1088 * support synchronous transfers, so no point in even asking...
1089 */
1090 if (csr == (SBIC_CSR_MIS_2 | MESG_OUT_PHASE)) {
1091 if (ti->flags & T_NEGOTIATE) {
1092 /* Initiate a SDTR message */
1093 SBIC_DEBUG(SYNC, ("Sending SDTR to target %d\n", id));
1094 if (ti->flags & T_WANTSYNC) {
1095 ti->period = sc->sc_minsyncperiod;
1096 ti->offset = sc->sc_maxoffset;
1097 } else {
1098 ti->period = 0;
1099 ti->offset = 0;
1100 }
1101 /* Send Sync negotiation message */
1102 sc->sc_omsg[0] = MSG_IDENTIFY(lun, 0); /* No Disc */
1103 sc->sc_omsg[1] = MSG_EXTENDED;
1104 sc->sc_omsg[2] = MSG_EXT_SDTR_LEN;
1105 sc->sc_omsg[3] = MSG_EXT_SDTR;
1106 if (ti->flags & T_WANTSYNC) {
1107 sc->sc_omsg[4] = sc->sc_minsyncperiod;
1108 sc->sc_omsg[5] = sc->sc_maxoffset;
1109 } else {
1110 sc->sc_omsg[4] = 0;
1111 sc->sc_omsg[5] = 0;
1112 }
1113 wd33c93_xfout(sc, 6, sc->sc_omsg);
1114 sc->sc_msgout |= SEND_SDTR; /* may be rejected */
1115 sc->sc_flags |= SBICF_SYNCNEGO;
1116 } else {
1117 if (sc->sc_nexus->tag_type != 0) {
1118 /* Use TAGS */
1119 SBIC_DEBUG(TAGS, ("<select %d:%d TAG=%x>\n",
1120 sc->target, sc->lun,
1121 sc->sc_nexus->tag_id));
1122 sc->sc_omsg[0] = MSG_IDENTIFY(lun, 1);
1123 sc->sc_omsg[1] = sc->sc_nexus->tag_type;
1124 sc->sc_omsg[2] = sc->sc_nexus->tag_id;
1125 wd33c93_xfout(sc, 3, sc->sc_omsg);
1126 sc->sc_msgout |= SEND_TAG;
1127 } else {
1128 int no_disc;
1129
1130 /* Setup LUN nexus and disconnect privilege */
1131 no_disc = xs->xs_control & XS_CTL_POLL ||
1132 ti->flags & T_NODISC;
1133 SEND_BYTE(sc, MSG_IDENTIFY(lun, !no_disc));
1134 }
1135 }
1136 /*
1137 * There's one interrupt still to come:
1138 * the change to CMD phase...
1139 */
1140 SBIC_WAIT(sc, SBIC_ASR_INT , 0);
1141 GET_SBIC_csr(sc, csr);
1142 }
1143
1144 return csr;
1145 }
1146
1147 /*
1148 * Information Transfer *to* a SCSI Target.
1149 *
1150 * Note: Don't expect there to be an interrupt immediately after all
1151 * the data is transferred out. The WD spec sheet says that the Transfer-
1152 * Info command for non-MSG_IN phases only completes when the target
1153 * next asserts 'REQ'. That is, when the SCSI bus changes to a new state.
1154 *
1155 * This can have a nasty effect on commands which take a relatively long
1156 * time to complete, for example a START/STOP unit command may remain in
1157 * CMD phase until the disk has spun up. Only then will the target change
1158 * to STATUS phase. This is really only a problem for immediate commands
1159 * since we don't allow disconnection for them (yet).
1160 */
1161 int
wd33c93_xfout(struct wd33c93_softc * sc,int len,void * bp)1162 wd33c93_xfout(struct wd33c93_softc *sc, int len, void *bp)
1163 {
1164 int wait = wd33c93_data_wait;
1165 u_char asr, *buf = bp;
1166
1167 QPRINTF(("wd33c93_xfout {%d} %02x %02x %02x %02x %02x "
1168 "%02x %02x %02x %02x %02x\n", len, buf[0], buf[1], buf[2],
1169 buf[3], buf[4], buf[5], buf[6], buf[7], buf[8], buf[9]));
1170
1171 /*
1172 * sigh.. WD-PROTO strikes again.. sending the command in one go
1173 * causes the chip to lock up if talking to certain (misbehaving?)
1174 * targets. Anyway, this procedure should work for all targets, but
1175 * it's slightly slower due to the overhead
1176 */
1177
1178 SET_SBIC_control(sc, SBIC_CTL_EDI | SBIC_CTL_IDI);
1179 SBIC_TC_PUT (sc, (unsigned)len);
1180
1181 WAIT_CIP (sc);
1182 SET_SBIC_cmd (sc, SBIC_CMD_XFER_INFO);
1183
1184 /*
1185 * Loop for each byte transferred
1186 */
1187 do {
1188 GET_SBIC_asr (sc, asr);
1189
1190 if (asr & SBIC_ASR_DBR) {
1191 if (len) {
1192 SET_SBIC_data (sc, *buf);
1193 buf++;
1194 len--;
1195 } else {
1196 SET_SBIC_data (sc, 0);
1197 }
1198 wait = wd33c93_data_wait;
1199 }
1200 } while (len && (asr & SBIC_ASR_INT) == 0 && wait-- > 0);
1201
1202 QPRINTF(("wd33c93_xfout done: %d bytes remaining (wait:%d)\n", len, wait));
1203
1204 /*
1205 * Normally, an interrupt will be pending when this routing returns.
1206 */
1207 return(len);
1208 }
1209
1210 /*
1211 * Information Transfer *from* a Scsi Target
1212 * returns # bytes left to read
1213 */
1214 int
wd33c93_xfin(struct wd33c93_softc * sc,int len,void * bp)1215 wd33c93_xfin(struct wd33c93_softc *sc, int len, void *bp)
1216 {
1217 int wait = wd33c93_data_wait;
1218 u_char *buf = bp;
1219 u_char asr;
1220 #ifdef DEBUG
1221 u_char *obp = bp;
1222 #endif
1223 SET_SBIC_control(sc, SBIC_CTL_EDI | SBIC_CTL_IDI);
1224 SBIC_TC_PUT (sc, (unsigned)len);
1225
1226 WAIT_CIP (sc);
1227 SET_SBIC_cmd (sc, SBIC_CMD_XFER_INFO);
1228
1229 /*
1230 * Loop for each byte transferred
1231 */
1232 do {
1233 GET_SBIC_asr (sc, asr);
1234
1235 if (asr & SBIC_ASR_DBR) {
1236 if (len) {
1237 GET_SBIC_data (sc, *buf);
1238 buf++;
1239 len--;
1240 } else {
1241 u_char foo;
1242 GET_SBIC_data (sc, foo);
1243 __USE(foo);
1244 }
1245 wait = wd33c93_data_wait;
1246 }
1247
1248 } while ((asr & SBIC_ASR_INT) == 0 && wait-- > 0);
1249
1250 QPRINTF(("wd33c93_xfin {%d} %02x %02x %02x %02x %02x %02x "
1251 "%02x %02x %02x %02x\n", len, obp[0], obp[1], obp[2],
1252 obp[3], obp[4], obp[5], obp[6], obp[7], obp[8], obp[9]));
1253
1254 SBIC_TC_PUT (sc, 0);
1255
1256 /*
1257 * this leaves with one csr to be read
1258 */
1259 return len;
1260 }
1261
1262
1263 /*
1264 * Finish SCSI xfer command: After the completion interrupt from
1265 * a read/write operation, sequence through the final phases in
1266 * programmed i/o.
1267 */
1268 void
wd33c93_xferdone(struct wd33c93_softc * sc)1269 wd33c93_xferdone(struct wd33c93_softc *sc)
1270 {
1271 u_char phase, csr;
1272 int s;
1273
1274 QPRINTF(("{"));
1275 s = splbio();
1276
1277 /*
1278 * have the wd33c93 complete on its own
1279 */
1280 SBIC_TC_PUT(sc, 0);
1281 SET_SBIC_cmd_phase(sc, 0x46);
1282 SET_SBIC_cmd(sc, SBIC_CMD_SEL_ATN_XFER);
1283
1284 do {
1285 SBIC_WAIT (sc, SBIC_ASR_INT, 0);
1286 GET_SBIC_csr (sc, csr);
1287 QPRINTF(("%02x:", csr));
1288 } while ((csr != SBIC_CSR_DISC) &&
1289 (csr != SBIC_CSR_DISC_1) &&
1290 (csr != SBIC_CSR_S_XFERRED));
1291
1292 sc->sc_flags &= ~SBICF_SELECTED;
1293 sc->sc_state = SBIC_DISCONNECT;
1294
1295 GET_SBIC_cmd_phase (sc, phase);
1296 QPRINTF(("}%02x", phase));
1297
1298 if (phase == 0x60)
1299 GET_SBIC_tlun(sc, sc->sc_status);
1300 else
1301 wd33c93_error(sc, sc->sc_nexus);
1302
1303 QPRINTF(("=STS:%02x=\n", sc->sc_status));
1304 splx(s);
1305 }
1306
1307
1308 int
wd33c93_go(struct wd33c93_softc * sc,struct wd33c93_acb * acb)1309 wd33c93_go(struct wd33c93_softc *sc, struct wd33c93_acb *acb)
1310 {
1311 struct scsipi_xfer *xs = acb->xs;
1312 int i, dmaok;
1313 u_char csr, asr;
1314
1315 SBIC_DEBUG(ACBS, ("wd33c93_go(%d:%d)\n", sc->target, sc->lun));
1316
1317 sc->sc_nexus = acb;
1318
1319 sc->target = xs->xs_periph->periph_target;
1320 sc->lun = xs->xs_periph->periph_lun;
1321
1322 sc->sc_status = STATUS_UNKNOWN;
1323 sc->sc_daddr = acb->daddr;
1324 sc->sc_dleft = acb->dleft;
1325
1326 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0;
1327 sc->sc_flags = 0;
1328
1329 dmaok = wd33c93_dmaok(sc, xs);
1330
1331 if (dmaok == 0)
1332 sc->sc_flags |= SBICF_NODMA;
1333
1334 SBIC_DEBUG(DMA, ("wd33c93_go dmago:%d(tcnt=%zx) dmaok=%dx\n",
1335 sc->target, sc->sc_tcnt, dmaok));
1336
1337 /* select the SCSI bus (it's an error if bus isn't free) */
1338 if ((csr = wd33c93_selectbus(sc, acb)) == 0)
1339 return(0); /* Not done: needs to be rescheduled */
1340
1341 /*
1342 * Lets cycle a while then let the interrupt handler take over.
1343 */
1344 GET_SBIC_asr(sc, asr);
1345 do {
1346 QPRINTF(("go[0x%x] ", csr));
1347
1348 /* Handle the new phase */
1349 i = wd33c93_nextstate(sc, acb, csr, asr);
1350 WAIT_CIP(sc); /* XXX */
1351 if (sc->sc_state == SBIC_CONNECTED) {
1352
1353 GET_SBIC_asr(sc, asr);
1354
1355 if (asr & SBIC_ASR_LCI)
1356 printf("wd33c93_go: LCI asr:%02x csr:%02x\n", asr, csr);
1357
1358 if (asr & SBIC_ASR_INT)
1359 GET_SBIC_csr(sc, csr);
1360 }
1361
1362 } while (sc->sc_state == SBIC_CONNECTED &&
1363 asr & (SBIC_ASR_INT|SBIC_ASR_LCI));
1364
1365 QPRINTF(("> done i=%d stat=%02x\n", i, sc->sc_status));
1366
1367 if (i == SBIC_STATE_DONE) {
1368 if (sc->sc_status == STATUS_UNKNOWN) {
1369 printf("wd33c93_go: done & stat == UNKNOWN\n");
1370 return 1; /* Did we really finish that fast? */
1371 }
1372 }
1373 return 0;
1374 }
1375
1376
1377 int
wd33c93_intr(struct wd33c93_softc * sc)1378 wd33c93_intr(struct wd33c93_softc *sc)
1379 {
1380 u_char asr, csr;
1381
1382 /*
1383 * pending interrupt?
1384 */
1385 GET_SBIC_asr (sc, asr);
1386 if ((asr & SBIC_ASR_INT) == 0)
1387 return(0);
1388
1389 GET_SBIC_csr(sc, csr);
1390
1391 do {
1392 SBIC_DEBUG(INTS, ("intr[csr=0x%x]", csr));
1393
1394 (void)wd33c93_nextstate(sc, sc->sc_nexus, csr, asr);
1395 WAIT_CIP(sc); /* XXX */
1396 if (sc->sc_state == SBIC_CONNECTED) {
1397 GET_SBIC_asr(sc, asr);
1398
1399 if (asr & SBIC_ASR_LCI)
1400 printf("wd33c93_intr: LCI asr:%02x csr:%02x\n",
1401 asr, csr);
1402
1403 if (asr & SBIC_ASR_INT)
1404 GET_SBIC_csr(sc, csr);
1405 }
1406 } while (sc->sc_state == SBIC_CONNECTED &&
1407 asr & (SBIC_ASR_INT|SBIC_ASR_LCI));
1408
1409 SBIC_DEBUG(INTS, ("intr done. state=%d, asr=0x%02x\n", i, asr));
1410
1411 return(1);
1412 }
1413
1414 /*
1415 * Complete current command using polled I/O. Used when interrupt driven
1416 * I/O is not allowed (ie. during boot and shutdown)
1417 *
1418 * Polled I/O is very processor intensive
1419 */
1420 int
wd33c93_poll(struct wd33c93_softc * sc,struct wd33c93_acb * acb)1421 wd33c93_poll(struct wd33c93_softc *sc, struct wd33c93_acb *acb)
1422 {
1423 u_char asr, csr=0;
1424 int count;
1425 struct scsipi_xfer *xs = acb->xs;
1426
1427 SBIC_WAIT(sc, SBIC_ASR_INT, wd33c93_cmd_wait);
1428 for (count=acb->timeout; count;) {
1429 GET_SBIC_asr (sc, asr);
1430 if (asr & SBIC_ASR_LCI)
1431 printf("wd33c93_poll: LCI; asr:%02x csr:%02x\n",
1432 asr, csr);
1433 if (asr & SBIC_ASR_INT) {
1434 GET_SBIC_csr(sc, csr);
1435 sc->sc_flags |= SBICF_NODMA;
1436 (void)wd33c93_nextstate(sc, sc->sc_nexus, csr, asr);
1437 WAIT_CIP(sc); /* XXX */
1438 } else {
1439 DELAY(1000);
1440 count--;
1441 }
1442
1443 if ((xs->xs_status & XS_STS_DONE) != 0)
1444 return (0);
1445
1446 if (sc->sc_state == SBIC_IDLE) {
1447 SBIC_DEBUG(ACBS, ("[poll: rescheduling] "));
1448 wd33c93_sched(sc);
1449 }
1450 }
1451 return (1);
1452 }
1453
1454 static inline int
__verify_msg_format(u_char * p,int len)1455 __verify_msg_format(u_char *p, int len)
1456 {
1457
1458 if (len == 1 && MSG_IS1BYTE(p[0]))
1459 return 1;
1460 if (len == 2 && MSG_IS2BYTE(p[0]))
1461 return 1;
1462 if (len >= 3 && MSG_ISEXTENDED(p[0]) &&
1463 len == p[1] + 2)
1464 return 1;
1465 return 0;
1466 }
1467
1468 /*
1469 * Handle message_in phase
1470 */
1471 int
wd33c93_msgin_phase(struct wd33c93_softc * sc,int reselect)1472 wd33c93_msgin_phase(struct wd33c93_softc *sc, int reselect)
1473 {
1474 int len;
1475 u_char asr, csr, *msg;
1476
1477 GET_SBIC_asr(sc, asr);
1478 __USE(asr);
1479
1480 SBIC_DEBUG(MSGS, ("wd33c93msgin asr=%02x\n", asr));
1481
1482 GET_SBIC_selid (sc, csr);
1483 SET_SBIC_selid (sc, csr | SBIC_SID_FROM_SCSI);
1484
1485 SBIC_TC_PUT(sc, 0);
1486
1487 SET_SBIC_control(sc, SBIC_CTL_EDI | SBIC_CTL_IDI);
1488
1489 msg = sc->sc_imsg;
1490 len = 0;
1491
1492 do {
1493 /* Fetch the next byte of the message */
1494 RECV_BYTE(sc, *msg++);
1495 len++;
1496
1497 /*
1498 * get the command completion interrupt, or we
1499 * can't send a new command (LCI)
1500 */
1501 SBIC_WAIT(sc, SBIC_ASR_INT, 0);
1502 GET_SBIC_csr(sc, csr);
1503
1504 if (__verify_msg_format(sc->sc_imsg, len))
1505 break; /* Complete message received */
1506
1507 /*
1508 * Clear ACK, and wait for the interrupt
1509 * for the next byte or phase change
1510 */
1511 SET_SBIC_cmd(sc, SBIC_CMD_CLR_ACK);
1512 SBIC_WAIT(sc, SBIC_ASR_INT, 0);
1513
1514 GET_SBIC_csr(sc, csr);
1515 } while (len < SBIC_MAX_MSGLEN);
1516
1517 if (__verify_msg_format(sc->sc_imsg, len))
1518 wd33c93_msgin(sc, sc->sc_imsg, len);
1519
1520 /*
1521 * Clear ACK, and wait for the interrupt
1522 * for the phase change
1523 */
1524 SET_SBIC_cmd(sc, SBIC_CMD_CLR_ACK);
1525 SBIC_WAIT(sc, SBIC_ASR_INT, 0);
1526
1527 /* Should still have one CSR to read */
1528 return SBIC_STATE_RUNNING;
1529 }
1530
1531
wd33c93_msgin(struct wd33c93_softc * sc,u_char * msgaddr,int msglen)1532 void wd33c93_msgin(struct wd33c93_softc *sc, u_char *msgaddr, int msglen)
1533 {
1534 struct wd33c93_acb *acb = sc->sc_nexus;
1535 struct wd33c93_tinfo *ti = &sc->sc_tinfo[sc->target];
1536 struct wd33c93_linfo *li;
1537 u_char asr;
1538
1539 switch (sc->sc_state) {
1540 case SBIC_CONNECTED:
1541 switch (msgaddr[0]) {
1542 case MSG_MESSAGE_REJECT:
1543 SBIC_DEBUG(MSGS, ("msgin: MSG_REJECT, "
1544 "last msgout=%x\n", sc->sc_msgout));
1545 switch (sc->sc_msgout) {
1546 case SEND_TAG:
1547 printf("%s: tagged queuing rejected: "
1548 "target %d\n",
1549 device_xname(sc->sc_dev), sc->target);
1550 ti->flags &= ~T_TAG;
1551 li = TINFO_LUN(ti, sc->lun);
1552 if (acb->tag_type &&
1553 li->queued[acb->tag_id] != NULL) {
1554 li->queued[acb->tag_id] = NULL;
1555 li->used--;
1556 }
1557 acb->tag_type = acb->tag_id = 0;
1558 li->untagged = acb;
1559 li->state = L_STATE_BUSY;
1560 break;
1561
1562 case SEND_SDTR:
1563 printf("%s: sync transfer rejected: target %d\n",
1564 device_xname(sc->sc_dev), sc->target);
1565
1566 sc->sc_flags &= ~SBICF_SYNCNEGO;
1567 ti->flags &= ~(T_NEGOTIATE | T_SYNCMODE);
1568 wd33c93_update_xfer_mode(sc,
1569 acb->xs->xs_periph->periph_target);
1570 wd33c93_setsync(sc, ti);
1571
1572 case SEND_INIT_DET_ERR:
1573 goto abort;
1574
1575 default:
1576 SBIC_DEBUG(MSGS, ("Unexpected MSG_REJECT\n"));
1577 break;
1578 }
1579 sc->sc_msgout = 0;
1580 break;
1581
1582 case MSG_HEAD_OF_Q_TAG:
1583 case MSG_ORDERED_Q_TAG:
1584 case MSG_SIMPLE_Q_TAG:
1585 printf("-- Out of phase TAG;"
1586 "Nexus=%d:%d Tag=%02x/%02x\n",
1587 sc->target, sc->lun, msgaddr[0], msgaddr[1]);
1588 break;
1589
1590 case MSG_DISCONNECT:
1591 SBIC_DEBUG(MSGS, ("msgin: DISCONNECT"));
1592 /*
1593 * Mark the fact that all bytes have moved. The
1594 * target may not bother to do a SAVE POINTERS
1595 * at this stage. This flag will set the residual
1596 * count to zero on MSG COMPLETE.
1597 */
1598 if (sc->sc_dleft == 0)
1599 acb->flags |= ACB_COMPLETE;
1600
1601 if (acb->xs->xs_control & XS_CTL_POLL)
1602 /* Don't allow disconnect in immediate mode */
1603 goto reject;
1604 else { /* Allow disconnect */
1605 sc->sc_flags &= ~SBICF_SELECTED;
1606 sc->sc_state = SBIC_DISCONNECT;
1607 }
1608 if ((acb->xs->xs_periph->periph_quirks &
1609 PQUIRK_AUTOSAVE) == 0)
1610 break;
1611 /*FALLTHROUGH*/
1612
1613 case MSG_SAVEDATAPOINTER:
1614 SBIC_DEBUG(MSGS, ("msgin: SAVEDATAPTR"));
1615 acb->daddr = sc->sc_daddr;
1616 acb->dleft = sc->sc_dleft;
1617 break;
1618
1619 case MSG_RESTOREPOINTERS:
1620 SBIC_DEBUG(MSGS, ("msgin: RESTOREPTR"));
1621 sc->sc_daddr = acb->daddr;
1622 sc->sc_dleft = acb->dleft;
1623 break;
1624
1625 case MSG_CMDCOMPLETE:
1626 /*
1627 * !! KLUDGE ALERT !! quite a few drives don't seem to
1628 * really like the current way of sending the
1629 * sync-handshake together with the ident-message, and
1630 * they react by sending command-complete and
1631 * disconnecting right after returning the valid sync
1632 * handshake. So, all I can do is reselect the drive,
1633 * and hope it won't disconnect again. I don't think
1634 * this is valid behavior, but I can't help fixing a
1635 * problem that apparently exists.
1636 *
1637 * Note: we should not get here on `normal' command
1638 * completion, as that condition is handled by the
1639 * high-level sel&xfer resume command used to walk
1640 * thru status/cc-phase.
1641 */
1642 SBIC_DEBUG(MSGS, ("msgin: CMD_COMPLETE"));
1643 SBIC_DEBUG(SYNC, ("GOT MSG %d! target %d"
1644 " acting weird.."
1645 " waiting for disconnect...\n",
1646 msgaddr[0], sc->target));
1647
1648 /* Check to see if wd33c93 is handling this */
1649 GET_SBIC_asr(sc, asr);
1650 if (asr & SBIC_ASR_BSY)
1651 break;
1652
1653 /* XXX: Assume it works and set status to 00 */
1654 sc->sc_status = 0;
1655 sc->sc_state = SBIC_CMDCOMPLETE;
1656 break;
1657
1658 case MSG_EXTENDED:
1659 switch(msgaddr[2]) {
1660 case MSG_EXT_SDTR: /* Sync negotiation */
1661 SBIC_DEBUG(MSGS, ("msgin: EXT_SDTR; "
1662 "period %d, offset %d",
1663 msgaddr[3], msgaddr[4]));
1664 if (msgaddr[1] != 3)
1665 goto reject;
1666
1667 ti->period =
1668 MAX(msgaddr[3], sc->sc_minsyncperiod);
1669 ti->offset = MIN(msgaddr[4], sc->sc_maxoffset);
1670
1671 /*
1672 * <SGI, IBM DORS-32160, WA6A> will do nothing
1673 * but attempt sync negotiation until it gets
1674 * what it wants. To avoid an infinite loop set
1675 * off by the identify request, oblige them.
1676 */
1677 if ((sc->sc_flags&SBICF_SYNCNEGO) == 0 &&
1678 msgaddr[3] != 0)
1679 ti->flags |= T_WANTSYNC;
1680
1681 if (!(ti->flags & T_WANTSYNC))
1682 ti->period = ti->offset = 0;
1683
1684 ti->flags &= ~T_NEGOTIATE;
1685
1686 if (ti->offset == 0)
1687 ti->flags &= ~T_SYNCMODE; /* Async */
1688 else
1689 ti->flags |= T_SYNCMODE; /* Sync */
1690
1691 /* target initiated negotiation */
1692 if ((sc->sc_flags&SBICF_SYNCNEGO) == 0)
1693 wd33c93_sched_msgout(sc, SEND_SDTR);
1694 sc->sc_flags &= ~SBICF_SYNCNEGO;
1695
1696 SBIC_DEBUG(SYNC, ("msgin(%d): SDTR(o=%d,p=%d)",
1697 sc->target, ti->offset,
1698 ti->period));
1699 wd33c93_update_xfer_mode(sc,
1700 acb->xs->xs_periph->periph_target);
1701 wd33c93_setsync(sc, ti);
1702 break;
1703
1704 case MSG_EXT_WDTR:
1705 SBIC_DEBUG(MSGS, ("msgin: EXT_WDTR rejected"));
1706 goto reject;
1707
1708 default:
1709 scsipi_printaddr(acb->xs->xs_periph);
1710 printf("unrecognized MESSAGE EXTENDED;"
1711 " sending REJECT\n");
1712 goto reject;
1713 }
1714 break;
1715
1716 default:
1717 scsipi_printaddr(acb->xs->xs_periph);
1718 printf("unrecognized MESSAGE; sending REJECT\n");
1719
1720 reject:
1721 /* We don't support whatever this message is... */
1722 wd33c93_sched_msgout(sc, SEND_REJECT);
1723 break;
1724 }
1725 break;
1726
1727 case SBIC_IDENTIFIED:
1728 /*
1729 * IDENTIFY message was received and queue tag is expected now
1730 */
1731 if ((msgaddr[0]!=MSG_SIMPLE_Q_TAG) || (sc->sc_msgify==0)) {
1732 printf("%s: TAG reselect without IDENTIFY;"
1733 " MSG %x; sending DEVICE RESET\n",
1734 device_xname(sc->sc_dev), msgaddr[0]);
1735 goto reset;
1736 }
1737 SBIC_DEBUG(TAGS, ("TAG %x/%x\n", msgaddr[0], msgaddr[1]));
1738 if (sc->sc_nexus)
1739 printf("*TAG Recv with active nexus!!\n");
1740 wd33c93_reselect(sc, sc->target, sc->lun,
1741 msgaddr[0], msgaddr[1]);
1742 break;
1743
1744 case SBIC_RESELECTED:
1745 /*
1746 * IDENTIFY message with target
1747 */
1748 if (MSG_ISIDENTIFY(msgaddr[0])) {
1749 SBIC_DEBUG(PHASE, ("IFFY[%x] ", msgaddr[0]));
1750 sc->sc_msgify = msgaddr[0];
1751 } else {
1752 printf("%s: reselect without IDENTIFY;"
1753 " MSG %x;"
1754 " sending DEVICE RESET\n",
1755 device_xname(sc->sc_dev), msgaddr[0]);
1756 goto reset;
1757 }
1758 break;
1759
1760 default:
1761 printf("Unexpected MESSAGE IN. State=%d - Sending RESET\n",
1762 sc->sc_state);
1763 reset:
1764 wd33c93_sched_msgout(sc, SEND_DEV_RESET);
1765 break;
1766 abort:
1767 wd33c93_sched_msgout(sc, SEND_ABORT);
1768 break;
1769 }
1770 }
1771
1772 void
wd33c93_sched_msgout(struct wd33c93_softc * sc,u_short msg)1773 wd33c93_sched_msgout(struct wd33c93_softc *sc, u_short msg)
1774 {
1775 u_char asr;
1776
1777 SBIC_DEBUG(SYNC,("sched_msgout: %04x\n", msg));
1778 sc->sc_msgpriq |= msg;
1779
1780 /* Schedule MSGOUT Phase to send message */
1781
1782 WAIT_CIP(sc);
1783 SET_SBIC_cmd(sc, SBIC_CMD_SET_ATN);
1784 WAIT_CIP(sc);
1785 GET_SBIC_asr(sc, asr);
1786 if (asr & SBIC_ASR_LCI) {
1787 printf("MSGOUT Failed!\n");
1788 }
1789 SET_SBIC_cmd(sc, SBIC_CMD_CLR_ACK);
1790 WAIT_CIP(sc);
1791 }
1792
1793 /*
1794 * Send the highest priority, scheduled message
1795 */
1796 void
wd33c93_msgout(struct wd33c93_softc * sc)1797 wd33c93_msgout(struct wd33c93_softc *sc)
1798 {
1799 struct wd33c93_tinfo *ti;
1800 struct wd33c93_acb *acb = sc->sc_nexus;
1801
1802 if (acb == NULL)
1803 panic("MSGOUT with no nexus");
1804
1805 if (sc->sc_omsglen == 0) {
1806 /* Pick up highest priority message */
1807 sc->sc_msgout = sc->sc_msgpriq & -sc->sc_msgpriq;
1808 sc->sc_msgoutq |= sc->sc_msgout;
1809 sc->sc_msgpriq &= ~sc->sc_msgout;
1810 sc->sc_omsglen = 1; /* "Default" message len */
1811 switch (sc->sc_msgout) {
1812 case SEND_SDTR:
1813 ti = &sc->sc_tinfo[acb->xs->xs_periph->periph_target];
1814 sc->sc_omsg[0] = MSG_EXTENDED;
1815 sc->sc_omsg[1] = MSG_EXT_SDTR_LEN;
1816 sc->sc_omsg[2] = MSG_EXT_SDTR;
1817 if (ti->flags & T_WANTSYNC) {
1818 sc->sc_omsg[3] = ti->period;
1819 sc->sc_omsg[4] = ti->offset;
1820 } else {
1821 sc->sc_omsg[3] = 0;
1822 sc->sc_omsg[4] = 0;
1823 }
1824 sc->sc_omsglen = 5;
1825 if ((sc->sc_flags & SBICF_SYNCNEGO) == 0) {
1826 if (ti->flags & T_WANTSYNC)
1827 ti->flags |= T_SYNCMODE;
1828 else
1829 ti->flags &= ~T_SYNCMODE;
1830 wd33c93_setsync(sc, ti);
1831 }
1832 break;
1833 case SEND_IDENTIFY:
1834 if (sc->sc_state != SBIC_CONNECTED) {
1835 printf("%s at line %d: no nexus\n",
1836 device_xname(sc->sc_dev), __LINE__);
1837 }
1838 sc->sc_omsg[0] =
1839 MSG_IDENTIFY(acb->xs->xs_periph->periph_lun, 0);
1840 break;
1841 case SEND_TAG:
1842 if (sc->sc_state != SBIC_CONNECTED) {
1843 printf("%s at line %d: no nexus\n",
1844 device_xname(sc->sc_dev), __LINE__);
1845 }
1846 sc->sc_omsg[0] = acb->tag_type;
1847 sc->sc_omsg[1] = acb->tag_id;
1848 sc->sc_omsglen = 2;
1849 break;
1850 case SEND_DEV_RESET:
1851 sc->sc_omsg[0] = MSG_BUS_DEV_RESET;
1852 ti = &sc->sc_tinfo[sc->target];
1853 ti->flags &= ~T_SYNCMODE;
1854 wd33c93_update_xfer_mode(sc, sc->target);
1855 if ((ti->flags & T_NOSYNC) == 0)
1856 /* We can re-start sync negotiation */
1857 ti->flags |= T_NEGOTIATE;
1858 break;
1859 case SEND_PARITY_ERROR:
1860 sc->sc_omsg[0] = MSG_PARITY_ERROR;
1861 break;
1862 case SEND_ABORT:
1863 sc->sc_flags |= SBICF_ABORTING;
1864 sc->sc_omsg[0] = MSG_ABORT;
1865 break;
1866 case SEND_INIT_DET_ERR:
1867 sc->sc_omsg[0] = MSG_INITIATOR_DET_ERR;
1868 break;
1869 case SEND_REJECT:
1870 sc->sc_omsg[0] = MSG_MESSAGE_REJECT;
1871 break;
1872 default:
1873 /* Wasn't expecting MSGOUT Phase */
1874 sc->sc_omsg[0] = MSG_NOOP;
1875 break;
1876 }
1877 }
1878
1879 wd33c93_xfout(sc, sc->sc_omsglen, sc->sc_omsg);
1880 }
1881
1882
1883 /*
1884 * wd33c93_nextstate()
1885 * return:
1886 * SBIC_STATE_DONE == done
1887 * SBIC_STATE_RUNNING == working
1888 * SBIC_STATE_DISCONNECT == disconnected
1889 * SBIC_STATE_ERROR == error
1890 */
1891 int
wd33c93_nextstate(struct wd33c93_softc * sc,struct wd33c93_acb * acb,u_char csr,u_char asr)1892 wd33c93_nextstate(struct wd33c93_softc *sc, struct wd33c93_acb *acb, u_char csr, u_char asr)
1893 {
1894 SBIC_DEBUG(PHASE, ("next[a=%02x,c=%02x]: ",asr,csr));
1895
1896 switch (csr) {
1897
1898 case SBIC_CSR_XFERRED | CMD_PHASE:
1899 case SBIC_CSR_MIS | CMD_PHASE:
1900 case SBIC_CSR_MIS_1 | CMD_PHASE:
1901 case SBIC_CSR_MIS_2 | CMD_PHASE:
1902
1903 if (wd33c93_xfout(sc, acb->clen, &acb->cmd))
1904 goto abort;
1905 break;
1906
1907 case SBIC_CSR_XFERRED | STATUS_PHASE:
1908 case SBIC_CSR_MIS | STATUS_PHASE:
1909 case SBIC_CSR_MIS_1 | STATUS_PHASE:
1910 case SBIC_CSR_MIS_2 | STATUS_PHASE:
1911
1912 SET_SBIC_control(sc, SBIC_CTL_EDI | SBIC_CTL_IDI);
1913
1914 /*
1915 * this should be the normal i/o completion case.
1916 * get the status & cmd complete msg then let the
1917 * device driver look at what happened.
1918 */
1919 wd33c93_xferdone(sc);
1920
1921 wd33c93_dma_stop(sc);
1922
1923 /* Fixup byte count to be passed to higher layer */
1924 acb->dleft = (acb->flags & ACB_COMPLETE) ? 0 :
1925 sc->sc_dleft;
1926
1927 /*
1928 * Indicate to the upper layers that the command is done
1929 */
1930 wd33c93_scsidone(sc, acb, sc->sc_status);
1931
1932 return SBIC_STATE_DONE;
1933
1934
1935 case SBIC_CSR_XFERRED | DATA_IN_PHASE:
1936 case SBIC_CSR_MIS | DATA_IN_PHASE:
1937 case SBIC_CSR_MIS_1 | DATA_IN_PHASE:
1938 case SBIC_CSR_MIS_2 | DATA_IN_PHASE:
1939 case SBIC_CSR_XFERRED | DATA_OUT_PHASE:
1940 case SBIC_CSR_MIS | DATA_OUT_PHASE:
1941 case SBIC_CSR_MIS_1 | DATA_OUT_PHASE:
1942 case SBIC_CSR_MIS_2 | DATA_OUT_PHASE:
1943 /*
1944 * Verify that we expected to transfer data...
1945 */
1946 if (acb->dleft <= 0) {
1947 printf("next: DATA phase with xfer count == %zd, asr:0x%02x csr:0x%02x\n",
1948 acb->dleft, asr, csr);
1949 goto abort;
1950 }
1951
1952 /*
1953 * Should we transfer using PIO or DMA ?
1954 */
1955 if (acb->xs->xs_control & XS_CTL_POLL ||
1956 sc->sc_flags & SBICF_NODMA) {
1957 /* Perform transfer using PIO */
1958 int resid;
1959
1960 SBIC_DEBUG(DMA, ("PIO xfer: %d(%p:%zx)\n", sc->target,
1961 sc->sc_daddr, sc->sc_dleft));
1962
1963 if (SBIC_PHASE(csr) == DATA_IN_PHASE)
1964 /* data in */
1965 resid = wd33c93_xfin(sc, sc->sc_dleft,
1966 sc->sc_daddr);
1967 else /* data out */
1968 resid = wd33c93_xfout(sc, sc->sc_dleft,
1969 sc->sc_daddr);
1970
1971 sc->sc_daddr = (char *)sc->sc_daddr +
1972 (acb->dleft - resid);
1973 sc->sc_dleft = resid;
1974 } else {
1975 int datain = SBIC_PHASE(csr) == DATA_IN_PHASE;
1976
1977 /* Perform transfer using DMA */
1978 wd33c93_dma_setup(sc, datain);
1979
1980 SET_SBIC_control(sc, SBIC_CTL_EDI | SBIC_CTL_IDI |
1981 sc->sc_dmamode);
1982
1983 SBIC_DEBUG(DMA, ("DMA xfer: %d(%p:%zx)\n", sc->target,
1984 sc->sc_daddr, sc->sc_dleft));
1985
1986 /* Setup byte count for transfer */
1987 SBIC_TC_PUT(sc, (unsigned)sc->sc_dleft);
1988
1989 /* Start the transfer */
1990 SET_SBIC_cmd(sc, SBIC_CMD_XFER_INFO);
1991
1992 /* Start the DMA chip going */
1993 sc->sc_tcnt = sc->sc_dmago(sc);
1994
1995 /* Indicate that we're in DMA mode */
1996 sc->sc_flags |= SBICF_INDMA;
1997 }
1998 break;
1999
2000 case SBIC_CSR_XFERRED | MESG_IN_PHASE:
2001 case SBIC_CSR_MIS | MESG_IN_PHASE:
2002 case SBIC_CSR_MIS_1 | MESG_IN_PHASE:
2003 case SBIC_CSR_MIS_2 | MESG_IN_PHASE:
2004
2005 wd33c93_dma_stop(sc);
2006
2007 /* Handle a single message in... */
2008 return wd33c93_msgin_phase(sc, 0);
2009
2010 case SBIC_CSR_MSGIN_W_ACK:
2011
2012 /*
2013 * We should never see this since it's handled in
2014 * 'wd33c93_msgin_phase()' but just for the sake of paranoia...
2015 */
2016 SET_SBIC_cmd(sc, SBIC_CMD_CLR_ACK);
2017
2018 printf("Acking unknown msgin CSR:%02x",csr);
2019 break;
2020
2021 case SBIC_CSR_XFERRED | MESG_OUT_PHASE:
2022 case SBIC_CSR_MIS | MESG_OUT_PHASE:
2023 case SBIC_CSR_MIS_1 | MESG_OUT_PHASE:
2024 case SBIC_CSR_MIS_2 | MESG_OUT_PHASE:
2025
2026 /*
2027 * Message out phase. ATN signal has been asserted
2028 */
2029 wd33c93_dma_stop(sc);
2030 wd33c93_msgout(sc);
2031 return SBIC_STATE_RUNNING;
2032
2033 case SBIC_CSR_DISC:
2034 case SBIC_CSR_DISC_1:
2035 SBIC_DEBUG(RSEL, ("wd33c93next target %d disconnected\n",
2036 sc->target));
2037 wd33c93_dma_stop(sc);
2038
2039 sc->sc_nexus = NULL;
2040 sc->sc_state = SBIC_IDLE;
2041 sc->sc_flags = 0;
2042
2043 ++sc->sc_tinfo[sc->target].dconns;
2044 ++sc->sc_disc;
2045
2046 if (acb->xs->xs_control & XS_CTL_POLL || wd33c93_nodisc)
2047 return SBIC_STATE_DISCONNECT;
2048
2049 /* Try to schedule another target */
2050 wd33c93_sched(sc);
2051
2052 return SBIC_STATE_DISCONNECT;
2053
2054 case SBIC_CSR_RSLT_NI:
2055 case SBIC_CSR_RSLT_IFY:
2056 {
2057 /*
2058 * A reselection.
2059 * Note that since we don't enable Advanced Features (assuming
2060 * the WD chip is at least the 'A' revision), we're only ever
2061 * likely to see the 'SBIC_CSR_RSLT_NI' status. But for the
2062 * hell of it, we'll handle it anyway, for all the extra code
2063 * it needs...
2064 */
2065 u_char newtarget, newlun;
2066
2067 if (sc->sc_flags & SBICF_INDMA) {
2068 printf("**** RESELECT WHILE DMA ACTIVE!!! ***\n");
2069 wd33c93_dma_stop(sc);
2070 }
2071
2072 sc->sc_state = SBIC_RESELECTED;
2073 GET_SBIC_rselid(sc, newtarget);
2074
2075 /* check SBIC_RID_SIV? */
2076 newtarget &= SBIC_RID_MASK;
2077
2078 if (csr == SBIC_CSR_RSLT_IFY) {
2079 /* Read Identify msg to avoid lockup */
2080 GET_SBIC_data(sc, newlun);
2081 WAIT_CIP(sc);
2082 newlun &= SBIC_TLUN_MASK;
2083 sc->sc_msgify = MSG_IDENTIFY(newlun, 0);
2084 } else {
2085 /*
2086 * Need to read Identify message the hard way, assuming
2087 * the target even sends us one...
2088 */
2089 for (newlun = 255; newlun; --newlun) {
2090 GET_SBIC_asr(sc, asr);
2091 if (asr & SBIC_ASR_INT)
2092 break;
2093 DELAY(10);
2094 }
2095
2096 /* If we didn't get an interrupt, something's up */
2097 if ((asr & SBIC_ASR_INT) == 0) {
2098 printf("%s: Reselect without identify? asr %x\n",
2099 device_xname(sc->sc_dev), asr);
2100 newlun = 0; /* XXXX */
2101 } else {
2102 /*
2103 * We got an interrupt, verify that it's a
2104 * change to message in phase, and if so
2105 * read the message.
2106 */
2107 GET_SBIC_csr(sc,csr);
2108
2109 if (csr == (SBIC_CSR_MIS | MESG_IN_PHASE) ||
2110 csr == (SBIC_CSR_MIS_1 | MESG_IN_PHASE) ||
2111 csr == (SBIC_CSR_MIS_2 | MESG_IN_PHASE)) {
2112 /*
2113 * Yup, gone to message in.
2114 * Fetch the target LUN
2115 */
2116 sc->sc_msgify = 0;
2117 wd33c93_msgin_phase(sc, 1);
2118 newlun = sc->sc_msgify & SBIC_TLUN_MASK;
2119 } else {
2120 /*
2121 * Whoops! Target didn't go to msg_in
2122 * phase!!
2123 */
2124 printf("RSLT_NI - not MESG_IN_PHASE %x\n", csr);
2125 newlun = 0; /* XXXSCW */
2126 }
2127 }
2128 }
2129
2130 /* Ok, we have the identity of the reselecting target. */
2131 SBIC_DEBUG(RSEL, ("wd33c93next: reselect from targ %d lun %d",
2132 newtarget, newlun));
2133 wd33c93_reselect(sc, newtarget, newlun, 0, 0);
2134 sc->sc_disc--;
2135
2136 if (csr == SBIC_CSR_RSLT_IFY)
2137 SET_SBIC_cmd(sc, SBIC_CMD_CLR_ACK);
2138 break;
2139 }
2140
2141 default:
2142 abort:
2143 /* Something unexpected happened -- deal with it. */
2144 printf("next: aborting asr 0x%02x csr 0x%02x\n", asr, csr);
2145
2146 #ifdef DDB
2147 Debugger();
2148 #endif
2149
2150 SET_SBIC_control(sc, SBIC_CTL_EDI | SBIC_CTL_IDI);
2151 if (acb->xs)
2152 wd33c93_error(sc, acb);
2153 wd33c93_abort(sc, acb, "next");
2154
2155 if (sc->sc_flags & SBICF_INDMA) {
2156 wd33c93_dma_stop(sc);
2157 wd33c93_scsidone(sc, acb, STATUS_UNKNOWN);
2158 }
2159 return SBIC_STATE_ERROR;
2160 }
2161 return SBIC_STATE_RUNNING;
2162 }
2163
2164
2165 void
wd33c93_reselect(struct wd33c93_softc * sc,int target,int lun,int tag_type,int tag_id)2166 wd33c93_reselect(struct wd33c93_softc *sc, int target, int lun, int tag_type, int tag_id)
2167 {
2168
2169 struct wd33c93_tinfo *ti;
2170 struct wd33c93_linfo *li;
2171 struct wd33c93_acb *acb;
2172
2173 if (sc->sc_nexus) {
2174 /*
2175 * Whoops! We've been reselected with a
2176 * command in progress!
2177 * The best we can do is to put the current
2178 * command back on the ready list and hope
2179 * for the best.
2180 */
2181 SBIC_DEBUG(RSEL, ("%s: reselect with active command\n",
2182 device_xname(sc->sc_dev)));
2183 ti = &sc->sc_tinfo[sc->target];
2184 li = TINFO_LUN(ti, sc->lun);
2185 li->state = L_STATE_IDLE;
2186
2187 wd33c93_dequeue(sc, sc->sc_nexus);
2188 TAILQ_INSERT_HEAD(&sc->ready_list, sc->sc_nexus, chain);
2189 sc->sc_nexus->flags |= ACB_READY;
2190
2191 sc->sc_nexus = NULL;
2192 }
2193
2194 /* Setup state for new nexus */
2195 acb = NULL;
2196 sc->sc_flags = SBICF_SELECTED;
2197 sc->sc_msgpriq = sc->sc_msgout = sc->sc_msgoutq = 0;
2198
2199 ti = &sc->sc_tinfo[target];
2200 li = TINFO_LUN(ti, lun);
2201
2202 if (li != NULL) {
2203 if (li->untagged != NULL && li->state)
2204 acb = li->untagged;
2205 else if (tag_type != MSG_SIMPLE_Q_TAG) {
2206 /* Wait for tag to come by during MESG_IN Phase */
2207 sc->target = target; /* setup I_T_L nexus */
2208 sc->lun = lun;
2209 sc->sc_state = SBIC_IDENTIFIED;
2210 return;
2211 } else if (tag_type)
2212 acb = li->queued[tag_id];
2213 }
2214
2215 if (acb == NULL) {
2216 printf("%s: reselect from target %d lun %d tag %x:%x "
2217 "with no nexus; sending ABORT\n",
2218 device_xname(sc->sc_dev), target, lun, tag_type, tag_id);
2219 goto abort;
2220 }
2221
2222 sc->target = target;
2223 sc->lun = lun;
2224 sc->sc_nexus = acb;
2225 sc->sc_state = SBIC_CONNECTED;
2226
2227 if (!wd33c93_dmaok(sc, acb->xs))
2228 sc->sc_flags |= SBICF_NODMA;
2229
2230 /* Do an implicit RESTORE POINTERS. */
2231 sc->sc_daddr = acb->daddr;
2232 sc->sc_dleft = acb->dleft;
2233
2234 /* Set sync modes for new target */
2235 wd33c93_setsync(sc, ti);
2236
2237 if (acb->flags & ACB_RESET)
2238 wd33c93_sched_msgout(sc, SEND_DEV_RESET);
2239 else if (acb->flags & ACB_ABORT)
2240 wd33c93_sched_msgout(sc, SEND_ABORT);
2241 return;
2242
2243 abort:
2244 wd33c93_sched_msgout(sc, SEND_ABORT);
2245 return;
2246
2247 }
2248
2249 void
wd33c93_update_xfer_mode(struct wd33c93_softc * sc,int target)2250 wd33c93_update_xfer_mode(struct wd33c93_softc *sc, int target)
2251 {
2252 struct wd33c93_tinfo *ti = &sc->sc_tinfo[target];
2253 struct scsipi_xfer_mode xm;
2254
2255 xm.xm_target = target;
2256 xm.xm_mode = 0;
2257 xm.xm_period = 0;
2258 xm.xm_offset = 0;
2259
2260 if (ti->flags & T_SYNCMODE) {
2261 xm.xm_mode |= PERIPH_CAP_SYNC;
2262 xm.xm_period = ti->period;
2263 xm.xm_offset = ti->offset;
2264 }
2265
2266 if ((ti->flags & (T_NODISC|T_TAG)) == T_TAG)
2267 xm.xm_mode |= PERIPH_CAP_TQING;
2268
2269 SBIC_DEBUG(SYNC, ("wd33c93_update_xfer_mode: reporting target %d %s\n",
2270 xm.xm_target,
2271 (xm.xm_mode & PERIPH_CAP_SYNC) ? "sync" : "async"));
2272
2273 scsipi_async_event(&sc->sc_channel, ASYNC_EVENT_XFER_MODE, &xm);
2274 }
2275
2276 void
wd33c93_timeout(void * arg)2277 wd33c93_timeout(void *arg)
2278 {
2279 struct wd33c93_acb *acb = arg;
2280 struct scsipi_xfer *xs = acb->xs;
2281 struct scsipi_periph *periph = xs->xs_periph;
2282 struct wd33c93_softc *sc =
2283 device_private(periph->periph_channel->chan_adapter->adapt_dev);
2284 int s, asr;
2285
2286 s = splbio();
2287
2288 GET_SBIC_asr(sc, asr);
2289
2290 scsipi_printaddr(periph);
2291 printf("%s: timed out; asr=0x%02x [acb %p (flags 0x%x, dleft %zx)], "
2292 "<state %d, nexus %p, resid %lx, msg(q %x,o %x)>",
2293 device_xname(sc->sc_dev), asr, acb, acb->flags, acb->dleft,
2294 sc->sc_state, sc->sc_nexus, (long)sc->sc_dleft,
2295 sc->sc_msgpriq, sc->sc_msgout);
2296
2297 if (asr & SBIC_ASR_INT) {
2298 /* We need to service a missed IRQ */
2299 wd33c93_intr(sc);
2300 } else {
2301 (void) wd33c93_abort(sc, sc->sc_nexus, "timeout");
2302 }
2303 splx(s);
2304 }
2305
2306
2307 void
wd33c93_watchdog(void * arg)2308 wd33c93_watchdog(void *arg)
2309 {
2310 struct wd33c93_softc *sc = arg;
2311 struct wd33c93_tinfo *ti;
2312 struct wd33c93_linfo *li;
2313 int t, s, l;
2314 /* scrub LUN's that have not been used in the last 10min. */
2315 time_t old = time_second - (10 * 60);
2316
2317 for (t = 0; t < SBIC_NTARG; t++) {
2318 ti = &sc->sc_tinfo[t];
2319 for (l = 0; l < SBIC_NLUN; l++) {
2320 s = splbio();
2321 li = TINFO_LUN(ti, l);
2322 if (li && li->last_used < old &&
2323 li->untagged == NULL && li->used == 0) {
2324 ti->lun[li->lun] = NULL;
2325 free(li, M_DEVBUF);
2326 }
2327 splx(s);
2328 }
2329 }
2330 callout_reset(&sc->sc_watchdog, 60 * hz, wd33c93_watchdog, sc);
2331 }
2332
2333
2334 #ifdef DEBUG
2335 void
wd33c93_hexdump(u_char * buf,int len)2336 wd33c93_hexdump(u_char *buf, int len)
2337 {
2338 printf("{%d}:", len);
2339 while (len--)
2340 printf(" %02x", *buf++);
2341 printf("\n");
2342 }
2343
2344
2345 void
wd33c93_print_csr(u_char csr)2346 wd33c93_print_csr(u_char csr)
2347 {
2348 switch (SCSI_PHASE(csr)) {
2349 case CMD_PHASE:
2350 printf("CMD_PHASE\n");
2351 break;
2352
2353 case STATUS_PHASE:
2354 printf("STATUS_PHASE\n");
2355 break;
2356
2357 case DATA_IN_PHASE:
2358 printf("DATAIN_PHASE\n");
2359 break;
2360
2361 case DATA_OUT_PHASE:
2362 printf("DATAOUT_PHASE\n");
2363 break;
2364
2365 case MESG_IN_PHASE:
2366 printf("MESG_IN_PHASE\n");
2367 break;
2368
2369 case MESG_OUT_PHASE:
2370 printf("MESG_OUT_PHASE\n");
2371 break;
2372
2373 default:
2374 switch (csr) {
2375 case SBIC_CSR_DISC_1:
2376 printf("DISC_1\n");
2377 break;
2378
2379 case SBIC_CSR_RSLT_NI:
2380 printf("RESELECT_NO_IFY\n");
2381 break;
2382
2383 case SBIC_CSR_RSLT_IFY:
2384 printf("RESELECT_IFY\n");
2385 break;
2386
2387 case SBIC_CSR_SLT:
2388 printf("SELECT\n");
2389 break;
2390
2391 case SBIC_CSR_SLT_ATN:
2392 printf("SELECT, ATN\n");
2393 break;
2394
2395 case SBIC_CSR_UNK_GROUP:
2396 printf("UNK_GROUP\n");
2397 break;
2398
2399 default:
2400 printf("UNKNOWN csr=%02x\n", csr);
2401 }
2402 }
2403 }
2404 #endif
2405