1 /* $NetBSD: uhareg.h,v 1.2 1996/09/01 00:54:41 mycroft Exp $ */ 2 3 /* 4 * Copyright (c) 1994, 1996 Charles M. Hannum. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Charles M. Hannum. 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Ported for use with the UltraStor 14f by Gary Close (gclose@wvnvms.wvnet.edu) 34 * Slight fixes to timeouts to run with the 34F 35 * Thanks to Julian Elischer for advice and help with this port. 36 * 37 * Originally written by Julian Elischer (julian@tfs.com) 38 * for TRW Financial Systems for use under the MACH(2.5) operating system. 39 * 40 * TRW Financial Systems, in accordance with their agreement with Carnegie 41 * Mellon University, makes this software available to CMU to distribute 42 * or use in any manner that they see fit as long as this message is kept with 43 * the software. For this reason TFS also grants any other persons or 44 * organisations permission to use or modify this software. 45 * 46 * TFS supplies this software to be publicly redistributed 47 * on the understanding that TFS is not responsible for the correct 48 * functioning of this software in any circumstances. 49 * 50 * commenced: Sun Sep 27 18:14:01 PDT 1992 51 * slight mod to make work with 34F as well: Wed Jun 2 18:05:48 WST 1993 52 */ 53 54 typedef u_long physaddr; 55 typedef u_long physlen; 56 57 /************************** board definitions *******************************/ 58 /* 59 * I/O Port Interface 60 */ 61 #define U14_LMASK 0x0000 /* local doorbell mask reg */ 62 #define U14_LINT 0x0001 /* local doorbell int/stat reg */ 63 #define U14_SMASK 0x0002 /* system doorbell mask reg */ 64 #define U14_SINT 0x0003 /* system doorbell int/stat reg */ 65 #define U14_ID 0x0004 /* product id reg (2 ports) */ 66 #define U14_CONFIG 0x0006 /* config reg (2 ports) */ 67 #define U14_OGMPTR 0x0008 /* outgoing mail ptr (4 ports) */ 68 #define U14_ICMPTR 0x000c /* incoming mail ptr (4 ports) */ 69 70 #define U24_CONFIG 0x0005 /* config reg (3 ports) */ 71 #define U24_LMASK 0x000c /* local doorbell mask reg */ 72 #define U24_LINT 0x000d /* local doorbell int/stat reg */ 73 #define U24_SMASK 0x000e /* system doorbell mask reg */ 74 #define U24_SINT 0x000f /* system doorbell int/stat reg */ 75 #define U24_OGMCMD 0x0016 /* outgoing commands */ 76 #define U24_OGMPTR 0x0017 /* outgoing mail ptr (4 ports) */ 77 #define U24_ICMCMD 0x001b /* incoming commands */ 78 #define U24_ICMPTR 0x001c /* incoming mail ptr (4 ports) */ 79 80 /* 81 * UHA_LMASK bits (read only) 82 */ 83 #define UHA_LDIE 0x80 /* local doorbell int enabled */ 84 #define UHA_SRSTE 0x40 /* soft reset enabled */ 85 #define UHA_ABORTEN 0x10 /* abort MSCP enabled */ 86 #define UHA_OGMINTEN 0x01 /* outgoing mail interrupt enabled */ 87 88 /* 89 * UHA_LINT bits (read only) 90 */ 91 #define U14_LDIP 0x80 /* local doorbell int pending */ 92 #define U24_LDIP 0x02 /* local doorbell int pending */ 93 94 /* 95 * UHA_LINT bits (write only) 96 */ 97 #define U14_OGMFULL 0x01 /* outgoing mailbox is full */ 98 #define U14_ABORT 0x10 /* abort MSCP */ 99 100 #define U24_OGMFULL 0x02 /* outgoing mailbox is full */ 101 102 #define UHA_SBRST 0x40 /* scsi bus reset */ 103 #define UHA_ADRST 0x80 /* adapter soft reset */ 104 #define UHA_ASRST 0xc0 /* adapter and scsi reset */ 105 106 /* 107 * UHA_SMASK bits (read/write) 108 */ 109 #define UHA_ENSINT 0x80 /* enable system doorbell interrupt */ 110 #define UHA_EN_ABORT_COMPLETE 0x10 /* enable abort MSCP complete int */ 111 #define UHA_ENICM 0x01 /* enable ICM interrupt */ 112 113 /* 114 * UHA_SINT bits (read) 115 */ 116 #define U14_SDIP 0x80 /* system doorbell int pending */ 117 #define U24_SDIP 0x02 /* system doorbell int pending */ 118 119 #define UHA_ABORT_SUCC 0x10 /* abort MSCP successful */ 120 #define UHA_ABORT_FAIL 0x18 /* abort MSCP failed */ 121 122 /* 123 * UHA_SINT bits (write) 124 */ 125 #define U14_ICM_ACK 0x01 /* acknowledge ICM and clear */ 126 #define U24_ICM_ACK 0x02 /* acknowledge ICM and clear */ 127 128 #define UHA_ABORT_ACK 0x18 /* acknowledge status and clear */ 129 130 /* 131 * U14_CONFIG bits (read only) 132 */ 133 #define U14_DMA_CH5 0x0000 /* DMA channel 5 */ 134 #define U14_DMA_CH6 0x4000 /* 6 */ 135 #define U14_DMA_CH7 0x8000 /* 7 */ 136 #define U14_DMA_MASK 0xc000 137 #define U14_IRQ15 0x0000 /* IRQ 15 */ 138 #define U14_IRQ14 0x1000 /* 14 */ 139 #define U14_IRQ11 0x2000 /* 11 */ 140 #define U14_IRQ10 0x3000 /* 10 */ 141 #define U14_IRQ_MASK 0x3000 142 #define U14_HOSTID_MASK 0x0007 143 144 /* 145 * U24_CONFIG bits (read only) 146 */ 147 #define U24_MAGIC1 0x08 148 #define U24_IRQ15 0x10 149 #define U24_IRQ14 0x20 150 #define U24_IRQ11 0x40 151 #define U24_IRQ10 0x80 152 #define U24_IRQ_MASK 0xf0 153 154 #define U24_MAGIC2 0x04 155 156 #define U24_HOSTID_MASK 0x07 157 158 /* 159 * EISA registers (offset from slot base) 160 */ 161 #define EISA_VENDOR 0x0c80 /* vendor ID (2 ports) */ 162 #define EISA_MODEL 0x0c82 /* model number (2 ports) */ 163 #define EISA_CONTROL 0x0c84 164 #define EISA_RESET 0x04 165 #define EISA_ERROR 0x02 166 #define EISA_ENABLE 0x01 167 168 /* 169 * host_stat error codes 170 */ 171 #define UHA_NO_ERR 0x00 /* No error supposedly */ 172 #define UHA_SBUS_ABORT_ERR 0x84 /* scsi bus abort error */ 173 #define UHA_SBUS_TIMEOUT 0x91 /* scsi bus selection timeout */ 174 #define UHA_SBUS_OVER_UNDER 0x92 /* scsi bus over/underrun */ 175 #define UHA_BAD_SCSI_CMD 0x96 /* illegal scsi command */ 176 #define UHA_AUTO_SENSE_ERR 0x9b /* auto request sense err */ 177 #define UHA_SBUS_RES_ERR 0xa3 /* scsi bus reset error */ 178 #define UHA_BAD_SG_LIST 0xff /* invalid scatter gath list */ 179 180 #define UHA_NSEG 33 /* number of dma segments supported */ 181 182 struct uha_dma_seg { 183 physaddr seg_addr; 184 physlen seg_len; 185 }; 186 187 #pragma pack(1) 188 struct uha_mscp { 189 u_char opcode:3; 190 #define UHA_HAC 0x01 /* host adapter command */ 191 #define UHA_TSP 0x02 /* target scsi pass through command */ 192 #define UHA_SDR 0x04 /* scsi device reset */ 193 u_char xdir:2; /* xfer direction */ 194 #define UHA_SDET 0x00 /* determined by scsi command */ 195 #define UHA_SDIN 0x01 /* scsi data in */ 196 #define UHA_SDOUT 0x02 /* scsi data out */ 197 #define UHA_NODATA 0x03 /* no data xfer */ 198 u_char dcn:1; /* disable disconnect for this command */ 199 u_char ca:1; /* cache control */ 200 u_char sgth:1; /* scatter gather flag */ 201 u_char target:3; 202 u_char chan:2; /* scsi channel (always 0 for 14f) */ 203 u_char lun:3; 204 physaddr data_addr; 205 physlen data_length; 206 physaddr link_addr; 207 u_char link_id; 208 u_char sg_num; /* number of scat gath segs */ 209 /*in s-g list if sg flag is */ 210 /*set. starts at 1, 8bytes per */ 211 u_char req_sense_length; 212 u_char scsi_cmd_length; 213 struct scsi_generic scsi_cmd; 214 u_char host_stat; 215 u_char target_stat; 216 physaddr sense_ptr; /* if 0 no auto sense */ 217 218 struct uha_dma_seg uha_dma[UHA_NSEG]; 219 struct scsi_sense_data mscp_sense; 220 /*-----------------end of hardware supported fields----------------*/ 221 TAILQ_ENTRY(uha_mscp) chain; 222 struct uha_mscp *nexthash; 223 long hashkey; 224 struct scsi_xfer *xs; /* the scsi_xfer for this cmd */ 225 int flags; 226 #define MSCP_ALLOC 0x01 227 #define MSCP_ABORT 0x02 228 int timeout; 229 }; 230 #pragma pack(4) 231 232