1 /* $NetBSD: tcic2var.h,v 1.7 2005/12/24 23:41:33 perry Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 Christoph Badura. All rights reserved. 5 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Marc Horowitz. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #ifndef _TCIC2VAR_H 34 #define _TCIC2VAR_H 35 36 #include <sys/device.h> 37 38 #include <dev/pcmcia/pcmciareg.h> 39 #include <dev/pcmcia/pcmciachip.h> 40 41 #include <dev/ic/tcic2reg.h> 42 43 struct proc; 44 45 struct tcic_event { 46 SIMPLEQ_ENTRY(tcic_event) pe_q; 47 int pe_type; 48 }; 49 50 /* pe_type */ 51 #define TCIC_EVENT_INSERTION 0 52 #define TCIC_EVENT_REMOVAL 1 53 54 55 struct tcic_handle { 56 struct tcic_softc *sc; 57 int sock; /* socket number */ 58 int flags; 59 int sstat; /* last value of R_SSTAT */ 60 int memalloc; 61 int memwins; 62 struct { 63 bus_addr_t addr; 64 bus_size_t size; 65 int size2; /* size as 2^n scaled by 4K */ 66 long offset; 67 int speed; /* in ns */ 68 int kind; 69 } mem[TCIC_MAX_MEM_WINS]; 70 int ioalloc; 71 struct { 72 bus_addr_t addr; 73 bus_size_t size; 74 int width; 75 int speed; /* in ns */ 76 } io[TCIC_IO_WINS]; 77 int ih_irq; 78 struct device *pcmcia; 79 80 int shutdown; 81 struct proc *event_thread; 82 SIMPLEQ_HEAD(, tcic_event) events; 83 }; 84 85 #define TCIC_FLAG_SOCKETP 0x0001 86 #define TCIC_FLAG_CARDP 0x0002 87 88 /* 89 * This is sort of arbitrary. It merely needs to be "enough". It can be 90 * overridden in the conf file, anyway. 91 */ 92 93 #define TCIC_MEM_PAGES 4 94 #define TCIC_MEMSIZE TCIC_MEM_PAGES*TCIC_MEM_PAGESIZE 95 96 #define TCIC_NSLOTS 2 97 98 struct tcic_softc { 99 struct device dev; 100 101 bus_space_tag_t memt; 102 bus_space_handle_t memh; 103 bus_space_tag_t iot; 104 bus_space_handle_t ioh; 105 106 int chipid; 107 int validirqs; 108 int pwrena; /* holds TCIC_PWR_ENA on'084 and successors */ 109 110 /* XXX isa_chipset_tag_t, pci_chipset_tag_t, etc. */ 111 void *intr_est; 112 113 pcmcia_chipset_tag_t pct; 114 115 /* this needs to be large enough to hold TCIC_MEM_PAGES bits */ 116 int subregionmask; 117 118 /* used by memory window mapping functions */ 119 bus_addr_t membase; 120 int memsize2; /* int(log2(memsize)) */ 121 122 /* 123 * used by io window mapping functions. These can actually overlap 124 * with another tcic, since the underlying extent mapper will deal 125 * with individual allocations. This is here to deal with the fact 126 * that different busses have different real widths (different pc 127 * hardware seems to use 10 or 12 bits for the I/O bus). 128 */ 129 bus_addr_t iobase; 130 bus_size_t iosize; 131 132 int irq; 133 void *ih; 134 135 struct tcic_handle handle[TCIC_NSLOTS]; 136 }; 137 138 int tcic_log2(u_int); 139 int tcic_ns2wscnt(int); 140 141 int tcic_check_reserved_bits(bus_space_tag_t, bus_space_handle_t); 142 int tcic_chipid(bus_space_tag_t, bus_space_handle_t); 143 int tcic_chipid_known(int); 144 const char *tcic_chipid_to_string(int); 145 int tcic_validirqs(int); 146 147 void tcic_attach(struct tcic_softc *); 148 void tcic_attach_sockets(struct tcic_softc *); 149 int tcic_intr(void *arg); 150 151 static inline int tcic_read_1(struct tcic_handle *, int); 152 static inline int tcic_read_2(struct tcic_handle *, int); 153 static inline int tcic_read_4(struct tcic_handle *, int); 154 static inline void tcic_write_1(struct tcic_handle *, int, int); 155 static inline void tcic_write_2(struct tcic_handle *, int, int); 156 static inline void tcic_write_4(struct tcic_handle *, int, int); 157 static inline int tcic_read_ind_2(struct tcic_handle *, int); 158 static inline void tcic_write_ind_2(struct tcic_handle *, int, int); 159 static inline void tcic_sel_sock(struct tcic_handle *); 160 static inline void tcic_wait_ready(struct tcic_handle *); 161 static inline int tcic_read_aux_1(bus_space_tag_t, bus_space_handle_t, int, int); 162 static inline int tcic_read_aux_2(bus_space_tag_t, bus_space_handle_t, int); 163 static inline void tcic_write_aux_1(bus_space_tag_t, bus_space_handle_t, int, int, int); 164 static inline void tcic_write_aux_2(bus_space_tag_t, bus_space_handle_t, int, int); 165 166 int tcic_chip_mem_alloc(pcmcia_chipset_handle_t, bus_size_t, 167 struct pcmcia_mem_handle *); 168 void tcic_chip_mem_free(pcmcia_chipset_handle_t, 169 struct pcmcia_mem_handle *); 170 int tcic_chip_mem_map(pcmcia_chipset_handle_t, int, bus_addr_t, 171 bus_size_t, struct pcmcia_mem_handle *, bus_size_t *, int *); 172 void tcic_chip_mem_unmap(pcmcia_chipset_handle_t, int); 173 174 int tcic_chip_io_alloc(pcmcia_chipset_handle_t, bus_addr_t, 175 bus_size_t, bus_size_t, struct pcmcia_io_handle *); 176 void tcic_chip_io_free(pcmcia_chipset_handle_t, 177 struct pcmcia_io_handle *); 178 int tcic_chip_io_map(pcmcia_chipset_handle_t, int, bus_addr_t, 179 bus_size_t, struct pcmcia_io_handle *, int *); 180 void tcic_chip_io_unmap(pcmcia_chipset_handle_t, int); 181 182 void tcic_chip_socket_enable(pcmcia_chipset_handle_t); 183 void tcic_chip_socket_disable(pcmcia_chipset_handle_t); 184 void tcic_chip_socket_settype(pcmcia_chipset_handle_t, int); 185 186 static inline int tcic_read_1(struct tcic_handle *, int); 187 static inline int 188 tcic_read_1(h, reg) 189 struct tcic_handle *h; 190 int reg; 191 { 192 return (bus_space_read_1(h->sc->iot, h->sc->ioh, reg)); 193 } 194 195 static inline int tcic_read_2(struct tcic_handle *, int); 196 static inline int 197 tcic_read_2(h, reg) 198 struct tcic_handle *h; 199 int reg; 200 { 201 return (bus_space_read_2(h->sc->iot, h->sc->ioh, reg)); 202 } 203 204 static inline int tcic_read_4(struct tcic_handle *, int); 205 static inline int 206 tcic_read_4(h, reg) 207 struct tcic_handle *h; 208 int reg; 209 { 210 int val; 211 val = bus_space_read_2(h->sc->iot, h->sc->ioh, reg); 212 val |= bus_space_read_2(h->sc->iot, h->sc->ioh, reg+2) << 16; 213 return val; 214 } 215 216 static inline void tcic_write_1(struct tcic_handle *, int, int); 217 static inline void 218 tcic_write_1(h, reg, data) 219 struct tcic_handle *h; 220 int reg; 221 int data; 222 { 223 bus_space_write_1(h->sc->iot, h->sc->ioh, reg, (data)); 224 } 225 226 static inline void tcic_write_2(struct tcic_handle *, int, int); 227 static inline void 228 tcic_write_2(h, reg, data) 229 struct tcic_handle *h; 230 int reg; 231 int data; 232 { 233 bus_space_write_2(h->sc->iot, h->sc->ioh, reg, (data)); 234 } 235 236 static inline void tcic_write_4(struct tcic_handle *, int, int); 237 static inline void 238 tcic_write_4(h, reg, data) 239 struct tcic_handle *h; 240 int reg; 241 int data; 242 { 243 bus_space_write_2(h->sc->iot, h->sc->ioh, reg, (data)); 244 bus_space_write_2(h->sc->iot, h->sc->ioh, reg+2, (data)>>16); 245 } 246 247 static inline int tcic_read_ind_2(struct tcic_handle *, int); 248 static inline int 249 tcic_read_ind_2(h, reg) 250 struct tcic_handle *h; 251 int reg; 252 { 253 int r_addr, val; 254 r_addr = tcic_read_4(h, TCIC_R_ADDR); 255 tcic_write_4(h, TCIC_R_ADDR, reg|TCIC_ADDR_INDREG); 256 val = bus_space_read_2(h->sc->iot, h->sc->ioh, TCIC_R_DATA); 257 tcic_write_4(h, TCIC_R_ADDR, r_addr); 258 return val; 259 } 260 261 static inline void tcic_write_ind_2(struct tcic_handle *, int, int); 262 static inline void 263 tcic_write_ind_2(h, reg, data) 264 struct tcic_handle *h; 265 int reg; 266 int data; 267 { 268 int r_addr; 269 r_addr = tcic_read_4(h, TCIC_R_ADDR); 270 tcic_write_4(h, TCIC_R_ADDR, reg|TCIC_ADDR_INDREG); 271 bus_space_write_2(h->sc->iot, h->sc->ioh, TCIC_R_DATA, (data)); 272 tcic_write_4(h, TCIC_R_ADDR, r_addr); 273 } 274 275 static inline void tcic_sel_sock(struct tcic_handle *); 276 static inline void 277 tcic_sel_sock(h) 278 struct tcic_handle *h; 279 { 280 int r_addr; 281 r_addr = tcic_read_2(h, TCIC_R_ADDR2); 282 tcic_write_2(h, TCIC_R_ADDR2, 283 (h->sock<<TCIC_ADDR2_SS_SHFT)|(r_addr & ~TCIC_ADDR2_SS_MASK)); 284 } 285 286 static inline void tcic_wait_ready(struct tcic_handle *); 287 static inline void 288 tcic_wait_ready(h) 289 struct tcic_handle *h; 290 { 291 int i; 292 293 /* XXX appropriate socket must have been selected already. */ 294 for (i = 0; i < 10000; i++) { 295 if (tcic_read_1(h, TCIC_R_SSTAT) & TCIC_SSTAT_RDY) 296 return; 297 delay(500); 298 } 299 300 #ifdef DIAGNOSTIC 301 printf("tcic_wait_ready ready never happened\n"); 302 #endif 303 } 304 305 static inline int tcic_read_aux_1(bus_space_tag_t, bus_space_handle_t, int, int); 306 static inline int 307 tcic_read_aux_1(iot, ioh, auxreg, reg) 308 bus_space_tag_t iot; 309 bus_space_handle_t ioh; 310 int auxreg; 311 { 312 int mode, val; 313 mode = bus_space_read_1(iot, ioh, TCIC_R_MODE); 314 bus_space_write_1(iot, ioh, TCIC_R_MODE, (mode & ~TCIC_AR_MASK)|auxreg); 315 val = bus_space_read_1(iot, ioh, reg); 316 return val; 317 } 318 319 static inline int tcic_read_aux_2(bus_space_tag_t, bus_space_handle_t, int); 320 static inline int 321 tcic_read_aux_2(iot, ioh, auxreg) 322 bus_space_tag_t iot; 323 bus_space_handle_t ioh; 324 int auxreg; 325 { 326 int mode, val; 327 mode = bus_space_read_1(iot, ioh, TCIC_R_MODE); 328 bus_space_write_1(iot, ioh, TCIC_R_MODE, (mode & ~TCIC_AR_MASK)|auxreg); 329 val = bus_space_read_2(iot, ioh, TCIC_R_AUX); 330 return val; 331 } 332 333 static inline void tcic_write_aux_1(bus_space_tag_t, bus_space_handle_t, int, int, int); 334 static inline void 335 tcic_write_aux_1(iot, ioh, auxreg, reg, val) 336 bus_space_tag_t iot; 337 bus_space_handle_t ioh; 338 int auxreg, reg, val; 339 { 340 int mode; 341 mode = bus_space_read_1(iot, ioh, TCIC_R_MODE); 342 bus_space_write_1(iot, ioh, TCIC_R_MODE, (mode & ~TCIC_AR_MASK)|auxreg); 343 bus_space_write_1(iot, ioh, reg, val); 344 } 345 346 static inline void tcic_write_aux_2(bus_space_tag_t, bus_space_handle_t, int, int); 347 static inline void 348 tcic_write_aux_2(iot, ioh, auxreg, val) 349 bus_space_tag_t iot; 350 bus_space_handle_t ioh; 351 int auxreg, val; 352 { 353 int mode; 354 mode = bus_space_read_1(iot, ioh, TCIC_R_MODE); 355 bus_space_write_1(iot, ioh, TCIC_R_MODE, (mode & ~TCIC_AR_MASK)|auxreg); 356 bus_space_write_2(iot, ioh, TCIC_R_AUX, val); 357 } 358 359 #endif /* _TCIC2VAR_H */ 360