1 /* $NetBSD: tcic2.c,v 1.35 2010/04/19 18:24:26 dyoung Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 Christoph Badura. All rights reserved. 5 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Marc Horowitz. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: tcic2.c,v 1.35 2010/04/19 18:24:26 dyoung Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/device.h> 39 #include <sys/extent.h> 40 #include <sys/malloc.h> 41 #include <sys/kthread.h> 42 43 #include <sys/bus.h> 44 #include <sys/intr.h> 45 46 #include <dev/pcmcia/pcmciareg.h> 47 #include <dev/pcmcia/pcmciavar.h> 48 49 #include <dev/ic/tcic2reg.h> 50 #include <dev/ic/tcic2var.h> 51 52 #include "locators.h" 53 54 #ifdef TCICDEBUG 55 int tcic_debug = 1; 56 #define DPRINTF(arg) if (tcic_debug) printf arg; 57 #else 58 #define DPRINTF(arg) 59 #endif 60 61 /* 62 * Individual drivers will allocate their own memory and io regions. Memory 63 * regions must be a multiple of 4k, aligned on a 4k boundary. 64 */ 65 66 #define TCIC_MEM_ALIGN TCIC_MEM_PAGESIZE 67 68 void tcic_attach_socket(struct tcic_handle *); 69 void tcic_init_socket(struct tcic_handle *); 70 71 int tcic_print(void *arg, const char *pnp); 72 int tcic_intr_socket(struct tcic_handle *); 73 74 void tcic_attach_card(struct tcic_handle *); 75 void tcic_detach_card(struct tcic_handle *, int); 76 void tcic_deactivate_card(struct tcic_handle *); 77 78 void tcic_chip_do_mem_map(struct tcic_handle *, int); 79 void tcic_chip_do_io_map(struct tcic_handle *, int); 80 81 void tcic_create_event_thread(void *); 82 void tcic_event_thread(void *); 83 84 void tcic_queue_event(struct tcic_handle *, int); 85 86 /* Map between irq numbers and internal representation */ 87 #if 1 88 int tcic_irqmap[] = 89 { 0, 0, 0, 3, 4, 5, 6, 7, 0, 0, 10, 1, 0, 0, 14, 0 }; 90 int tcic_valid_irqs = 0x4cf8; 91 #else 92 int tcic_irqmap[] = /* irqs 9 and 6 switched, some ISA cards */ 93 { 0, 0, 0, 3, 4, 5, 0, 7, 0, 6, 10, 1, 0, 0, 14, 0 }; 94 int tcic_valid_irqs = 0x4eb8; 95 #endif 96 97 int tcic_mem_speed = 250; /* memory access time in nanoseconds */ 98 int tcic_io_speed = 165; /* io access time in nanoseconds */ 99 100 /* 101 * Check various reserved and otherwise in their value restricted bits. 102 */ 103 int 104 tcic_check_reserved_bits(bus_space_tag_t iot, bus_space_handle_t ioh) 105 { 106 int val, auxreg; 107 108 DPRINTF(("tcic: chkrsvd 1\n")); 109 /* R_ADDR bit 30:28 have a restricted range. */ 110 val = (bus_space_read_2(iot, ioh, TCIC_R_ADDR2) & TCIC_SS_MASK) 111 >> TCIC_SS_SHIFT; 112 if (val > 1) 113 return 0; 114 115 DPRINTF(("tcic: chkrsvd 2\n")); 116 /* R_SCTRL bits 6,2,1 are reserved. */ 117 val = bus_space_read_1(iot, ioh, TCIC_R_SCTRL); 118 if (val & TCIC_SCTRL_RSVD) 119 return 0; 120 121 DPRINTF(("tcic: chkrsvd 3\n")); 122 /* R_ICSR bit 2 must be same as bit 3. */ 123 val = bus_space_read_1(iot, ioh, TCIC_R_ICSR); 124 if (((val >> 1) & 1) != ((val >> 2) & 1)) 125 return 0; 126 127 DPRINTF(("tcic: chkrsvd 4\n")); 128 /* R_IENA bits 7,2 are reserverd. */ 129 val = bus_space_read_1(iot, ioh, TCIC_R_IENA); 130 if (val & TCIC_IENA_RSVD) 131 return 0; 132 133 DPRINTF(("tcic: chkrsvd 5\n")); 134 /* Some aux registers have reserved bits. */ 135 /* Which are we looking at? */ 136 auxreg = bus_space_read_1(iot, ioh, TCIC_R_MODE) 137 & TCIC_AR_MASK; 138 val = bus_space_read_2(iot, ioh, TCIC_R_AUX); 139 DPRINTF(("tcic: auxreg 0x%02x val 0x%04x\n", auxreg, val)); 140 switch (auxreg) { 141 case TCIC_AR_SYSCFG: 142 if (INVALID_AR_SYSCFG(val)) 143 return 0; 144 break; 145 case TCIC_AR_ILOCK: 146 if (INVALID_AR_ILOCK(val)) 147 return 0; 148 break; 149 case TCIC_AR_TEST: 150 if (INVALID_AR_TEST(val)) 151 return 0; 152 break; 153 } 154 155 DPRINTF(("tcic: chkrsvd 6\n")); 156 /* XXX fails if pcmcia bios is enabled. */ 157 /* Various bits set or not depending if in RESET mode. */ 158 val = bus_space_read_1(iot, ioh, TCIC_R_SCTRL); 159 if (val & TCIC_SCTRL_RESET) { 160 DPRINTF(("tcic: chkrsvd 7\n")); 161 /* Address bits must be 0 */ 162 val = bus_space_read_2(iot, ioh, TCIC_R_ADDR); 163 if (val != 0) 164 return 0; 165 val = bus_space_read_2(iot, ioh, TCIC_R_ADDR2); 166 if (val != 0) 167 return 0; 168 DPRINTF(("tcic: chkrsvd 8\n")); 169 /* EDC bits must be 0 */ 170 val = bus_space_read_2(iot, ioh, TCIC_R_EDC); 171 if (val != 0) 172 return 0; 173 /* We're OK, so take it out of reset. XXX -chb */ 174 bus_space_write_1(iot, ioh, TCIC_R_SCTRL, 0); 175 } 176 else { /* not in RESET mode */ 177 int omode; 178 int val1, val2; 179 DPRINTF(("tcic: chkrsvd 9\n")); 180 /* Programming timers must have expired. */ 181 val = bus_space_read_1(iot, ioh, TCIC_R_SSTAT); 182 if ((val & (TCIC_SSTAT_6US|TCIC_SSTAT_10US|TCIC_SSTAT_PROGTIME)) 183 != (TCIC_SSTAT_6US|TCIC_SSTAT_10US|TCIC_SSTAT_PROGTIME)) 184 return 0; 185 DPRINTF(("tcic: chkrsvd 10\n")); 186 /* 187 * EDC bits should change on read from data space 188 * as long as either EDC or the data are nonzero. 189 */ 190 if ((bus_space_read_2(iot, ioh, TCIC_R_ADDR2) 191 & TCIC_ADDR2_INDREG) != 0) { 192 val1 = bus_space_read_2(iot, ioh, TCIC_R_EDC); 193 val2 = bus_space_read_2(iot, ioh, TCIC_R_DATA); 194 if (val1 | val2) { 195 val1 = bus_space_read_2(iot, ioh, TCIC_R_EDC); 196 if (val1 == val2) 197 return 0; 198 } 199 } 200 DPRINTF(("tcic: chkrsvd 11\n")); 201 /* XXX what does this check? -chb */ 202 omode = bus_space_read_1(iot, ioh, TCIC_R_MODE); 203 val1 = omode ^ TCIC_AR_MASK; 204 bus_space_write_1(iot, ioh, TCIC_R_MODE, val1); 205 val2 = bus_space_read_1(iot, ioh, TCIC_R_MODE); 206 bus_space_write_1(iot, ioh, TCIC_R_MODE, omode); 207 if ( val1 != val2) 208 return 0; 209 } 210 /* All tests passed */ 211 return 1; 212 } 213 214 /* 215 * Read chip ID from AR_ILOCK in test mode. 216 */ 217 int 218 tcic_chipid(bus_space_tag_t iot, bus_space_handle_t ioh) 219 { 220 unsigned id, otest; 221 222 otest = tcic_read_aux_2(iot, ioh, TCIC_AR_TEST); 223 tcic_write_aux_2(iot, ioh, TCIC_AR_TEST, TCIC_TEST_DIAG); 224 id = tcic_read_aux_2(iot, ioh, TCIC_AR_ILOCK); 225 tcic_write_aux_2(iot, ioh, TCIC_AR_TEST, otest); 226 id &= TCIC_ILOCKTEST_ID_MASK; 227 id >>= TCIC_ILOCKTEST_ID_SHFT; 228 229 /* clear up IRQs inside tcic. XXX -chb */ 230 while (bus_space_read_1(iot, ioh, TCIC_R_ICSR)) 231 bus_space_write_1(iot, ioh, TCIC_R_ICSR, TCIC_ICSR_JAM); 232 233 return id; 234 } 235 /* 236 * Indicate whether the driver can handle the chip. 237 */ 238 int 239 tcic_chipid_known(int id) 240 { 241 /* XXX only know how to handle DB86082 -chb */ 242 switch (id) { 243 case TCIC_CHIPID_DB86082_1: 244 case TCIC_CHIPID_DB86082A: 245 case TCIC_CHIPID_DB86082B_ES: 246 case TCIC_CHIPID_DB86082B: 247 case TCIC_CHIPID_DB86084_1: 248 case TCIC_CHIPID_DB86084A: 249 case TCIC_CHIPID_DB86184_1: 250 case TCIC_CHIPID_DB86072_1_ES: 251 case TCIC_CHIPID_DB86072_1: 252 return 1; 253 } 254 255 return 0; 256 } 257 258 const char * 259 tcic_chipid_to_string(int id) 260 { 261 switch (id) { 262 case TCIC_CHIPID_DB86082_1: 263 return ("Databook DB86082"); 264 case TCIC_CHIPID_DB86082A: 265 return ("Databook DB86082A"); 266 case TCIC_CHIPID_DB86082B_ES: 267 return ("Databook DB86082B-es"); 268 case TCIC_CHIPID_DB86082B: 269 return ("Databook DB86082B"); 270 case TCIC_CHIPID_DB86084_1: 271 return ("Databook DB86084"); 272 case TCIC_CHIPID_DB86084A: 273 return ("Databook DB86084A"); 274 case TCIC_CHIPID_DB86184_1: 275 return ("Databook DB86184"); 276 case TCIC_CHIPID_DB86072_1_ES: 277 return ("Databook DB86072-es"); 278 case TCIC_CHIPID_DB86072_1: 279 return ("Databook DB86072"); 280 } 281 282 return ("Unknown controller"); 283 } 284 /* 285 * Return bitmask of IRQs that the chip can handle. 286 * XXX should be table driven. 287 */ 288 int 289 tcic_validirqs(int chipid) 290 { 291 switch (chipid) { 292 case TCIC_CHIPID_DB86082_1: 293 case TCIC_CHIPID_DB86082A: 294 case TCIC_CHIPID_DB86082B_ES: 295 case TCIC_CHIPID_DB86082B: 296 case TCIC_CHIPID_DB86084_1: 297 case TCIC_CHIPID_DB86084A: 298 case TCIC_CHIPID_DB86184_1: 299 case TCIC_CHIPID_DB86072_1_ES: 300 case TCIC_CHIPID_DB86072_1: 301 return tcic_valid_irqs; 302 } 303 return 0; 304 } 305 306 void 307 tcic_attach(struct tcic_softc *sc) 308 { 309 int i, reg; 310 311 /* set more chipset dependent parameters in the softc. */ 312 switch (sc->chipid) { 313 case TCIC_CHIPID_DB86084_1: 314 case TCIC_CHIPID_DB86084A: 315 case TCIC_CHIPID_DB86184_1: 316 sc->pwrena = TCIC_PWR_ENA; 317 break; 318 default: 319 sc->pwrena = 0; 320 break; 321 } 322 323 /* set up global config registers */ 324 reg = TCIC_WAIT_SYNC | TCIC_WAIT_CCLK | TCIC_WAIT_RISING; 325 reg |= (tcic_ns2wscnt(250) & TCIC_WAIT_COUNT_MASK); 326 tcic_write_aux_1(sc->iot, sc->ioh, TCIC_AR_WCTL, TCIC_R_WCTL_WAIT, reg); 327 reg = TCIC_SYSCFG_MPSEL_RI | TCIC_SYSCFG_MCSFULL; 328 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, reg); 329 reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_ILOCK); 330 reg |= TCIC_ILOCK_HOLD_CCLK; 331 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_ILOCK, reg); 332 333 /* the TCIC has two sockets */ 334 /* XXX should i check for actual presence of sockets? -chb */ 335 for (i = 0; i < TCIC_NSLOTS; i++) { 336 sc->handle[i].sc = sc; 337 sc->handle[i].sock = i; 338 sc->handle[i].flags = TCIC_FLAG_SOCKETP; 339 sc->handle[i].memwins 340 = sc->chipid == TCIC_CHIPID_DB86082_1 ? 4 : 5; 341 } 342 343 /* establish the interrupt */ 344 reg = tcic_read_1(&sc->handle[0], TCIC_R_IENA); 345 tcic_write_1(&sc->handle[0], TCIC_R_IENA, 346 (reg & ~TCIC_IENA_CFG_MASK) | TCIC_IENA_CFG_HIGH); 347 reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG); 348 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, 349 (reg & ~TCIC_SYSCFG_IRQ_MASK) | tcic_irqmap[sc->irq]); 350 351 /* XXX block interrupts? */ 352 353 for (i = 0; i < TCIC_NSLOTS; i++) { 354 /* XXX make more clear what happens here -chb */ 355 tcic_sel_sock(&sc->handle[i]); 356 tcic_write_ind_2(&sc->handle[i], TCIC_IR_SCF1_N(i), 0); 357 tcic_write_ind_2(&sc->handle[i], TCIC_IR_SCF2_N(i), 358 (TCIC_SCF2_MCD|TCIC_SCF2_MWP|TCIC_SCF2_MRDY 359 #if 1 /* XXX explain byte routing issue */ 360 |TCIC_SCF2_MLBAT2|TCIC_SCF2_MLBAT1|TCIC_SCF2_IDBR)); 361 #else 362 |TCIC_SCF2_MLBAT2|TCIC_SCF2_MLBAT1)); 363 #endif 364 tcic_write_1(&sc->handle[i], TCIC_R_MODE, 0); 365 reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG); 366 reg &= ~TCIC_SYSCFG_AUTOBUSY; 367 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, reg); 368 SIMPLEQ_INIT(&sc->handle[i].events); 369 } 370 371 if ((sc->handle[0].flags & TCIC_FLAG_SOCKETP) || 372 (sc->handle[1].flags & TCIC_FLAG_SOCKETP)) { 373 printf("%s: %s has ", device_xname(&sc->dev), 374 tcic_chipid_to_string(sc->chipid)); 375 376 if ((sc->handle[0].flags & TCIC_FLAG_SOCKETP) && 377 (sc->handle[1].flags & TCIC_FLAG_SOCKETP)) 378 printf("sockets A and B\n"); 379 else if (sc->handle[0].flags & TCIC_FLAG_SOCKETP) 380 printf("socket A only\n"); 381 else 382 printf("socket B only\n"); 383 384 } 385 } 386 387 void 388 tcic_attach_sockets(struct tcic_softc *sc) 389 { 390 int i; 391 392 for (i = 0; i < TCIC_NSLOTS; i++) 393 if (sc->handle[i].flags & TCIC_FLAG_SOCKETP) 394 tcic_attach_socket(&sc->handle[i]); 395 } 396 397 void 398 tcic_attach_socket(struct tcic_handle *h) 399 { 400 struct pcmciabus_attach_args paa; 401 int locs[PCMCIABUSCF_NLOCS]; 402 403 /* initialize the rest of the handle */ 404 405 h->shutdown = 0; 406 h->memalloc = 0; 407 h->ioalloc = 0; 408 h->ih_irq = 0; 409 410 /* now, config one pcmcia device per socket */ 411 412 paa.paa_busname = "pcmcia"; 413 paa.pct = (pcmcia_chipset_tag_t) h->sc->pct; 414 paa.pch = (pcmcia_chipset_handle_t) h; 415 paa.iobase = h->sc->iobase; 416 paa.iosize = h->sc->iosize; 417 418 locs[PCMCIABUSCF_CONTROLLER] = 0; 419 locs[PCMCIABUSCF_SOCKET] = h->sock; 420 421 h->pcmcia = config_found_sm_loc(&h->sc->dev, "pcmciabus", locs, &paa, 422 tcic_print, config_stdsubmatch); 423 424 /* if there's actually a pcmcia device attached, initialize the slot */ 425 426 if (h->pcmcia) 427 tcic_init_socket(h); 428 } 429 430 void 431 tcic_create_event_thread(void *arg) 432 { 433 struct tcic_handle *h = arg; 434 const char *cs; 435 436 switch (h->sock) { 437 case 0: 438 cs = "0"; 439 break; 440 case 1: 441 cs = "1"; 442 break; 443 default: 444 panic("tcic_create_event_thread: unknown tcic socket"); 445 } 446 447 if (kthread_create(PRI_NONE, 0, NULL, tcic_event_thread, h, 448 &h->event_thread, "%s,%s", device_xname(&h->sc->dev), cs)) { 449 aprint_error_dev(&h->sc->dev, "unable to create event thread for sock 0x%02x\n", h->sock); 450 panic("tcic_create_event_thread"); 451 } 452 } 453 454 void 455 tcic_event_thread(void *arg) 456 { 457 struct tcic_handle *h = arg; 458 struct tcic_event *pe; 459 int s; 460 461 while (h->shutdown == 0) { 462 s = splhigh(); 463 if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) { 464 splx(s); 465 (void) tsleep(&h->events, PWAIT, "tcicev", 0); 466 continue; 467 } 468 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 469 splx(s); 470 471 switch (pe->pe_type) { 472 case TCIC_EVENT_INSERTION: 473 DPRINTF(("%s: insertion event\n", device_xname(&h->sc->dev))); 474 tcic_attach_card(h); 475 break; 476 477 case TCIC_EVENT_REMOVAL: 478 DPRINTF(("%s: removal event\n", device_xname(&h->sc->dev))); 479 tcic_detach_card(h, DETACH_FORCE); 480 break; 481 482 default: 483 panic("tcic_event_thread: unknown event %d", 484 pe->pe_type); 485 } 486 free(pe, M_TEMP); 487 } 488 489 h->event_thread = NULL; 490 491 /* In case parent is waiting for us to exit. */ 492 wakeup(h->sc); 493 494 kthread_exit(0); 495 } 496 497 498 void 499 tcic_init_socket(struct tcic_handle *h) 500 { 501 int reg; 502 503 /* select this socket's config registers */ 504 tcic_sel_sock(h); 505 506 /* set up the socket to interrupt on card detect */ 507 reg = tcic_read_ind_2(h, TCIC_IR_SCF2_N(h->sock)); 508 tcic_write_ind_2(h, TCIC_IR_SCF2_N(h->sock), reg & ~TCIC_SCF2_MCD); 509 510 /* enable CD irq in R_IENA */ 511 reg = tcic_read_2(h, TCIC_R_IENA); 512 tcic_write_2(h, TCIC_R_IENA, reg |= TCIC_IENA_CDCHG); 513 514 /* if there's a card there, then attach it. also save sstat */ 515 h->sstat = reg = tcic_read_1(h, TCIC_R_SSTAT) & TCIC_SSTAT_STAT_MASK; 516 if (reg & TCIC_SSTAT_CD) 517 tcic_attach_card(h); 518 } 519 520 int 521 tcic_print(void *arg, const char *pnp) 522 { 523 struct pcmciabus_attach_args *paa = arg; 524 struct tcic_handle *h = (struct tcic_handle *) paa->pch; 525 526 /* Only "pcmcia"s can attach to "tcic"s... easy. */ 527 if (pnp) 528 aprint_normal("pcmcia at %s", pnp); 529 530 aprint_normal(" socket %d", h->sock); 531 532 return (UNCONF); 533 } 534 535 int 536 tcic_intr(void *arg) 537 { 538 struct tcic_softc *sc = arg; 539 int i, ret = 0; 540 541 DPRINTF(("%s: intr\n", device_xname(&sc->dev))); 542 543 for (i = 0; i < TCIC_NSLOTS; i++) 544 if (sc->handle[i].flags & TCIC_FLAG_SOCKETP) 545 ret += tcic_intr_socket(&sc->handle[i]); 546 547 return (ret ? 1 : 0); 548 } 549 550 int 551 tcic_intr_socket(struct tcic_handle *h) 552 { 553 int icsr, rv; 554 555 rv = 0; 556 tcic_sel_sock(h); 557 icsr = tcic_read_1(h, TCIC_R_ICSR); 558 559 DPRINTF(("%s: %d icsr: 0x%02x \n", device_xname(&h->sc->dev), h->sock, icsr)); 560 561 /* XXX or should the next three be handled in tcic_intr? -chb */ 562 if (icsr & TCIC_ICSR_PROGTIME) { 563 DPRINTF(("%s: %02x PROGTIME\n", device_xname(&h->sc->dev), h->sock)); 564 rv = 1; 565 } 566 if (icsr & TCIC_ICSR_ILOCK) { 567 DPRINTF(("%s: %02x ILOCK\n", device_xname(&h->sc->dev), h->sock)); 568 rv = 1; 569 } 570 if (icsr & TCIC_ICSR_ERR) { 571 DPRINTF(("%s: %02x ERR\n", device_xname(&h->sc->dev), h->sock)); 572 rv = 1; 573 } 574 if (icsr & TCIC_ICSR_CDCHG) { 575 int sstat, delta; 576 577 /* compute what changed since last interrupt */ 578 sstat = tcic_read_aux_1(h->sc->iot, h->sc->ioh, 579 TCIC_AR_WCTL, TCIC_R_WCTL_XCSR) & TCIC_XCSR_STAT_MASK; 580 delta = h->sstat ^ sstat; 581 h->sstat = sstat; 582 583 if (delta) 584 rv = 1; 585 586 DPRINTF(("%s: %02x CDCHG %x\n", device_xname(&h->sc->dev), h->sock, 587 delta)); 588 589 /* 590 * XXX This should probably schedule something to happen 591 * after the interrupt handler completes 592 */ 593 594 if (delta & TCIC_SSTAT_CD) { 595 if (sstat & TCIC_SSTAT_CD) { 596 if (!(h->flags & TCIC_FLAG_CARDP)) { 597 DPRINTF(("%s: enqueing INSERTION event\n", 598 device_xname(&h->sc->dev))); 599 tcic_queue_event(h, TCIC_EVENT_INSERTION); 600 } 601 } else { 602 if (h->flags & TCIC_FLAG_CARDP) { 603 /* Deactivate the card now. */ 604 DPRINTF(("%s: deactivating card\n", 605 device_xname(&h->sc->dev))); 606 tcic_deactivate_card(h); 607 608 DPRINTF(("%s: enqueing REMOVAL event\n", 609 device_xname(&h->sc->dev))); 610 tcic_queue_event(h, TCIC_EVENT_REMOVAL); 611 } 612 } 613 } 614 if (delta & TCIC_SSTAT_RDY) { 615 DPRINTF(("%s: %02x READY\n", device_xname(&h->sc->dev), h->sock)); 616 /* shouldn't happen */ 617 } 618 if (delta & TCIC_SSTAT_LBAT1) { 619 DPRINTF(("%s: %02x LBAT1\n", device_xname(&h->sc->dev), h->sock)); 620 } 621 if (delta & TCIC_SSTAT_LBAT2) { 622 DPRINTF(("%s: %02x LBAT2\n", device_xname(&h->sc->dev), h->sock)); 623 } 624 if (delta & TCIC_SSTAT_WP) { 625 DPRINTF(("%s: %02x WP\n", device_xname(&h->sc->dev), h->sock)); 626 } 627 } 628 return rv; 629 } 630 631 void 632 tcic_queue_event(struct tcic_handle *h, int event) 633 { 634 struct tcic_event *pe; 635 int s; 636 637 pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT); 638 if (pe == NULL) 639 panic("tcic_queue_event: can't allocate event"); 640 641 pe->pe_type = event; 642 s = splhigh(); 643 SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q); 644 splx(s); 645 wakeup(&h->events); 646 } 647 void 648 tcic_attach_card(struct tcic_handle *h) 649 { 650 DPRINTF(("tcic_attach_card\n")); 651 652 if (h->flags & TCIC_FLAG_CARDP) 653 panic("tcic_attach_card: already attached"); 654 655 /* call the MI attach function */ 656 657 pcmcia_card_attach(h->pcmcia); 658 659 h->flags |= TCIC_FLAG_CARDP; 660 } 661 662 void 663 tcic_detach_card(struct tcic_handle *h, int flags) 664 /* flags: DETACH_* */ 665 { 666 DPRINTF(("tcic_detach_card\n")); 667 668 if (!(h->flags & TCIC_FLAG_CARDP)) 669 panic("tcic_detach_card: already detached"); 670 671 h->flags &= ~TCIC_FLAG_CARDP; 672 673 /* call the MI detach function */ 674 675 pcmcia_card_detach(h->pcmcia, flags); 676 677 } 678 679 void 680 tcic_deactivate_card(struct tcic_handle *h) 681 { 682 int val, reg; 683 684 if (!(h->flags & TCIC_FLAG_CARDP)) 685 panic("tcic_deactivate_card: already detached"); 686 687 /* call the MI deactivate function */ 688 pcmcia_card_deactivate(h->pcmcia); 689 690 tcic_sel_sock(h); 691 692 /* XXX disable card detect resume and configuration reset??? */ 693 694 /* power down the socket */ 695 tcic_write_1(h, TCIC_R_PWR, 0); 696 697 /* reset the card XXX ? -chb */ 698 699 /* turn off irq's for this socket */ 700 reg = TCIC_IR_SCF1_N(h->sock); 701 val = tcic_read_ind_2(h, reg); 702 tcic_write_ind_2(h, reg, (val & ~TCIC_SCF1_IRQ_MASK)|TCIC_SCF1_IRQOFF); 703 reg = TCIC_IR_SCF2_N(h->sock); 704 val = tcic_read_ind_2(h, reg); 705 tcic_write_ind_2(h, reg, 706 (val | (TCIC_SCF2_MLBAT1|TCIC_SCF2_MLBAT2|TCIC_SCF2_MRDY 707 |TCIC_SCF2_MWP|TCIC_SCF2_MCD))); 708 } 709 710 /* XXX the following routine may need to be rewritten. -chb */ 711 int 712 tcic_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, struct pcmcia_mem_handle *pcmhp) 713 { 714 struct tcic_handle *h = (struct tcic_handle *) pch; 715 bus_space_handle_t memh; 716 bus_addr_t addr; 717 bus_size_t sizepg; 718 int i, mask, mhandle, got = 0; 719 720 /* out of sc->memh, allocate as many pages as necessary */ 721 722 /* 723 * The TCIC can map memory only in sizes that are 724 * powers of two, aligned at the natural boundary for the size. 725 */ 726 i = tcic_log2((u_int)size); 727 if ((1<<i) < size) 728 i++; 729 sizepg = max(i, TCIC_MEM_SHIFT) - (TCIC_MEM_SHIFT-1); 730 731 DPRINTF(("tcic_chip_mem_alloc: size %ld sizepg %ld\n", (u_long)size, 732 (u_long)sizepg)); 733 734 /* can't allocate that much anyway */ 735 if (sizepg > TCIC_MEM_PAGES) /* XXX -chb */ 736 return 1; 737 738 mask = (1 << sizepg) - 1; 739 740 addr = 0; /* XXX gcc -Wuninitialized */ 741 mhandle = 0; /* XXX gcc -Wuninitialized */ 742 743 /* XXX i should be initialised to always lay on boundary. -chb */ 744 for (i = 0; i < (TCIC_MEM_PAGES + 1 - sizepg); i += sizepg) { 745 if ((h->sc->subregionmask & (mask << i)) == (mask << i)) { 746 if (bus_space_subregion(h->sc->memt, h->sc->memh, 747 i * TCIC_MEM_PAGESIZE, 748 sizepg * TCIC_MEM_PAGESIZE, &memh)) 749 return (1); 750 mhandle = mask << i; 751 addr = h->sc->membase + (i * TCIC_MEM_PAGESIZE); 752 h->sc->subregionmask &= ~(mhandle); 753 got = 1; 754 break; 755 } 756 } 757 758 if (got == 0) 759 return (1); 760 761 DPRINTF(("tcic_chip_mem_alloc bus addr 0x%lx+0x%lx\n", (u_long) addr, 762 (u_long) size)); 763 764 pcmhp->memt = h->sc->memt; 765 pcmhp->memh = memh; 766 pcmhp->addr = addr; 767 pcmhp->size = size; 768 pcmhp->mhandle = mhandle; 769 pcmhp->realsize = sizepg * TCIC_MEM_PAGESIZE; 770 771 return (0); 772 } 773 774 /* XXX the following routine may need to be rewritten. -chb */ 775 void 776 tcic_chip_mem_free(pcmcia_chipset_handle_t pch, struct pcmcia_mem_handle *pcmhp) 777 { 778 struct tcic_handle *h = (struct tcic_handle *) pch; 779 780 h->sc->subregionmask |= pcmhp->mhandle; 781 } 782 783 void 784 tcic_chip_do_mem_map(struct tcic_handle *h, int win) 785 { 786 int reg, hwwin, wscnt; 787 788 int kind = h->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 789 int mem8 = (h->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8; 790 DPRINTF(("tcic_chip_do_mem_map window %d: 0x%lx+0x%lx 0x%lx\n", 791 win, (u_long)h->mem[win].addr, (u_long)h->mem[win].size, 792 (u_long)h->mem[win].offset)); 793 /* 794 * the even windows are used for socket 0, 795 * the odd ones for socket 1. 796 */ 797 hwwin = (win << 1) + h->sock; 798 799 /* the WR_MEXT register is MBZ */ 800 tcic_write_ind_2(h, TCIC_WR_MEXT_N(hwwin), 0); 801 802 /* set the host base address and window size */ 803 if (h->mem[win].size2 <= 1) { 804 reg = ((h->mem[win].addr >> TCIC_MEM_SHIFT) & 805 TCIC_MBASE_ADDR_MASK) | TCIC_MBASE_4K; 806 } else { 807 reg = ((h->mem[win].addr >> TCIC_MEM_SHIFT) & 808 TCIC_MBASE_ADDR_MASK) | (h->mem[win].size2 >> 1); 809 } 810 tcic_write_ind_2(h, TCIC_WR_MBASE_N(hwwin), reg); 811 812 /* set the card address and address space */ 813 reg = 0; 814 reg = ((h->mem[win].offset >> TCIC_MEM_SHIFT) & TCIC_MMAP_ADDR_MASK); 815 reg |= (kind == PCMCIA_MEM_ATTR) ? TCIC_MMAP_ATTR : 0; 816 DPRINTF(("tcic_chip_do_map_mem window %d(%d) mmap 0x%04x\n", 817 win, hwwin, reg)); 818 tcic_write_ind_2(h, TCIC_WR_MMAP_N(hwwin), reg); 819 820 /* set the MCTL register */ 821 /* must save WSCNT field in case this is a DB86082 rev 0 */ 822 /* XXX why can't I do the following two in one statement? */ 823 reg = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin)) & TCIC_MCTL_WSCNT_MASK; 824 reg |= TCIC_MCTL_ENA|TCIC_MCTL_QUIET; 825 reg |= mem8 ? TCIC_MCTL_B8 : 0; 826 reg |= (h->sock << TCIC_MCTL_SS_SHIFT) & TCIC_MCTL_SS_MASK; 827 #ifdef notyet /* XXX must get speed from CIS somehow. -chb */ 828 wscnt = tcic_ns2wscnt(h->mem[win].speed); 829 #else 830 wscnt = tcic_ns2wscnt(tcic_mem_speed); /* 300 is "save" default for CIS memory */ 831 #endif 832 if (h->sc->chipid == TCIC_CHIPID_DB86082_1) { 833 /* 834 * this chip has the wait state count in window 835 * register 7 - hwwin. 836 */ 837 int reg2; 838 reg2 = tcic_read_ind_2(h, TCIC_WR_MCTL_N(7-hwwin)); 839 reg2 &= ~TCIC_MCTL_WSCNT_MASK; 840 reg2 |= wscnt & TCIC_MCTL_WSCNT_MASK; 841 tcic_write_ind_2(h, TCIC_WR_MCTL_N(7-hwwin), reg2); 842 } else { 843 reg |= wscnt & TCIC_MCTL_WSCNT_MASK; 844 } 845 tcic_write_ind_2(h, TCIC_WR_MCTL_N(hwwin), reg); 846 847 #ifdef TCICDEBUG 848 { 849 int r1, r2, r3; 850 851 r1 = tcic_read_ind_2(h, TCIC_WR_MBASE_N(hwwin)); 852 r2 = tcic_read_ind_2(h, TCIC_WR_MMAP_N(hwwin)); 853 r3 = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin)); 854 855 DPRINTF(("tcic_chip_do_mem_map window %d(%d): %04x %04x %04x\n", 856 win, hwwin, r1, r2, r3)); 857 } 858 #endif 859 } 860 861 /* XXX needs work */ 862 int 863 tcic_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, bus_size_t *offsetp, int *windowp) 864 { 865 struct tcic_handle *h = (struct tcic_handle *) pch; 866 bus_addr_t busaddr; 867 long card_offset; 868 int i, win; 869 870 win = -1; 871 for (i = 0; i < h->memwins; i++) { 872 if ((h->memalloc & (1 << i)) == 0) { 873 win = i; 874 h->memalloc |= (1 << i); 875 break; 876 } 877 } 878 879 if (win == -1) 880 return (1); 881 882 *windowp = win; 883 884 /* XXX this is pretty gross */ 885 886 if (!bus_space_is_equal(h->sc->memt, pcmhp->memt)) 887 panic("tcic_chip_mem_map memt is bogus"); 888 889 busaddr = pcmhp->addr; 890 891 /* 892 * compute the address offset to the pcmcia address space for the 893 * tcic. this is intentionally signed. The masks and shifts below 894 * will cause TRT to happen in the tcic registers. Deal with making 895 * sure the address is aligned, and return the alignment offset. 896 */ 897 898 *offsetp = card_addr % TCIC_MEM_ALIGN; 899 card_addr -= *offsetp; 900 901 DPRINTF(("tcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 902 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 903 (u_long) card_addr)); 904 905 /* XXX we can't use size. -chb */ 906 /* 907 * include the offset in the size, and decrement size by one, since 908 * the hw wants start/stop 909 */ 910 size += *offsetp - 1; 911 912 card_offset = (((long) card_addr) - ((long) busaddr)); 913 914 DPRINTF(("tcic_chip_mem_map window %d card_offset 0x%lx\n", 915 win, (u_long)card_offset)); 916 917 h->mem[win].addr = busaddr; 918 h->mem[win].size = size; 919 h->mem[win].size2 = tcic_log2((u_int)pcmhp->realsize) - TCIC_MEM_SHIFT; 920 h->mem[win].offset = card_offset; 921 h->mem[win].kind = kind; 922 923 tcic_chip_do_mem_map(h, win); 924 925 return (0); 926 } 927 928 void 929 tcic_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 930 { 931 struct tcic_handle *h = (struct tcic_handle *) pch; 932 int hwwin; 933 934 if (window >= h->memwins) 935 panic("tcic_chip_mem_unmap: window out of range"); 936 937 hwwin = (window << 1) + h->sock; 938 tcic_write_ind_2(h, TCIC_WR_MCTL_N(hwwin), 0); 939 940 h->memalloc &= ~(1 << window); 941 } 942 943 int 944 tcic_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 945 { 946 struct tcic_handle *h = (struct tcic_handle *) pch; 947 bus_space_tag_t iot; 948 bus_space_handle_t ioh; 949 bus_addr_t ioaddr; 950 int size2, flags = 0; 951 952 /* 953 * Allocate some arbitrary I/O space. 954 */ 955 956 DPRINTF(("tcic_chip_io_alloc req 0x%lx %ld %ld\n", 957 (u_long) start, (u_long) size, (u_long) align)); 958 /* 959 * The TCIC can map I/O space only in sizes that are 960 * powers of two, aligned at the natural boundary for the size. 961 */ 962 size2 = tcic_log2((u_int)size); 963 if ((1 << size2) < size) 964 size2++; 965 /* can't allocate that much anyway */ 966 if (size2 > 16) /* XXX 64K -chb */ 967 return 1; 968 if (align) { 969 if ((1 << size2) != align) 970 return 1; /* not suitably aligned */ 971 } else { 972 align = 1 << size2; /* no alignment given, make it natural */ 973 } 974 if (start & (align - 1)) 975 return 1; /* not suitably aligned */ 976 977 iot = h->sc->iot; 978 979 if (start) { 980 ioaddr = start; 981 if (bus_space_map(iot, start, size, 0, &ioh)) 982 return (1); 983 DPRINTF(("tcic_chip_io_alloc map port %lx+%lx\n", 984 (u_long) ioaddr, (u_long) size)); 985 } else { 986 flags |= PCMCIA_IO_ALLOCATED; 987 if (bus_space_alloc(iot, h->sc->iobase, 988 h->sc->iobase + h->sc->iosize, size, align, 0, 0, 989 &ioaddr, &ioh)) 990 return (1); 991 DPRINTF(("tcic_chip_io_alloc alloc port %lx+%lx\n", 992 (u_long) ioaddr, (u_long) size)); 993 } 994 995 pcihp->iot = iot; 996 pcihp->ioh = ioh; 997 pcihp->addr = ioaddr; 998 pcihp->size = size; 999 pcihp->flags = flags; 1000 1001 return (0); 1002 } 1003 1004 void 1005 tcic_chip_io_free(pcmcia_chipset_handle_t pch, 1006 struct pcmcia_io_handle *pcihp) 1007 { 1008 bus_space_tag_t iot = pcihp->iot; 1009 bus_space_handle_t ioh = pcihp->ioh; 1010 bus_size_t size = pcihp->size; 1011 1012 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1013 bus_space_free(iot, ioh, size); 1014 else 1015 bus_space_unmap(iot, ioh, size); 1016 } 1017 1018 static int tcic_iowidth_map[] = 1019 { TCIC_ICTL_AUTOSZ, TCIC_ICTL_B8, TCIC_ICTL_B16 }; 1020 1021 void 1022 tcic_chip_do_io_map(struct tcic_handle *h, int win) 1023 { 1024 int reg, size2, iotiny, wbase, hwwin, wscnt; 1025 1026 DPRINTF(("tcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 1027 win, (long) h->io[win].addr, (long) h->io[win].size, 1028 h->io[win].width * 8)); 1029 1030 /* 1031 * the even windows are used for socket 0, 1032 * the odd ones for socket 1. 1033 */ 1034 hwwin = (win << 1) + h->sock; 1035 1036 /* set the WR_BASE register */ 1037 /* XXX what if size isn't power of 2? -chb */ 1038 size2 = tcic_log2((u_int)h->io[win].size); 1039 DPRINTF(("tcic_chip_do_io_map win %d size2 %d\n", win, size2)); 1040 if (size2 < 1) { 1041 iotiny = TCIC_ICTL_TINY; 1042 wbase = h->io[win].addr; 1043 } else { 1044 iotiny = 0; 1045 /* XXX we should do better -chb */ 1046 wbase = h->io[win].addr | (1 << (size2 - 1)); 1047 } 1048 tcic_write_ind_2(h, TCIC_WR_IBASE_N(hwwin), wbase); 1049 1050 /* set the WR_ICTL register */ 1051 reg = TCIC_ICTL_ENA | TCIC_ICTL_QUIET; 1052 reg |= (h->sock << TCIC_ICTL_SS_SHIFT) & TCIC_ICTL_SS_MASK; 1053 reg |= iotiny | tcic_iowidth_map[h->io[win].width]; 1054 if (h->sc->chipid != TCIC_CHIPID_DB86082_1) 1055 reg |= TCIC_ICTL_PASS16; 1056 #ifdef notyet /* XXX must get speed from CIS somehow. -chb */ 1057 wscnt = tcic_ns2wscnt(h->io[win].speed); 1058 #else 1059 wscnt = tcic_ns2wscnt(tcic_io_speed); /* linux uses 0 as default */ 1060 #endif 1061 reg |= wscnt & TCIC_ICTL_WSCNT_MASK; 1062 tcic_write_ind_2(h, TCIC_WR_ICTL_N(hwwin), reg); 1063 1064 #ifdef TCICDEBUG 1065 { 1066 int r1, r2; 1067 1068 r1 = tcic_read_ind_2(h, TCIC_WR_IBASE_N(hwwin)); 1069 r2 = tcic_read_ind_2(h, TCIC_WR_ICTL_N(hwwin)); 1070 1071 DPRINTF(("tcic_chip_do_io_map window %d(%d): %04x %04x\n", 1072 win, hwwin, r1, r2)); 1073 } 1074 #endif 1075 } 1076 1077 int 1078 tcic_chip_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 1079 { 1080 struct tcic_handle *h = (struct tcic_handle *) pch; 1081 bus_addr_t ioaddr = pcihp->addr + offset; 1082 int i, win; 1083 #ifdef TCICDEBUG 1084 static const char *width_names[] = { "auto", "io8", "io16" }; 1085 #endif 1086 1087 /* XXX Sanity check offset/size. */ 1088 1089 win = -1; 1090 for (i = 0; i < TCIC_IO_WINS; i++) { 1091 if ((h->ioalloc & (1 << i)) == 0) { 1092 win = i; 1093 h->ioalloc |= (1 << i); 1094 break; 1095 } 1096 } 1097 1098 if (win == -1) 1099 return (1); 1100 1101 *windowp = win; 1102 1103 /* XXX this is pretty gross */ 1104 1105 if (!bus_space_is_equal(h->sc->iot, pcihp->iot)) 1106 panic("tcic_chip_io_map iot is bogus"); 1107 1108 DPRINTF(("tcic_chip_io_map window %d %s port %lx+%lx\n", 1109 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1110 1111 /* XXX wtf is this doing here? */ 1112 1113 printf("%s: port 0x%lx", device_xname(&h->sc->dev), (u_long) ioaddr); 1114 if (size > 1) 1115 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1116 printf("\n"); 1117 1118 h->io[win].addr = ioaddr; 1119 h->io[win].size = size; 1120 h->io[win].width = width; 1121 1122 tcic_chip_do_io_map(h, win); 1123 1124 return (0); 1125 } 1126 1127 void 1128 tcic_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 1129 { 1130 struct tcic_handle *h = (struct tcic_handle *) pch; 1131 int hwwin; 1132 1133 if (window >= TCIC_IO_WINS) 1134 panic("tcic_chip_io_unmap: window out of range"); 1135 1136 hwwin = (window << 1) + h->sock; 1137 tcic_write_ind_2(h, TCIC_WR_ICTL_N(hwwin), 0); 1138 1139 h->ioalloc &= ~(1 << window); 1140 } 1141 1142 void 1143 tcic_chip_socket_enable(pcmcia_chipset_handle_t pch) 1144 { 1145 struct tcic_handle *h = (struct tcic_handle *) pch; 1146 int reg, win; 1147 1148 tcic_sel_sock(h); 1149 1150 /* 1151 * power down the socket to reset it. 1152 * put card reset into high-z, put chip outputs to card into high-z 1153 */ 1154 1155 tcic_write_1(h, TCIC_R_PWR, 0); 1156 reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1157 reg |= TCIC_ILOCK_CWAIT; 1158 reg &= ~(TCIC_ILOCK_CRESET|TCIC_ILOCK_CRESENA); 1159 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1160 tcic_write_1(h, TCIC_R_SCTRL, 0); /* clear TCIC_SCTRL_ENA */ 1161 1162 /* zero out the address windows */ 1163 1164 tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), 0); 1165 /* writing to WR_MBASE_N disables the window */ 1166 for (win = 0; win < h->memwins; win++) { 1167 tcic_write_ind_2(h, TCIC_WR_MBASE_N((win << 1) + h->sock), 0); 1168 } 1169 /* writing to WR_IBASE_N disables the window */ 1170 for (win = 0; win < TCIC_IO_WINS; win++) { 1171 tcic_write_ind_2(h, TCIC_WR_IBASE_N((win << 1) + h->sock), 0); 1172 } 1173 1174 /* power up the socket */ 1175 1176 /* turn on VCC, turn of VPP */ 1177 reg = TCIC_PWR_VCC_N(h->sock) | TCIC_PWR_VPP_N(h->sock) | h->sc->pwrena; 1178 if (h->sc->pwrena) /* this is a '84 type chip */ 1179 reg |= TCIC_PWR_VCC5V; 1180 tcic_write_1(h, TCIC_R_PWR, reg); 1181 delay(10000); 1182 1183 /* enable reset and wiggle it to reset the card */ 1184 reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1185 reg |= TCIC_ILOCK_CRESENA; 1186 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1187 /* XXX need bus_space_barrier here */ 1188 reg |= TCIC_ILOCK_CRESET; 1189 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1190 /* enable card signals */ 1191 tcic_write_1(h, TCIC_R_SCTRL, TCIC_SCTRL_ENA); 1192 delay(10); /* wait 10 us */ 1193 1194 /* clear the reset flag */ 1195 reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1196 reg &= ~(TCIC_ILOCK_CRESET); 1197 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1198 1199 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1200 delay(20000); 1201 1202 /* wait for the chip to finish initializing */ 1203 tcic_wait_ready(h); 1204 1205 /* WWW */ 1206 1207 /* reinstall all the memory and io mappings */ 1208 1209 for (win = 0; win < h->memwins; win++) 1210 if (h->memalloc & (1 << win)) 1211 tcic_chip_do_mem_map(h, win); 1212 1213 for (win = 0; win < TCIC_IO_WINS; win++) 1214 if (h->ioalloc & (1 << win)) 1215 tcic_chip_do_io_map(h, win); 1216 } 1217 1218 void 1219 tcic_chip_socket_settype(pcmcia_chipset_handle_t pch, int type) 1220 { 1221 struct tcic_handle *h = (struct tcic_handle *) pch; 1222 int reg; 1223 1224 tcic_sel_sock(h); 1225 1226 /* set the card type */ 1227 1228 reg = 0; 1229 if (type == PCMCIA_IFTYPE_IO) { 1230 reg |= TCIC_SCF1_IOSTS; 1231 reg |= tcic_irqmap[h->ih_irq]; /* enable interrupts */ 1232 } 1233 tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), reg); 1234 1235 DPRINTF(("%s: tcic_chip_socket_enable %d cardtype %s 0x%02x\n", 1236 device_xname(&h->sc->dev), h->sock, 1237 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg)); 1238 } 1239 1240 void 1241 tcic_chip_socket_disable(pcmcia_chipset_handle_t pch) 1242 { 1243 struct tcic_handle *h = (struct tcic_handle *) pch; 1244 int val; 1245 1246 DPRINTF(("tcic_chip_socket_disable\n")); 1247 1248 tcic_sel_sock(h); 1249 1250 /* disable interrupts */ 1251 val = tcic_read_ind_2(h, TCIC_IR_SCF1_N(h->sock)); 1252 val &= TCIC_SCF1_IRQ_MASK; 1253 tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), val); 1254 1255 /* disable the output signals */ 1256 tcic_write_1(h, TCIC_R_SCTRL, 0); 1257 val = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1258 val &= ~TCIC_ILOCK_CRESENA; 1259 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, val); 1260 1261 /* power down the socket */ 1262 tcic_write_1(h, TCIC_R_PWR, 0); 1263 } 1264 1265 /* 1266 * XXX The following is Linux driver but doesn't match the table 1267 * in the manual. 1268 */ 1269 int 1270 tcic_ns2wscnt(int ns) 1271 { 1272 if (ns < 14) { 1273 return 0; 1274 } else { 1275 return (2*(ns-14))/70; /* XXX assumes 14.31818 MHz clock. */ 1276 } 1277 } 1278 1279 int 1280 tcic_log2(u_int val) 1281 { 1282 int i, l2; 1283 1284 l2 = i = 0; 1285 while (val) { 1286 if (val & 1) 1287 l2 = i; 1288 i++; 1289 val >>= 1; 1290 } 1291 return l2; 1292 } 1293