1 /* $NetBSD: tcic2.c,v 1.23 2005/12/11 12:21:28 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 Christoph Badura. All rights reserved. 5 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Marc Horowitz. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: tcic2.c,v 1.23 2005/12/11 12:21:28 christos Exp $"); 35 36 #undef TCICDEBUG 37 38 #include <sys/param.h> 39 #include <sys/systm.h> 40 #include <sys/device.h> 41 #include <sys/extent.h> 42 #include <sys/malloc.h> 43 #include <sys/kthread.h> 44 45 #include <machine/bus.h> 46 #include <machine/intr.h> 47 48 #include <dev/pcmcia/pcmciareg.h> 49 #include <dev/pcmcia/pcmciavar.h> 50 51 #include <dev/ic/tcic2reg.h> 52 #include <dev/ic/tcic2var.h> 53 54 #include "locators.h" 55 56 #ifdef TCICDEBUG 57 int tcic_debug = 1; 58 #define DPRINTF(arg) if (tcic_debug) printf arg; 59 #else 60 #define DPRINTF(arg) 61 #endif 62 63 /* 64 * Individual drivers will allocate their own memory and io regions. Memory 65 * regions must be a multiple of 4k, aligned on a 4k boundary. 66 */ 67 68 #define TCIC_MEM_ALIGN TCIC_MEM_PAGESIZE 69 70 void tcic_attach_socket(struct tcic_handle *); 71 void tcic_init_socket(struct tcic_handle *); 72 73 int tcic_print(void *arg, const char *pnp); 74 int tcic_intr_socket(struct tcic_handle *); 75 76 void tcic_attach_card(struct tcic_handle *); 77 void tcic_detach_card(struct tcic_handle *, int); 78 void tcic_deactivate_card(struct tcic_handle *); 79 80 void tcic_chip_do_mem_map(struct tcic_handle *, int); 81 void tcic_chip_do_io_map(struct tcic_handle *, int); 82 83 void tcic_create_event_thread(void *); 84 void tcic_event_thread(void *); 85 86 void tcic_queue_event(struct tcic_handle *, int); 87 88 /* Map between irq numbers and internal representation */ 89 #if 1 90 int tcic_irqmap[] = 91 { 0, 0, 0, 3, 4, 5, 6, 7, 0, 0, 10, 1, 0, 0, 14, 0 }; 92 int tcic_valid_irqs = 0x4cf8; 93 #else 94 int tcic_irqmap[] = /* irqs 9 and 6 switched, some ISA cards */ 95 { 0, 0, 0, 3, 4, 5, 0, 7, 0, 6, 10, 1, 0, 0, 14, 0 }; 96 int tcic_valid_irqs = 0x4eb8; 97 #endif 98 99 int tcic_mem_speed = 250; /* memory access time in nanoseconds */ 100 int tcic_io_speed = 165; /* io access time in nanoseconds */ 101 102 /* 103 * Check various reserved and otherwise in their value restricted bits. 104 */ 105 int 106 tcic_check_reserved_bits(iot, ioh) 107 bus_space_tag_t iot; 108 bus_space_handle_t ioh; 109 { 110 int val, auxreg; 111 112 DPRINTF(("tcic: chkrsvd 1\n")); 113 /* R_ADDR bit 30:28 have a restricted range. */ 114 val = (bus_space_read_2(iot, ioh, TCIC_R_ADDR2) & TCIC_SS_MASK) 115 >> TCIC_SS_SHIFT; 116 if (val > 1) 117 return 0; 118 119 DPRINTF(("tcic: chkrsvd 2\n")); 120 /* R_SCTRL bits 6,2,1 are reserved. */ 121 val = bus_space_read_1(iot, ioh, TCIC_R_SCTRL); 122 if (val & TCIC_SCTRL_RSVD) 123 return 0; 124 125 DPRINTF(("tcic: chkrsvd 3\n")); 126 /* R_ICSR bit 2 must be same as bit 3. */ 127 val = bus_space_read_1(iot, ioh, TCIC_R_ICSR); 128 if (((val >> 1) & 1) != ((val >> 2) & 1)) 129 return 0; 130 131 DPRINTF(("tcic: chkrsvd 4\n")); 132 /* R_IENA bits 7,2 are reserverd. */ 133 val = bus_space_read_1(iot, ioh, TCIC_R_IENA); 134 if (val & TCIC_IENA_RSVD) 135 return 0; 136 137 DPRINTF(("tcic: chkrsvd 5\n")); 138 /* Some aux registers have reserved bits. */ 139 /* Which are we looking at? */ 140 auxreg = bus_space_read_1(iot, ioh, TCIC_R_MODE) 141 & TCIC_AR_MASK; 142 val = bus_space_read_2(iot, ioh, TCIC_R_AUX); 143 DPRINTF(("tcic: auxreg 0x%02x val 0x%04x\n", auxreg, val)); 144 switch (auxreg) { 145 case TCIC_AR_SYSCFG: 146 if (INVALID_AR_SYSCFG(val)) 147 return 0; 148 break; 149 case TCIC_AR_ILOCK: 150 if (INVALID_AR_ILOCK(val)) 151 return 0; 152 break; 153 case TCIC_AR_TEST: 154 if (INVALID_AR_TEST(val)) 155 return 0; 156 break; 157 } 158 159 DPRINTF(("tcic: chkrsvd 6\n")); 160 /* XXX fails if pcmcia bios is enabled. */ 161 /* Various bits set or not depending if in RESET mode. */ 162 val = bus_space_read_1(iot, ioh, TCIC_R_SCTRL); 163 if (val & TCIC_SCTRL_RESET) { 164 DPRINTF(("tcic: chkrsvd 7\n")); 165 /* Address bits must be 0 */ 166 val = bus_space_read_2(iot, ioh, TCIC_R_ADDR); 167 if (val != 0) 168 return 0; 169 val = bus_space_read_2(iot, ioh, TCIC_R_ADDR2); 170 if (val != 0) 171 return 0; 172 DPRINTF(("tcic: chkrsvd 8\n")); 173 /* EDC bits must be 0 */ 174 val = bus_space_read_2(iot, ioh, TCIC_R_EDC); 175 if (val != 0) 176 return 0; 177 /* We're OK, so take it out of reset. XXX -chb */ 178 bus_space_write_1(iot, ioh, TCIC_R_SCTRL, 0); 179 } 180 else { /* not in RESET mode */ 181 int omode; 182 int val1, val2; 183 DPRINTF(("tcic: chkrsvd 9\n")); 184 /* Programming timers must have expired. */ 185 val = bus_space_read_1(iot, ioh, TCIC_R_SSTAT); 186 if ((val & (TCIC_SSTAT_6US|TCIC_SSTAT_10US|TCIC_SSTAT_PROGTIME)) 187 != (TCIC_SSTAT_6US|TCIC_SSTAT_10US|TCIC_SSTAT_PROGTIME)) 188 return 0; 189 DPRINTF(("tcic: chkrsvd 10\n")); 190 /* 191 * EDC bits should change on read from data space 192 * as long as either EDC or the data are nonzero. 193 */ 194 if ((bus_space_read_2(iot, ioh, TCIC_R_ADDR2) 195 & TCIC_ADDR2_INDREG) != 0) { 196 val1 = bus_space_read_2(iot, ioh, TCIC_R_EDC); 197 val2 = bus_space_read_2(iot, ioh, TCIC_R_DATA); 198 if (val1 | val2) { 199 val1 = bus_space_read_2(iot, ioh, TCIC_R_EDC); 200 if (val1 == val2) 201 return 0; 202 } 203 } 204 DPRINTF(("tcic: chkrsvd 11\n")); 205 /* XXX what does this check? -chb */ 206 omode = bus_space_read_1(iot, ioh, TCIC_R_MODE); 207 val1 = omode ^ TCIC_AR_MASK; 208 bus_space_write_1(iot, ioh, TCIC_R_MODE, val1); 209 val2 = bus_space_read_1(iot, ioh, TCIC_R_MODE); 210 bus_space_write_1(iot, ioh, TCIC_R_MODE, omode); 211 if ( val1 != val2) 212 return 0; 213 } 214 /* All tests passed */ 215 return 1; 216 } 217 218 /* 219 * Read chip ID from AR_ILOCK in test mode. 220 */ 221 int 222 tcic_chipid(iot, ioh) 223 bus_space_tag_t iot; 224 bus_space_handle_t ioh; 225 { 226 unsigned id, otest; 227 228 otest = tcic_read_aux_2(iot, ioh, TCIC_AR_TEST); 229 tcic_write_aux_2(iot, ioh, TCIC_AR_TEST, TCIC_TEST_DIAG); 230 id = tcic_read_aux_2(iot, ioh, TCIC_AR_ILOCK); 231 tcic_write_aux_2(iot, ioh, TCIC_AR_TEST, otest); 232 id &= TCIC_ILOCKTEST_ID_MASK; 233 id >>= TCIC_ILOCKTEST_ID_SHFT; 234 235 /* clear up IRQs inside tcic. XXX -chb */ 236 while (bus_space_read_1(iot, ioh, TCIC_R_ICSR)) 237 bus_space_write_1(iot, ioh, TCIC_R_ICSR, TCIC_ICSR_JAM); 238 239 return id; 240 } 241 /* 242 * Indicate whether the driver can handle the chip. 243 */ 244 int 245 tcic_chipid_known(id) 246 int id; 247 { 248 /* XXX only know how to handle DB86082 -chb */ 249 switch (id) { 250 case TCIC_CHIPID_DB86082_1: 251 case TCIC_CHIPID_DB86082A: 252 case TCIC_CHIPID_DB86082B_ES: 253 case TCIC_CHIPID_DB86082B: 254 case TCIC_CHIPID_DB86084_1: 255 case TCIC_CHIPID_DB86084A: 256 case TCIC_CHIPID_DB86184_1: 257 case TCIC_CHIPID_DB86072_1_ES: 258 case TCIC_CHIPID_DB86072_1: 259 return 1; 260 } 261 262 return 0; 263 } 264 265 const char * 266 tcic_chipid_to_string(id) 267 int id; 268 { 269 switch (id) { 270 case TCIC_CHIPID_DB86082_1: 271 return ("Databook DB86082"); 272 case TCIC_CHIPID_DB86082A: 273 return ("Databook DB86082A"); 274 case TCIC_CHIPID_DB86082B_ES: 275 return ("Databook DB86082B-es"); 276 case TCIC_CHIPID_DB86082B: 277 return ("Databook DB86082B"); 278 case TCIC_CHIPID_DB86084_1: 279 return ("Databook DB86084"); 280 case TCIC_CHIPID_DB86084A: 281 return ("Databook DB86084A"); 282 case TCIC_CHIPID_DB86184_1: 283 return ("Databook DB86184"); 284 case TCIC_CHIPID_DB86072_1_ES: 285 return ("Databook DB86072-es"); 286 case TCIC_CHIPID_DB86072_1: 287 return ("Databook DB86072"); 288 } 289 290 return ("Unknown controller"); 291 } 292 /* 293 * Return bitmask of IRQs that the chip can handle. 294 * XXX should be table driven. 295 */ 296 int 297 tcic_validirqs(chipid) 298 int chipid; 299 { 300 switch (chipid) { 301 case TCIC_CHIPID_DB86082_1: 302 case TCIC_CHIPID_DB86082A: 303 case TCIC_CHIPID_DB86082B_ES: 304 case TCIC_CHIPID_DB86082B: 305 case TCIC_CHIPID_DB86084_1: 306 case TCIC_CHIPID_DB86084A: 307 case TCIC_CHIPID_DB86184_1: 308 case TCIC_CHIPID_DB86072_1_ES: 309 case TCIC_CHIPID_DB86072_1: 310 return tcic_valid_irqs; 311 } 312 return 0; 313 } 314 315 void 316 tcic_attach(sc) 317 struct tcic_softc *sc; 318 { 319 int i, reg; 320 321 /* set more chipset dependent parameters in the softc. */ 322 switch (sc->chipid) { 323 case TCIC_CHIPID_DB86084_1: 324 case TCIC_CHIPID_DB86084A: 325 case TCIC_CHIPID_DB86184_1: 326 sc->pwrena = TCIC_PWR_ENA; 327 break; 328 default: 329 sc->pwrena = 0; 330 break; 331 } 332 333 /* set up global config registers */ 334 reg = TCIC_WAIT_SYNC | TCIC_WAIT_CCLK | TCIC_WAIT_RISING; 335 reg |= (tcic_ns2wscnt(250) & TCIC_WAIT_COUNT_MASK); 336 tcic_write_aux_1(sc->iot, sc->ioh, TCIC_AR_WCTL, TCIC_R_WCTL_WAIT, reg); 337 reg = TCIC_SYSCFG_MPSEL_RI | TCIC_SYSCFG_MCSFULL; 338 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, reg); 339 reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_ILOCK); 340 reg |= TCIC_ILOCK_HOLD_CCLK; 341 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_ILOCK, reg); 342 343 /* the TCIC has two sockets */ 344 /* XXX should i check for actual presence of sockets? -chb */ 345 for (i = 0; i < TCIC_NSLOTS; i++) { 346 sc->handle[i].sc = sc; 347 sc->handle[i].sock = i; 348 sc->handle[i].flags = TCIC_FLAG_SOCKETP; 349 sc->handle[i].memwins 350 = sc->chipid == TCIC_CHIPID_DB86082_1 ? 4 : 5; 351 } 352 353 /* establish the interrupt */ 354 reg = tcic_read_1(&sc->handle[0], TCIC_R_IENA); 355 tcic_write_1(&sc->handle[0], TCIC_R_IENA, 356 (reg & ~TCIC_IENA_CFG_MASK) | TCIC_IENA_CFG_HIGH); 357 reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG); 358 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, 359 (reg & ~TCIC_SYSCFG_IRQ_MASK) | tcic_irqmap[sc->irq]); 360 361 /* XXX block interrupts? */ 362 363 for (i = 0; i < TCIC_NSLOTS; i++) { 364 /* XXX make more clear what happens here -chb */ 365 tcic_sel_sock(&sc->handle[i]); 366 tcic_write_ind_2(&sc->handle[i], TCIC_IR_SCF1_N(i), 0); 367 tcic_write_ind_2(&sc->handle[i], TCIC_IR_SCF2_N(i), 368 (TCIC_SCF2_MCD|TCIC_SCF2_MWP|TCIC_SCF2_MRDY 369 #if 1 /* XXX explain byte routing issue */ 370 |TCIC_SCF2_MLBAT2|TCIC_SCF2_MLBAT1|TCIC_SCF2_IDBR)); 371 #else 372 |TCIC_SCF2_MLBAT2|TCIC_SCF2_MLBAT1)); 373 #endif 374 tcic_write_1(&sc->handle[i], TCIC_R_MODE, 0); 375 reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG); 376 reg &= ~TCIC_SYSCFG_AUTOBUSY; 377 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, reg); 378 SIMPLEQ_INIT(&sc->handle[i].events); 379 } 380 381 if ((sc->handle[0].flags & TCIC_FLAG_SOCKETP) || 382 (sc->handle[1].flags & TCIC_FLAG_SOCKETP)) { 383 printf("%s: %s has ", sc->dev.dv_xname, 384 tcic_chipid_to_string(sc->chipid)); 385 386 if ((sc->handle[0].flags & TCIC_FLAG_SOCKETP) && 387 (sc->handle[1].flags & TCIC_FLAG_SOCKETP)) 388 printf("sockets A and B\n"); 389 else if (sc->handle[0].flags & TCIC_FLAG_SOCKETP) 390 printf("socket A only\n"); 391 else 392 printf("socket B only\n"); 393 394 } 395 } 396 397 void 398 tcic_attach_sockets(sc) 399 struct tcic_softc *sc; 400 { 401 int i; 402 403 for (i = 0; i < TCIC_NSLOTS; i++) 404 if (sc->handle[i].flags & TCIC_FLAG_SOCKETP) 405 tcic_attach_socket(&sc->handle[i]); 406 } 407 408 void 409 tcic_attach_socket(h) 410 struct tcic_handle *h; 411 { 412 struct pcmciabus_attach_args paa; 413 int locs[PCMCIABUSCF_NLOCS]; 414 415 /* initialize the rest of the handle */ 416 417 h->shutdown = 0; 418 h->memalloc = 0; 419 h->ioalloc = 0; 420 h->ih_irq = 0; 421 422 /* now, config one pcmcia device per socket */ 423 424 paa.paa_busname = "pcmcia"; 425 paa.pct = (pcmcia_chipset_tag_t) h->sc->pct; 426 paa.pch = (pcmcia_chipset_handle_t) h; 427 paa.iobase = h->sc->iobase; 428 paa.iosize = h->sc->iosize; 429 430 locs[PCMCIABUSCF_CONTROLLER] = 0; 431 locs[PCMCIABUSCF_SOCKET] = h->sock; 432 433 h->pcmcia = config_found_sm_loc(&h->sc->dev, "pcmciabus", locs, &paa, 434 tcic_print, config_stdsubmatch); 435 436 /* if there's actually a pcmcia device attached, initialize the slot */ 437 438 if (h->pcmcia) 439 tcic_init_socket(h); 440 } 441 442 void 443 tcic_create_event_thread(arg) 444 void *arg; 445 { 446 struct tcic_handle *h = arg; 447 const char *cs; 448 449 switch (h->sock) { 450 case 0: 451 cs = "0"; 452 break; 453 case 1: 454 cs = "1"; 455 break; 456 default: 457 panic("tcic_create_event_thread: unknown tcic socket"); 458 } 459 460 if (kthread_create1(tcic_event_thread, h, &h->event_thread, 461 "%s,%s", h->sc->dev.dv_xname, cs)) { 462 printf("%s: unable to create event thread for sock 0x%02x\n", 463 h->sc->dev.dv_xname, h->sock); 464 panic("tcic_create_event_thread"); 465 } 466 } 467 468 void 469 tcic_event_thread(arg) 470 void *arg; 471 { 472 struct tcic_handle *h = arg; 473 struct tcic_event *pe; 474 int s; 475 476 while (h->shutdown == 0) { 477 s = splhigh(); 478 if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) { 479 splx(s); 480 (void) tsleep(&h->events, PWAIT, "tcicev", 0); 481 continue; 482 } 483 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 484 splx(s); 485 486 switch (pe->pe_type) { 487 case TCIC_EVENT_INSERTION: 488 DPRINTF(("%s: insertion event\n", h->sc->dev.dv_xname)); 489 tcic_attach_card(h); 490 break; 491 492 case TCIC_EVENT_REMOVAL: 493 DPRINTF(("%s: removal event\n", h->sc->dev.dv_xname)); 494 tcic_detach_card(h, DETACH_FORCE); 495 break; 496 497 default: 498 panic("tcic_event_thread: unknown event %d", 499 pe->pe_type); 500 } 501 free(pe, M_TEMP); 502 } 503 504 h->event_thread = NULL; 505 506 /* In case parent is waiting for us to exit. */ 507 wakeup(h->sc); 508 509 kthread_exit(0); 510 } 511 512 513 void 514 tcic_init_socket(h) 515 struct tcic_handle *h; 516 { 517 int reg; 518 519 /* select this socket's config registers */ 520 tcic_sel_sock(h); 521 522 /* set up the socket to interrupt on card detect */ 523 reg = tcic_read_ind_2(h, TCIC_IR_SCF2_N(h->sock)); 524 tcic_write_ind_2(h, TCIC_IR_SCF2_N(h->sock), reg & ~TCIC_SCF2_MCD); 525 526 /* enable CD irq in R_IENA */ 527 reg = tcic_read_2(h, TCIC_R_IENA); 528 tcic_write_2(h, TCIC_R_IENA, reg |= TCIC_IENA_CDCHG); 529 530 /* if there's a card there, then attach it. also save sstat */ 531 h->sstat = reg = tcic_read_1(h, TCIC_R_SSTAT) & TCIC_SSTAT_STAT_MASK; 532 if (reg & TCIC_SSTAT_CD) 533 tcic_attach_card(h); 534 } 535 536 int 537 tcic_print(arg, pnp) 538 void *arg; 539 const char *pnp; 540 { 541 struct pcmciabus_attach_args *paa = arg; 542 struct tcic_handle *h = (struct tcic_handle *) paa->pch; 543 544 /* Only "pcmcia"s can attach to "tcic"s... easy. */ 545 if (pnp) 546 aprint_normal("pcmcia at %s", pnp); 547 548 aprint_normal(" socket %d", h->sock); 549 550 return (UNCONF); 551 } 552 553 int 554 tcic_intr(arg) 555 void *arg; 556 { 557 struct tcic_softc *sc = arg; 558 int i, ret = 0; 559 560 DPRINTF(("%s: intr\n", sc->dev.dv_xname)); 561 562 for (i = 0; i < TCIC_NSLOTS; i++) 563 if (sc->handle[i].flags & TCIC_FLAG_SOCKETP) 564 ret += tcic_intr_socket(&sc->handle[i]); 565 566 return (ret ? 1 : 0); 567 } 568 569 int 570 tcic_intr_socket(h) 571 struct tcic_handle *h; 572 { 573 int icsr, rv; 574 575 rv = 0; 576 tcic_sel_sock(h); 577 icsr = tcic_read_1(h, TCIC_R_ICSR); 578 579 DPRINTF(("%s: %d icsr: 0x%02x \n", h->sc->dev.dv_xname, h->sock, icsr)); 580 581 /* XXX or should the next three be handled in tcic_intr? -chb */ 582 if (icsr & TCIC_ICSR_PROGTIME) { 583 DPRINTF(("%s: %02x PROGTIME\n", h->sc->dev.dv_xname, h->sock)); 584 rv = 1; 585 } 586 if (icsr & TCIC_ICSR_ILOCK) { 587 DPRINTF(("%s: %02x ILOCK\n", h->sc->dev.dv_xname, h->sock)); 588 rv = 1; 589 } 590 if (icsr & TCIC_ICSR_ERR) { 591 DPRINTF(("%s: %02x ERR\n", h->sc->dev.dv_xname, h->sock)); 592 rv = 1; 593 } 594 if (icsr & TCIC_ICSR_CDCHG) { 595 int sstat, delta; 596 597 /* compute what changed since last interrupt */ 598 sstat = tcic_read_aux_1(h->sc->iot, h->sc->ioh, 599 TCIC_AR_WCTL, TCIC_R_WCTL_XCSR) & TCIC_XCSR_STAT_MASK; 600 delta = h->sstat ^ sstat; 601 h->sstat = sstat; 602 603 if (delta) 604 rv = 1; 605 606 DPRINTF(("%s: %02x CDCHG %x\n", h->sc->dev.dv_xname, h->sock, 607 delta)); 608 609 /* 610 * XXX This should probably schedule something to happen 611 * after the interrupt handler completes 612 */ 613 614 if (delta & TCIC_SSTAT_CD) { 615 if (sstat & TCIC_SSTAT_CD) { 616 if (!(h->flags & TCIC_FLAG_CARDP)) { 617 DPRINTF(("%s: enqueing INSERTION event\n", 618 h->sc->dev.dv_xname)); 619 tcic_queue_event(h, TCIC_EVENT_INSERTION); 620 } 621 } else { 622 if (h->flags & TCIC_FLAG_CARDP) { 623 /* Deactivate the card now. */ 624 DPRINTF(("%s: deactivating card\n", 625 h->sc->dev.dv_xname)); 626 tcic_deactivate_card(h); 627 628 DPRINTF(("%s: enqueing REMOVAL event\n", 629 h->sc->dev.dv_xname)); 630 tcic_queue_event(h, TCIC_EVENT_REMOVAL); 631 } 632 } 633 } 634 if (delta & TCIC_SSTAT_RDY) { 635 DPRINTF(("%s: %02x READY\n", h->sc->dev.dv_xname, h->sock)); 636 /* shouldn't happen */ 637 } 638 if (delta & TCIC_SSTAT_LBAT1) { 639 DPRINTF(("%s: %02x LBAT1\n", h->sc->dev.dv_xname, h->sock)); 640 } 641 if (delta & TCIC_SSTAT_LBAT2) { 642 DPRINTF(("%s: %02x LBAT2\n", h->sc->dev.dv_xname, h->sock)); 643 } 644 if (delta & TCIC_SSTAT_WP) { 645 DPRINTF(("%s: %02x WP\n", h->sc->dev.dv_xname, h->sock)); 646 } 647 } 648 return rv; 649 } 650 651 void 652 tcic_queue_event(h, event) 653 struct tcic_handle *h; 654 int event; 655 { 656 struct tcic_event *pe; 657 int s; 658 659 pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT); 660 if (pe == NULL) 661 panic("tcic_queue_event: can't allocate event"); 662 663 pe->pe_type = event; 664 s = splhigh(); 665 SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q); 666 splx(s); 667 wakeup(&h->events); 668 } 669 void 670 tcic_attach_card(h) 671 struct tcic_handle *h; 672 { 673 DPRINTF(("tcic_attach_card\n")); 674 675 if (h->flags & TCIC_FLAG_CARDP) 676 panic("tcic_attach_card: already attached"); 677 678 /* call the MI attach function */ 679 680 pcmcia_card_attach(h->pcmcia); 681 682 h->flags |= TCIC_FLAG_CARDP; 683 } 684 685 void 686 tcic_detach_card(h, flags) 687 struct tcic_handle *h; 688 int flags; /* DETACH_* */ 689 { 690 DPRINTF(("tcic_detach_card\n")); 691 692 if (!(h->flags & TCIC_FLAG_CARDP)) 693 panic("tcic_detach_card: already detached"); 694 695 h->flags &= ~TCIC_FLAG_CARDP; 696 697 /* call the MI detach function */ 698 699 pcmcia_card_detach(h->pcmcia, flags); 700 701 } 702 703 void 704 tcic_deactivate_card(h) 705 struct tcic_handle *h; 706 { 707 int val, reg; 708 709 if (!(h->flags & TCIC_FLAG_CARDP)) 710 panic("tcic_deactivate_card: already detached"); 711 712 /* call the MI deactivate function */ 713 pcmcia_card_deactivate(h->pcmcia); 714 715 tcic_sel_sock(h); 716 717 /* XXX disable card detect resume and configuration reset??? */ 718 719 /* power down the socket */ 720 tcic_write_1(h, TCIC_R_PWR, 0); 721 722 /* reset the card XXX ? -chb */ 723 724 /* turn off irq's for this socket */ 725 reg = TCIC_IR_SCF1_N(h->sock); 726 val = tcic_read_ind_2(h, reg); 727 tcic_write_ind_2(h, reg, (val & ~TCIC_SCF1_IRQ_MASK)|TCIC_SCF1_IRQOFF); 728 reg = TCIC_IR_SCF2_N(h->sock); 729 val = tcic_read_ind_2(h, reg); 730 tcic_write_ind_2(h, reg, 731 (val | (TCIC_SCF2_MLBAT1|TCIC_SCF2_MLBAT2|TCIC_SCF2_MRDY 732 |TCIC_SCF2_MWP|TCIC_SCF2_MCD))); 733 } 734 735 /* XXX the following routine may need to be rewritten. -chb */ 736 int 737 tcic_chip_mem_alloc(pch, size, pcmhp) 738 pcmcia_chipset_handle_t pch; 739 bus_size_t size; 740 struct pcmcia_mem_handle *pcmhp; 741 { 742 struct tcic_handle *h = (struct tcic_handle *) pch; 743 bus_space_handle_t memh; 744 bus_addr_t addr; 745 bus_size_t sizepg; 746 int i, mask, mhandle; 747 748 /* out of sc->memh, allocate as many pages as necessary */ 749 750 /* 751 * The TCIC can map memory only in sizes that are 752 * powers of two, aligned at the natural boundary for the size. 753 */ 754 i = tcic_log2((u_int)size); 755 if ((1<<i) < size) 756 i++; 757 sizepg = max(i, TCIC_MEM_SHIFT) - (TCIC_MEM_SHIFT-1); 758 759 DPRINTF(("tcic_chip_mem_alloc: size %ld sizepg %ld\n", size, sizepg)); 760 761 /* can't allocate that much anyway */ 762 if (sizepg > TCIC_MEM_PAGES) /* XXX -chb */ 763 return 1; 764 765 mask = (1 << sizepg) - 1; 766 767 addr = 0; /* XXX gcc -Wuninitialized */ 768 mhandle = 0; /* XXX gcc -Wuninitialized */ 769 770 /* XXX i should be initialised to always lay on boundary. -chb */ 771 for (i = 0; i < (TCIC_MEM_PAGES + 1 - sizepg); i += sizepg) { 772 if ((h->sc->subregionmask & (mask << i)) == (mask << i)) { 773 if (bus_space_subregion(h->sc->memt, h->sc->memh, 774 i * TCIC_MEM_PAGESIZE, 775 sizepg * TCIC_MEM_PAGESIZE, &memh)) 776 return (1); 777 mhandle = mask << i; 778 addr = h->sc->membase + (i * TCIC_MEM_PAGESIZE); 779 h->sc->subregionmask &= ~(mhandle); 780 break; 781 } 782 } 783 784 if (i == (TCIC_MEM_PAGES + 1 - sizepg)) 785 return (1); 786 787 DPRINTF(("tcic_chip_mem_alloc bus addr 0x%lx+0x%lx\n", (u_long) addr, 788 (u_long) size)); 789 790 pcmhp->memt = h->sc->memt; 791 pcmhp->memh = memh; 792 pcmhp->addr = addr; 793 pcmhp->size = size; 794 pcmhp->mhandle = mhandle; 795 pcmhp->realsize = sizepg * TCIC_MEM_PAGESIZE; 796 797 return (0); 798 } 799 800 /* XXX the following routine may need to be rewritten. -chb */ 801 void 802 tcic_chip_mem_free(pch, pcmhp) 803 pcmcia_chipset_handle_t pch; 804 struct pcmcia_mem_handle *pcmhp; 805 { 806 struct tcic_handle *h = (struct tcic_handle *) pch; 807 808 h->sc->subregionmask |= pcmhp->mhandle; 809 } 810 811 void 812 tcic_chip_do_mem_map(h, win) 813 struct tcic_handle *h; 814 int win; 815 { 816 int reg, hwwin, wscnt; 817 818 int kind = h->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 819 int mem8 = (h->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8; 820 DPRINTF(("tcic_chip_do_mem_map window %d: 0x%lx+0x%lx 0x%lx\n", 821 win, (u_long)h->mem[win].addr, (u_long)h->mem[win].size, 822 (u_long)h->mem[win].offset)); 823 /* 824 * the even windows are used for socket 0, 825 * the odd ones for socket 1. 826 */ 827 hwwin = (win << 1) + h->sock; 828 829 /* the WR_MEXT register is MBZ */ 830 tcic_write_ind_2(h, TCIC_WR_MEXT_N(hwwin), 0); 831 832 /* set the host base address and window size */ 833 if (h->mem[win].size2 <= 1) { 834 reg = ((h->mem[win].addr >> TCIC_MEM_SHIFT) & 835 TCIC_MBASE_ADDR_MASK) | TCIC_MBASE_4K; 836 } else { 837 reg = ((h->mem[win].addr >> TCIC_MEM_SHIFT) & 838 TCIC_MBASE_ADDR_MASK) | (h->mem[win].size2 >> 1); 839 } 840 tcic_write_ind_2(h, TCIC_WR_MBASE_N(hwwin), reg); 841 842 /* set the card address and address space */ 843 reg = 0; 844 reg = ((h->mem[win].offset >> TCIC_MEM_SHIFT) & TCIC_MMAP_ADDR_MASK); 845 reg |= (kind == PCMCIA_MEM_ATTR) ? TCIC_MMAP_ATTR : 0; 846 DPRINTF(("tcic_chip_do_map_mem window %d(%d) mmap 0x%04x\n", 847 win, hwwin, reg)); 848 tcic_write_ind_2(h, TCIC_WR_MMAP_N(hwwin), reg); 849 850 /* set the MCTL register */ 851 /* must save WSCNT field in case this is a DB86082 rev 0 */ 852 /* XXX why can't I do the following two in one statement? */ 853 reg = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin)) & TCIC_MCTL_WSCNT_MASK; 854 reg |= TCIC_MCTL_ENA|TCIC_MCTL_QUIET; 855 reg |= mem8 ? TCIC_MCTL_B8 : 0; 856 reg |= (h->sock << TCIC_MCTL_SS_SHIFT) & TCIC_MCTL_SS_MASK; 857 #ifdef notyet /* XXX must get speed from CIS somehow. -chb */ 858 wscnt = tcic_ns2wscnt(h->mem[win].speed); 859 #else 860 wscnt = tcic_ns2wscnt(tcic_mem_speed); /* 300 is "save" default for CIS memory */ 861 #endif 862 if (h->sc->chipid == TCIC_CHIPID_DB86082_1) { 863 /* 864 * this chip has the wait state count in window 865 * register 7 - hwwin. 866 */ 867 int reg2; 868 reg2 = tcic_read_ind_2(h, TCIC_WR_MCTL_N(7-hwwin)); 869 reg2 &= ~TCIC_MCTL_WSCNT_MASK; 870 reg2 |= wscnt & TCIC_MCTL_WSCNT_MASK; 871 tcic_write_ind_2(h, TCIC_WR_MCTL_N(7-hwwin), reg2); 872 } else { 873 reg |= wscnt & TCIC_MCTL_WSCNT_MASK; 874 } 875 tcic_write_ind_2(h, TCIC_WR_MCTL_N(hwwin), reg); 876 877 #ifdef TCICDEBUG 878 { 879 int r1, r2, r3; 880 881 r1 = tcic_read_ind_2(h, TCIC_WR_MBASE_N(hwwin)); 882 r2 = tcic_read_ind_2(h, TCIC_WR_MMAP_N(hwwin)); 883 r3 = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin)); 884 885 DPRINTF(("tcic_chip_do_mem_map window %d(%d): %04x %04x %04x\n", 886 win, hwwin, r1, r2, r3)); 887 } 888 #endif 889 } 890 891 /* XXX needs work */ 892 int 893 tcic_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 894 pcmcia_chipset_handle_t pch; 895 int kind; 896 bus_addr_t card_addr; 897 bus_size_t size; 898 struct pcmcia_mem_handle *pcmhp; 899 bus_size_t *offsetp; 900 int *windowp; 901 { 902 struct tcic_handle *h = (struct tcic_handle *) pch; 903 bus_addr_t busaddr; 904 long card_offset; 905 int i, win; 906 907 win = -1; 908 for (i = 0; i < h->memwins; i++) { 909 if ((h->memalloc & (1 << i)) == 0) { 910 win = i; 911 h->memalloc |= (1 << i); 912 break; 913 } 914 } 915 916 if (win == -1) 917 return (1); 918 919 *windowp = win; 920 921 /* XXX this is pretty gross */ 922 923 if (h->sc->memt != pcmhp->memt) 924 panic("tcic_chip_mem_map memt is bogus"); 925 926 busaddr = pcmhp->addr; 927 928 /* 929 * compute the address offset to the pcmcia address space for the 930 * tcic. this is intentionally signed. The masks and shifts below 931 * will cause TRT to happen in the tcic registers. Deal with making 932 * sure the address is aligned, and return the alignment offset. 933 */ 934 935 *offsetp = card_addr % TCIC_MEM_ALIGN; 936 card_addr -= *offsetp; 937 938 DPRINTF(("tcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 939 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 940 (u_long) card_addr)); 941 942 /* XXX we can't use size. -chb */ 943 /* 944 * include the offset in the size, and decrement size by one, since 945 * the hw wants start/stop 946 */ 947 size += *offsetp - 1; 948 949 card_offset = (((long) card_addr) - ((long) busaddr)); 950 951 DPRINTF(("tcic_chip_mem_map window %d card_offset 0x%lx\n", 952 win, (u_long)card_offset)); 953 954 h->mem[win].addr = busaddr; 955 h->mem[win].size = size; 956 h->mem[win].size2 = tcic_log2((u_int)pcmhp->realsize) - TCIC_MEM_SHIFT; 957 h->mem[win].offset = card_offset; 958 h->mem[win].kind = kind; 959 960 tcic_chip_do_mem_map(h, win); 961 962 return (0); 963 } 964 965 void 966 tcic_chip_mem_unmap(pch, window) 967 pcmcia_chipset_handle_t pch; 968 int window; 969 { 970 struct tcic_handle *h = (struct tcic_handle *) pch; 971 int hwwin; 972 973 if (window >= h->memwins) 974 panic("tcic_chip_mem_unmap: window out of range"); 975 976 hwwin = (window << 1) + h->sock; 977 tcic_write_ind_2(h, TCIC_WR_MCTL_N(hwwin), 0); 978 979 h->memalloc &= ~(1 << window); 980 } 981 982 int 983 tcic_chip_io_alloc(pch, start, size, align, pcihp) 984 pcmcia_chipset_handle_t pch; 985 bus_addr_t start; 986 bus_size_t size; 987 bus_size_t align; 988 struct pcmcia_io_handle *pcihp; 989 { 990 struct tcic_handle *h = (struct tcic_handle *) pch; 991 bus_space_tag_t iot; 992 bus_space_handle_t ioh; 993 bus_addr_t ioaddr; 994 int size2, flags = 0; 995 996 /* 997 * Allocate some arbitrary I/O space. 998 */ 999 1000 DPRINTF(("tcic_chip_io_alloc req 0x%lx %ld %ld\n", 1001 (u_long) start, (u_long) size, (u_long) align)); 1002 /* 1003 * The TCIC can map I/O space only in sizes that are 1004 * powers of two, aligned at the natural boundary for the size. 1005 */ 1006 size2 = tcic_log2((u_int)size); 1007 if ((1 << size2) < size) 1008 size2++; 1009 /* can't allocate that much anyway */ 1010 if (size2 > 16) /* XXX 64K -chb */ 1011 return 1; 1012 if (align) { 1013 if ((1 << size2) != align) 1014 return 1; /* not suitably aligned */ 1015 } else { 1016 align = 1 << size2; /* no alignment given, make it natural */ 1017 } 1018 if (start & (align - 1)) 1019 return 1; /* not suitably aligned */ 1020 1021 iot = h->sc->iot; 1022 1023 if (start) { 1024 ioaddr = start; 1025 if (bus_space_map(iot, start, size, 0, &ioh)) 1026 return (1); 1027 DPRINTF(("tcic_chip_io_alloc map port %lx+%lx\n", 1028 (u_long) ioaddr, (u_long) size)); 1029 } else { 1030 flags |= PCMCIA_IO_ALLOCATED; 1031 if (bus_space_alloc(iot, h->sc->iobase, 1032 h->sc->iobase + h->sc->iosize, size, align, 0, 0, 1033 &ioaddr, &ioh)) 1034 return (1); 1035 DPRINTF(("tcic_chip_io_alloc alloc port %lx+%lx\n", 1036 (u_long) ioaddr, (u_long) size)); 1037 } 1038 1039 pcihp->iot = iot; 1040 pcihp->ioh = ioh; 1041 pcihp->addr = ioaddr; 1042 pcihp->size = size; 1043 pcihp->flags = flags; 1044 1045 return (0); 1046 } 1047 1048 void 1049 tcic_chip_io_free(pch, pcihp) 1050 pcmcia_chipset_handle_t pch; 1051 struct pcmcia_io_handle *pcihp; 1052 { 1053 bus_space_tag_t iot = pcihp->iot; 1054 bus_space_handle_t ioh = pcihp->ioh; 1055 bus_size_t size = pcihp->size; 1056 1057 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1058 bus_space_free(iot, ioh, size); 1059 else 1060 bus_space_unmap(iot, ioh, size); 1061 } 1062 1063 static int tcic_iowidth_map[] = 1064 { TCIC_ICTL_AUTOSZ, TCIC_ICTL_B8, TCIC_ICTL_B16 }; 1065 1066 void 1067 tcic_chip_do_io_map(h, win) 1068 struct tcic_handle *h; 1069 int win; 1070 { 1071 int reg, size2, iotiny, wbase, hwwin, wscnt; 1072 1073 DPRINTF(("tcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 1074 win, (long) h->io[win].addr, (long) h->io[win].size, 1075 h->io[win].width * 8)); 1076 1077 /* 1078 * the even windows are used for socket 0, 1079 * the odd ones for socket 1. 1080 */ 1081 hwwin = (win << 1) + h->sock; 1082 1083 /* set the WR_BASE register */ 1084 /* XXX what if size isn't power of 2? -chb */ 1085 size2 = tcic_log2((u_int)h->io[win].size); 1086 DPRINTF(("tcic_chip_do_io_map win %d size2 %d\n", win, size2)); 1087 if (size2 < 1) { 1088 iotiny = TCIC_ICTL_TINY; 1089 wbase = h->io[win].addr; 1090 } else { 1091 iotiny = 0; 1092 /* XXX we should do better -chb */ 1093 wbase = h->io[win].addr | (1 << (size2 - 1)); 1094 } 1095 tcic_write_ind_2(h, TCIC_WR_IBASE_N(hwwin), wbase); 1096 1097 /* set the WR_ICTL register */ 1098 reg = TCIC_ICTL_ENA | TCIC_ICTL_QUIET; 1099 reg |= (h->sock << TCIC_ICTL_SS_SHIFT) & TCIC_ICTL_SS_MASK; 1100 reg |= iotiny | tcic_iowidth_map[h->io[win].width]; 1101 if (h->sc->chipid != TCIC_CHIPID_DB86082_1) 1102 reg |= TCIC_ICTL_PASS16; 1103 #ifdef notyet /* XXX must get speed from CIS somehow. -chb */ 1104 wscnt = tcic_ns2wscnt(h->io[win].speed); 1105 #else 1106 wscnt = tcic_ns2wscnt(tcic_io_speed); /* linux uses 0 as default */ 1107 #endif 1108 reg |= wscnt & TCIC_ICTL_WSCNT_MASK; 1109 tcic_write_ind_2(h, TCIC_WR_ICTL_N(hwwin), reg); 1110 1111 #ifdef TCICDEBUG 1112 { 1113 int r1, r2; 1114 1115 r1 = tcic_read_ind_2(h, TCIC_WR_IBASE_N(hwwin)); 1116 r2 = tcic_read_ind_2(h, TCIC_WR_ICTL_N(hwwin)); 1117 1118 DPRINTF(("tcic_chip_do_io_map window %d(%d): %04x %04x\n", 1119 win, hwwin, r1, r2)); 1120 } 1121 #endif 1122 } 1123 1124 int 1125 tcic_chip_io_map(pch, width, offset, size, pcihp, windowp) 1126 pcmcia_chipset_handle_t pch; 1127 int width; 1128 bus_addr_t offset; 1129 bus_size_t size; 1130 struct pcmcia_io_handle *pcihp; 1131 int *windowp; 1132 { 1133 struct tcic_handle *h = (struct tcic_handle *) pch; 1134 bus_addr_t ioaddr = pcihp->addr + offset; 1135 int i, win; 1136 #ifdef TCICDEBUG 1137 static char *width_names[] = { "auto", "io8", "io16" }; 1138 #endif 1139 1140 /* XXX Sanity check offset/size. */ 1141 1142 win = -1; 1143 for (i = 0; i < TCIC_IO_WINS; i++) { 1144 if ((h->ioalloc & (1 << i)) == 0) { 1145 win = i; 1146 h->ioalloc |= (1 << i); 1147 break; 1148 } 1149 } 1150 1151 if (win == -1) 1152 return (1); 1153 1154 *windowp = win; 1155 1156 /* XXX this is pretty gross */ 1157 1158 if (h->sc->iot != pcihp->iot) 1159 panic("tcic_chip_io_map iot is bogus"); 1160 1161 DPRINTF(("tcic_chip_io_map window %d %s port %lx+%lx\n", 1162 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1163 1164 /* XXX wtf is this doing here? */ 1165 1166 printf("%s: port 0x%lx", h->sc->dev.dv_xname, (u_long) ioaddr); 1167 if (size > 1) 1168 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1169 printf("\n"); 1170 1171 h->io[win].addr = ioaddr; 1172 h->io[win].size = size; 1173 h->io[win].width = width; 1174 1175 tcic_chip_do_io_map(h, win); 1176 1177 return (0); 1178 } 1179 1180 void 1181 tcic_chip_io_unmap(pch, window) 1182 pcmcia_chipset_handle_t pch; 1183 int window; 1184 { 1185 struct tcic_handle *h = (struct tcic_handle *) pch; 1186 int hwwin; 1187 1188 if (window >= TCIC_IO_WINS) 1189 panic("tcic_chip_io_unmap: window out of range"); 1190 1191 hwwin = (window << 1) + h->sock; 1192 tcic_write_ind_2(h, TCIC_WR_ICTL_N(hwwin), 0); 1193 1194 h->ioalloc &= ~(1 << window); 1195 } 1196 1197 void 1198 tcic_chip_socket_enable(pch) 1199 pcmcia_chipset_handle_t pch; 1200 { 1201 struct tcic_handle *h = (struct tcic_handle *) pch; 1202 int reg, win; 1203 1204 tcic_sel_sock(h); 1205 1206 /* 1207 * power down the socket to reset it. 1208 * put card reset into high-z, put chip outputs to card into high-z 1209 */ 1210 1211 tcic_write_1(h, TCIC_R_PWR, 0); 1212 reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1213 reg |= TCIC_ILOCK_CWAIT; 1214 reg &= ~(TCIC_ILOCK_CRESET|TCIC_ILOCK_CRESENA); 1215 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1216 tcic_write_1(h, TCIC_R_SCTRL, 0); /* clear TCIC_SCTRL_ENA */ 1217 1218 /* zero out the address windows */ 1219 1220 tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), 0); 1221 /* writing to WR_MBASE_N disables the window */ 1222 for (win = 0; win < h->memwins; win++) { 1223 tcic_write_ind_2(h, TCIC_WR_MBASE_N((win << 1) + h->sock), 0); 1224 } 1225 /* writing to WR_IBASE_N disables the window */ 1226 for (win = 0; win < TCIC_IO_WINS; win++) { 1227 tcic_write_ind_2(h, TCIC_WR_IBASE_N((win << 1) + h->sock), 0); 1228 } 1229 1230 /* power up the socket */ 1231 1232 /* turn on VCC, turn of VPP */ 1233 reg = TCIC_PWR_VCC_N(h->sock) | TCIC_PWR_VPP_N(h->sock) | h->sc->pwrena; 1234 if (h->sc->pwrena) /* this is a '84 type chip */ 1235 reg |= TCIC_PWR_VCC5V; 1236 tcic_write_1(h, TCIC_R_PWR, reg); 1237 delay(10000); 1238 1239 /* enable reset and wiggle it to reset the card */ 1240 reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1241 reg |= TCIC_ILOCK_CRESENA; 1242 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1243 /* XXX need bus_space_barrier here */ 1244 reg |= TCIC_ILOCK_CRESET; 1245 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1246 /* enable card signals */ 1247 tcic_write_1(h, TCIC_R_SCTRL, TCIC_SCTRL_ENA); 1248 delay(10); /* wait 10 us */ 1249 1250 /* clear the reset flag */ 1251 reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1252 reg &= ~(TCIC_ILOCK_CRESET); 1253 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1254 1255 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1256 delay(20000); 1257 1258 /* wait for the chip to finish initializing */ 1259 tcic_wait_ready(h); 1260 1261 /* WWW */ 1262 1263 /* reinstall all the memory and io mappings */ 1264 1265 for (win = 0; win < h->memwins; win++) 1266 if (h->memalloc & (1 << win)) 1267 tcic_chip_do_mem_map(h, win); 1268 1269 for (win = 0; win < TCIC_IO_WINS; win++) 1270 if (h->ioalloc & (1 << win)) 1271 tcic_chip_do_io_map(h, win); 1272 } 1273 1274 void 1275 tcic_chip_socket_settype(pch, type) 1276 pcmcia_chipset_handle_t pch; 1277 int type; 1278 { 1279 struct tcic_handle *h = (struct tcic_handle *) pch; 1280 int reg; 1281 1282 tcic_sel_sock(h); 1283 1284 /* set the card type */ 1285 1286 reg = 0; 1287 if (type == PCMCIA_IFTYPE_IO) { 1288 reg |= TCIC_SCF1_IOSTS; 1289 reg |= tcic_irqmap[h->ih_irq]; /* enable interrupts */ 1290 } 1291 tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), reg); 1292 1293 DPRINTF(("%s: tcic_chip_socket_enable %d cardtype %s 0x%02x\n", 1294 h->sc->dev.dv_xname, h->sock, 1295 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg)); 1296 } 1297 1298 void 1299 tcic_chip_socket_disable(pch) 1300 pcmcia_chipset_handle_t pch; 1301 { 1302 struct tcic_handle *h = (struct tcic_handle *) pch; 1303 int val; 1304 1305 DPRINTF(("tcic_chip_socket_disable\n")); 1306 1307 tcic_sel_sock(h); 1308 1309 /* disable interrupts */ 1310 val = tcic_read_ind_2(h, TCIC_IR_SCF1_N(h->sock)); 1311 val &= TCIC_SCF1_IRQ_MASK; 1312 tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), val); 1313 1314 /* disable the output signals */ 1315 tcic_write_1(h, TCIC_R_SCTRL, 0); 1316 val = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1317 val &= ~TCIC_ILOCK_CRESENA; 1318 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, val); 1319 1320 /* power down the socket */ 1321 tcic_write_1(h, TCIC_R_PWR, 0); 1322 } 1323 1324 /* 1325 * XXX The following is Linux driver but doesn't match the table 1326 * in the manual. 1327 */ 1328 int 1329 tcic_ns2wscnt(ns) 1330 int ns; 1331 { 1332 if (ns < 14) { 1333 return 0; 1334 } else { 1335 return (2*(ns-14))/70; /* XXX assumes 14.31818 MHz clock. */ 1336 } 1337 } 1338 1339 int 1340 tcic_log2(val) 1341 u_int val; 1342 { 1343 int i, l2; 1344 1345 l2 = i = 0; 1346 while (val) { 1347 if (val & 1) 1348 l2 = i; 1349 i++; 1350 val >>= 1; 1351 } 1352 return l2; 1353 } 1354