1 /* $NetBSD: tcic2.c,v 1.38 2012/10/27 17:18:22 chs Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 Christoph Badura. All rights reserved. 5 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Marc Horowitz. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: tcic2.c,v 1.38 2012/10/27 17:18:22 chs Exp $"); 35 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/device.h> 39 #include <sys/extent.h> 40 #include <sys/malloc.h> 41 #include <sys/kthread.h> 42 43 #include <sys/bus.h> 44 #include <sys/intr.h> 45 46 #include <dev/pcmcia/pcmciareg.h> 47 #include <dev/pcmcia/pcmciavar.h> 48 49 #include <dev/ic/tcic2reg.h> 50 #include <dev/ic/tcic2var.h> 51 52 #include "locators.h" 53 54 #ifdef TCICDEBUG 55 int tcic_debug = 1; 56 #define DPRINTF(arg) if (tcic_debug) printf arg; 57 #else 58 #define DPRINTF(arg) 59 #endif 60 61 /* 62 * Individual drivers will allocate their own memory and io regions. Memory 63 * regions must be a multiple of 4k, aligned on a 4k boundary. 64 */ 65 66 #define TCIC_MEM_ALIGN TCIC_MEM_PAGESIZE 67 68 void tcic_attach_socket(struct tcic_handle *); 69 void tcic_init_socket(struct tcic_handle *); 70 71 int tcic_print(void *arg, const char *pnp); 72 int tcic_intr_socket(struct tcic_handle *); 73 74 void tcic_attach_card(struct tcic_handle *); 75 void tcic_detach_card(struct tcic_handle *, int); 76 void tcic_deactivate_card(struct tcic_handle *); 77 78 void tcic_chip_do_mem_map(struct tcic_handle *, int); 79 void tcic_chip_do_io_map(struct tcic_handle *, int); 80 81 void tcic_create_event_thread(void *); 82 void tcic_event_thread(void *); 83 84 void tcic_queue_event(struct tcic_handle *, int); 85 86 /* Map between irq numbers and internal representation */ 87 #if 1 88 int tcic_irqmap[] = 89 { 0, 0, 0, 3, 4, 5, 6, 7, 0, 0, 10, 1, 0, 0, 14, 0 }; 90 int tcic_valid_irqs = 0x4cf8; 91 #else 92 int tcic_irqmap[] = /* irqs 9 and 6 switched, some ISA cards */ 93 { 0, 0, 0, 3, 4, 5, 0, 7, 0, 6, 10, 1, 0, 0, 14, 0 }; 94 int tcic_valid_irqs = 0x4eb8; 95 #endif 96 97 int tcic_mem_speed = 250; /* memory access time in nanoseconds */ 98 int tcic_io_speed = 165; /* io access time in nanoseconds */ 99 100 /* 101 * Check various reserved and otherwise in their value restricted bits. 102 */ 103 int 104 tcic_check_reserved_bits(bus_space_tag_t iot, bus_space_handle_t ioh) 105 { 106 int val, auxreg; 107 108 DPRINTF(("tcic: chkrsvd 1\n")); 109 /* R_ADDR bit 30:28 have a restricted range. */ 110 val = (bus_space_read_2(iot, ioh, TCIC_R_ADDR2) & TCIC_SS_MASK) 111 >> TCIC_SS_SHIFT; 112 if (val > 1) 113 return 0; 114 115 DPRINTF(("tcic: chkrsvd 2\n")); 116 /* R_SCTRL bits 6,2,1 are reserved. */ 117 val = bus_space_read_1(iot, ioh, TCIC_R_SCTRL); 118 if (val & TCIC_SCTRL_RSVD) 119 return 0; 120 121 DPRINTF(("tcic: chkrsvd 3\n")); 122 /* R_ICSR bit 2 must be same as bit 3. */ 123 val = bus_space_read_1(iot, ioh, TCIC_R_ICSR); 124 if (((val >> 1) & 1) != ((val >> 2) & 1)) 125 return 0; 126 127 DPRINTF(("tcic: chkrsvd 4\n")); 128 /* R_IENA bits 7,2 are reserved. */ 129 val = bus_space_read_1(iot, ioh, TCIC_R_IENA); 130 if (val & TCIC_IENA_RSVD) 131 return 0; 132 133 DPRINTF(("tcic: chkrsvd 5\n")); 134 /* Some aux registers have reserved bits. */ 135 /* Which are we looking at? */ 136 auxreg = bus_space_read_1(iot, ioh, TCIC_R_MODE) 137 & TCIC_AR_MASK; 138 val = bus_space_read_2(iot, ioh, TCIC_R_AUX); 139 DPRINTF(("tcic: auxreg 0x%02x val 0x%04x\n", auxreg, val)); 140 switch (auxreg) { 141 case TCIC_AR_SYSCFG: 142 if (INVALID_AR_SYSCFG(val)) 143 return 0; 144 break; 145 case TCIC_AR_ILOCK: 146 if (INVALID_AR_ILOCK(val)) 147 return 0; 148 break; 149 case TCIC_AR_TEST: 150 if (INVALID_AR_TEST(val)) 151 return 0; 152 break; 153 } 154 155 DPRINTF(("tcic: chkrsvd 6\n")); 156 /* XXX fails if pcmcia bios is enabled. */ 157 /* Various bits set or not depending if in RESET mode. */ 158 val = bus_space_read_1(iot, ioh, TCIC_R_SCTRL); 159 if (val & TCIC_SCTRL_RESET) { 160 DPRINTF(("tcic: chkrsvd 7\n")); 161 /* Address bits must be 0 */ 162 val = bus_space_read_2(iot, ioh, TCIC_R_ADDR); 163 if (val != 0) 164 return 0; 165 val = bus_space_read_2(iot, ioh, TCIC_R_ADDR2); 166 if (val != 0) 167 return 0; 168 DPRINTF(("tcic: chkrsvd 8\n")); 169 /* EDC bits must be 0 */ 170 val = bus_space_read_2(iot, ioh, TCIC_R_EDC); 171 if (val != 0) 172 return 0; 173 /* We're OK, so take it out of reset. XXX -chb */ 174 bus_space_write_1(iot, ioh, TCIC_R_SCTRL, 0); 175 } 176 else { /* not in RESET mode */ 177 int omode; 178 int val1, val2; 179 DPRINTF(("tcic: chkrsvd 9\n")); 180 /* Programming timers must have expired. */ 181 val = bus_space_read_1(iot, ioh, TCIC_R_SSTAT); 182 if ((val & (TCIC_SSTAT_6US|TCIC_SSTAT_10US|TCIC_SSTAT_PROGTIME)) 183 != (TCIC_SSTAT_6US|TCIC_SSTAT_10US|TCIC_SSTAT_PROGTIME)) 184 return 0; 185 DPRINTF(("tcic: chkrsvd 10\n")); 186 /* 187 * EDC bits should change on read from data space 188 * as long as either EDC or the data are nonzero. 189 */ 190 if ((bus_space_read_2(iot, ioh, TCIC_R_ADDR2) 191 & TCIC_ADDR2_INDREG) != 0) { 192 val1 = bus_space_read_2(iot, ioh, TCIC_R_EDC); 193 val2 = bus_space_read_2(iot, ioh, TCIC_R_DATA); 194 if (val1 | val2) { 195 val1 = bus_space_read_2(iot, ioh, TCIC_R_EDC); 196 if (val1 == val2) 197 return 0; 198 } 199 } 200 DPRINTF(("tcic: chkrsvd 11\n")); 201 /* XXX what does this check? -chb */ 202 omode = bus_space_read_1(iot, ioh, TCIC_R_MODE); 203 val1 = omode ^ TCIC_AR_MASK; 204 bus_space_write_1(iot, ioh, TCIC_R_MODE, val1); 205 val2 = bus_space_read_1(iot, ioh, TCIC_R_MODE); 206 bus_space_write_1(iot, ioh, TCIC_R_MODE, omode); 207 if ( val1 != val2) 208 return 0; 209 } 210 /* All tests passed */ 211 return 1; 212 } 213 214 /* 215 * Read chip ID from AR_ILOCK in test mode. 216 */ 217 int 218 tcic_chipid(bus_space_tag_t iot, bus_space_handle_t ioh) 219 { 220 unsigned id, otest; 221 222 otest = tcic_read_aux_2(iot, ioh, TCIC_AR_TEST); 223 tcic_write_aux_2(iot, ioh, TCIC_AR_TEST, TCIC_TEST_DIAG); 224 id = tcic_read_aux_2(iot, ioh, TCIC_AR_ILOCK); 225 tcic_write_aux_2(iot, ioh, TCIC_AR_TEST, otest); 226 id &= TCIC_ILOCKTEST_ID_MASK; 227 id >>= TCIC_ILOCKTEST_ID_SHFT; 228 229 /* clear up IRQs inside tcic. XXX -chb */ 230 while (bus_space_read_1(iot, ioh, TCIC_R_ICSR)) 231 bus_space_write_1(iot, ioh, TCIC_R_ICSR, TCIC_ICSR_JAM); 232 233 return id; 234 } 235 /* 236 * Indicate whether the driver can handle the chip. 237 */ 238 int 239 tcic_chipid_known(int id) 240 { 241 /* XXX only know how to handle DB86082 -chb */ 242 switch (id) { 243 case TCIC_CHIPID_DB86082_1: 244 case TCIC_CHIPID_DB86082A: 245 case TCIC_CHIPID_DB86082B_ES: 246 case TCIC_CHIPID_DB86082B: 247 case TCIC_CHIPID_DB86084_1: 248 case TCIC_CHIPID_DB86084A: 249 case TCIC_CHIPID_DB86184_1: 250 case TCIC_CHIPID_DB86072_1_ES: 251 case TCIC_CHIPID_DB86072_1: 252 return 1; 253 } 254 255 return 0; 256 } 257 258 const char * 259 tcic_chipid_to_string(int id) 260 { 261 switch (id) { 262 case TCIC_CHIPID_DB86082_1: 263 return ("Databook DB86082"); 264 case TCIC_CHIPID_DB86082A: 265 return ("Databook DB86082A"); 266 case TCIC_CHIPID_DB86082B_ES: 267 return ("Databook DB86082B-es"); 268 case TCIC_CHIPID_DB86082B: 269 return ("Databook DB86082B"); 270 case TCIC_CHIPID_DB86084_1: 271 return ("Databook DB86084"); 272 case TCIC_CHIPID_DB86084A: 273 return ("Databook DB86084A"); 274 case TCIC_CHIPID_DB86184_1: 275 return ("Databook DB86184"); 276 case TCIC_CHIPID_DB86072_1_ES: 277 return ("Databook DB86072-es"); 278 case TCIC_CHIPID_DB86072_1: 279 return ("Databook DB86072"); 280 } 281 282 return ("Unknown controller"); 283 } 284 /* 285 * Return bitmask of IRQs that the chip can handle. 286 * XXX should be table driven. 287 */ 288 int 289 tcic_validirqs(int chipid) 290 { 291 switch (chipid) { 292 case TCIC_CHIPID_DB86082_1: 293 case TCIC_CHIPID_DB86082A: 294 case TCIC_CHIPID_DB86082B_ES: 295 case TCIC_CHIPID_DB86082B: 296 case TCIC_CHIPID_DB86084_1: 297 case TCIC_CHIPID_DB86084A: 298 case TCIC_CHIPID_DB86184_1: 299 case TCIC_CHIPID_DB86072_1_ES: 300 case TCIC_CHIPID_DB86072_1: 301 return tcic_valid_irqs; 302 } 303 return 0; 304 } 305 306 void 307 tcic_attach(struct tcic_softc *sc) 308 { 309 int i, reg; 310 311 /* set more chipset dependent parameters in the softc. */ 312 switch (sc->chipid) { 313 case TCIC_CHIPID_DB86084_1: 314 case TCIC_CHIPID_DB86084A: 315 case TCIC_CHIPID_DB86184_1: 316 sc->pwrena = TCIC_PWR_ENA; 317 break; 318 default: 319 sc->pwrena = 0; 320 break; 321 } 322 323 /* set up global config registers */ 324 reg = TCIC_WAIT_SYNC | TCIC_WAIT_CCLK | TCIC_WAIT_RISING; 325 reg |= (tcic_ns2wscnt(250) & TCIC_WAIT_COUNT_MASK); 326 tcic_write_aux_1(sc->iot, sc->ioh, TCIC_AR_WCTL, TCIC_R_WCTL_WAIT, reg); 327 reg = TCIC_SYSCFG_MPSEL_RI | TCIC_SYSCFG_MCSFULL; 328 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, reg); 329 reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_ILOCK); 330 reg |= TCIC_ILOCK_HOLD_CCLK; 331 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_ILOCK, reg); 332 333 /* the TCIC has two sockets */ 334 /* XXX should i check for actual presence of sockets? -chb */ 335 for (i = 0; i < TCIC_NSLOTS; i++) { 336 sc->handle[i].sc = sc; 337 sc->handle[i].sock = i; 338 sc->handle[i].flags = TCIC_FLAG_SOCKETP; 339 sc->handle[i].memwins 340 = sc->chipid == TCIC_CHIPID_DB86082_1 ? 4 : 5; 341 } 342 343 /* establish the interrupt */ 344 reg = tcic_read_1(&sc->handle[0], TCIC_R_IENA); 345 tcic_write_1(&sc->handle[0], TCIC_R_IENA, 346 (reg & ~TCIC_IENA_CFG_MASK) | TCIC_IENA_CFG_HIGH); 347 reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG); 348 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, 349 (reg & ~TCIC_SYSCFG_IRQ_MASK) | tcic_irqmap[sc->irq]); 350 351 /* XXX block interrupts? */ 352 353 for (i = 0; i < TCIC_NSLOTS; i++) { 354 /* XXX make more clear what happens here -chb */ 355 tcic_sel_sock(&sc->handle[i]); 356 tcic_write_ind_2(&sc->handle[i], TCIC_IR_SCF1_N(i), 0); 357 tcic_write_ind_2(&sc->handle[i], TCIC_IR_SCF2_N(i), 358 (TCIC_SCF2_MCD|TCIC_SCF2_MWP|TCIC_SCF2_MRDY 359 #if 1 /* XXX explain byte routing issue */ 360 |TCIC_SCF2_MLBAT2|TCIC_SCF2_MLBAT1|TCIC_SCF2_IDBR)); 361 #else 362 |TCIC_SCF2_MLBAT2|TCIC_SCF2_MLBAT1)); 363 #endif 364 tcic_write_1(&sc->handle[i], TCIC_R_MODE, 0); 365 reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG); 366 reg &= ~TCIC_SYSCFG_AUTOBUSY; 367 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, reg); 368 SIMPLEQ_INIT(&sc->handle[i].events); 369 } 370 371 if ((sc->handle[0].flags & TCIC_FLAG_SOCKETP) || 372 (sc->handle[1].flags & TCIC_FLAG_SOCKETP)) { 373 printf("%s: %s has ", device_xname(sc->sc_dev), 374 tcic_chipid_to_string(sc->chipid)); 375 376 if ((sc->handle[0].flags & TCIC_FLAG_SOCKETP) && 377 (sc->handle[1].flags & TCIC_FLAG_SOCKETP)) 378 printf("sockets A and B\n"); 379 else if (sc->handle[0].flags & TCIC_FLAG_SOCKETP) 380 printf("socket A only\n"); 381 else 382 printf("socket B only\n"); 383 384 } 385 } 386 387 void 388 tcic_attach_sockets(struct tcic_softc *sc) 389 { 390 int i; 391 392 for (i = 0; i < TCIC_NSLOTS; i++) 393 if (sc->handle[i].flags & TCIC_FLAG_SOCKETP) 394 tcic_attach_socket(&sc->handle[i]); 395 } 396 397 void 398 tcic_attach_socket(struct tcic_handle *h) 399 { 400 struct pcmciabus_attach_args paa; 401 int locs[PCMCIABUSCF_NLOCS]; 402 403 /* initialize the rest of the handle */ 404 405 h->shutdown = 0; 406 h->memalloc = 0; 407 h->ioalloc = 0; 408 h->ih_irq = 0; 409 410 /* now, config one pcmcia device per socket */ 411 412 paa.paa_busname = "pcmcia"; 413 paa.pct = (pcmcia_chipset_tag_t) h->sc->pct; 414 paa.pch = (pcmcia_chipset_handle_t) h; 415 416 locs[PCMCIABUSCF_CONTROLLER] = 0; 417 locs[PCMCIABUSCF_SOCKET] = h->sock; 418 419 h->pcmcia = config_found_sm_loc(h->sc->sc_dev, "pcmciabus", locs, &paa, 420 tcic_print, config_stdsubmatch); 421 422 /* if there's actually a pcmcia device attached, initialize the slot */ 423 424 if (h->pcmcia) 425 tcic_init_socket(h); 426 } 427 428 void 429 tcic_create_event_thread(void *arg) 430 { 431 struct tcic_handle *h = arg; 432 const char *cs; 433 434 switch (h->sock) { 435 case 0: 436 cs = "0"; 437 break; 438 case 1: 439 cs = "1"; 440 break; 441 default: 442 panic("tcic_create_event_thread: unknown tcic socket"); 443 } 444 445 if (kthread_create(PRI_NONE, 0, NULL, tcic_event_thread, h, 446 &h->event_thread, "%s,%s", device_xname(h->sc->sc_dev), cs)) { 447 aprint_error_dev(h->sc->sc_dev, "unable to create event thread for sock 0x%02x\n", h->sock); 448 panic("tcic_create_event_thread"); 449 } 450 } 451 452 void 453 tcic_event_thread(void *arg) 454 { 455 struct tcic_handle *h = arg; 456 struct tcic_event *pe; 457 int s; 458 459 while (h->shutdown == 0) { 460 s = splhigh(); 461 if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) { 462 splx(s); 463 (void) tsleep(&h->events, PWAIT, "tcicev", 0); 464 continue; 465 } 466 SIMPLEQ_REMOVE_HEAD(&h->events, pe_q); 467 splx(s); 468 469 switch (pe->pe_type) { 470 case TCIC_EVENT_INSERTION: 471 DPRINTF(("%s: insertion event\n", device_xname(h->sc->sc_dev))); 472 tcic_attach_card(h); 473 break; 474 475 case TCIC_EVENT_REMOVAL: 476 DPRINTF(("%s: removal event\n", device_xname(h->sc->sc_dev))); 477 tcic_detach_card(h, DETACH_FORCE); 478 break; 479 480 default: 481 panic("tcic_event_thread: unknown event %d", 482 pe->pe_type); 483 } 484 free(pe, M_TEMP); 485 } 486 487 h->event_thread = NULL; 488 489 /* In case parent is waiting for us to exit. */ 490 wakeup(h->sc); 491 492 kthread_exit(0); 493 } 494 495 496 void 497 tcic_init_socket(struct tcic_handle *h) 498 { 499 int reg; 500 501 /* select this socket's config registers */ 502 tcic_sel_sock(h); 503 504 /* set up the socket to interrupt on card detect */ 505 reg = tcic_read_ind_2(h, TCIC_IR_SCF2_N(h->sock)); 506 tcic_write_ind_2(h, TCIC_IR_SCF2_N(h->sock), reg & ~TCIC_SCF2_MCD); 507 508 /* enable CD irq in R_IENA */ 509 reg = tcic_read_2(h, TCIC_R_IENA); 510 tcic_write_2(h, TCIC_R_IENA, reg |= TCIC_IENA_CDCHG); 511 512 /* if there's a card there, then attach it. also save sstat */ 513 h->sstat = reg = tcic_read_1(h, TCIC_R_SSTAT) & TCIC_SSTAT_STAT_MASK; 514 if (reg & TCIC_SSTAT_CD) 515 tcic_attach_card(h); 516 } 517 518 int 519 tcic_print(void *arg, const char *pnp) 520 { 521 struct pcmciabus_attach_args *paa = arg; 522 struct tcic_handle *h = (struct tcic_handle *) paa->pch; 523 524 /* Only "pcmcia"s can attach to "tcic"s... easy. */ 525 if (pnp) 526 aprint_normal("pcmcia at %s", pnp); 527 528 aprint_normal(" socket %d", h->sock); 529 530 return (UNCONF); 531 } 532 533 int 534 tcic_intr(void *arg) 535 { 536 struct tcic_softc *sc = arg; 537 int i, ret = 0; 538 539 DPRINTF(("%s: intr\n", device_xname(sc->sc_dev))); 540 541 for (i = 0; i < TCIC_NSLOTS; i++) 542 if (sc->handle[i].flags & TCIC_FLAG_SOCKETP) 543 ret += tcic_intr_socket(&sc->handle[i]); 544 545 return (ret ? 1 : 0); 546 } 547 548 int 549 tcic_intr_socket(struct tcic_handle *h) 550 { 551 int icsr, rv; 552 553 rv = 0; 554 tcic_sel_sock(h); 555 icsr = tcic_read_1(h, TCIC_R_ICSR); 556 557 DPRINTF(("%s: %d icsr: 0x%02x \n", device_xname(h->sc->sc_dev), h->sock, icsr)); 558 559 /* XXX or should the next three be handled in tcic_intr? -chb */ 560 if (icsr & TCIC_ICSR_PROGTIME) { 561 DPRINTF(("%s: %02x PROGTIME\n", device_xname(h->sc->sc_dev), h->sock)); 562 rv = 1; 563 } 564 if (icsr & TCIC_ICSR_ILOCK) { 565 DPRINTF(("%s: %02x ILOCK\n", device_xname(h->sc->sc_dev), h->sock)); 566 rv = 1; 567 } 568 if (icsr & TCIC_ICSR_ERR) { 569 DPRINTF(("%s: %02x ERR\n", device_xname(h->sc->sc_dev), h->sock)); 570 rv = 1; 571 } 572 if (icsr & TCIC_ICSR_CDCHG) { 573 int sstat, delta; 574 575 /* compute what changed since last interrupt */ 576 sstat = tcic_read_aux_1(h->sc->iot, h->sc->ioh, 577 TCIC_AR_WCTL, TCIC_R_WCTL_XCSR) & TCIC_XCSR_STAT_MASK; 578 delta = h->sstat ^ sstat; 579 h->sstat = sstat; 580 581 if (delta) 582 rv = 1; 583 584 DPRINTF(("%s: %02x CDCHG %x\n", device_xname(h->sc->sc_dev), h->sock, 585 delta)); 586 587 /* 588 * XXX This should probably schedule something to happen 589 * after the interrupt handler completes 590 */ 591 592 if (delta & TCIC_SSTAT_CD) { 593 if (sstat & TCIC_SSTAT_CD) { 594 if (!(h->flags & TCIC_FLAG_CARDP)) { 595 DPRINTF(("%s: enqueing INSERTION event\n", 596 device_xname(h->sc->sc_dev))); 597 tcic_queue_event(h, TCIC_EVENT_INSERTION); 598 } 599 } else { 600 if (h->flags & TCIC_FLAG_CARDP) { 601 /* Deactivate the card now. */ 602 DPRINTF(("%s: deactivating card\n", 603 device_xname(h->sc->sc_dev))); 604 tcic_deactivate_card(h); 605 606 DPRINTF(("%s: enqueing REMOVAL event\n", 607 device_xname(h->sc->sc_dev))); 608 tcic_queue_event(h, TCIC_EVENT_REMOVAL); 609 } 610 } 611 } 612 if (delta & TCIC_SSTAT_RDY) { 613 DPRINTF(("%s: %02x READY\n", device_xname(h->sc->sc_dev), h->sock)); 614 /* shouldn't happen */ 615 } 616 if (delta & TCIC_SSTAT_LBAT1) { 617 DPRINTF(("%s: %02x LBAT1\n", device_xname(h->sc->sc_dev), h->sock)); 618 } 619 if (delta & TCIC_SSTAT_LBAT2) { 620 DPRINTF(("%s: %02x LBAT2\n", device_xname(h->sc->sc_dev), h->sock)); 621 } 622 if (delta & TCIC_SSTAT_WP) { 623 DPRINTF(("%s: %02x WP\n", device_xname(h->sc->sc_dev), h->sock)); 624 } 625 } 626 return rv; 627 } 628 629 void 630 tcic_queue_event(struct tcic_handle *h, int event) 631 { 632 struct tcic_event *pe; 633 int s; 634 635 pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT); 636 if (pe == NULL) 637 panic("tcic_queue_event: can't allocate event"); 638 639 pe->pe_type = event; 640 s = splhigh(); 641 SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q); 642 splx(s); 643 wakeup(&h->events); 644 } 645 void 646 tcic_attach_card(struct tcic_handle *h) 647 { 648 DPRINTF(("tcic_attach_card\n")); 649 650 if (h->flags & TCIC_FLAG_CARDP) 651 panic("tcic_attach_card: already attached"); 652 653 /* call the MI attach function */ 654 655 pcmcia_card_attach(h->pcmcia); 656 657 h->flags |= TCIC_FLAG_CARDP; 658 } 659 660 void 661 tcic_detach_card(struct tcic_handle *h, int flags) 662 /* flags: DETACH_* */ 663 { 664 DPRINTF(("tcic_detach_card\n")); 665 666 if (!(h->flags & TCIC_FLAG_CARDP)) 667 panic("tcic_detach_card: already detached"); 668 669 h->flags &= ~TCIC_FLAG_CARDP; 670 671 /* call the MI detach function */ 672 673 pcmcia_card_detach(h->pcmcia, flags); 674 675 } 676 677 void 678 tcic_deactivate_card(struct tcic_handle *h) 679 { 680 int val, reg; 681 682 if (!(h->flags & TCIC_FLAG_CARDP)) 683 panic("tcic_deactivate_card: already detached"); 684 685 /* call the MI deactivate function */ 686 pcmcia_card_deactivate(h->pcmcia); 687 688 tcic_sel_sock(h); 689 690 /* XXX disable card detect resume and configuration reset??? */ 691 692 /* power down the socket */ 693 tcic_write_1(h, TCIC_R_PWR, 0); 694 695 /* reset the card XXX ? -chb */ 696 697 /* turn off irq's for this socket */ 698 reg = TCIC_IR_SCF1_N(h->sock); 699 val = tcic_read_ind_2(h, reg); 700 tcic_write_ind_2(h, reg, (val & ~TCIC_SCF1_IRQ_MASK)|TCIC_SCF1_IRQOFF); 701 reg = TCIC_IR_SCF2_N(h->sock); 702 val = tcic_read_ind_2(h, reg); 703 tcic_write_ind_2(h, reg, 704 (val | (TCIC_SCF2_MLBAT1|TCIC_SCF2_MLBAT2|TCIC_SCF2_MRDY 705 |TCIC_SCF2_MWP|TCIC_SCF2_MCD))); 706 } 707 708 /* XXX the following routine may need to be rewritten. -chb */ 709 int 710 tcic_chip_mem_alloc(pcmcia_chipset_handle_t pch, bus_size_t size, struct pcmcia_mem_handle *pcmhp) 711 { 712 struct tcic_handle *h = (struct tcic_handle *) pch; 713 bus_space_handle_t memh; 714 bus_addr_t addr; 715 bus_size_t sizepg; 716 int i, mask, mhandle, got = 0; 717 718 /* out of sc->memh, allocate as many pages as necessary */ 719 720 /* 721 * The TCIC can map memory only in sizes that are 722 * powers of two, aligned at the natural boundary for the size. 723 */ 724 i = tcic_log2((u_int)size); 725 if ((1<<i) < size) 726 i++; 727 sizepg = max(i, TCIC_MEM_SHIFT) - (TCIC_MEM_SHIFT-1); 728 729 DPRINTF(("tcic_chip_mem_alloc: size %ld sizepg %ld\n", (u_long)size, 730 (u_long)sizepg)); 731 732 /* can't allocate that much anyway */ 733 if (sizepg > TCIC_MEM_PAGES) /* XXX -chb */ 734 return 1; 735 736 mask = (1 << sizepg) - 1; 737 738 addr = 0; /* XXX gcc -Wuninitialized */ 739 mhandle = 0; /* XXX gcc -Wuninitialized */ 740 741 /* XXX i should be initialised to always lay on boundary. -chb */ 742 for (i = 0; i < (TCIC_MEM_PAGES + 1 - sizepg); i += sizepg) { 743 if ((h->sc->subregionmask & (mask << i)) == (mask << i)) { 744 if (bus_space_subregion(h->sc->memt, h->sc->memh, 745 i * TCIC_MEM_PAGESIZE, 746 sizepg * TCIC_MEM_PAGESIZE, &memh)) 747 return (1); 748 mhandle = mask << i; 749 addr = h->sc->membase + (i * TCIC_MEM_PAGESIZE); 750 h->sc->subregionmask &= ~(mhandle); 751 got = 1; 752 break; 753 } 754 } 755 756 if (got == 0) 757 return (1); 758 759 DPRINTF(("tcic_chip_mem_alloc bus addr 0x%lx+0x%lx\n", (u_long) addr, 760 (u_long) size)); 761 762 pcmhp->memt = h->sc->memt; 763 pcmhp->memh = memh; 764 pcmhp->addr = addr; 765 pcmhp->size = size; 766 pcmhp->mhandle = mhandle; 767 pcmhp->realsize = sizepg * TCIC_MEM_PAGESIZE; 768 769 return (0); 770 } 771 772 /* XXX the following routine may need to be rewritten. -chb */ 773 void 774 tcic_chip_mem_free(pcmcia_chipset_handle_t pch, struct pcmcia_mem_handle *pcmhp) 775 { 776 struct tcic_handle *h = (struct tcic_handle *) pch; 777 778 h->sc->subregionmask |= pcmhp->mhandle; 779 } 780 781 void 782 tcic_chip_do_mem_map(struct tcic_handle *h, int win) 783 { 784 int reg, hwwin, wscnt; 785 786 int kind = h->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 787 int mem8 = (h->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8; 788 DPRINTF(("tcic_chip_do_mem_map window %d: 0x%lx+0x%lx 0x%lx\n", 789 win, (u_long)h->mem[win].addr, (u_long)h->mem[win].size, 790 (u_long)h->mem[win].offset)); 791 /* 792 * the even windows are used for socket 0, 793 * the odd ones for socket 1. 794 */ 795 hwwin = (win << 1) + h->sock; 796 797 /* the WR_MEXT register is MBZ */ 798 tcic_write_ind_2(h, TCIC_WR_MEXT_N(hwwin), 0); 799 800 /* set the host base address and window size */ 801 if (h->mem[win].size2 <= 1) { 802 reg = ((h->mem[win].addr >> TCIC_MEM_SHIFT) & 803 TCIC_MBASE_ADDR_MASK) | TCIC_MBASE_4K; 804 } else { 805 reg = ((h->mem[win].addr >> TCIC_MEM_SHIFT) & 806 TCIC_MBASE_ADDR_MASK) | (h->mem[win].size2 >> 1); 807 } 808 tcic_write_ind_2(h, TCIC_WR_MBASE_N(hwwin), reg); 809 810 /* set the card address and address space */ 811 reg = 0; 812 reg = ((h->mem[win].offset >> TCIC_MEM_SHIFT) & TCIC_MMAP_ADDR_MASK); 813 reg |= (kind == PCMCIA_MEM_ATTR) ? TCIC_MMAP_ATTR : 0; 814 DPRINTF(("tcic_chip_do_map_mem window %d(%d) mmap 0x%04x\n", 815 win, hwwin, reg)); 816 tcic_write_ind_2(h, TCIC_WR_MMAP_N(hwwin), reg); 817 818 /* set the MCTL register */ 819 /* must save WSCNT field in case this is a DB86082 rev 0 */ 820 /* XXX why can't I do the following two in one statement? */ 821 reg = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin)) & TCIC_MCTL_WSCNT_MASK; 822 reg |= TCIC_MCTL_ENA|TCIC_MCTL_QUIET; 823 reg |= mem8 ? TCIC_MCTL_B8 : 0; 824 reg |= (h->sock << TCIC_MCTL_SS_SHIFT) & TCIC_MCTL_SS_MASK; 825 #ifdef notyet /* XXX must get speed from CIS somehow. -chb */ 826 wscnt = tcic_ns2wscnt(h->mem[win].speed); 827 #else 828 wscnt = tcic_ns2wscnt(tcic_mem_speed); /* 300 is "save" default for CIS memory */ 829 #endif 830 if (h->sc->chipid == TCIC_CHIPID_DB86082_1) { 831 /* 832 * this chip has the wait state count in window 833 * register 7 - hwwin. 834 */ 835 int reg2; 836 reg2 = tcic_read_ind_2(h, TCIC_WR_MCTL_N(7-hwwin)); 837 reg2 &= ~TCIC_MCTL_WSCNT_MASK; 838 reg2 |= wscnt & TCIC_MCTL_WSCNT_MASK; 839 tcic_write_ind_2(h, TCIC_WR_MCTL_N(7-hwwin), reg2); 840 } else { 841 reg |= wscnt & TCIC_MCTL_WSCNT_MASK; 842 } 843 tcic_write_ind_2(h, TCIC_WR_MCTL_N(hwwin), reg); 844 845 #ifdef TCICDEBUG 846 { 847 int r1, r2, r3; 848 849 r1 = tcic_read_ind_2(h, TCIC_WR_MBASE_N(hwwin)); 850 r2 = tcic_read_ind_2(h, TCIC_WR_MMAP_N(hwwin)); 851 r3 = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin)); 852 853 DPRINTF(("tcic_chip_do_mem_map window %d(%d): %04x %04x %04x\n", 854 win, hwwin, r1, r2, r3)); 855 } 856 #endif 857 } 858 859 /* XXX needs work */ 860 int 861 tcic_chip_mem_map(pcmcia_chipset_handle_t pch, int kind, bus_addr_t card_addr, bus_size_t size, struct pcmcia_mem_handle *pcmhp, bus_size_t *offsetp, int *windowp) 862 { 863 struct tcic_handle *h = (struct tcic_handle *) pch; 864 bus_addr_t busaddr; 865 long card_offset; 866 int i, win; 867 868 win = -1; 869 for (i = 0; i < h->memwins; i++) { 870 if ((h->memalloc & (1 << i)) == 0) { 871 win = i; 872 h->memalloc |= (1 << i); 873 break; 874 } 875 } 876 877 if (win == -1) 878 return (1); 879 880 *windowp = win; 881 882 /* XXX this is pretty gross */ 883 884 if (!bus_space_is_equal(h->sc->memt, pcmhp->memt)) 885 panic("tcic_chip_mem_map memt is bogus"); 886 887 busaddr = pcmhp->addr; 888 889 /* 890 * compute the address offset to the pcmcia address space for the 891 * tcic. this is intentionally signed. The masks and shifts below 892 * will cause TRT to happen in the tcic registers. Deal with making 893 * sure the address is aligned, and return the alignment offset. 894 */ 895 896 *offsetp = card_addr % TCIC_MEM_ALIGN; 897 card_addr -= *offsetp; 898 899 DPRINTF(("tcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 900 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 901 (u_long) card_addr)); 902 903 /* XXX we can't use size. -chb */ 904 /* 905 * include the offset in the size, and decrement size by one, since 906 * the hw wants start/stop 907 */ 908 size += *offsetp - 1; 909 910 card_offset = (((long) card_addr) - ((long) busaddr)); 911 912 DPRINTF(("tcic_chip_mem_map window %d card_offset 0x%lx\n", 913 win, (u_long)card_offset)); 914 915 h->mem[win].addr = busaddr; 916 h->mem[win].size = size; 917 h->mem[win].size2 = tcic_log2((u_int)pcmhp->realsize) - TCIC_MEM_SHIFT; 918 h->mem[win].offset = card_offset; 919 h->mem[win].kind = kind; 920 921 tcic_chip_do_mem_map(h, win); 922 923 return (0); 924 } 925 926 void 927 tcic_chip_mem_unmap(pcmcia_chipset_handle_t pch, int window) 928 { 929 struct tcic_handle *h = (struct tcic_handle *) pch; 930 int hwwin; 931 932 if (window >= h->memwins) 933 panic("tcic_chip_mem_unmap: window out of range"); 934 935 hwwin = (window << 1) + h->sock; 936 tcic_write_ind_2(h, TCIC_WR_MCTL_N(hwwin), 0); 937 938 h->memalloc &= ~(1 << window); 939 } 940 941 int 942 tcic_chip_io_alloc(pcmcia_chipset_handle_t pch, bus_addr_t start, bus_size_t size, bus_size_t align, struct pcmcia_io_handle *pcihp) 943 { 944 struct tcic_handle *h = (struct tcic_handle *) pch; 945 bus_space_tag_t iot; 946 bus_space_handle_t ioh; 947 bus_addr_t ioaddr; 948 int size2, flags = 0; 949 950 /* 951 * Allocate some arbitrary I/O space. 952 */ 953 954 DPRINTF(("tcic_chip_io_alloc req 0x%lx %ld %ld\n", 955 (u_long) start, (u_long) size, (u_long) align)); 956 /* 957 * The TCIC can map I/O space only in sizes that are 958 * powers of two, aligned at the natural boundary for the size. 959 */ 960 size2 = tcic_log2((u_int)size); 961 if ((1 << size2) < size) 962 size2++; 963 /* can't allocate that much anyway */ 964 if (size2 > 16) /* XXX 64K -chb */ 965 return 1; 966 if (align) { 967 if ((1 << size2) != align) 968 return 1; /* not suitably aligned */ 969 } else { 970 align = 1 << size2; /* no alignment given, make it natural */ 971 } 972 if (start & (align - 1)) 973 return 1; /* not suitably aligned */ 974 975 iot = h->sc->iot; 976 977 if (start) { 978 ioaddr = start; 979 if (bus_space_map(iot, start, size, 0, &ioh)) 980 return (1); 981 DPRINTF(("tcic_chip_io_alloc map port %lx+%lx\n", 982 (u_long) ioaddr, (u_long) size)); 983 } else { 984 flags |= PCMCIA_IO_ALLOCATED; 985 if (bus_space_alloc(iot, h->sc->iobase, 986 h->sc->iobase + h->sc->iosize, size, align, 0, 0, 987 &ioaddr, &ioh)) 988 return (1); 989 DPRINTF(("tcic_chip_io_alloc alloc port %lx+%lx\n", 990 (u_long) ioaddr, (u_long) size)); 991 } 992 993 pcihp->iot = iot; 994 pcihp->ioh = ioh; 995 pcihp->addr = ioaddr; 996 pcihp->size = size; 997 pcihp->flags = flags; 998 999 return (0); 1000 } 1001 1002 void 1003 tcic_chip_io_free(pcmcia_chipset_handle_t pch, 1004 struct pcmcia_io_handle *pcihp) 1005 { 1006 bus_space_tag_t iot = pcihp->iot; 1007 bus_space_handle_t ioh = pcihp->ioh; 1008 bus_size_t size = pcihp->size; 1009 1010 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1011 bus_space_free(iot, ioh, size); 1012 else 1013 bus_space_unmap(iot, ioh, size); 1014 } 1015 1016 static int tcic_iowidth_map[] = 1017 { TCIC_ICTL_AUTOSZ, TCIC_ICTL_B8, TCIC_ICTL_B16 }; 1018 1019 void 1020 tcic_chip_do_io_map(struct tcic_handle *h, int win) 1021 { 1022 int reg, size2, iotiny, wbase, hwwin, wscnt; 1023 1024 DPRINTF(("tcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 1025 win, (long) h->io[win].addr, (long) h->io[win].size, 1026 h->io[win].width * 8)); 1027 1028 /* 1029 * the even windows are used for socket 0, 1030 * the odd ones for socket 1. 1031 */ 1032 hwwin = (win << 1) + h->sock; 1033 1034 /* set the WR_BASE register */ 1035 /* XXX what if size isn't power of 2? -chb */ 1036 size2 = tcic_log2((u_int)h->io[win].size); 1037 DPRINTF(("tcic_chip_do_io_map win %d size2 %d\n", win, size2)); 1038 if (size2 < 1) { 1039 iotiny = TCIC_ICTL_TINY; 1040 wbase = h->io[win].addr; 1041 } else { 1042 iotiny = 0; 1043 /* XXX we should do better -chb */ 1044 wbase = h->io[win].addr | (1 << (size2 - 1)); 1045 } 1046 tcic_write_ind_2(h, TCIC_WR_IBASE_N(hwwin), wbase); 1047 1048 /* set the WR_ICTL register */ 1049 reg = TCIC_ICTL_ENA | TCIC_ICTL_QUIET; 1050 reg |= (h->sock << TCIC_ICTL_SS_SHIFT) & TCIC_ICTL_SS_MASK; 1051 reg |= iotiny | tcic_iowidth_map[h->io[win].width]; 1052 if (h->sc->chipid != TCIC_CHIPID_DB86082_1) 1053 reg |= TCIC_ICTL_PASS16; 1054 #ifdef notyet /* XXX must get speed from CIS somehow. -chb */ 1055 wscnt = tcic_ns2wscnt(h->io[win].speed); 1056 #else 1057 wscnt = tcic_ns2wscnt(tcic_io_speed); /* linux uses 0 as default */ 1058 #endif 1059 reg |= wscnt & TCIC_ICTL_WSCNT_MASK; 1060 tcic_write_ind_2(h, TCIC_WR_ICTL_N(hwwin), reg); 1061 1062 #ifdef TCICDEBUG 1063 { 1064 int r1, r2; 1065 1066 r1 = tcic_read_ind_2(h, TCIC_WR_IBASE_N(hwwin)); 1067 r2 = tcic_read_ind_2(h, TCIC_WR_ICTL_N(hwwin)); 1068 1069 DPRINTF(("tcic_chip_do_io_map window %d(%d): %04x %04x\n", 1070 win, hwwin, r1, r2)); 1071 } 1072 #endif 1073 } 1074 1075 int 1076 tcic_chip_io_map(pcmcia_chipset_handle_t pch, int width, bus_addr_t offset, bus_size_t size, struct pcmcia_io_handle *pcihp, int *windowp) 1077 { 1078 struct tcic_handle *h = (struct tcic_handle *) pch; 1079 bus_addr_t ioaddr = pcihp->addr + offset; 1080 int i, win; 1081 #ifdef TCICDEBUG 1082 static const char *width_names[] = { "auto", "io8", "io16" }; 1083 #endif 1084 1085 /* XXX Sanity check offset/size. */ 1086 1087 win = -1; 1088 for (i = 0; i < TCIC_IO_WINS; i++) { 1089 if ((h->ioalloc & (1 << i)) == 0) { 1090 win = i; 1091 h->ioalloc |= (1 << i); 1092 break; 1093 } 1094 } 1095 1096 if (win == -1) 1097 return (1); 1098 1099 *windowp = win; 1100 1101 /* XXX this is pretty gross */ 1102 1103 if (!bus_space_is_equal(h->sc->iot, pcihp->iot)) 1104 panic("tcic_chip_io_map iot is bogus"); 1105 1106 DPRINTF(("tcic_chip_io_map window %d %s port %lx+%lx\n", 1107 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1108 1109 /* XXX wtf is this doing here? */ 1110 1111 printf("%s: port 0x%lx", device_xname(h->sc->sc_dev), (u_long) ioaddr); 1112 if (size > 1) 1113 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1114 printf("\n"); 1115 1116 h->io[win].addr = ioaddr; 1117 h->io[win].size = size; 1118 h->io[win].width = width; 1119 1120 tcic_chip_do_io_map(h, win); 1121 1122 return (0); 1123 } 1124 1125 void 1126 tcic_chip_io_unmap(pcmcia_chipset_handle_t pch, int window) 1127 { 1128 struct tcic_handle *h = (struct tcic_handle *) pch; 1129 int hwwin; 1130 1131 if (window >= TCIC_IO_WINS) 1132 panic("tcic_chip_io_unmap: window out of range"); 1133 1134 hwwin = (window << 1) + h->sock; 1135 tcic_write_ind_2(h, TCIC_WR_ICTL_N(hwwin), 0); 1136 1137 h->ioalloc &= ~(1 << window); 1138 } 1139 1140 void 1141 tcic_chip_socket_enable(pcmcia_chipset_handle_t pch) 1142 { 1143 struct tcic_handle *h = (struct tcic_handle *) pch; 1144 int reg, win; 1145 1146 tcic_sel_sock(h); 1147 1148 /* 1149 * power down the socket to reset it. 1150 * put card reset into high-z, put chip outputs to card into high-z 1151 */ 1152 1153 tcic_write_1(h, TCIC_R_PWR, 0); 1154 reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1155 reg |= TCIC_ILOCK_CWAIT; 1156 reg &= ~(TCIC_ILOCK_CRESET|TCIC_ILOCK_CRESENA); 1157 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1158 tcic_write_1(h, TCIC_R_SCTRL, 0); /* clear TCIC_SCTRL_ENA */ 1159 1160 /* zero out the address windows */ 1161 1162 tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), 0); 1163 /* writing to WR_MBASE_N disables the window */ 1164 for (win = 0; win < h->memwins; win++) { 1165 tcic_write_ind_2(h, TCIC_WR_MBASE_N((win << 1) + h->sock), 0); 1166 } 1167 /* writing to WR_IBASE_N disables the window */ 1168 for (win = 0; win < TCIC_IO_WINS; win++) { 1169 tcic_write_ind_2(h, TCIC_WR_IBASE_N((win << 1) + h->sock), 0); 1170 } 1171 1172 /* power up the socket */ 1173 1174 /* turn on VCC, turn of VPP */ 1175 reg = TCIC_PWR_VCC_N(h->sock) | TCIC_PWR_VPP_N(h->sock) | h->sc->pwrena; 1176 if (h->sc->pwrena) /* this is a '84 type chip */ 1177 reg |= TCIC_PWR_VCC5V; 1178 tcic_write_1(h, TCIC_R_PWR, reg); 1179 delay(10000); 1180 1181 /* enable reset and wiggle it to reset the card */ 1182 reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1183 reg |= TCIC_ILOCK_CRESENA; 1184 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1185 /* XXX need bus_space_barrier here */ 1186 reg |= TCIC_ILOCK_CRESET; 1187 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1188 /* enable card signals */ 1189 tcic_write_1(h, TCIC_R_SCTRL, TCIC_SCTRL_ENA); 1190 delay(10); /* wait 10 us */ 1191 1192 /* clear the reset flag */ 1193 reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1194 reg &= ~(TCIC_ILOCK_CRESET); 1195 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1196 1197 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1198 delay(20000); 1199 1200 /* wait for the chip to finish initializing */ 1201 tcic_wait_ready(h); 1202 1203 /* WWW */ 1204 1205 /* reinstall all the memory and io mappings */ 1206 1207 for (win = 0; win < h->memwins; win++) 1208 if (h->memalloc & (1 << win)) 1209 tcic_chip_do_mem_map(h, win); 1210 1211 for (win = 0; win < TCIC_IO_WINS; win++) 1212 if (h->ioalloc & (1 << win)) 1213 tcic_chip_do_io_map(h, win); 1214 } 1215 1216 void 1217 tcic_chip_socket_settype(pcmcia_chipset_handle_t pch, int type) 1218 { 1219 struct tcic_handle *h = (struct tcic_handle *) pch; 1220 int reg; 1221 1222 tcic_sel_sock(h); 1223 1224 /* set the card type */ 1225 1226 reg = 0; 1227 if (type == PCMCIA_IFTYPE_IO) { 1228 reg |= TCIC_SCF1_IOSTS; 1229 reg |= tcic_irqmap[h->ih_irq]; /* enable interrupts */ 1230 } 1231 tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), reg); 1232 1233 DPRINTF(("%s: tcic_chip_socket_enable %d cardtype %s 0x%02x\n", 1234 device_xname(h->sc->sc_dev), h->sock, 1235 ((type == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg)); 1236 } 1237 1238 void 1239 tcic_chip_socket_disable(pcmcia_chipset_handle_t pch) 1240 { 1241 struct tcic_handle *h = (struct tcic_handle *) pch; 1242 int val; 1243 1244 DPRINTF(("tcic_chip_socket_disable\n")); 1245 1246 tcic_sel_sock(h); 1247 1248 /* disable interrupts */ 1249 val = tcic_read_ind_2(h, TCIC_IR_SCF1_N(h->sock)); 1250 val &= TCIC_SCF1_IRQ_MASK; 1251 tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), val); 1252 1253 /* disable the output signals */ 1254 tcic_write_1(h, TCIC_R_SCTRL, 0); 1255 val = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1256 val &= ~TCIC_ILOCK_CRESENA; 1257 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, val); 1258 1259 /* power down the socket */ 1260 tcic_write_1(h, TCIC_R_PWR, 0); 1261 } 1262 1263 /* 1264 * XXX The following is Linux driver but doesn't match the table 1265 * in the manual. 1266 */ 1267 int 1268 tcic_ns2wscnt(int ns) 1269 { 1270 if (ns < 14) { 1271 return 0; 1272 } else { 1273 return (2*(ns-14))/70; /* XXX assumes 14.31818 MHz clock. */ 1274 } 1275 } 1276 1277 int 1278 tcic_log2(u_int val) 1279 { 1280 int i, l2; 1281 1282 l2 = i = 0; 1283 while (val) { 1284 if (val & 1) 1285 l2 = i; 1286 i++; 1287 val >>= 1; 1288 } 1289 return l2; 1290 } 1291