1 /* $NetBSD: tcic2.c,v 1.6 2000/06/28 17:13:04 mrg Exp $ */ 2 3 #undef TCICDEBUG 4 5 /* 6 * Copyright (c) 1998, 1999 Christoph Badura. All rights reserved. 7 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. All advertising materials mentioning features or use of this software 18 * must display the following acknowledgement: 19 * This product includes software developed by Marc Horowitz. 20 * 4. The name of the author may not be used to endorse or promote products 21 * derived from this software without specific prior written permission. 22 * 23 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 24 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 25 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 26 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 27 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 28 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 29 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 30 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 31 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 32 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/types.h> 36 #include <sys/param.h> 37 #include <sys/systm.h> 38 #include <sys/device.h> 39 #include <sys/extent.h> 40 #include <sys/malloc.h> 41 #include <sys/kthread.h> 42 43 #include <machine/bus.h> 44 #include <machine/intr.h> 45 46 #include <dev/pcmcia/pcmciareg.h> 47 #include <dev/pcmcia/pcmciavar.h> 48 49 #include <dev/ic/tcic2reg.h> 50 #include <dev/ic/tcic2var.h> 51 52 #include "locators.h" 53 54 #ifdef TCICDEBUG 55 int tcic_debug = 1; 56 #define DPRINTF(arg) if (tcic_debug) printf arg; 57 #else 58 #define DPRINTF(arg) 59 #endif 60 61 /* 62 * Individual drivers will allocate their own memory and io regions. Memory 63 * regions must be a multiple of 4k, aligned on a 4k boundary. 64 */ 65 66 #define TCIC_MEM_ALIGN TCIC_MEM_PAGESIZE 67 68 void tcic_attach_socket __P((struct tcic_handle *)); 69 void tcic_init_socket __P((struct tcic_handle *)); 70 71 int tcic_submatch __P((struct device *, struct cfdata *, void *)); 72 int tcic_print __P((void *arg, const char *pnp)); 73 int tcic_intr_socket __P((struct tcic_handle *)); 74 75 void tcic_attach_card __P((struct tcic_handle *)); 76 void tcic_detach_card __P((struct tcic_handle *, int)); 77 void tcic_deactivate_card __P((struct tcic_handle *)); 78 79 void tcic_chip_do_mem_map __P((struct tcic_handle *, int)); 80 void tcic_chip_do_io_map __P((struct tcic_handle *, int)); 81 82 void tcic_create_event_thread __P((void *)); 83 void tcic_event_thread __P((void *)); 84 85 void tcic_queue_event __P((struct tcic_handle *, int)); 86 87 /* Map between irq numbers and internal representation */ 88 #if 1 89 int tcic_irqmap[] = 90 { 0, 0, 0, 3, 4, 5, 6, 7, 0, 0, 10, 1, 0, 0, 14, 0 }; 91 int tcic_valid_irqs = 0x4cf8; 92 #else 93 int tcic_irqmap[] = /* irqs 9 and 6 switched, some ISA cards */ 94 { 0, 0, 0, 3, 4, 5, 0, 7, 0, 6, 10, 1, 0, 0, 14, 0 }; 95 int tcic_valid_irqs = 0x4eb8; 96 #endif 97 98 int tcic_mem_speed = 250; /* memory access time in nanoseconds */ 99 int tcic_io_speed = 165; /* io access time in nanoseconds */ 100 101 /* 102 * Check various reserved and otherwise in their value restricted bits. 103 */ 104 int 105 tcic_check_reserved_bits(iot, ioh) 106 bus_space_tag_t iot; 107 bus_space_handle_t ioh; 108 { 109 int val, auxreg; 110 111 DPRINTF(("tcic: chkrsvd 1\n")); 112 /* R_ADDR bit 30:28 have a restricted range. */ 113 val = (bus_space_read_2(iot, ioh, TCIC_R_ADDR2) & TCIC_SS_MASK) 114 >> TCIC_SS_SHIFT; 115 if (val > 1) 116 return 0; 117 118 DPRINTF(("tcic: chkrsvd 2\n")); 119 /* R_SCTRL bits 6,2,1 are reserved. */ 120 val = bus_space_read_1(iot, ioh, TCIC_R_SCTRL); 121 if (val & TCIC_SCTRL_RSVD) 122 return 0; 123 124 DPRINTF(("tcic: chkrsvd 3\n")); 125 /* R_ICSR bit 2 must be same as bit 3. */ 126 val = bus_space_read_1(iot, ioh, TCIC_R_ICSR); 127 if (((val >> 1) & 1) != ((val >> 2) & 1)) 128 return 0; 129 130 DPRINTF(("tcic: chkrsvd 4\n")); 131 /* R_IENA bits 7,2 are reserverd. */ 132 val = bus_space_read_1(iot, ioh, TCIC_R_IENA); 133 if (val & TCIC_IENA_RSVD) 134 return 0; 135 136 DPRINTF(("tcic: chkrsvd 5\n")); 137 /* Some aux registers have reserved bits. */ 138 /* Which are we looking at? */ 139 auxreg = bus_space_read_1(iot, ioh, TCIC_R_MODE) 140 & TCIC_AR_MASK; 141 val = bus_space_read_2(iot, ioh, TCIC_R_AUX); 142 DPRINTF(("tcic: auxreg 0x%02x val 0x%04x\n", auxreg, val)); 143 switch (auxreg) { 144 case TCIC_AR_SYSCFG: 145 if (INVALID_AR_SYSCFG(val)) 146 return 0; 147 break; 148 case TCIC_AR_ILOCK: 149 if (INVALID_AR_ILOCK(val)) 150 return 0; 151 break; 152 case TCIC_AR_TEST: 153 if (INVALID_AR_TEST(val)) 154 return 0; 155 break; 156 } 157 158 DPRINTF(("tcic: chkrsvd 6\n")); 159 /* XXX fails if pcmcia bios is enabled. */ 160 /* Various bits set or not depending if in RESET mode. */ 161 val = bus_space_read_1(iot, ioh, TCIC_R_SCTRL); 162 if (val & TCIC_SCTRL_RESET) { 163 DPRINTF(("tcic: chkrsvd 7\n")); 164 /* Address bits must be 0 */ 165 val = bus_space_read_2(iot, ioh, TCIC_R_ADDR); 166 if (val != 0) 167 return 0; 168 val = bus_space_read_2(iot, ioh, TCIC_R_ADDR2); 169 if (val != 0) 170 return 0; 171 DPRINTF(("tcic: chkrsvd 8\n")); 172 /* EDC bits must be 0 */ 173 val = bus_space_read_2(iot, ioh, TCIC_R_EDC); 174 if (val != 0) 175 return 0; 176 /* We're OK, so take it out of reset. XXX -chb */ 177 bus_space_write_1(iot, ioh, TCIC_R_SCTRL, 0); 178 } 179 else { /* not in RESET mode */ 180 int omode; 181 int val1, val2; 182 DPRINTF(("tcic: chkrsvd 9\n")); 183 /* Programming timers must have expired. */ 184 val = bus_space_read_1(iot, ioh, TCIC_R_SSTAT); 185 if ((val & (TCIC_SSTAT_6US|TCIC_SSTAT_10US|TCIC_SSTAT_PROGTIME)) 186 != (TCIC_SSTAT_6US|TCIC_SSTAT_10US|TCIC_SSTAT_PROGTIME)) 187 return 0; 188 DPRINTF(("tcic: chkrsvd 10\n")); 189 /* 190 * EDC bits should change on read from data space 191 * as long as either EDC or the data are nonzero. 192 */ 193 if ((bus_space_read_2(iot, ioh, TCIC_R_ADDR2) 194 & TCIC_ADDR2_INDREG) != 0) { 195 val1 = bus_space_read_2(iot, ioh, TCIC_R_EDC); 196 val2 = bus_space_read_2(iot, ioh, TCIC_R_DATA); 197 if (val1 | val2) { 198 val1 = bus_space_read_2(iot, ioh, TCIC_R_EDC); 199 if (val1 == val2) 200 return 0; 201 } 202 } 203 DPRINTF(("tcic: chkrsvd 11\n")); 204 /* XXX what does this check? -chb */ 205 omode = bus_space_read_1(iot, ioh, TCIC_R_MODE); 206 val1 = omode ^ TCIC_AR_MASK; 207 bus_space_write_1(iot, ioh, TCIC_R_MODE, val1); 208 val2 = bus_space_read_1(iot, ioh, TCIC_R_MODE); 209 bus_space_write_1(iot, ioh, TCIC_R_MODE, omode); 210 if ( val1 != val2) 211 return 0; 212 } 213 /* All tests passed */ 214 return 1; 215 } 216 217 /* 218 * Read chip ID from AR_ILOCK in test mode. 219 */ 220 int 221 tcic_chipid(iot, ioh) 222 bus_space_tag_t iot; 223 bus_space_handle_t ioh; 224 { 225 unsigned id, otest; 226 227 otest = tcic_read_aux_2(iot, ioh, TCIC_AR_TEST); 228 tcic_write_aux_2(iot, ioh, TCIC_AR_TEST, TCIC_TEST_DIAG); 229 id = tcic_read_aux_2(iot, ioh, TCIC_AR_ILOCK); 230 tcic_write_aux_2(iot, ioh, TCIC_AR_TEST, otest); 231 id &= TCIC_ILOCKTEST_ID_MASK; 232 id >>= TCIC_ILOCKTEST_ID_SHFT; 233 234 /* clear up IRQs inside tcic. XXX -chb */ 235 while (bus_space_read_1(iot, ioh, TCIC_R_ICSR)) 236 bus_space_write_1(iot, ioh, TCIC_R_ICSR, TCIC_ICSR_JAM); 237 238 return id; 239 } 240 /* 241 * Indicate whether the driver can handle the chip. 242 */ 243 int 244 tcic_chipid_known(id) 245 int id; 246 { 247 /* XXX only know how to handle DB86082 -chb */ 248 switch (id) { 249 case TCIC_CHIPID_DB86082_1: 250 case TCIC_CHIPID_DB86082A: 251 case TCIC_CHIPID_DB86082B_ES: 252 case TCIC_CHIPID_DB86082B: 253 case TCIC_CHIPID_DB86084_1: 254 case TCIC_CHIPID_DB86084A: 255 case TCIC_CHIPID_DB86184_1: 256 case TCIC_CHIPID_DB86072_1_ES: 257 case TCIC_CHIPID_DB86072_1: 258 return 1; 259 } 260 261 return 0; 262 } 263 264 char * 265 tcic_chipid_to_string(id) 266 int id; 267 { 268 switch (id) { 269 case TCIC_CHIPID_DB86082_1: 270 return ("Databook DB86082"); 271 case TCIC_CHIPID_DB86082A: 272 return ("Databook DB86082A"); 273 case TCIC_CHIPID_DB86082B_ES: 274 return ("Databook DB86082B-es"); 275 case TCIC_CHIPID_DB86082B: 276 return ("Databook DB86082B"); 277 case TCIC_CHIPID_DB86084_1: 278 return ("Databook DB86084"); 279 case TCIC_CHIPID_DB86084A: 280 return ("Databook DB86084A"); 281 case TCIC_CHIPID_DB86184_1: 282 return ("Databook DB86184"); 283 case TCIC_CHIPID_DB86072_1_ES: 284 return ("Databook DB86072-es"); 285 case TCIC_CHIPID_DB86072_1: 286 return ("Databook DB86072"); 287 } 288 289 return ("Unknown controller"); 290 } 291 /* 292 * Return bitmask of IRQs that the chip can handle. 293 * XXX should be table driven. 294 */ 295 int 296 tcic_validirqs(chipid) 297 int chipid; 298 { 299 switch (chipid) { 300 case TCIC_CHIPID_DB86082_1: 301 case TCIC_CHIPID_DB86082A: 302 case TCIC_CHIPID_DB86082B_ES: 303 case TCIC_CHIPID_DB86082B: 304 case TCIC_CHIPID_DB86084_1: 305 case TCIC_CHIPID_DB86084A: 306 case TCIC_CHIPID_DB86184_1: 307 case TCIC_CHIPID_DB86072_1_ES: 308 case TCIC_CHIPID_DB86072_1: 309 return tcic_valid_irqs; 310 } 311 return 0; 312 } 313 314 void 315 tcic_attach(sc) 316 struct tcic_softc *sc; 317 { 318 int i, reg; 319 320 /* set more chipset dependend parameters in the softc. */ 321 switch (sc->chipid) { 322 case TCIC_CHIPID_DB86084_1: 323 case TCIC_CHIPID_DB86084A: 324 case TCIC_CHIPID_DB86184_1: 325 sc->pwrena = TCIC_PWR_ENA; 326 break; 327 default: 328 sc->pwrena = 0; 329 break; 330 } 331 332 /* set up global config registers */ 333 reg = TCIC_WAIT_SYNC | TCIC_WAIT_CCLK | TCIC_WAIT_RISING; 334 reg |= (tcic_ns2wscnt(250) & TCIC_WAIT_COUNT_MASK); 335 tcic_write_aux_1(sc->iot, sc->ioh, TCIC_AR_WCTL, TCIC_R_WCTL_WAIT, reg); 336 reg = TCIC_SYSCFG_MPSEL_RI | TCIC_SYSCFG_MCSFULL; 337 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, reg); 338 reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_ILOCK); 339 reg |= TCIC_ILOCK_HOLD_CCLK; 340 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_ILOCK, reg); 341 342 /* the TCIC has two sockets */ 343 /* XXX should i check for actual presence of sockets? -chb */ 344 for (i = 0; i < TCIC_NSLOTS; i++) { 345 sc->handle[i].sc = sc; 346 sc->handle[i].sock = i; 347 sc->handle[i].flags = TCIC_FLAG_SOCKETP; 348 sc->handle[i].memwins 349 = sc->chipid == TCIC_CHIPID_DB86082_1 ? 4 : 5; 350 } 351 352 /* establish the interrupt */ 353 reg = tcic_read_1(&sc->handle[0], TCIC_R_IENA); 354 tcic_write_1(&sc->handle[0], TCIC_R_IENA, 355 (reg & ~TCIC_IENA_CFG_MASK) | TCIC_IENA_CFG_HIGH); 356 reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG); 357 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, 358 (reg & ~TCIC_SYSCFG_IRQ_MASK) | tcic_irqmap[sc->irq]); 359 360 /* XXX block interrupts? */ 361 362 for (i = 0; i < TCIC_NSLOTS; i++) { 363 /* XXX make more clear what happens here -chb */ 364 tcic_sel_sock(&sc->handle[i]); 365 tcic_write_ind_2(&sc->handle[i], TCIC_IR_SCF1_N(i), 0); 366 tcic_write_ind_2(&sc->handle[i], TCIC_IR_SCF2_N(i), 367 (TCIC_SCF2_MCD|TCIC_SCF2_MWP|TCIC_SCF2_MRDY 368 #if 1 /* XXX explain byte routing issue */ 369 |TCIC_SCF2_MLBAT2|TCIC_SCF2_MLBAT1|TCIC_SCF2_IDBR)); 370 #else 371 |TCIC_SCF2_MLBAT2|TCIC_SCF2_MLBAT1)); 372 #endif 373 tcic_write_1(&sc->handle[i], TCIC_R_MODE, 0); 374 reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG); 375 reg &= ~TCIC_SYSCFG_AUTOBUSY; 376 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, reg); 377 SIMPLEQ_INIT(&sc->handle[i].events); 378 } 379 380 if ((sc->handle[0].flags & TCIC_FLAG_SOCKETP) || 381 (sc->handle[1].flags & TCIC_FLAG_SOCKETP)) { 382 printf("%s: %s has ", sc->dev.dv_xname, 383 tcic_chipid_to_string(sc->chipid)); 384 385 if ((sc->handle[0].flags & TCIC_FLAG_SOCKETP) && 386 (sc->handle[1].flags & TCIC_FLAG_SOCKETP)) 387 printf("sockets A and B\n"); 388 else if (sc->handle[0].flags & TCIC_FLAG_SOCKETP) 389 printf("socket A only\n"); 390 else 391 printf("socket B only\n"); 392 393 } 394 } 395 396 void 397 tcic_attach_sockets(sc) 398 struct tcic_softc *sc; 399 { 400 int i; 401 402 for (i = 0; i < TCIC_NSLOTS; i++) 403 if (sc->handle[i].flags & TCIC_FLAG_SOCKETP) 404 tcic_attach_socket(&sc->handle[i]); 405 } 406 407 void 408 tcic_attach_socket(h) 409 struct tcic_handle *h; 410 { 411 struct pcmciabus_attach_args paa; 412 413 /* initialize the rest of the handle */ 414 415 h->shutdown = 0; 416 h->memalloc = 0; 417 h->ioalloc = 0; 418 h->ih_irq = 0; 419 420 /* now, config one pcmcia device per socket */ 421 422 paa.paa_busname = "pcmcia"; 423 paa.pct = (pcmcia_chipset_tag_t) h->sc->pct; 424 paa.pch = (pcmcia_chipset_handle_t) h; 425 paa.iobase = h->sc->iobase; 426 paa.iosize = h->sc->iosize; 427 428 h->pcmcia = config_found_sm(&h->sc->dev, &paa, tcic_print, 429 tcic_submatch); 430 431 /* if there's actually a pcmcia device attached, initialize the slot */ 432 433 if (h->pcmcia) 434 tcic_init_socket(h); 435 } 436 437 void 438 tcic_create_event_thread(arg) 439 void *arg; 440 { 441 struct tcic_handle *h = arg; 442 const char *cs; 443 444 switch (h->sock) { 445 case 0: 446 cs = "0"; 447 break; 448 case 1: 449 cs = "1"; 450 break; 451 default: 452 panic("tcic_create_event_thread: unknown tcic socket"); 453 } 454 455 if (kthread_create1(tcic_event_thread, h, &h->event_thread, 456 "%s,%s", h->sc->dev.dv_xname, cs)) { 457 printf("%s: unable to create event thread for sock 0x%02x\n", 458 h->sc->dev.dv_xname, h->sock); 459 panic("tcic_create_event_thread"); 460 } 461 } 462 463 void 464 tcic_event_thread(arg) 465 void *arg; 466 { 467 struct tcic_handle *h = arg; 468 struct tcic_event *pe; 469 int s; 470 471 while (h->shutdown == 0) { 472 s = splhigh(); 473 if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) { 474 splx(s); 475 (void) tsleep(&h->events, PWAIT, "tcicev", 0); 476 continue; 477 } 478 SIMPLEQ_REMOVE_HEAD(&h->events, pe, pe_q); 479 splx(s); 480 481 switch (pe->pe_type) { 482 case TCIC_EVENT_INSERTION: 483 DPRINTF(("%s: insertion event\n", h->sc->dev.dv_xname)); 484 tcic_attach_card(h); 485 break; 486 487 case TCIC_EVENT_REMOVAL: 488 DPRINTF(("%s: removal event\n", h->sc->dev.dv_xname)); 489 tcic_detach_card(h, DETACH_FORCE); 490 break; 491 492 default: 493 panic("tcic_event_thread: unknown event %d", 494 pe->pe_type); 495 } 496 free(pe, M_TEMP); 497 } 498 499 h->event_thread = NULL; 500 501 /* In case parent is waiting for us to exit. */ 502 wakeup(h->sc); 503 504 kthread_exit(0); 505 } 506 507 508 void 509 tcic_init_socket(h) 510 struct tcic_handle *h; 511 { 512 int reg; 513 514 /* select this socket's config registers */ 515 tcic_sel_sock(h); 516 517 /* set up the socket to interrupt on card detect */ 518 reg = tcic_read_ind_2(h, TCIC_IR_SCF2_N(h->sock)); 519 tcic_write_ind_2(h, TCIC_IR_SCF2_N(h->sock), reg & ~TCIC_SCF2_MCD); 520 521 /* enable CD irq in R_IENA */ 522 reg = tcic_read_2(h, TCIC_R_IENA); 523 tcic_write_2(h, TCIC_R_IENA, reg |= TCIC_IENA_CDCHG); 524 525 /* if there's a card there, then attach it. also save sstat */ 526 h->sstat = reg = tcic_read_1(h, TCIC_R_SSTAT) & TCIC_SSTAT_STAT_MASK; 527 if (reg & TCIC_SSTAT_CD) 528 tcic_attach_card(h); 529 } 530 531 int 532 tcic_submatch(parent, cf, aux) 533 struct device *parent; 534 struct cfdata *cf; 535 void *aux; 536 { 537 538 struct pcmciabus_attach_args *paa = aux; 539 struct tcic_handle *h = (struct tcic_handle *) paa->pch; 540 541 switch (h->sock) { 542 case 0: 543 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 544 PCMCIABUSCF_CONTROLLER_DEFAULT && 545 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 546 return 0; 547 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 548 PCMCIABUSCF_SOCKET_DEFAULT && 549 cf->cf_loc[PCMCIABUSCF_SOCKET] != 0) 550 return 0; 551 552 break; 553 case 1: 554 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 555 PCMCIABUSCF_CONTROLLER_DEFAULT && 556 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 557 return 0; 558 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 559 PCMCIABUSCF_SOCKET_DEFAULT && 560 cf->cf_loc[PCMCIABUSCF_SOCKET] != 1) 561 return 0; 562 563 break; 564 default: 565 panic("unknown tcic socket"); 566 } 567 568 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 569 } 570 571 int 572 tcic_print(arg, pnp) 573 void *arg; 574 const char *pnp; 575 { 576 struct pcmciabus_attach_args *paa = arg; 577 struct tcic_handle *h = (struct tcic_handle *) paa->pch; 578 579 /* Only "pcmcia"s can attach to "tcic"s... easy. */ 580 if (pnp) 581 printf("pcmcia at %s", pnp); 582 583 switch (h->sock) { 584 case 0: 585 printf(" socket 0"); 586 break; 587 case 1: 588 printf(" socket 1"); 589 break; 590 default: 591 panic("unknown tcic socket"); 592 } 593 return (UNCONF); 594 } 595 596 int 597 tcic_intr(arg) 598 void *arg; 599 { 600 struct tcic_softc *sc = arg; 601 int i, ret = 0; 602 603 DPRINTF(("%s: intr\n", sc->dev.dv_xname)); 604 605 for (i = 0; i < TCIC_NSLOTS; i++) 606 if (sc->handle[i].flags & TCIC_FLAG_SOCKETP) 607 ret += tcic_intr_socket(&sc->handle[i]); 608 609 return (ret ? 1 : 0); 610 } 611 612 int 613 tcic_intr_socket(h) 614 struct tcic_handle *h; 615 { 616 int icsr, rv; 617 618 rv = 0; 619 tcic_sel_sock(h); 620 icsr = tcic_read_1(h, TCIC_R_ICSR); 621 622 DPRINTF(("%s: %d icsr: 0x%02x \n", h->sc->dev.dv_xname, h->sock, icsr)); 623 624 /* XXX or should the next three be handled in tcic_intr? -chb */ 625 if (icsr & TCIC_ICSR_PROGTIME) { 626 DPRINTF(("%s: %02x PROGTIME\n", h->sc->dev.dv_xname, h->sock)); 627 rv = 1; 628 } 629 if (icsr & TCIC_ICSR_ILOCK) { 630 DPRINTF(("%s: %02x ILOCK\n", h->sc->dev.dv_xname, h->sock)); 631 rv = 1; 632 } 633 if (icsr & TCIC_ICSR_ERR) { 634 DPRINTF(("%s: %02x ERR\n", h->sc->dev.dv_xname, h->sock)); 635 rv = 1; 636 } 637 if (icsr & TCIC_ICSR_CDCHG) { 638 int sstat, delta; 639 640 /* compute what changed since last interrupt */ 641 sstat = tcic_read_aux_1(h->sc->iot, h->sc->ioh, 642 TCIC_AR_WCTL, TCIC_R_WCTL_XCSR) & TCIC_XCSR_STAT_MASK; 643 delta = h->sstat ^ sstat; 644 h->sstat = sstat; 645 646 if (delta) 647 rv = 1; 648 649 DPRINTF(("%s: %02x CDCHG %x\n", h->sc->dev.dv_xname, h->sock, 650 delta)); 651 652 /* 653 * XXX This should probably schedule something to happen 654 * after the interrupt handler completes 655 */ 656 657 if (delta & TCIC_SSTAT_CD) { 658 if (sstat & TCIC_SSTAT_CD) { 659 if (!(h->flags & TCIC_FLAG_CARDP)) { 660 DPRINTF(("%s: enqueing INSERTION event\n", 661 h->sc->dev.dv_xname)); 662 tcic_queue_event(h, TCIC_EVENT_INSERTION); 663 } 664 } else { 665 if (h->flags & TCIC_FLAG_CARDP) { 666 /* Deactivate the card now. */ 667 DPRINTF(("%s: deactivating card\n", 668 h->sc->dev.dv_xname)); 669 tcic_deactivate_card(h); 670 671 DPRINTF(("%s: enqueing REMOVAL event\n", 672 h->sc->dev.dv_xname)); 673 tcic_queue_event(h, TCIC_EVENT_REMOVAL); 674 } 675 } 676 } 677 if (delta & TCIC_SSTAT_RDY) { 678 DPRINTF(("%s: %02x READY\n", h->sc->dev.dv_xname, h->sock)); 679 /* shouldn't happen */ 680 } 681 if (delta & TCIC_SSTAT_LBAT1) { 682 DPRINTF(("%s: %02x LBAT1\n", h->sc->dev.dv_xname, h->sock)); 683 } 684 if (delta & TCIC_SSTAT_LBAT2) { 685 DPRINTF(("%s: %02x LBAT2\n", h->sc->dev.dv_xname, h->sock)); 686 } 687 if (delta & TCIC_SSTAT_WP) { 688 DPRINTF(("%s: %02x WP\n", h->sc->dev.dv_xname, h->sock)); 689 } 690 } 691 return rv; 692 } 693 694 void 695 tcic_queue_event(h, event) 696 struct tcic_handle *h; 697 int event; 698 { 699 struct tcic_event *pe; 700 int s; 701 702 pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT); 703 if (pe == NULL) 704 panic("tcic_queue_event: can't allocate event"); 705 706 pe->pe_type = event; 707 s = splhigh(); 708 SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q); 709 splx(s); 710 wakeup(&h->events); 711 } 712 void 713 tcic_attach_card(h) 714 struct tcic_handle *h; 715 { 716 DPRINTF(("tcic_attach_card\n")); 717 718 if (h->flags & TCIC_FLAG_CARDP) 719 panic("tcic_attach_card: already attached"); 720 721 /* call the MI attach function */ 722 723 pcmcia_card_attach(h->pcmcia); 724 725 h->flags |= TCIC_FLAG_CARDP; 726 } 727 728 void 729 tcic_detach_card(h, flags) 730 struct tcic_handle *h; 731 int flags; /* DETACH_* */ 732 { 733 DPRINTF(("tcic_detach_card\n")); 734 735 if (!(h->flags & TCIC_FLAG_CARDP)) 736 panic("tcic_detach_card: already detached"); 737 738 h->flags &= ~TCIC_FLAG_CARDP; 739 740 /* call the MI detach function */ 741 742 pcmcia_card_detach(h->pcmcia, flags); 743 744 } 745 746 void 747 tcic_deactivate_card(h) 748 struct tcic_handle *h; 749 { 750 int val, reg; 751 752 if (!(h->flags & TCIC_FLAG_CARDP)) 753 panic("tcic_deactivate_card: already detached"); 754 755 /* call the MI deactivate function */ 756 pcmcia_card_deactivate(h->pcmcia); 757 758 tcic_sel_sock(h); 759 760 /* XXX disable card detect resume and configuration reset??? */ 761 762 /* power down the socket */ 763 tcic_write_1(h, TCIC_R_PWR, 0); 764 765 /* reset the card XXX ? -chb */ 766 767 /* turn off irq's for this socket */ 768 reg = TCIC_IR_SCF1_N(h->sock); 769 val = tcic_read_ind_2(h, reg); 770 tcic_write_ind_2(h, reg, (val & ~TCIC_SCF1_IRQ_MASK)|TCIC_SCF1_IRQOFF); 771 reg = TCIC_IR_SCF2_N(h->sock); 772 val = tcic_read_ind_2(h, reg); 773 tcic_write_ind_2(h, reg, 774 (val | (TCIC_SCF2_MLBAT1|TCIC_SCF2_MLBAT2|TCIC_SCF2_MRDY 775 |TCIC_SCF2_MWP|TCIC_SCF2_MCD))); 776 } 777 778 /* XXX the following routine may need to be rewritten. -chb */ 779 int 780 tcic_chip_mem_alloc(pch, size, pcmhp) 781 pcmcia_chipset_handle_t pch; 782 bus_size_t size; 783 struct pcmcia_mem_handle *pcmhp; 784 { 785 struct tcic_handle *h = (struct tcic_handle *) pch; 786 bus_space_handle_t memh; 787 bus_addr_t addr; 788 bus_size_t sizepg; 789 int i, mask, mhandle; 790 791 /* out of sc->memh, allocate as many pages as necessary */ 792 793 /* 794 * The TCIC can map memory only in sizes that are 795 * powers of two, aligned at the natural boundary for the size. 796 */ 797 i = tcic_log2((u_int)size); 798 if ((1<<i) < size) 799 i++; 800 sizepg = max(i, TCIC_MEM_SHIFT) - (TCIC_MEM_SHIFT-1); 801 802 DPRINTF(("tcic_chip_mem_alloc: size %ld sizepg %ld\n", size, sizepg)); 803 804 /* can't allocate that much anyway */ 805 if (sizepg > TCIC_MEM_PAGES) /* XXX -chb */ 806 return 1; 807 808 mask = (1 << sizepg) - 1; 809 810 addr = 0; /* XXX gcc -Wuninitialized */ 811 mhandle = 0; /* XXX gcc -Wuninitialized */ 812 813 /* XXX i should be initialised to always lay on boundary. -chb */ 814 for (i = 0; i < (TCIC_MEM_PAGES + 1 - sizepg); i += sizepg) { 815 if ((h->sc->subregionmask & (mask << i)) == (mask << i)) { 816 if (bus_space_subregion(h->sc->memt, h->sc->memh, 817 i * TCIC_MEM_PAGESIZE, 818 sizepg * TCIC_MEM_PAGESIZE, &memh)) 819 return (1); 820 mhandle = mask << i; 821 addr = h->sc->membase + (i * TCIC_MEM_PAGESIZE); 822 h->sc->subregionmask &= ~(mhandle); 823 break; 824 } 825 } 826 827 if (i == (TCIC_MEM_PAGES + 1 - sizepg)) 828 return (1); 829 830 DPRINTF(("tcic_chip_mem_alloc bus addr 0x%lx+0x%lx\n", (u_long) addr, 831 (u_long) size)); 832 833 pcmhp->memt = h->sc->memt; 834 pcmhp->memh = memh; 835 pcmhp->addr = addr; 836 pcmhp->size = size; 837 pcmhp->mhandle = mhandle; 838 pcmhp->realsize = sizepg * TCIC_MEM_PAGESIZE; 839 840 return (0); 841 } 842 843 /* XXX the following routine may need to be rewritten. -chb */ 844 void 845 tcic_chip_mem_free(pch, pcmhp) 846 pcmcia_chipset_handle_t pch; 847 struct pcmcia_mem_handle *pcmhp; 848 { 849 struct tcic_handle *h = (struct tcic_handle *) pch; 850 851 h->sc->subregionmask |= pcmhp->mhandle; 852 } 853 854 void 855 tcic_chip_do_mem_map(h, win) 856 struct tcic_handle *h; 857 int win; 858 { 859 int reg, hwwin, wscnt; 860 861 int kind = h->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 862 int mem8 = (h->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8; 863 DPRINTF(("tcic_chip_do_mem_map window %d: 0x%lx+0x%lx 0x%lx\n", 864 win, (u_long)h->mem[win].addr, (u_long)h->mem[win].size, 865 (u_long)h->mem[win].offset)); 866 /* 867 * the even windows are used for socket 0, 868 * the odd ones for socket 1. 869 */ 870 hwwin = (win << 1) + h->sock; 871 872 /* the WR_MEXT register is MBZ */ 873 tcic_write_ind_2(h, TCIC_WR_MEXT_N(hwwin), 0); 874 875 /* set the host base address and window size */ 876 if (h->mem[win].size2 <= 1) { 877 reg = ((h->mem[win].addr >> TCIC_MEM_SHIFT) & 878 TCIC_MBASE_ADDR_MASK) | TCIC_MBASE_4K; 879 } else { 880 reg = ((h->mem[win].addr >> TCIC_MEM_SHIFT) & 881 TCIC_MBASE_ADDR_MASK) | (h->mem[win].size2 >> 1); 882 } 883 tcic_write_ind_2(h, TCIC_WR_MBASE_N(hwwin), reg); 884 885 /* set the card address and address space */ 886 reg = 0; 887 reg = ((h->mem[win].offset >> TCIC_MEM_SHIFT) & TCIC_MMAP_ADDR_MASK); 888 reg |= (kind == PCMCIA_MEM_ATTR) ? TCIC_MMAP_ATTR : 0; 889 DPRINTF(("tcic_chip_do_map_mem window %d(%d) mmap 0x%04x\n", 890 win, hwwin, reg)); 891 tcic_write_ind_2(h, TCIC_WR_MMAP_N(hwwin), reg); 892 893 /* set the MCTL register */ 894 /* must save WSCNT field in case this is a DB86082 rev 0 */ 895 /* XXX why can't I do the following two in one statement? */ 896 reg = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin)) & TCIC_MCTL_WSCNT_MASK; 897 reg |= TCIC_MCTL_ENA|TCIC_MCTL_QUIET; 898 reg |= mem8 ? TCIC_MCTL_B8 : 0; 899 reg |= (h->sock << TCIC_MCTL_SS_SHIFT) & TCIC_MCTL_SS_MASK; 900 #ifdef notyet /* XXX must get speed from CIS somehow. -chb */ 901 wscnt = tcic_ns2wscnt(h->mem[win].speed); 902 #else 903 wscnt = tcic_ns2wscnt(tcic_mem_speed); /* 300 is "save" default for CIS memory */ 904 #endif 905 if (h->sc->chipid == TCIC_CHIPID_DB86082_1) { 906 /* 907 * this chip has the wait state count in window 908 * register 7 - hwwin. 909 */ 910 int reg2; 911 reg2 = tcic_read_ind_2(h, TCIC_WR_MCTL_N(7-hwwin)); 912 reg2 &= ~TCIC_MCTL_WSCNT_MASK; 913 reg2 |= wscnt & TCIC_MCTL_WSCNT_MASK; 914 tcic_write_ind_2(h, TCIC_WR_MCTL_N(7-hwwin), reg2); 915 } else { 916 reg |= wscnt & TCIC_MCTL_WSCNT_MASK; 917 } 918 tcic_write_ind_2(h, TCIC_WR_MCTL_N(hwwin), reg); 919 920 #ifdef TCICDEBUG 921 { 922 int r1, r2, r3; 923 924 r1 = tcic_read_ind_2(h, TCIC_WR_MBASE_N(hwwin)); 925 r2 = tcic_read_ind_2(h, TCIC_WR_MMAP_N(hwwin)); 926 r3 = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin)); 927 928 DPRINTF(("tcic_chip_do_mem_map window %d(%d): %04x %04x %04x\n", 929 win, hwwin, r1, r2, r3)); 930 } 931 #endif 932 } 933 934 /* XXX needs work */ 935 int 936 tcic_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 937 pcmcia_chipset_handle_t pch; 938 int kind; 939 bus_addr_t card_addr; 940 bus_size_t size; 941 struct pcmcia_mem_handle *pcmhp; 942 bus_addr_t *offsetp; 943 int *windowp; 944 { 945 struct tcic_handle *h = (struct tcic_handle *) pch; 946 bus_addr_t busaddr; 947 long card_offset; 948 int i, win; 949 950 win = -1; 951 for (i = 0; i < h->memwins; i++) { 952 if ((h->memalloc & (1 << i)) == 0) { 953 win = i; 954 h->memalloc |= (1 << i); 955 break; 956 } 957 } 958 959 if (win == -1) 960 return (1); 961 962 *windowp = win; 963 964 /* XXX this is pretty gross */ 965 966 if (h->sc->memt != pcmhp->memt) 967 panic("tcic_chip_mem_map memt is bogus"); 968 969 busaddr = pcmhp->addr; 970 971 /* 972 * compute the address offset to the pcmcia address space for the 973 * tcic. this is intentionally signed. The masks and shifts below 974 * will cause TRT to happen in the tcic registers. Deal with making 975 * sure the address is aligned, and return the alignment offset. 976 */ 977 978 *offsetp = card_addr % TCIC_MEM_ALIGN; 979 card_addr -= *offsetp; 980 981 DPRINTF(("tcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 982 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 983 (u_long) card_addr)); 984 985 /* XXX we can't use size. -chb */ 986 /* 987 * include the offset in the size, and decrement size by one, since 988 * the hw wants start/stop 989 */ 990 size += *offsetp - 1; 991 992 card_offset = (((long) card_addr) - ((long) busaddr)); 993 994 DPRINTF(("tcic_chip_mem_map window %d card_offset 0x%lx\n", 995 win, (u_long)card_offset)); 996 997 h->mem[win].addr = busaddr; 998 h->mem[win].size = size; 999 h->mem[win].size2 = tcic_log2((u_int)pcmhp->realsize) - TCIC_MEM_SHIFT; 1000 h->mem[win].offset = card_offset; 1001 h->mem[win].kind = kind; 1002 1003 tcic_chip_do_mem_map(h, win); 1004 1005 return (0); 1006 } 1007 1008 void 1009 tcic_chip_mem_unmap(pch, window) 1010 pcmcia_chipset_handle_t pch; 1011 int window; 1012 { 1013 struct tcic_handle *h = (struct tcic_handle *) pch; 1014 int reg, hwwin; 1015 1016 if (window >= h->memwins) 1017 panic("tcic_chip_mem_unmap: window out of range"); 1018 1019 hwwin = (window << 1) + h->sock; 1020 reg = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin)); 1021 reg &= ~TCIC_MCTL_ENA; 1022 tcic_write_ind_2(h, TCIC_WR_MCTL_N(hwwin), reg); 1023 1024 h->memalloc &= ~(1 << window); 1025 } 1026 1027 int 1028 tcic_chip_io_alloc(pch, start, size, align, pcihp) 1029 pcmcia_chipset_handle_t pch; 1030 bus_addr_t start; 1031 bus_size_t size; 1032 bus_size_t align; 1033 struct pcmcia_io_handle *pcihp; 1034 { 1035 struct tcic_handle *h = (struct tcic_handle *) pch; 1036 bus_space_tag_t iot; 1037 bus_space_handle_t ioh; 1038 bus_addr_t ioaddr; 1039 int size2, flags = 0; 1040 1041 /* 1042 * Allocate some arbitrary I/O space. 1043 */ 1044 1045 DPRINTF(("tcic_chip_io_alloc req 0x%lx %ld %ld\n", 1046 (u_long) start, (u_long) size, (u_long) align)); 1047 /* 1048 * The TCIC can map I/O space only in sizes that are 1049 * powers of two, aligned at the natural boundary for the size. 1050 */ 1051 size2 = tcic_log2((u_int)size); 1052 if ((1 << size2) < size) 1053 size2++; 1054 /* can't allocate that much anyway */ 1055 if (size2 > 16) /* XXX 64K -chb */ 1056 return 1; 1057 if (align) { 1058 if ((1 << size2) != align) 1059 return 1; /* not suitably aligned */ 1060 } else { 1061 align = 1 << size2; /* no alignment given, make it natural */ 1062 } 1063 if (start & (align - 1)) 1064 return 1; /* not suitably aligned */ 1065 1066 iot = h->sc->iot; 1067 1068 if (start) { 1069 ioaddr = start; 1070 if (bus_space_map(iot, start, size, 0, &ioh)) 1071 return (1); 1072 DPRINTF(("tcic_chip_io_alloc map port %lx+%lx\n", 1073 (u_long) ioaddr, (u_long) size)); 1074 } else { 1075 flags |= PCMCIA_IO_ALLOCATED; 1076 if (bus_space_alloc(iot, h->sc->iobase, 1077 h->sc->iobase + h->sc->iosize, size, align, 0, 0, 1078 &ioaddr, &ioh)) 1079 return (1); 1080 DPRINTF(("tcic_chip_io_alloc alloc port %lx+%lx\n", 1081 (u_long) ioaddr, (u_long) size)); 1082 } 1083 1084 pcihp->iot = iot; 1085 pcihp->ioh = ioh; 1086 pcihp->addr = ioaddr; 1087 pcihp->size = size; 1088 pcihp->flags = flags; 1089 1090 return (0); 1091 } 1092 1093 void 1094 tcic_chip_io_free(pch, pcihp) 1095 pcmcia_chipset_handle_t pch; 1096 struct pcmcia_io_handle *pcihp; 1097 { 1098 bus_space_tag_t iot = pcihp->iot; 1099 bus_space_handle_t ioh = pcihp->ioh; 1100 bus_size_t size = pcihp->size; 1101 1102 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1103 bus_space_free(iot, ioh, size); 1104 else 1105 bus_space_unmap(iot, ioh, size); 1106 } 1107 1108 static int tcic_iowidth_map[] = 1109 { TCIC_ICTL_AUTOSZ, TCIC_ICTL_B8, TCIC_ICTL_B16 }; 1110 1111 void 1112 tcic_chip_do_io_map(h, win) 1113 struct tcic_handle *h; 1114 int win; 1115 { 1116 int reg, size2, iotiny, wbase, hwwin, wscnt; 1117 1118 DPRINTF(("tcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 1119 win, (long) h->io[win].addr, (long) h->io[win].size, 1120 h->io[win].width * 8)); 1121 1122 /* 1123 * the even windows are used for socket 0, 1124 * the odd ones for socket 1. 1125 */ 1126 hwwin = (win << 1) + h->sock; 1127 1128 /* set the WR_BASE register */ 1129 /* XXX what if size isn't power of 2? -chb */ 1130 size2 = tcic_log2((u_int)h->io[win].size); 1131 DPRINTF(("tcic_chip_do_io_map win %d size2 %d\n", win, size2)); 1132 if (size2 < 1) { 1133 iotiny = TCIC_ICTL_TINY; 1134 wbase = h->io[win].addr; 1135 } else { 1136 iotiny = 0; 1137 /* XXX we should do better -chb */ 1138 wbase = h->io[win].addr | (1 << (size2 - 1)); 1139 } 1140 tcic_write_ind_2(h, TCIC_WR_IBASE_N(hwwin), wbase); 1141 1142 /* set the WR_ICTL register */ 1143 reg = TCIC_ICTL_ENA | TCIC_ICTL_QUIET; 1144 reg |= (h->sock << TCIC_ICTL_SS_SHIFT) & TCIC_ICTL_SS_MASK; 1145 reg |= iotiny | tcic_iowidth_map[h->io[win].width]; 1146 if (h->sc->chipid != TCIC_CHIPID_DB86082_1) 1147 reg |= TCIC_ICTL_PASS16; 1148 #ifdef notyet /* XXX must get speed from CIS somehow. -chb */ 1149 wscnt = tcic_ns2wscnt(h->io[win].speed); 1150 #else 1151 wscnt = tcic_ns2wscnt(tcic_io_speed); /* linux uses 0 as default */ 1152 #endif 1153 reg |= wscnt & TCIC_ICTL_WSCNT_MASK; 1154 tcic_write_ind_2(h, TCIC_WR_ICTL_N(hwwin), reg); 1155 1156 #ifdef TCICDEBUG 1157 { 1158 int r1, r2; 1159 1160 r1 = tcic_read_ind_2(h, TCIC_WR_IBASE_N(hwwin)); 1161 r2 = tcic_read_ind_2(h, TCIC_WR_ICTL_N(hwwin)); 1162 1163 DPRINTF(("tcic_chip_do_io_map window %d(%d): %04x %04x\n", 1164 win, hwwin, r1, r2)); 1165 } 1166 #endif 1167 } 1168 1169 int 1170 tcic_chip_io_map(pch, width, offset, size, pcihp, windowp) 1171 pcmcia_chipset_handle_t pch; 1172 int width; 1173 bus_addr_t offset; 1174 bus_size_t size; 1175 struct pcmcia_io_handle *pcihp; 1176 int *windowp; 1177 { 1178 struct tcic_handle *h = (struct tcic_handle *) pch; 1179 bus_addr_t ioaddr = pcihp->addr + offset; 1180 int i, win; 1181 #ifdef TCICDEBUG 1182 static char *width_names[] = { "auto", "io8", "io16" }; 1183 #endif 1184 1185 /* XXX Sanity check offset/size. */ 1186 1187 win = -1; 1188 for (i = 0; i < TCIC_IO_WINS; i++) { 1189 if ((h->ioalloc & (1 << i)) == 0) { 1190 win = i; 1191 h->ioalloc |= (1 << i); 1192 break; 1193 } 1194 } 1195 1196 if (win == -1) 1197 return (1); 1198 1199 *windowp = win; 1200 1201 /* XXX this is pretty gross */ 1202 1203 if (h->sc->iot != pcihp->iot) 1204 panic("tcic_chip_io_map iot is bogus"); 1205 1206 DPRINTF(("tcic_chip_io_map window %d %s port %lx+%lx\n", 1207 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1208 1209 /* XXX wtf is this doing here? */ 1210 1211 printf(" port 0x%lx", (u_long) ioaddr); 1212 if (size > 1) 1213 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1214 1215 h->io[win].addr = ioaddr; 1216 h->io[win].size = size; 1217 h->io[win].width = width; 1218 1219 tcic_chip_do_io_map(h, win); 1220 1221 return (0); 1222 } 1223 1224 void 1225 tcic_chip_io_unmap(pch, window) 1226 pcmcia_chipset_handle_t pch; 1227 int window; 1228 { 1229 struct tcic_handle *h = (struct tcic_handle *) pch; 1230 int reg, hwwin; 1231 1232 if (window >= TCIC_IO_WINS) 1233 panic("tcic_chip_io_unmap: window out of range"); 1234 1235 hwwin = (window << 1) + h->sock; 1236 reg = tcic_read_ind_2(h, TCIC_WR_ICTL_N(hwwin)); 1237 reg &= ~TCIC_ICTL_ENA; 1238 tcic_write_ind_2(h, TCIC_WR_ICTL_N(hwwin), reg); 1239 1240 h->ioalloc &= ~(1 << window); 1241 } 1242 1243 void 1244 tcic_chip_socket_enable(pch) 1245 pcmcia_chipset_handle_t pch; 1246 { 1247 struct tcic_handle *h = (struct tcic_handle *) pch; 1248 int cardtype, reg, win; 1249 1250 tcic_sel_sock(h); 1251 1252 /* 1253 * power down the socket to reset it. 1254 * put card reset into high-z, put chip outputs to card into high-z 1255 */ 1256 1257 tcic_write_1(h, TCIC_R_PWR, 0); 1258 reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1259 reg |= TCIC_ILOCK_CWAIT; 1260 reg &= ~(TCIC_ILOCK_CRESET|TCIC_ILOCK_CRESENA); 1261 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1262 tcic_write_1(h, TCIC_R_SCTRL, 0); /* clear TCIC_SCTRL_ENA */ 1263 1264 /* power up the socket */ 1265 1266 /* turn on VCC, turn of VPP */ 1267 reg = TCIC_PWR_VCC_N(h->sock) | TCIC_PWR_VPP_N(h->sock) | h->sc->pwrena; 1268 if (h->sc->pwrena) /* this is a '84 type chip */ 1269 reg |= TCIC_PWR_VCC5V; 1270 tcic_write_1(h, TCIC_R_PWR, reg); 1271 delay(10000); 1272 1273 /* enable reset and wiggle it to reset the card */ 1274 reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1275 reg |= TCIC_ILOCK_CRESENA; 1276 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1277 /* XXX need bus_space_barrier here */ 1278 reg |= TCIC_ILOCK_CRESET; 1279 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1280 /* enable card signals */ 1281 tcic_write_1(h, TCIC_R_SCTRL, TCIC_SCTRL_ENA); 1282 delay(10); /* wait 10 us */ 1283 1284 /* clear the reset flag */ 1285 reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1286 reg &= ~(TCIC_ILOCK_CRESET); 1287 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1288 1289 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1290 delay(20000); 1291 1292 /* wait for the chip to finish initializing */ 1293 tcic_wait_ready(h); 1294 1295 /* WWW */ 1296 /* zero out the address windows */ 1297 1298 /* writing to WR_MBASE_N disables the window */ 1299 for (win = 0; win < h->memwins; win++) { 1300 tcic_write_ind_2(h, TCIC_WR_MBASE_N((win<<1)+h->sock), 0); 1301 } 1302 /* writing to WR_IBASE_N disables the window */ 1303 for (win = 0; win < TCIC_IO_WINS; win++) { 1304 tcic_write_ind_2(h, TCIC_WR_IBASE_N((win<<1)+h->sock), 0); 1305 } 1306 1307 /* set the card type */ 1308 1309 cardtype = pcmcia_card_gettype(h->pcmcia); 1310 1311 #if 0 1312 reg = tcic_read_ind_2(h, TCIC_IR_SCF1_N(h->sock)); 1313 reg &= ~TCIC_SCF1_IRQ_MASK; 1314 #else 1315 reg = 0; 1316 #endif 1317 reg |= ((cardtype == PCMCIA_IFTYPE_IO) ? 1318 TCIC_SCF1_IOSTS : 0); 1319 reg |= tcic_irqmap[h->ih_irq]; /* enable interrupts */ 1320 reg &= ~TCIC_SCF1_IRQOD; 1321 tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), reg); 1322 1323 DPRINTF(("%s: tcic_chip_socket_enable %d cardtype %s 0x%02x\n", 1324 h->sc->dev.dv_xname, h->sock, 1325 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg)); 1326 1327 /* reinstall all the memory and io mappings */ 1328 1329 for (win = 0; win < h->memwins; win++) 1330 if (h->memalloc & (1 << win)) 1331 tcic_chip_do_mem_map(h, win); 1332 1333 for (win = 0; win < TCIC_IO_WINS; win++) 1334 if (h->ioalloc & (1 << win)) 1335 tcic_chip_do_io_map(h, win); 1336 } 1337 1338 void 1339 tcic_chip_socket_disable(pch) 1340 pcmcia_chipset_handle_t pch; 1341 { 1342 struct tcic_handle *h = (struct tcic_handle *) pch; 1343 int val; 1344 1345 DPRINTF(("tcic_chip_socket_disable\n")); 1346 1347 tcic_sel_sock(h); 1348 1349 /* disable interrupts */ 1350 val = tcic_read_ind_2(h, TCIC_IR_SCF1_N(h->sock)); 1351 val &= TCIC_SCF1_IRQ_MASK; 1352 tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), val); 1353 1354 /* disable the output signals */ 1355 tcic_write_1(h, TCIC_R_SCTRL, 0); 1356 val = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1357 val &= ~TCIC_ILOCK_CRESENA; 1358 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, val); 1359 1360 /* power down the socket */ 1361 tcic_write_1(h, TCIC_R_PWR, 0); 1362 } 1363 1364 /* 1365 * XXX The following is Linux driver but doesn't match the table 1366 * in the manual. 1367 */ 1368 int 1369 tcic_ns2wscnt(ns) 1370 int ns; 1371 { 1372 if (ns < 14) { 1373 return 0; 1374 } else { 1375 return (2*(ns-14))/70; /* XXX assumes 14.31818 MHz clock. */ 1376 } 1377 } 1378 1379 int 1380 tcic_log2(val) 1381 u_int val; 1382 { 1383 int i, l2; 1384 1385 l2 = i = 0; 1386 while (val) { 1387 if (val & 1) 1388 l2 = i; 1389 i++; 1390 val >>= 1; 1391 } 1392 return l2; 1393 } 1394