1 /* $NetBSD: tcic2.c,v 1.7 2001/11/13 13:14:45 lukem Exp $ */ 2 3 /* 4 * Copyright (c) 1998, 1999 Christoph Badura. All rights reserved. 5 * Copyright (c) 1997 Marc Horowitz. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Marc Horowitz. 18 * 4. The name of the author may not be used to endorse or promote products 19 * derived from this software without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 22 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 23 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 24 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 25 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 26 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 27 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 28 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 29 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 30 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 #include <sys/cdefs.h> 34 __KERNEL_RCSID(0, "$NetBSD: tcic2.c,v 1.7 2001/11/13 13:14:45 lukem Exp $"); 35 36 #undef TCICDEBUG 37 38 #include <sys/types.h> 39 #include <sys/param.h> 40 #include <sys/systm.h> 41 #include <sys/device.h> 42 #include <sys/extent.h> 43 #include <sys/malloc.h> 44 #include <sys/kthread.h> 45 46 #include <machine/bus.h> 47 #include <machine/intr.h> 48 49 #include <dev/pcmcia/pcmciareg.h> 50 #include <dev/pcmcia/pcmciavar.h> 51 52 #include <dev/ic/tcic2reg.h> 53 #include <dev/ic/tcic2var.h> 54 55 #include "locators.h" 56 57 #ifdef TCICDEBUG 58 int tcic_debug = 1; 59 #define DPRINTF(arg) if (tcic_debug) printf arg; 60 #else 61 #define DPRINTF(arg) 62 #endif 63 64 /* 65 * Individual drivers will allocate their own memory and io regions. Memory 66 * regions must be a multiple of 4k, aligned on a 4k boundary. 67 */ 68 69 #define TCIC_MEM_ALIGN TCIC_MEM_PAGESIZE 70 71 void tcic_attach_socket __P((struct tcic_handle *)); 72 void tcic_init_socket __P((struct tcic_handle *)); 73 74 int tcic_submatch __P((struct device *, struct cfdata *, void *)); 75 int tcic_print __P((void *arg, const char *pnp)); 76 int tcic_intr_socket __P((struct tcic_handle *)); 77 78 void tcic_attach_card __P((struct tcic_handle *)); 79 void tcic_detach_card __P((struct tcic_handle *, int)); 80 void tcic_deactivate_card __P((struct tcic_handle *)); 81 82 void tcic_chip_do_mem_map __P((struct tcic_handle *, int)); 83 void tcic_chip_do_io_map __P((struct tcic_handle *, int)); 84 85 void tcic_create_event_thread __P((void *)); 86 void tcic_event_thread __P((void *)); 87 88 void tcic_queue_event __P((struct tcic_handle *, int)); 89 90 /* Map between irq numbers and internal representation */ 91 #if 1 92 int tcic_irqmap[] = 93 { 0, 0, 0, 3, 4, 5, 6, 7, 0, 0, 10, 1, 0, 0, 14, 0 }; 94 int tcic_valid_irqs = 0x4cf8; 95 #else 96 int tcic_irqmap[] = /* irqs 9 and 6 switched, some ISA cards */ 97 { 0, 0, 0, 3, 4, 5, 0, 7, 0, 6, 10, 1, 0, 0, 14, 0 }; 98 int tcic_valid_irqs = 0x4eb8; 99 #endif 100 101 int tcic_mem_speed = 250; /* memory access time in nanoseconds */ 102 int tcic_io_speed = 165; /* io access time in nanoseconds */ 103 104 /* 105 * Check various reserved and otherwise in their value restricted bits. 106 */ 107 int 108 tcic_check_reserved_bits(iot, ioh) 109 bus_space_tag_t iot; 110 bus_space_handle_t ioh; 111 { 112 int val, auxreg; 113 114 DPRINTF(("tcic: chkrsvd 1\n")); 115 /* R_ADDR bit 30:28 have a restricted range. */ 116 val = (bus_space_read_2(iot, ioh, TCIC_R_ADDR2) & TCIC_SS_MASK) 117 >> TCIC_SS_SHIFT; 118 if (val > 1) 119 return 0; 120 121 DPRINTF(("tcic: chkrsvd 2\n")); 122 /* R_SCTRL bits 6,2,1 are reserved. */ 123 val = bus_space_read_1(iot, ioh, TCIC_R_SCTRL); 124 if (val & TCIC_SCTRL_RSVD) 125 return 0; 126 127 DPRINTF(("tcic: chkrsvd 3\n")); 128 /* R_ICSR bit 2 must be same as bit 3. */ 129 val = bus_space_read_1(iot, ioh, TCIC_R_ICSR); 130 if (((val >> 1) & 1) != ((val >> 2) & 1)) 131 return 0; 132 133 DPRINTF(("tcic: chkrsvd 4\n")); 134 /* R_IENA bits 7,2 are reserverd. */ 135 val = bus_space_read_1(iot, ioh, TCIC_R_IENA); 136 if (val & TCIC_IENA_RSVD) 137 return 0; 138 139 DPRINTF(("tcic: chkrsvd 5\n")); 140 /* Some aux registers have reserved bits. */ 141 /* Which are we looking at? */ 142 auxreg = bus_space_read_1(iot, ioh, TCIC_R_MODE) 143 & TCIC_AR_MASK; 144 val = bus_space_read_2(iot, ioh, TCIC_R_AUX); 145 DPRINTF(("tcic: auxreg 0x%02x val 0x%04x\n", auxreg, val)); 146 switch (auxreg) { 147 case TCIC_AR_SYSCFG: 148 if (INVALID_AR_SYSCFG(val)) 149 return 0; 150 break; 151 case TCIC_AR_ILOCK: 152 if (INVALID_AR_ILOCK(val)) 153 return 0; 154 break; 155 case TCIC_AR_TEST: 156 if (INVALID_AR_TEST(val)) 157 return 0; 158 break; 159 } 160 161 DPRINTF(("tcic: chkrsvd 6\n")); 162 /* XXX fails if pcmcia bios is enabled. */ 163 /* Various bits set or not depending if in RESET mode. */ 164 val = bus_space_read_1(iot, ioh, TCIC_R_SCTRL); 165 if (val & TCIC_SCTRL_RESET) { 166 DPRINTF(("tcic: chkrsvd 7\n")); 167 /* Address bits must be 0 */ 168 val = bus_space_read_2(iot, ioh, TCIC_R_ADDR); 169 if (val != 0) 170 return 0; 171 val = bus_space_read_2(iot, ioh, TCIC_R_ADDR2); 172 if (val != 0) 173 return 0; 174 DPRINTF(("tcic: chkrsvd 8\n")); 175 /* EDC bits must be 0 */ 176 val = bus_space_read_2(iot, ioh, TCIC_R_EDC); 177 if (val != 0) 178 return 0; 179 /* We're OK, so take it out of reset. XXX -chb */ 180 bus_space_write_1(iot, ioh, TCIC_R_SCTRL, 0); 181 } 182 else { /* not in RESET mode */ 183 int omode; 184 int val1, val2; 185 DPRINTF(("tcic: chkrsvd 9\n")); 186 /* Programming timers must have expired. */ 187 val = bus_space_read_1(iot, ioh, TCIC_R_SSTAT); 188 if ((val & (TCIC_SSTAT_6US|TCIC_SSTAT_10US|TCIC_SSTAT_PROGTIME)) 189 != (TCIC_SSTAT_6US|TCIC_SSTAT_10US|TCIC_SSTAT_PROGTIME)) 190 return 0; 191 DPRINTF(("tcic: chkrsvd 10\n")); 192 /* 193 * EDC bits should change on read from data space 194 * as long as either EDC or the data are nonzero. 195 */ 196 if ((bus_space_read_2(iot, ioh, TCIC_R_ADDR2) 197 & TCIC_ADDR2_INDREG) != 0) { 198 val1 = bus_space_read_2(iot, ioh, TCIC_R_EDC); 199 val2 = bus_space_read_2(iot, ioh, TCIC_R_DATA); 200 if (val1 | val2) { 201 val1 = bus_space_read_2(iot, ioh, TCIC_R_EDC); 202 if (val1 == val2) 203 return 0; 204 } 205 } 206 DPRINTF(("tcic: chkrsvd 11\n")); 207 /* XXX what does this check? -chb */ 208 omode = bus_space_read_1(iot, ioh, TCIC_R_MODE); 209 val1 = omode ^ TCIC_AR_MASK; 210 bus_space_write_1(iot, ioh, TCIC_R_MODE, val1); 211 val2 = bus_space_read_1(iot, ioh, TCIC_R_MODE); 212 bus_space_write_1(iot, ioh, TCIC_R_MODE, omode); 213 if ( val1 != val2) 214 return 0; 215 } 216 /* All tests passed */ 217 return 1; 218 } 219 220 /* 221 * Read chip ID from AR_ILOCK in test mode. 222 */ 223 int 224 tcic_chipid(iot, ioh) 225 bus_space_tag_t iot; 226 bus_space_handle_t ioh; 227 { 228 unsigned id, otest; 229 230 otest = tcic_read_aux_2(iot, ioh, TCIC_AR_TEST); 231 tcic_write_aux_2(iot, ioh, TCIC_AR_TEST, TCIC_TEST_DIAG); 232 id = tcic_read_aux_2(iot, ioh, TCIC_AR_ILOCK); 233 tcic_write_aux_2(iot, ioh, TCIC_AR_TEST, otest); 234 id &= TCIC_ILOCKTEST_ID_MASK; 235 id >>= TCIC_ILOCKTEST_ID_SHFT; 236 237 /* clear up IRQs inside tcic. XXX -chb */ 238 while (bus_space_read_1(iot, ioh, TCIC_R_ICSR)) 239 bus_space_write_1(iot, ioh, TCIC_R_ICSR, TCIC_ICSR_JAM); 240 241 return id; 242 } 243 /* 244 * Indicate whether the driver can handle the chip. 245 */ 246 int 247 tcic_chipid_known(id) 248 int id; 249 { 250 /* XXX only know how to handle DB86082 -chb */ 251 switch (id) { 252 case TCIC_CHIPID_DB86082_1: 253 case TCIC_CHIPID_DB86082A: 254 case TCIC_CHIPID_DB86082B_ES: 255 case TCIC_CHIPID_DB86082B: 256 case TCIC_CHIPID_DB86084_1: 257 case TCIC_CHIPID_DB86084A: 258 case TCIC_CHIPID_DB86184_1: 259 case TCIC_CHIPID_DB86072_1_ES: 260 case TCIC_CHIPID_DB86072_1: 261 return 1; 262 } 263 264 return 0; 265 } 266 267 char * 268 tcic_chipid_to_string(id) 269 int id; 270 { 271 switch (id) { 272 case TCIC_CHIPID_DB86082_1: 273 return ("Databook DB86082"); 274 case TCIC_CHIPID_DB86082A: 275 return ("Databook DB86082A"); 276 case TCIC_CHIPID_DB86082B_ES: 277 return ("Databook DB86082B-es"); 278 case TCIC_CHIPID_DB86082B: 279 return ("Databook DB86082B"); 280 case TCIC_CHIPID_DB86084_1: 281 return ("Databook DB86084"); 282 case TCIC_CHIPID_DB86084A: 283 return ("Databook DB86084A"); 284 case TCIC_CHIPID_DB86184_1: 285 return ("Databook DB86184"); 286 case TCIC_CHIPID_DB86072_1_ES: 287 return ("Databook DB86072-es"); 288 case TCIC_CHIPID_DB86072_1: 289 return ("Databook DB86072"); 290 } 291 292 return ("Unknown controller"); 293 } 294 /* 295 * Return bitmask of IRQs that the chip can handle. 296 * XXX should be table driven. 297 */ 298 int 299 tcic_validirqs(chipid) 300 int chipid; 301 { 302 switch (chipid) { 303 case TCIC_CHIPID_DB86082_1: 304 case TCIC_CHIPID_DB86082A: 305 case TCIC_CHIPID_DB86082B_ES: 306 case TCIC_CHIPID_DB86082B: 307 case TCIC_CHIPID_DB86084_1: 308 case TCIC_CHIPID_DB86084A: 309 case TCIC_CHIPID_DB86184_1: 310 case TCIC_CHIPID_DB86072_1_ES: 311 case TCIC_CHIPID_DB86072_1: 312 return tcic_valid_irqs; 313 } 314 return 0; 315 } 316 317 void 318 tcic_attach(sc) 319 struct tcic_softc *sc; 320 { 321 int i, reg; 322 323 /* set more chipset dependend parameters in the softc. */ 324 switch (sc->chipid) { 325 case TCIC_CHIPID_DB86084_1: 326 case TCIC_CHIPID_DB86084A: 327 case TCIC_CHIPID_DB86184_1: 328 sc->pwrena = TCIC_PWR_ENA; 329 break; 330 default: 331 sc->pwrena = 0; 332 break; 333 } 334 335 /* set up global config registers */ 336 reg = TCIC_WAIT_SYNC | TCIC_WAIT_CCLK | TCIC_WAIT_RISING; 337 reg |= (tcic_ns2wscnt(250) & TCIC_WAIT_COUNT_MASK); 338 tcic_write_aux_1(sc->iot, sc->ioh, TCIC_AR_WCTL, TCIC_R_WCTL_WAIT, reg); 339 reg = TCIC_SYSCFG_MPSEL_RI | TCIC_SYSCFG_MCSFULL; 340 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, reg); 341 reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_ILOCK); 342 reg |= TCIC_ILOCK_HOLD_CCLK; 343 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_ILOCK, reg); 344 345 /* the TCIC has two sockets */ 346 /* XXX should i check for actual presence of sockets? -chb */ 347 for (i = 0; i < TCIC_NSLOTS; i++) { 348 sc->handle[i].sc = sc; 349 sc->handle[i].sock = i; 350 sc->handle[i].flags = TCIC_FLAG_SOCKETP; 351 sc->handle[i].memwins 352 = sc->chipid == TCIC_CHIPID_DB86082_1 ? 4 : 5; 353 } 354 355 /* establish the interrupt */ 356 reg = tcic_read_1(&sc->handle[0], TCIC_R_IENA); 357 tcic_write_1(&sc->handle[0], TCIC_R_IENA, 358 (reg & ~TCIC_IENA_CFG_MASK) | TCIC_IENA_CFG_HIGH); 359 reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG); 360 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, 361 (reg & ~TCIC_SYSCFG_IRQ_MASK) | tcic_irqmap[sc->irq]); 362 363 /* XXX block interrupts? */ 364 365 for (i = 0; i < TCIC_NSLOTS; i++) { 366 /* XXX make more clear what happens here -chb */ 367 tcic_sel_sock(&sc->handle[i]); 368 tcic_write_ind_2(&sc->handle[i], TCIC_IR_SCF1_N(i), 0); 369 tcic_write_ind_2(&sc->handle[i], TCIC_IR_SCF2_N(i), 370 (TCIC_SCF2_MCD|TCIC_SCF2_MWP|TCIC_SCF2_MRDY 371 #if 1 /* XXX explain byte routing issue */ 372 |TCIC_SCF2_MLBAT2|TCIC_SCF2_MLBAT1|TCIC_SCF2_IDBR)); 373 #else 374 |TCIC_SCF2_MLBAT2|TCIC_SCF2_MLBAT1)); 375 #endif 376 tcic_write_1(&sc->handle[i], TCIC_R_MODE, 0); 377 reg = tcic_read_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG); 378 reg &= ~TCIC_SYSCFG_AUTOBUSY; 379 tcic_write_aux_2(sc->iot, sc->ioh, TCIC_AR_SYSCFG, reg); 380 SIMPLEQ_INIT(&sc->handle[i].events); 381 } 382 383 if ((sc->handle[0].flags & TCIC_FLAG_SOCKETP) || 384 (sc->handle[1].flags & TCIC_FLAG_SOCKETP)) { 385 printf("%s: %s has ", sc->dev.dv_xname, 386 tcic_chipid_to_string(sc->chipid)); 387 388 if ((sc->handle[0].flags & TCIC_FLAG_SOCKETP) && 389 (sc->handle[1].flags & TCIC_FLAG_SOCKETP)) 390 printf("sockets A and B\n"); 391 else if (sc->handle[0].flags & TCIC_FLAG_SOCKETP) 392 printf("socket A only\n"); 393 else 394 printf("socket B only\n"); 395 396 } 397 } 398 399 void 400 tcic_attach_sockets(sc) 401 struct tcic_softc *sc; 402 { 403 int i; 404 405 for (i = 0; i < TCIC_NSLOTS; i++) 406 if (sc->handle[i].flags & TCIC_FLAG_SOCKETP) 407 tcic_attach_socket(&sc->handle[i]); 408 } 409 410 void 411 tcic_attach_socket(h) 412 struct tcic_handle *h; 413 { 414 struct pcmciabus_attach_args paa; 415 416 /* initialize the rest of the handle */ 417 418 h->shutdown = 0; 419 h->memalloc = 0; 420 h->ioalloc = 0; 421 h->ih_irq = 0; 422 423 /* now, config one pcmcia device per socket */ 424 425 paa.paa_busname = "pcmcia"; 426 paa.pct = (pcmcia_chipset_tag_t) h->sc->pct; 427 paa.pch = (pcmcia_chipset_handle_t) h; 428 paa.iobase = h->sc->iobase; 429 paa.iosize = h->sc->iosize; 430 431 h->pcmcia = config_found_sm(&h->sc->dev, &paa, tcic_print, 432 tcic_submatch); 433 434 /* if there's actually a pcmcia device attached, initialize the slot */ 435 436 if (h->pcmcia) 437 tcic_init_socket(h); 438 } 439 440 void 441 tcic_create_event_thread(arg) 442 void *arg; 443 { 444 struct tcic_handle *h = arg; 445 const char *cs; 446 447 switch (h->sock) { 448 case 0: 449 cs = "0"; 450 break; 451 case 1: 452 cs = "1"; 453 break; 454 default: 455 panic("tcic_create_event_thread: unknown tcic socket"); 456 } 457 458 if (kthread_create1(tcic_event_thread, h, &h->event_thread, 459 "%s,%s", h->sc->dev.dv_xname, cs)) { 460 printf("%s: unable to create event thread for sock 0x%02x\n", 461 h->sc->dev.dv_xname, h->sock); 462 panic("tcic_create_event_thread"); 463 } 464 } 465 466 void 467 tcic_event_thread(arg) 468 void *arg; 469 { 470 struct tcic_handle *h = arg; 471 struct tcic_event *pe; 472 int s; 473 474 while (h->shutdown == 0) { 475 s = splhigh(); 476 if ((pe = SIMPLEQ_FIRST(&h->events)) == NULL) { 477 splx(s); 478 (void) tsleep(&h->events, PWAIT, "tcicev", 0); 479 continue; 480 } 481 SIMPLEQ_REMOVE_HEAD(&h->events, pe, pe_q); 482 splx(s); 483 484 switch (pe->pe_type) { 485 case TCIC_EVENT_INSERTION: 486 DPRINTF(("%s: insertion event\n", h->sc->dev.dv_xname)); 487 tcic_attach_card(h); 488 break; 489 490 case TCIC_EVENT_REMOVAL: 491 DPRINTF(("%s: removal event\n", h->sc->dev.dv_xname)); 492 tcic_detach_card(h, DETACH_FORCE); 493 break; 494 495 default: 496 panic("tcic_event_thread: unknown event %d", 497 pe->pe_type); 498 } 499 free(pe, M_TEMP); 500 } 501 502 h->event_thread = NULL; 503 504 /* In case parent is waiting for us to exit. */ 505 wakeup(h->sc); 506 507 kthread_exit(0); 508 } 509 510 511 void 512 tcic_init_socket(h) 513 struct tcic_handle *h; 514 { 515 int reg; 516 517 /* select this socket's config registers */ 518 tcic_sel_sock(h); 519 520 /* set up the socket to interrupt on card detect */ 521 reg = tcic_read_ind_2(h, TCIC_IR_SCF2_N(h->sock)); 522 tcic_write_ind_2(h, TCIC_IR_SCF2_N(h->sock), reg & ~TCIC_SCF2_MCD); 523 524 /* enable CD irq in R_IENA */ 525 reg = tcic_read_2(h, TCIC_R_IENA); 526 tcic_write_2(h, TCIC_R_IENA, reg |= TCIC_IENA_CDCHG); 527 528 /* if there's a card there, then attach it. also save sstat */ 529 h->sstat = reg = tcic_read_1(h, TCIC_R_SSTAT) & TCIC_SSTAT_STAT_MASK; 530 if (reg & TCIC_SSTAT_CD) 531 tcic_attach_card(h); 532 } 533 534 int 535 tcic_submatch(parent, cf, aux) 536 struct device *parent; 537 struct cfdata *cf; 538 void *aux; 539 { 540 541 struct pcmciabus_attach_args *paa = aux; 542 struct tcic_handle *h = (struct tcic_handle *) paa->pch; 543 544 switch (h->sock) { 545 case 0: 546 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 547 PCMCIABUSCF_CONTROLLER_DEFAULT && 548 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 549 return 0; 550 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 551 PCMCIABUSCF_SOCKET_DEFAULT && 552 cf->cf_loc[PCMCIABUSCF_SOCKET] != 0) 553 return 0; 554 555 break; 556 case 1: 557 if (cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 558 PCMCIABUSCF_CONTROLLER_DEFAULT && 559 cf->cf_loc[PCMCIABUSCF_CONTROLLER] != 0) 560 return 0; 561 if (cf->cf_loc[PCMCIABUSCF_SOCKET] != 562 PCMCIABUSCF_SOCKET_DEFAULT && 563 cf->cf_loc[PCMCIABUSCF_SOCKET] != 1) 564 return 0; 565 566 break; 567 default: 568 panic("unknown tcic socket"); 569 } 570 571 return ((*cf->cf_attach->ca_match)(parent, cf, aux)); 572 } 573 574 int 575 tcic_print(arg, pnp) 576 void *arg; 577 const char *pnp; 578 { 579 struct pcmciabus_attach_args *paa = arg; 580 struct tcic_handle *h = (struct tcic_handle *) paa->pch; 581 582 /* Only "pcmcia"s can attach to "tcic"s... easy. */ 583 if (pnp) 584 printf("pcmcia at %s", pnp); 585 586 switch (h->sock) { 587 case 0: 588 printf(" socket 0"); 589 break; 590 case 1: 591 printf(" socket 1"); 592 break; 593 default: 594 panic("unknown tcic socket"); 595 } 596 return (UNCONF); 597 } 598 599 int 600 tcic_intr(arg) 601 void *arg; 602 { 603 struct tcic_softc *sc = arg; 604 int i, ret = 0; 605 606 DPRINTF(("%s: intr\n", sc->dev.dv_xname)); 607 608 for (i = 0; i < TCIC_NSLOTS; i++) 609 if (sc->handle[i].flags & TCIC_FLAG_SOCKETP) 610 ret += tcic_intr_socket(&sc->handle[i]); 611 612 return (ret ? 1 : 0); 613 } 614 615 int 616 tcic_intr_socket(h) 617 struct tcic_handle *h; 618 { 619 int icsr, rv; 620 621 rv = 0; 622 tcic_sel_sock(h); 623 icsr = tcic_read_1(h, TCIC_R_ICSR); 624 625 DPRINTF(("%s: %d icsr: 0x%02x \n", h->sc->dev.dv_xname, h->sock, icsr)); 626 627 /* XXX or should the next three be handled in tcic_intr? -chb */ 628 if (icsr & TCIC_ICSR_PROGTIME) { 629 DPRINTF(("%s: %02x PROGTIME\n", h->sc->dev.dv_xname, h->sock)); 630 rv = 1; 631 } 632 if (icsr & TCIC_ICSR_ILOCK) { 633 DPRINTF(("%s: %02x ILOCK\n", h->sc->dev.dv_xname, h->sock)); 634 rv = 1; 635 } 636 if (icsr & TCIC_ICSR_ERR) { 637 DPRINTF(("%s: %02x ERR\n", h->sc->dev.dv_xname, h->sock)); 638 rv = 1; 639 } 640 if (icsr & TCIC_ICSR_CDCHG) { 641 int sstat, delta; 642 643 /* compute what changed since last interrupt */ 644 sstat = tcic_read_aux_1(h->sc->iot, h->sc->ioh, 645 TCIC_AR_WCTL, TCIC_R_WCTL_XCSR) & TCIC_XCSR_STAT_MASK; 646 delta = h->sstat ^ sstat; 647 h->sstat = sstat; 648 649 if (delta) 650 rv = 1; 651 652 DPRINTF(("%s: %02x CDCHG %x\n", h->sc->dev.dv_xname, h->sock, 653 delta)); 654 655 /* 656 * XXX This should probably schedule something to happen 657 * after the interrupt handler completes 658 */ 659 660 if (delta & TCIC_SSTAT_CD) { 661 if (sstat & TCIC_SSTAT_CD) { 662 if (!(h->flags & TCIC_FLAG_CARDP)) { 663 DPRINTF(("%s: enqueing INSERTION event\n", 664 h->sc->dev.dv_xname)); 665 tcic_queue_event(h, TCIC_EVENT_INSERTION); 666 } 667 } else { 668 if (h->flags & TCIC_FLAG_CARDP) { 669 /* Deactivate the card now. */ 670 DPRINTF(("%s: deactivating card\n", 671 h->sc->dev.dv_xname)); 672 tcic_deactivate_card(h); 673 674 DPRINTF(("%s: enqueing REMOVAL event\n", 675 h->sc->dev.dv_xname)); 676 tcic_queue_event(h, TCIC_EVENT_REMOVAL); 677 } 678 } 679 } 680 if (delta & TCIC_SSTAT_RDY) { 681 DPRINTF(("%s: %02x READY\n", h->sc->dev.dv_xname, h->sock)); 682 /* shouldn't happen */ 683 } 684 if (delta & TCIC_SSTAT_LBAT1) { 685 DPRINTF(("%s: %02x LBAT1\n", h->sc->dev.dv_xname, h->sock)); 686 } 687 if (delta & TCIC_SSTAT_LBAT2) { 688 DPRINTF(("%s: %02x LBAT2\n", h->sc->dev.dv_xname, h->sock)); 689 } 690 if (delta & TCIC_SSTAT_WP) { 691 DPRINTF(("%s: %02x WP\n", h->sc->dev.dv_xname, h->sock)); 692 } 693 } 694 return rv; 695 } 696 697 void 698 tcic_queue_event(h, event) 699 struct tcic_handle *h; 700 int event; 701 { 702 struct tcic_event *pe; 703 int s; 704 705 pe = malloc(sizeof(*pe), M_TEMP, M_NOWAIT); 706 if (pe == NULL) 707 panic("tcic_queue_event: can't allocate event"); 708 709 pe->pe_type = event; 710 s = splhigh(); 711 SIMPLEQ_INSERT_TAIL(&h->events, pe, pe_q); 712 splx(s); 713 wakeup(&h->events); 714 } 715 void 716 tcic_attach_card(h) 717 struct tcic_handle *h; 718 { 719 DPRINTF(("tcic_attach_card\n")); 720 721 if (h->flags & TCIC_FLAG_CARDP) 722 panic("tcic_attach_card: already attached"); 723 724 /* call the MI attach function */ 725 726 pcmcia_card_attach(h->pcmcia); 727 728 h->flags |= TCIC_FLAG_CARDP; 729 } 730 731 void 732 tcic_detach_card(h, flags) 733 struct tcic_handle *h; 734 int flags; /* DETACH_* */ 735 { 736 DPRINTF(("tcic_detach_card\n")); 737 738 if (!(h->flags & TCIC_FLAG_CARDP)) 739 panic("tcic_detach_card: already detached"); 740 741 h->flags &= ~TCIC_FLAG_CARDP; 742 743 /* call the MI detach function */ 744 745 pcmcia_card_detach(h->pcmcia, flags); 746 747 } 748 749 void 750 tcic_deactivate_card(h) 751 struct tcic_handle *h; 752 { 753 int val, reg; 754 755 if (!(h->flags & TCIC_FLAG_CARDP)) 756 panic("tcic_deactivate_card: already detached"); 757 758 /* call the MI deactivate function */ 759 pcmcia_card_deactivate(h->pcmcia); 760 761 tcic_sel_sock(h); 762 763 /* XXX disable card detect resume and configuration reset??? */ 764 765 /* power down the socket */ 766 tcic_write_1(h, TCIC_R_PWR, 0); 767 768 /* reset the card XXX ? -chb */ 769 770 /* turn off irq's for this socket */ 771 reg = TCIC_IR_SCF1_N(h->sock); 772 val = tcic_read_ind_2(h, reg); 773 tcic_write_ind_2(h, reg, (val & ~TCIC_SCF1_IRQ_MASK)|TCIC_SCF1_IRQOFF); 774 reg = TCIC_IR_SCF2_N(h->sock); 775 val = tcic_read_ind_2(h, reg); 776 tcic_write_ind_2(h, reg, 777 (val | (TCIC_SCF2_MLBAT1|TCIC_SCF2_MLBAT2|TCIC_SCF2_MRDY 778 |TCIC_SCF2_MWP|TCIC_SCF2_MCD))); 779 } 780 781 /* XXX the following routine may need to be rewritten. -chb */ 782 int 783 tcic_chip_mem_alloc(pch, size, pcmhp) 784 pcmcia_chipset_handle_t pch; 785 bus_size_t size; 786 struct pcmcia_mem_handle *pcmhp; 787 { 788 struct tcic_handle *h = (struct tcic_handle *) pch; 789 bus_space_handle_t memh; 790 bus_addr_t addr; 791 bus_size_t sizepg; 792 int i, mask, mhandle; 793 794 /* out of sc->memh, allocate as many pages as necessary */ 795 796 /* 797 * The TCIC can map memory only in sizes that are 798 * powers of two, aligned at the natural boundary for the size. 799 */ 800 i = tcic_log2((u_int)size); 801 if ((1<<i) < size) 802 i++; 803 sizepg = max(i, TCIC_MEM_SHIFT) - (TCIC_MEM_SHIFT-1); 804 805 DPRINTF(("tcic_chip_mem_alloc: size %ld sizepg %ld\n", size, sizepg)); 806 807 /* can't allocate that much anyway */ 808 if (sizepg > TCIC_MEM_PAGES) /* XXX -chb */ 809 return 1; 810 811 mask = (1 << sizepg) - 1; 812 813 addr = 0; /* XXX gcc -Wuninitialized */ 814 mhandle = 0; /* XXX gcc -Wuninitialized */ 815 816 /* XXX i should be initialised to always lay on boundary. -chb */ 817 for (i = 0; i < (TCIC_MEM_PAGES + 1 - sizepg); i += sizepg) { 818 if ((h->sc->subregionmask & (mask << i)) == (mask << i)) { 819 if (bus_space_subregion(h->sc->memt, h->sc->memh, 820 i * TCIC_MEM_PAGESIZE, 821 sizepg * TCIC_MEM_PAGESIZE, &memh)) 822 return (1); 823 mhandle = mask << i; 824 addr = h->sc->membase + (i * TCIC_MEM_PAGESIZE); 825 h->sc->subregionmask &= ~(mhandle); 826 break; 827 } 828 } 829 830 if (i == (TCIC_MEM_PAGES + 1 - sizepg)) 831 return (1); 832 833 DPRINTF(("tcic_chip_mem_alloc bus addr 0x%lx+0x%lx\n", (u_long) addr, 834 (u_long) size)); 835 836 pcmhp->memt = h->sc->memt; 837 pcmhp->memh = memh; 838 pcmhp->addr = addr; 839 pcmhp->size = size; 840 pcmhp->mhandle = mhandle; 841 pcmhp->realsize = sizepg * TCIC_MEM_PAGESIZE; 842 843 return (0); 844 } 845 846 /* XXX the following routine may need to be rewritten. -chb */ 847 void 848 tcic_chip_mem_free(pch, pcmhp) 849 pcmcia_chipset_handle_t pch; 850 struct pcmcia_mem_handle *pcmhp; 851 { 852 struct tcic_handle *h = (struct tcic_handle *) pch; 853 854 h->sc->subregionmask |= pcmhp->mhandle; 855 } 856 857 void 858 tcic_chip_do_mem_map(h, win) 859 struct tcic_handle *h; 860 int win; 861 { 862 int reg, hwwin, wscnt; 863 864 int kind = h->mem[win].kind & ~PCMCIA_WIDTH_MEM_MASK; 865 int mem8 = (h->mem[win].kind & PCMCIA_WIDTH_MEM_MASK) == PCMCIA_WIDTH_MEM8; 866 DPRINTF(("tcic_chip_do_mem_map window %d: 0x%lx+0x%lx 0x%lx\n", 867 win, (u_long)h->mem[win].addr, (u_long)h->mem[win].size, 868 (u_long)h->mem[win].offset)); 869 /* 870 * the even windows are used for socket 0, 871 * the odd ones for socket 1. 872 */ 873 hwwin = (win << 1) + h->sock; 874 875 /* the WR_MEXT register is MBZ */ 876 tcic_write_ind_2(h, TCIC_WR_MEXT_N(hwwin), 0); 877 878 /* set the host base address and window size */ 879 if (h->mem[win].size2 <= 1) { 880 reg = ((h->mem[win].addr >> TCIC_MEM_SHIFT) & 881 TCIC_MBASE_ADDR_MASK) | TCIC_MBASE_4K; 882 } else { 883 reg = ((h->mem[win].addr >> TCIC_MEM_SHIFT) & 884 TCIC_MBASE_ADDR_MASK) | (h->mem[win].size2 >> 1); 885 } 886 tcic_write_ind_2(h, TCIC_WR_MBASE_N(hwwin), reg); 887 888 /* set the card address and address space */ 889 reg = 0; 890 reg = ((h->mem[win].offset >> TCIC_MEM_SHIFT) & TCIC_MMAP_ADDR_MASK); 891 reg |= (kind == PCMCIA_MEM_ATTR) ? TCIC_MMAP_ATTR : 0; 892 DPRINTF(("tcic_chip_do_map_mem window %d(%d) mmap 0x%04x\n", 893 win, hwwin, reg)); 894 tcic_write_ind_2(h, TCIC_WR_MMAP_N(hwwin), reg); 895 896 /* set the MCTL register */ 897 /* must save WSCNT field in case this is a DB86082 rev 0 */ 898 /* XXX why can't I do the following two in one statement? */ 899 reg = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin)) & TCIC_MCTL_WSCNT_MASK; 900 reg |= TCIC_MCTL_ENA|TCIC_MCTL_QUIET; 901 reg |= mem8 ? TCIC_MCTL_B8 : 0; 902 reg |= (h->sock << TCIC_MCTL_SS_SHIFT) & TCIC_MCTL_SS_MASK; 903 #ifdef notyet /* XXX must get speed from CIS somehow. -chb */ 904 wscnt = tcic_ns2wscnt(h->mem[win].speed); 905 #else 906 wscnt = tcic_ns2wscnt(tcic_mem_speed); /* 300 is "save" default for CIS memory */ 907 #endif 908 if (h->sc->chipid == TCIC_CHIPID_DB86082_1) { 909 /* 910 * this chip has the wait state count in window 911 * register 7 - hwwin. 912 */ 913 int reg2; 914 reg2 = tcic_read_ind_2(h, TCIC_WR_MCTL_N(7-hwwin)); 915 reg2 &= ~TCIC_MCTL_WSCNT_MASK; 916 reg2 |= wscnt & TCIC_MCTL_WSCNT_MASK; 917 tcic_write_ind_2(h, TCIC_WR_MCTL_N(7-hwwin), reg2); 918 } else { 919 reg |= wscnt & TCIC_MCTL_WSCNT_MASK; 920 } 921 tcic_write_ind_2(h, TCIC_WR_MCTL_N(hwwin), reg); 922 923 #ifdef TCICDEBUG 924 { 925 int r1, r2, r3; 926 927 r1 = tcic_read_ind_2(h, TCIC_WR_MBASE_N(hwwin)); 928 r2 = tcic_read_ind_2(h, TCIC_WR_MMAP_N(hwwin)); 929 r3 = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin)); 930 931 DPRINTF(("tcic_chip_do_mem_map window %d(%d): %04x %04x %04x\n", 932 win, hwwin, r1, r2, r3)); 933 } 934 #endif 935 } 936 937 /* XXX needs work */ 938 int 939 tcic_chip_mem_map(pch, kind, card_addr, size, pcmhp, offsetp, windowp) 940 pcmcia_chipset_handle_t pch; 941 int kind; 942 bus_addr_t card_addr; 943 bus_size_t size; 944 struct pcmcia_mem_handle *pcmhp; 945 bus_addr_t *offsetp; 946 int *windowp; 947 { 948 struct tcic_handle *h = (struct tcic_handle *) pch; 949 bus_addr_t busaddr; 950 long card_offset; 951 int i, win; 952 953 win = -1; 954 for (i = 0; i < h->memwins; i++) { 955 if ((h->memalloc & (1 << i)) == 0) { 956 win = i; 957 h->memalloc |= (1 << i); 958 break; 959 } 960 } 961 962 if (win == -1) 963 return (1); 964 965 *windowp = win; 966 967 /* XXX this is pretty gross */ 968 969 if (h->sc->memt != pcmhp->memt) 970 panic("tcic_chip_mem_map memt is bogus"); 971 972 busaddr = pcmhp->addr; 973 974 /* 975 * compute the address offset to the pcmcia address space for the 976 * tcic. this is intentionally signed. The masks and shifts below 977 * will cause TRT to happen in the tcic registers. Deal with making 978 * sure the address is aligned, and return the alignment offset. 979 */ 980 981 *offsetp = card_addr % TCIC_MEM_ALIGN; 982 card_addr -= *offsetp; 983 984 DPRINTF(("tcic_chip_mem_map window %d bus %lx+%lx+%lx at card addr " 985 "%lx\n", win, (u_long) busaddr, (u_long) * offsetp, (u_long) size, 986 (u_long) card_addr)); 987 988 /* XXX we can't use size. -chb */ 989 /* 990 * include the offset in the size, and decrement size by one, since 991 * the hw wants start/stop 992 */ 993 size += *offsetp - 1; 994 995 card_offset = (((long) card_addr) - ((long) busaddr)); 996 997 DPRINTF(("tcic_chip_mem_map window %d card_offset 0x%lx\n", 998 win, (u_long)card_offset)); 999 1000 h->mem[win].addr = busaddr; 1001 h->mem[win].size = size; 1002 h->mem[win].size2 = tcic_log2((u_int)pcmhp->realsize) - TCIC_MEM_SHIFT; 1003 h->mem[win].offset = card_offset; 1004 h->mem[win].kind = kind; 1005 1006 tcic_chip_do_mem_map(h, win); 1007 1008 return (0); 1009 } 1010 1011 void 1012 tcic_chip_mem_unmap(pch, window) 1013 pcmcia_chipset_handle_t pch; 1014 int window; 1015 { 1016 struct tcic_handle *h = (struct tcic_handle *) pch; 1017 int reg, hwwin; 1018 1019 if (window >= h->memwins) 1020 panic("tcic_chip_mem_unmap: window out of range"); 1021 1022 hwwin = (window << 1) + h->sock; 1023 reg = tcic_read_ind_2(h, TCIC_WR_MCTL_N(hwwin)); 1024 reg &= ~TCIC_MCTL_ENA; 1025 tcic_write_ind_2(h, TCIC_WR_MCTL_N(hwwin), reg); 1026 1027 h->memalloc &= ~(1 << window); 1028 } 1029 1030 int 1031 tcic_chip_io_alloc(pch, start, size, align, pcihp) 1032 pcmcia_chipset_handle_t pch; 1033 bus_addr_t start; 1034 bus_size_t size; 1035 bus_size_t align; 1036 struct pcmcia_io_handle *pcihp; 1037 { 1038 struct tcic_handle *h = (struct tcic_handle *) pch; 1039 bus_space_tag_t iot; 1040 bus_space_handle_t ioh; 1041 bus_addr_t ioaddr; 1042 int size2, flags = 0; 1043 1044 /* 1045 * Allocate some arbitrary I/O space. 1046 */ 1047 1048 DPRINTF(("tcic_chip_io_alloc req 0x%lx %ld %ld\n", 1049 (u_long) start, (u_long) size, (u_long) align)); 1050 /* 1051 * The TCIC can map I/O space only in sizes that are 1052 * powers of two, aligned at the natural boundary for the size. 1053 */ 1054 size2 = tcic_log2((u_int)size); 1055 if ((1 << size2) < size) 1056 size2++; 1057 /* can't allocate that much anyway */ 1058 if (size2 > 16) /* XXX 64K -chb */ 1059 return 1; 1060 if (align) { 1061 if ((1 << size2) != align) 1062 return 1; /* not suitably aligned */ 1063 } else { 1064 align = 1 << size2; /* no alignment given, make it natural */ 1065 } 1066 if (start & (align - 1)) 1067 return 1; /* not suitably aligned */ 1068 1069 iot = h->sc->iot; 1070 1071 if (start) { 1072 ioaddr = start; 1073 if (bus_space_map(iot, start, size, 0, &ioh)) 1074 return (1); 1075 DPRINTF(("tcic_chip_io_alloc map port %lx+%lx\n", 1076 (u_long) ioaddr, (u_long) size)); 1077 } else { 1078 flags |= PCMCIA_IO_ALLOCATED; 1079 if (bus_space_alloc(iot, h->sc->iobase, 1080 h->sc->iobase + h->sc->iosize, size, align, 0, 0, 1081 &ioaddr, &ioh)) 1082 return (1); 1083 DPRINTF(("tcic_chip_io_alloc alloc port %lx+%lx\n", 1084 (u_long) ioaddr, (u_long) size)); 1085 } 1086 1087 pcihp->iot = iot; 1088 pcihp->ioh = ioh; 1089 pcihp->addr = ioaddr; 1090 pcihp->size = size; 1091 pcihp->flags = flags; 1092 1093 return (0); 1094 } 1095 1096 void 1097 tcic_chip_io_free(pch, pcihp) 1098 pcmcia_chipset_handle_t pch; 1099 struct pcmcia_io_handle *pcihp; 1100 { 1101 bus_space_tag_t iot = pcihp->iot; 1102 bus_space_handle_t ioh = pcihp->ioh; 1103 bus_size_t size = pcihp->size; 1104 1105 if (pcihp->flags & PCMCIA_IO_ALLOCATED) 1106 bus_space_free(iot, ioh, size); 1107 else 1108 bus_space_unmap(iot, ioh, size); 1109 } 1110 1111 static int tcic_iowidth_map[] = 1112 { TCIC_ICTL_AUTOSZ, TCIC_ICTL_B8, TCIC_ICTL_B16 }; 1113 1114 void 1115 tcic_chip_do_io_map(h, win) 1116 struct tcic_handle *h; 1117 int win; 1118 { 1119 int reg, size2, iotiny, wbase, hwwin, wscnt; 1120 1121 DPRINTF(("tcic_chip_do_io_map win %d addr %lx size %lx width %d\n", 1122 win, (long) h->io[win].addr, (long) h->io[win].size, 1123 h->io[win].width * 8)); 1124 1125 /* 1126 * the even windows are used for socket 0, 1127 * the odd ones for socket 1. 1128 */ 1129 hwwin = (win << 1) + h->sock; 1130 1131 /* set the WR_BASE register */ 1132 /* XXX what if size isn't power of 2? -chb */ 1133 size2 = tcic_log2((u_int)h->io[win].size); 1134 DPRINTF(("tcic_chip_do_io_map win %d size2 %d\n", win, size2)); 1135 if (size2 < 1) { 1136 iotiny = TCIC_ICTL_TINY; 1137 wbase = h->io[win].addr; 1138 } else { 1139 iotiny = 0; 1140 /* XXX we should do better -chb */ 1141 wbase = h->io[win].addr | (1 << (size2 - 1)); 1142 } 1143 tcic_write_ind_2(h, TCIC_WR_IBASE_N(hwwin), wbase); 1144 1145 /* set the WR_ICTL register */ 1146 reg = TCIC_ICTL_ENA | TCIC_ICTL_QUIET; 1147 reg |= (h->sock << TCIC_ICTL_SS_SHIFT) & TCIC_ICTL_SS_MASK; 1148 reg |= iotiny | tcic_iowidth_map[h->io[win].width]; 1149 if (h->sc->chipid != TCIC_CHIPID_DB86082_1) 1150 reg |= TCIC_ICTL_PASS16; 1151 #ifdef notyet /* XXX must get speed from CIS somehow. -chb */ 1152 wscnt = tcic_ns2wscnt(h->io[win].speed); 1153 #else 1154 wscnt = tcic_ns2wscnt(tcic_io_speed); /* linux uses 0 as default */ 1155 #endif 1156 reg |= wscnt & TCIC_ICTL_WSCNT_MASK; 1157 tcic_write_ind_2(h, TCIC_WR_ICTL_N(hwwin), reg); 1158 1159 #ifdef TCICDEBUG 1160 { 1161 int r1, r2; 1162 1163 r1 = tcic_read_ind_2(h, TCIC_WR_IBASE_N(hwwin)); 1164 r2 = tcic_read_ind_2(h, TCIC_WR_ICTL_N(hwwin)); 1165 1166 DPRINTF(("tcic_chip_do_io_map window %d(%d): %04x %04x\n", 1167 win, hwwin, r1, r2)); 1168 } 1169 #endif 1170 } 1171 1172 int 1173 tcic_chip_io_map(pch, width, offset, size, pcihp, windowp) 1174 pcmcia_chipset_handle_t pch; 1175 int width; 1176 bus_addr_t offset; 1177 bus_size_t size; 1178 struct pcmcia_io_handle *pcihp; 1179 int *windowp; 1180 { 1181 struct tcic_handle *h = (struct tcic_handle *) pch; 1182 bus_addr_t ioaddr = pcihp->addr + offset; 1183 int i, win; 1184 #ifdef TCICDEBUG 1185 static char *width_names[] = { "auto", "io8", "io16" }; 1186 #endif 1187 1188 /* XXX Sanity check offset/size. */ 1189 1190 win = -1; 1191 for (i = 0; i < TCIC_IO_WINS; i++) { 1192 if ((h->ioalloc & (1 << i)) == 0) { 1193 win = i; 1194 h->ioalloc |= (1 << i); 1195 break; 1196 } 1197 } 1198 1199 if (win == -1) 1200 return (1); 1201 1202 *windowp = win; 1203 1204 /* XXX this is pretty gross */ 1205 1206 if (h->sc->iot != pcihp->iot) 1207 panic("tcic_chip_io_map iot is bogus"); 1208 1209 DPRINTF(("tcic_chip_io_map window %d %s port %lx+%lx\n", 1210 win, width_names[width], (u_long) ioaddr, (u_long) size)); 1211 1212 /* XXX wtf is this doing here? */ 1213 1214 printf(" port 0x%lx", (u_long) ioaddr); 1215 if (size > 1) 1216 printf("-0x%lx", (u_long) ioaddr + (u_long) size - 1); 1217 1218 h->io[win].addr = ioaddr; 1219 h->io[win].size = size; 1220 h->io[win].width = width; 1221 1222 tcic_chip_do_io_map(h, win); 1223 1224 return (0); 1225 } 1226 1227 void 1228 tcic_chip_io_unmap(pch, window) 1229 pcmcia_chipset_handle_t pch; 1230 int window; 1231 { 1232 struct tcic_handle *h = (struct tcic_handle *) pch; 1233 int reg, hwwin; 1234 1235 if (window >= TCIC_IO_WINS) 1236 panic("tcic_chip_io_unmap: window out of range"); 1237 1238 hwwin = (window << 1) + h->sock; 1239 reg = tcic_read_ind_2(h, TCIC_WR_ICTL_N(hwwin)); 1240 reg &= ~TCIC_ICTL_ENA; 1241 tcic_write_ind_2(h, TCIC_WR_ICTL_N(hwwin), reg); 1242 1243 h->ioalloc &= ~(1 << window); 1244 } 1245 1246 void 1247 tcic_chip_socket_enable(pch) 1248 pcmcia_chipset_handle_t pch; 1249 { 1250 struct tcic_handle *h = (struct tcic_handle *) pch; 1251 int cardtype, reg, win; 1252 1253 tcic_sel_sock(h); 1254 1255 /* 1256 * power down the socket to reset it. 1257 * put card reset into high-z, put chip outputs to card into high-z 1258 */ 1259 1260 tcic_write_1(h, TCIC_R_PWR, 0); 1261 reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1262 reg |= TCIC_ILOCK_CWAIT; 1263 reg &= ~(TCIC_ILOCK_CRESET|TCIC_ILOCK_CRESENA); 1264 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1265 tcic_write_1(h, TCIC_R_SCTRL, 0); /* clear TCIC_SCTRL_ENA */ 1266 1267 /* power up the socket */ 1268 1269 /* turn on VCC, turn of VPP */ 1270 reg = TCIC_PWR_VCC_N(h->sock) | TCIC_PWR_VPP_N(h->sock) | h->sc->pwrena; 1271 if (h->sc->pwrena) /* this is a '84 type chip */ 1272 reg |= TCIC_PWR_VCC5V; 1273 tcic_write_1(h, TCIC_R_PWR, reg); 1274 delay(10000); 1275 1276 /* enable reset and wiggle it to reset the card */ 1277 reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1278 reg |= TCIC_ILOCK_CRESENA; 1279 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1280 /* XXX need bus_space_barrier here */ 1281 reg |= TCIC_ILOCK_CRESET; 1282 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1283 /* enable card signals */ 1284 tcic_write_1(h, TCIC_R_SCTRL, TCIC_SCTRL_ENA); 1285 delay(10); /* wait 10 us */ 1286 1287 /* clear the reset flag */ 1288 reg = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1289 reg &= ~(TCIC_ILOCK_CRESET); 1290 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, reg); 1291 1292 /* wait 20ms as per pc card standard (r2.01) section 4.3.6 */ 1293 delay(20000); 1294 1295 /* wait for the chip to finish initializing */ 1296 tcic_wait_ready(h); 1297 1298 /* WWW */ 1299 /* zero out the address windows */ 1300 1301 /* writing to WR_MBASE_N disables the window */ 1302 for (win = 0; win < h->memwins; win++) { 1303 tcic_write_ind_2(h, TCIC_WR_MBASE_N((win<<1)+h->sock), 0); 1304 } 1305 /* writing to WR_IBASE_N disables the window */ 1306 for (win = 0; win < TCIC_IO_WINS; win++) { 1307 tcic_write_ind_2(h, TCIC_WR_IBASE_N((win<<1)+h->sock), 0); 1308 } 1309 1310 /* set the card type */ 1311 1312 cardtype = pcmcia_card_gettype(h->pcmcia); 1313 1314 #if 0 1315 reg = tcic_read_ind_2(h, TCIC_IR_SCF1_N(h->sock)); 1316 reg &= ~TCIC_SCF1_IRQ_MASK; 1317 #else 1318 reg = 0; 1319 #endif 1320 reg |= ((cardtype == PCMCIA_IFTYPE_IO) ? 1321 TCIC_SCF1_IOSTS : 0); 1322 reg |= tcic_irqmap[h->ih_irq]; /* enable interrupts */ 1323 reg &= ~TCIC_SCF1_IRQOD; 1324 tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), reg); 1325 1326 DPRINTF(("%s: tcic_chip_socket_enable %d cardtype %s 0x%02x\n", 1327 h->sc->dev.dv_xname, h->sock, 1328 ((cardtype == PCMCIA_IFTYPE_IO) ? "io" : "mem"), reg)); 1329 1330 /* reinstall all the memory and io mappings */ 1331 1332 for (win = 0; win < h->memwins; win++) 1333 if (h->memalloc & (1 << win)) 1334 tcic_chip_do_mem_map(h, win); 1335 1336 for (win = 0; win < TCIC_IO_WINS; win++) 1337 if (h->ioalloc & (1 << win)) 1338 tcic_chip_do_io_map(h, win); 1339 } 1340 1341 void 1342 tcic_chip_socket_disable(pch) 1343 pcmcia_chipset_handle_t pch; 1344 { 1345 struct tcic_handle *h = (struct tcic_handle *) pch; 1346 int val; 1347 1348 DPRINTF(("tcic_chip_socket_disable\n")); 1349 1350 tcic_sel_sock(h); 1351 1352 /* disable interrupts */ 1353 val = tcic_read_ind_2(h, TCIC_IR_SCF1_N(h->sock)); 1354 val &= TCIC_SCF1_IRQ_MASK; 1355 tcic_write_ind_2(h, TCIC_IR_SCF1_N(h->sock), val); 1356 1357 /* disable the output signals */ 1358 tcic_write_1(h, TCIC_R_SCTRL, 0); 1359 val = tcic_read_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK); 1360 val &= ~TCIC_ILOCK_CRESENA; 1361 tcic_write_aux_2(h->sc->iot, h->sc->ioh, TCIC_AR_ILOCK, val); 1362 1363 /* power down the socket */ 1364 tcic_write_1(h, TCIC_R_PWR, 0); 1365 } 1366 1367 /* 1368 * XXX The following is Linux driver but doesn't match the table 1369 * in the manual. 1370 */ 1371 int 1372 tcic_ns2wscnt(ns) 1373 int ns; 1374 { 1375 if (ns < 14) { 1376 return 0; 1377 } else { 1378 return (2*(ns-14))/70; /* XXX assumes 14.31818 MHz clock. */ 1379 } 1380 } 1381 1382 int 1383 tcic_log2(val) 1384 u_int val; 1385 { 1386 int i, l2; 1387 1388 l2 = i = 0; 1389 while (val) { 1390 if (val & 1) 1391 l2 = i; 1392 i++; 1393 val >>= 1; 1394 } 1395 return l2; 1396 } 1397