1 /* $NetBSD: spdmem.c,v 1.12 2015/04/01 06:08:39 matt Exp $ */ 2 3 /* 4 * Copyright (c) 2007 Nicolas Joly 5 * Copyright (c) 2007 Paul Goyette 6 * Copyright (c) 2007 Tobias Nygren 7 * All rights reserved. 8 * 9 * Redistribution and use in source and binary forms, with or without 10 * modification, are permitted provided that the following conditions 11 * are met: 12 * 1. Redistributions of source code must retain the above copyright 13 * notice, this list of conditions and the following disclaimer. 14 * 2. Redistributions in binary form must reproduce the above copyright 15 * notice, this list of conditions and the following disclaimer in the 16 * documentation and/or other materials provided with the distribution. 17 * 3. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Serial Presence Detect (SPD) memory identification 35 */ 36 37 #include <sys/cdefs.h> 38 __KERNEL_RCSID(0, "$NetBSD: spdmem.c,v 1.12 2015/04/01 06:08:39 matt Exp $"); 39 40 #include <sys/param.h> 41 #include <sys/device.h> 42 #include <sys/endian.h> 43 #include <sys/sysctl.h> 44 #include <machine/bswap.h> 45 46 #include <dev/i2c/i2cvar.h> 47 #include <dev/ic/spdmemreg.h> 48 #include <dev/ic/spdmemvar.h> 49 50 /* Routines for decoding spd data */ 51 static void decode_edofpm(const struct sysctlnode *, device_t, struct spdmem *); 52 static void decode_rom(const struct sysctlnode *, device_t, struct spdmem *); 53 static void decode_sdram(const struct sysctlnode *, device_t, struct spdmem *, 54 int); 55 static void decode_ddr(const struct sysctlnode *, device_t, struct spdmem *); 56 static void decode_ddr2(const struct sysctlnode *, device_t, struct spdmem *); 57 static void decode_ddr3(const struct sysctlnode *, device_t, struct spdmem *); 58 static void decode_fbdimm(const struct sysctlnode *, device_t, struct spdmem *); 59 60 static void decode_size_speed(device_t, const struct sysctlnode *, 61 int, int, int, int, bool, const char *, int); 62 static void decode_voltage_refresh(device_t, struct spdmem *); 63 64 #define IS_RAMBUS_TYPE (s->sm_len < 4) 65 66 static const char* const spdmem_basic_types[] = { 67 "unknown", 68 "FPM", 69 "EDO", 70 "Pipelined Nibble", 71 "SDRAM", 72 "ROM", 73 "DDR SGRAM", 74 "DDR SDRAM", 75 "DDR2 SDRAM", 76 "DDR2 SDRAM FB", 77 "DDR2 SDRAM FB Probe", 78 "DDR3 SDRAM", 79 "DDR4 SDRAM" 80 }; 81 82 static const char* const spdmem_superset_types[] = { 83 "unknown", 84 "ESDRAM", 85 "DDR ESDRAM", 86 "PEM EDO", 87 "PEM SDRAM" 88 }; 89 90 static const char* const spdmem_voltage_types[] = { 91 "TTL (5V tolerant)", 92 "LvTTL (not 5V tolerant)", 93 "HSTL 1.5V", 94 "SSTL 3.3V", 95 "SSTL 2.5V", 96 "SSTL 1.8V" 97 }; 98 99 static const char* const spdmem_refresh_types[] = { 100 "15.625us", 101 "3.9us", 102 "7.8us", 103 "31.3us", 104 "62.5us", 105 "125us" 106 }; 107 108 static const char* const spdmem_parity_types[] = { 109 "no parity or ECC", 110 "data parity", 111 "data ECC", 112 "data parity and ECC", 113 "cmd/addr parity", 114 "cmd/addr/data parity", 115 "cmd/addr parity, data ECC", 116 "cmd/addr/data parity, data ECC" 117 }; 118 119 /* Cycle time fractional values (units of .001 ns) for DDR2 SDRAM */ 120 static const uint16_t spdmem_cycle_frac[] = { 121 0, 100, 200, 300, 400, 500, 600, 700, 800, 900, 122 250, 333, 667, 750, 999, 999 123 }; 124 125 /* Format string for timing info */ 126 #define LATENCY "tAA-tRCD-tRP-tRAS: %d-%d-%d-%d\n" 127 128 /* CRC functions used for certain memory types */ 129 130 static uint16_t spdcrc16 (struct spdmem_softc *sc, int count) 131 { 132 uint16_t crc; 133 int i, j; 134 uint8_t val; 135 crc = 0; 136 for (j = 0; j <= count; j++) { 137 val = (sc->sc_read)(sc, j); 138 crc = crc ^ val << 8; 139 for (i = 0; i < 8; ++i) 140 if (crc & 0x8000) 141 crc = crc << 1 ^ 0x1021; 142 else 143 crc = crc << 1; 144 } 145 return (crc & 0xFFFF); 146 } 147 148 int 149 spdmem_common_probe(struct spdmem_softc *sc) 150 { 151 int cksum = 0; 152 uint8_t i, val, spd_type; 153 int spd_len, spd_crc_cover; 154 uint16_t crc_calc, crc_spd; 155 156 spd_type = (sc->sc_read)(sc, 2); 157 158 /* For older memory types, validate the checksum over 1st 63 bytes */ 159 if (spd_type <= SPDMEM_MEMTYPE_DDR2SDRAM) { 160 for (i = 0; i < 63; i++) 161 cksum += (sc->sc_read)(sc, i); 162 163 val = (sc->sc_read)(sc, 63); 164 165 if (cksum == 0 || (cksum & 0xff) != val) { 166 aprint_debug("spd checksum failed, calc = 0x%02x, " 167 "spd = 0x%02x\n", cksum, val); 168 return 0; 169 } else 170 return 1; 171 } 172 173 /* For DDR3 and FBDIMM, verify the CRC */ 174 else if (spd_type <= SPDMEM_MEMTYPE_DDR3SDRAM) { 175 spd_len = (sc->sc_read)(sc, 0); 176 if (spd_len & SPDMEM_SPDCRC_116) 177 spd_crc_cover = 116; 178 else 179 spd_crc_cover = 125; 180 switch (spd_len & SPDMEM_SPDLEN_MASK) { 181 case SPDMEM_SPDLEN_128: 182 spd_len = 128; 183 break; 184 case SPDMEM_SPDLEN_176: 185 spd_len = 176; 186 break; 187 case SPDMEM_SPDLEN_256: 188 spd_len = 256; 189 break; 190 default: 191 return 0; 192 } 193 if (spd_crc_cover > spd_len) 194 return 0; 195 crc_calc = spdcrc16(sc, spd_crc_cover); 196 crc_spd = (sc->sc_read)(sc, 127) << 8; 197 crc_spd |= (sc->sc_read)(sc, 126); 198 if (crc_calc != crc_spd) { 199 aprint_debug("crc16 failed, covers %d bytes, " 200 "calc = 0x%04x, spd = 0x%04x\n", 201 spd_crc_cover, crc_calc, crc_spd); 202 return 0; 203 } 204 return 1; 205 } 206 207 /* For unrecognized memory types, don't match at all */ 208 return 0; 209 } 210 211 void 212 spdmem_common_attach(struct spdmem_softc *sc, device_t self) 213 { 214 struct spdmem *s = &(sc->sc_spd_data); 215 const char *type; 216 const char *rambus_rev = "Reserved"; 217 int dimm_size; 218 unsigned int i, spd_len, spd_size; 219 const struct sysctlnode *node = NULL; 220 221 /* 222 * FBDIMM and DDR3 (and probably all newer) have a different 223 * encoding of the SPD EEPROM used/total sizes 224 */ 225 s->sm_len = (sc->sc_read)(sc, 0); 226 s->sm_size = (sc->sc_read)(sc, 1); 227 s->sm_type = (sc->sc_read)(sc, 2); 228 229 if (s->sm_type >= SPDMEM_MEMTYPE_FBDIMM) { 230 spd_size = 64 << (s->sm_len & SPDMEM_SPDSIZE_MASK); 231 switch (s->sm_len & SPDMEM_SPDLEN_MASK) { 232 case SPDMEM_SPDLEN_128: 233 spd_len = 128; 234 break; 235 case SPDMEM_SPDLEN_176: 236 spd_len = 176; 237 break; 238 case SPDMEM_SPDLEN_256: 239 spd_len = 256; 240 break; 241 default: 242 spd_len = 64; 243 break; 244 } 245 } else { 246 spd_size = 1 << s->sm_size; 247 spd_len = s->sm_len; 248 if (spd_len < 64) 249 spd_len = 64; 250 } 251 if (spd_len > spd_size) 252 spd_len = spd_size; 253 if (spd_len > sizeof(struct spdmem)) 254 spd_len = sizeof(struct spdmem); 255 for (i = 3; i < spd_len; i++) 256 ((uint8_t *)s)[i] = (sc->sc_read)(sc, i); 257 258 /* 259 * Setup our sysctl subtree, hw.spdmemN 260 */ 261 sc->sc_sysctl_log = NULL; 262 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, &node, 263 0, CTLTYPE_NODE, 264 device_xname(self), NULL, NULL, 0, NULL, 0, 265 CTL_HW, CTL_CREATE, CTL_EOL); 266 if (node != NULL && spd_len != 0) 267 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, NULL, 268 0, 269 CTLTYPE_STRUCT, "spd_data", 270 SYSCTL_DESCR("raw spd data"), NULL, 271 0, s, spd_len, 272 CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL); 273 274 /* 275 * Decode and print key SPD contents 276 */ 277 if (IS_RAMBUS_TYPE) { 278 if (s->sm_type == SPDMEM_MEMTYPE_RAMBUS) 279 type = "Rambus"; 280 else if (s->sm_type == SPDMEM_MEMTYPE_DIRECTRAMBUS) 281 type = "Direct Rambus"; 282 else 283 type = "Rambus (unknown)"; 284 285 switch (s->sm_len) { 286 case 0: 287 rambus_rev = "Invalid"; 288 break; 289 case 1: 290 rambus_rev = "0.7"; 291 break; 292 case 2: 293 rambus_rev = "1.0"; 294 break; 295 default: 296 rambus_rev = "Reserved"; 297 break; 298 } 299 } else { 300 if (s->sm_type < __arraycount(spdmem_basic_types)) 301 type = spdmem_basic_types[s->sm_type]; 302 else 303 type = "unknown memory type"; 304 305 if (s->sm_type == SPDMEM_MEMTYPE_EDO && 306 s->sm_fpm.fpm_superset == SPDMEM_SUPERSET_EDO_PEM) 307 type = spdmem_superset_types[SPDMEM_SUPERSET_EDO_PEM]; 308 if (s->sm_type == SPDMEM_MEMTYPE_SDRAM && 309 s->sm_sdr.sdr_superset == SPDMEM_SUPERSET_SDRAM_PEM) 310 type = spdmem_superset_types[SPDMEM_SUPERSET_SDRAM_PEM]; 311 if (s->sm_type == SPDMEM_MEMTYPE_DDRSDRAM && 312 s->sm_ddr.ddr_superset == SPDMEM_SUPERSET_DDR_ESDRAM) 313 type = 314 spdmem_superset_types[SPDMEM_SUPERSET_DDR_ESDRAM]; 315 if (s->sm_type == SPDMEM_MEMTYPE_SDRAM && 316 s->sm_sdr.sdr_superset == SPDMEM_SUPERSET_ESDRAM) { 317 type = spdmem_superset_types[SPDMEM_SUPERSET_ESDRAM]; 318 } 319 } 320 321 strlcpy(sc->sc_type, type, SPDMEM_TYPE_MAXLEN); 322 if (node != NULL) 323 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, NULL, 324 0, 325 CTLTYPE_STRING, "mem_type", 326 SYSCTL_DESCR("memory module type"), NULL, 327 0, sc->sc_type, 0, 328 CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL); 329 330 if (IS_RAMBUS_TYPE) { 331 aprint_naive("\n"); 332 aprint_normal("\n"); 333 aprint_normal_dev(self, "%s, SPD Revision %s", type, rambus_rev); 334 dimm_size = 1 << (s->sm_rdr.rdr_rows + s->sm_rdr.rdr_cols - 13); 335 if (dimm_size >= 1024) 336 aprint_normal(", %dGB\n", dimm_size / 1024); 337 else 338 aprint_normal(", %dMB\n", dimm_size); 339 340 /* No further decode for RAMBUS memory */ 341 return; 342 } 343 switch (s->sm_type) { 344 case SPDMEM_MEMTYPE_EDO: 345 case SPDMEM_MEMTYPE_FPM: 346 decode_edofpm(node, self, s); 347 break; 348 case SPDMEM_MEMTYPE_ROM: 349 decode_rom(node, self, s); 350 break; 351 case SPDMEM_MEMTYPE_SDRAM: 352 decode_sdram(node, self, s, spd_len); 353 break; 354 case SPDMEM_MEMTYPE_DDRSDRAM: 355 decode_ddr(node, self, s); 356 break; 357 case SPDMEM_MEMTYPE_DDR2SDRAM: 358 decode_ddr2(node, self, s); 359 break; 360 case SPDMEM_MEMTYPE_DDR3SDRAM: 361 decode_ddr3(node, self, s); 362 break; 363 case SPDMEM_MEMTYPE_FBDIMM: 364 case SPDMEM_MEMTYPE_FBDIMM_PROBE: 365 decode_fbdimm(node, self, s); 366 break; 367 } 368 369 /* Dump SPD */ 370 for (i = 0; i < spd_len; i += 16) { 371 unsigned int j, k; 372 aprint_debug_dev(self, "0x%02x:", i); 373 k = (spd_len > (i + 16)) ? i + 16 : spd_len; 374 for (j = i; j < k; j++) 375 aprint_debug(" %02x", ((uint8_t *)s)[j]); 376 aprint_debug("\n"); 377 } 378 } 379 380 int 381 spdmem_common_detach(struct spdmem_softc *sc, device_t self) 382 { 383 sysctl_teardown(&sc->sc_sysctl_log); 384 385 return 0; 386 } 387 388 static void 389 decode_size_speed(device_t self, const struct sysctlnode *node, 390 int dimm_size, int cycle_time, int d_clk, int bits, 391 bool round, const char *ddr_type_string, int speed) 392 { 393 int p_clk; 394 struct spdmem_softc *sc = device_private(self); 395 396 if (dimm_size < 1024) 397 aprint_normal("%dMB", dimm_size); 398 else 399 aprint_normal("%dGB", dimm_size / 1024); 400 if (node != NULL) 401 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, NULL, 402 CTLFLAG_IMMEDIATE, 403 CTLTYPE_INT, "size", 404 SYSCTL_DESCR("module size in MB"), NULL, 405 dimm_size, NULL, 0, 406 CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL); 407 408 if (cycle_time == 0) { 409 aprint_normal("\n"); 410 return; 411 } 412 413 /* 414 * Calculate p_clk first, since for DDR3 we need maximum significance. 415 * DDR3 rating is not rounded to a multiple of 100. This results in 416 * cycle_time of 1.5ns displayed as PC3-10666. 417 * 418 * For SDRAM, the speed is provided by the caller so we use it. 419 */ 420 d_clk *= 1000 * 1000; 421 if (speed) 422 p_clk = speed; 423 else 424 p_clk = (d_clk * bits) / 8 / cycle_time; 425 d_clk = ((d_clk + cycle_time / 2) ) / cycle_time; 426 if (round) { 427 if ((p_clk % 100) >= 50) 428 p_clk += 50; 429 p_clk -= p_clk % 100; 430 } 431 aprint_normal(", %dMHz (%s-%d)\n", 432 d_clk, ddr_type_string, p_clk); 433 if (node != NULL) 434 sysctl_createv(&sc->sc_sysctl_log, 0, NULL, NULL, 435 CTLFLAG_IMMEDIATE, 436 CTLTYPE_INT, "speed", 437 SYSCTL_DESCR("memory speed in MHz"), 438 NULL, d_clk, NULL, 0, 439 CTL_HW, node->sysctl_num, CTL_CREATE, CTL_EOL); 440 } 441 442 static void 443 decode_voltage_refresh(device_t self, struct spdmem *s) 444 { 445 const char *voltage, *refresh; 446 447 if (s->sm_voltage < __arraycount(spdmem_voltage_types)) 448 voltage = spdmem_voltage_types[s->sm_voltage]; 449 else 450 voltage = "unknown"; 451 452 if (s->sm_refresh < __arraycount(spdmem_refresh_types)) 453 refresh = spdmem_refresh_types[s->sm_refresh]; 454 else 455 refresh = "unknown"; 456 457 aprint_verbose_dev(self, "voltage %s, refresh time %s%s\n", 458 voltage, refresh, 459 s->sm_selfrefresh?" (self-refreshing)":""); 460 } 461 462 static void 463 decode_edofpm(const struct sysctlnode *node, device_t self, struct spdmem *s) { 464 aprint_naive("\n"); 465 aprint_normal("\n"); 466 aprint_normal_dev(self, "%s", spdmem_basic_types[s->sm_type]); 467 468 aprint_normal("\n"); 469 aprint_verbose_dev(self, 470 "%d rows, %d cols, %d banks, %dns tRAC, %dns tCAC\n", 471 s->sm_fpm.fpm_rows, s->sm_fpm.fpm_cols, s->sm_fpm.fpm_banks, 472 s->sm_fpm.fpm_tRAC, s->sm_fpm.fpm_tCAC); 473 } 474 475 static void 476 decode_rom(const struct sysctlnode *node, device_t self, struct spdmem *s) { 477 aprint_naive("\n"); 478 aprint_normal("\n"); 479 aprint_normal_dev(self, "%s", spdmem_basic_types[s->sm_type]); 480 481 aprint_normal("\n"); 482 aprint_verbose_dev(self, "%d rows, %d cols, %d banks\n", 483 s->sm_rom.rom_rows, s->sm_rom.rom_cols, s->sm_rom.rom_banks); 484 } 485 486 static void 487 decode_sdram(const struct sysctlnode *node, device_t self, struct spdmem *s, 488 int spd_len) { 489 int dimm_size, cycle_time, bits, tAA, i, speed, freq; 490 491 aprint_naive("\n"); 492 aprint_normal("\n"); 493 aprint_normal_dev(self, "%s", spdmem_basic_types[s->sm_type]); 494 495 aprint_normal("%s, %s, ", 496 (s->sm_sdr.sdr_mod_attrs & SPDMEM_SDR_MASK_REG)? 497 " (registered)":"", 498 (s->sm_config < __arraycount(spdmem_parity_types))? 499 spdmem_parity_types[s->sm_config]:"invalid parity"); 500 501 dimm_size = 1 << (s->sm_sdr.sdr_rows + s->sm_sdr.sdr_cols - 17); 502 dimm_size *= s->sm_sdr.sdr_banks * s->sm_sdr.sdr_banks_per_chip; 503 504 cycle_time = s->sm_sdr.sdr_cycle_whole * 1000 + 505 s->sm_sdr.sdr_cycle_tenths * 100; 506 bits = le16toh(s->sm_sdr.sdr_datawidth); 507 if (s->sm_config == 1 || s->sm_config == 2) 508 bits -= 8; 509 510 /* Calculate speed here - from OpenBSD */ 511 if (spd_len >= 128) 512 freq = ((uint8_t *)s)[126]; 513 else 514 freq = 0; 515 switch (freq) { 516 /* 517 * Must check cycle time since some PC-133 DIMMs 518 * actually report PC-100 519 */ 520 case 100: 521 case 133: 522 if (cycle_time < 8000) 523 speed = 133; 524 else 525 speed = 100; 526 break; 527 case 0x66: /* Legacy DIMMs use _hex_ 66! */ 528 default: 529 speed = 66; 530 } 531 decode_size_speed(self, node, dimm_size, cycle_time, 1, bits, FALSE, 532 "PC", speed); 533 534 aprint_verbose_dev(self, 535 "%d rows, %d cols, %d banks, %d banks/chip, %d.%dns cycle time\n", 536 s->sm_sdr.sdr_rows, s->sm_sdr.sdr_cols, s->sm_sdr.sdr_banks, 537 s->sm_sdr.sdr_banks_per_chip, cycle_time/1000, 538 (cycle_time % 1000) / 100); 539 540 tAA = 0; 541 for (i = 0; i < 8; i++) 542 if (s->sm_sdr.sdr_tCAS & (1 << i)) 543 tAA = i; 544 tAA++; 545 aprint_verbose_dev(self, LATENCY, tAA, s->sm_sdr.sdr_tRCD, 546 s->sm_sdr.sdr_tRP, s->sm_sdr.sdr_tRAS); 547 548 decode_voltage_refresh(self, s); 549 } 550 551 static void 552 decode_ddr(const struct sysctlnode *node, device_t self, struct spdmem *s) { 553 int dimm_size, cycle_time, bits, tAA, i; 554 555 aprint_naive("\n"); 556 aprint_normal("\n"); 557 aprint_normal_dev(self, "%s", spdmem_basic_types[s->sm_type]); 558 559 aprint_normal("%s, %s, ", 560 (s->sm_ddr.ddr_mod_attrs & SPDMEM_DDR_MASK_REG)? 561 " (registered)":"", 562 (s->sm_config < __arraycount(spdmem_parity_types))? 563 spdmem_parity_types[s->sm_config]:"invalid parity"); 564 565 dimm_size = 1 << (s->sm_ddr.ddr_rows + s->sm_ddr.ddr_cols - 17); 566 dimm_size *= s->sm_ddr.ddr_ranks * s->sm_ddr.ddr_banks_per_chip; 567 568 cycle_time = s->sm_ddr.ddr_cycle_whole * 1000 + 569 spdmem_cycle_frac[s->sm_ddr.ddr_cycle_tenths]; 570 bits = le16toh(s->sm_ddr.ddr_datawidth); 571 if (s->sm_config == 1 || s->sm_config == 2) 572 bits -= 8; 573 decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, TRUE, 574 "PC", 0); 575 576 aprint_verbose_dev(self, 577 "%d rows, %d cols, %d ranks, %d banks/chip, %d.%dns cycle time\n", 578 s->sm_ddr.ddr_rows, s->sm_ddr.ddr_cols, s->sm_ddr.ddr_ranks, 579 s->sm_ddr.ddr_banks_per_chip, cycle_time/1000, 580 (cycle_time % 1000 + 50) / 100); 581 582 tAA = 0; 583 for (i = 2; i < 8; i++) 584 if (s->sm_ddr.ddr_tCAS & (1 << i)) 585 tAA = i; 586 tAA /= 2; 587 588 #define __DDR_ROUND(scale, field) \ 589 ((scale * s->sm_ddr.field + cycle_time - 1) / cycle_time) 590 591 aprint_verbose_dev(self, LATENCY, tAA, __DDR_ROUND(250, ddr_tRCD), 592 __DDR_ROUND(250, ddr_tRP), __DDR_ROUND(1000, ddr_tRAS)); 593 594 #undef __DDR_ROUND 595 596 decode_voltage_refresh(self, s); 597 } 598 599 static void 600 decode_ddr2(const struct sysctlnode *node, device_t self, struct spdmem *s) { 601 int dimm_size, cycle_time, bits, tAA, i; 602 603 aprint_naive("\n"); 604 aprint_normal("\n"); 605 aprint_normal_dev(self, "%s", spdmem_basic_types[s->sm_type]); 606 607 aprint_normal("%s, %s, ", 608 (s->sm_ddr2.ddr2_mod_attrs & SPDMEM_DDR2_MASK_REG)? 609 " (registered)":"", 610 (s->sm_config < __arraycount(spdmem_parity_types))? 611 spdmem_parity_types[s->sm_config]:"invalid parity"); 612 613 dimm_size = 1 << (s->sm_ddr2.ddr2_rows + s->sm_ddr2.ddr2_cols - 17); 614 dimm_size *= (s->sm_ddr2.ddr2_ranks + 1) * 615 s->sm_ddr2.ddr2_banks_per_chip; 616 617 cycle_time = s->sm_ddr2.ddr2_cycle_whole * 1000 + 618 spdmem_cycle_frac[s->sm_ddr2.ddr2_cycle_frac]; 619 bits = s->sm_ddr2.ddr2_datawidth; 620 if ((s->sm_config & 0x03) != 0) 621 bits -= 8; 622 decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, TRUE, 623 "PC2", 0); 624 625 aprint_verbose_dev(self, 626 "%d rows, %d cols, %d ranks, %d banks/chip, %d.%02dns cycle time\n", 627 s->sm_ddr2.ddr2_rows, s->sm_ddr2.ddr2_cols, 628 s->sm_ddr2.ddr2_ranks + 1, s->sm_ddr2.ddr2_banks_per_chip, 629 cycle_time / 1000, (cycle_time % 1000 + 5) /10 ); 630 631 tAA = 0; 632 for (i = 2; i < 8; i++) 633 if (s->sm_ddr2.ddr2_tCAS & (1 << i)) 634 tAA = i; 635 636 #define __DDR2_ROUND(scale, field) \ 637 ((scale * s->sm_ddr2.field + cycle_time - 1) / cycle_time) 638 639 aprint_verbose_dev(self, LATENCY, tAA, __DDR2_ROUND(250, ddr2_tRCD), 640 __DDR2_ROUND(250, ddr2_tRP), __DDR2_ROUND(1000, ddr2_tRAS)); 641 642 #undef __DDR_ROUND 643 644 decode_voltage_refresh(self, s); 645 } 646 647 static void 648 decode_ddr3(const struct sysctlnode *node, device_t self, struct spdmem *s) { 649 int dimm_size, cycle_time, bits; 650 651 aprint_naive("\n"); 652 aprint_normal(": %18s\n", s->sm_ddr3.ddr3_part); 653 aprint_normal_dev(self, "%s", spdmem_basic_types[s->sm_type]); 654 655 if (s->sm_ddr3.ddr3_mod_type == 656 SPDMEM_DDR3_TYPE_MINI_RDIMM || 657 s->sm_ddr3.ddr3_mod_type == SPDMEM_DDR3_TYPE_RDIMM) 658 aprint_normal(" (registered)"); 659 aprint_normal(", %sECC, %stemp-sensor, ", 660 (s->sm_ddr3.ddr3_hasECC)?"":"no ", 661 (s->sm_ddr3.ddr3_has_therm_sensor)?"":"no "); 662 663 /* 664 * DDR3 size specification is quite different from others 665 * 666 * Module capacity is defined as 667 * Chip_Capacity_in_bits / 8bits-per-byte * 668 * external_bus_width / internal_bus_width 669 * We further divide by 2**20 to get our answer in MB 670 */ 671 dimm_size = (s->sm_ddr3.ddr3_chipsize + 28 - 20) - 3 + 672 (s->sm_ddr3.ddr3_datawidth + 3) - 673 (s->sm_ddr3.ddr3_chipwidth + 2); 674 dimm_size = (1 << dimm_size) * (s->sm_ddr3.ddr3_physbanks + 1); 675 676 cycle_time = (1000 * s->sm_ddr3.ddr3_mtb_dividend + 677 (s->sm_ddr3.ddr3_mtb_divisor / 2)) / 678 s->sm_ddr3.ddr3_mtb_divisor; 679 cycle_time *= s->sm_ddr3.ddr3_tCKmin; 680 bits = 1 << (s->sm_ddr3.ddr3_datawidth + 3); 681 decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, FALSE, 682 "PC3", 0); 683 684 aprint_verbose_dev(self, 685 "%d rows, %d cols, %d log. banks, %d phys. banks, " 686 "%d.%03dns cycle time\n", 687 s->sm_ddr3.ddr3_rows + 9, s->sm_ddr3.ddr3_cols + 12, 688 1 << (s->sm_ddr3.ddr3_logbanks + 3), 689 s->sm_ddr3.ddr3_physbanks + 1, 690 cycle_time/1000, cycle_time % 1000); 691 692 #define __DDR3_CYCLES(field) (s->sm_ddr3.field / s->sm_ddr3.ddr3_tCKmin) 693 694 aprint_verbose_dev(self, LATENCY, __DDR3_CYCLES(ddr3_tAAmin), 695 __DDR3_CYCLES(ddr3_tRCDmin), __DDR3_CYCLES(ddr3_tRPmin), 696 (s->sm_ddr3.ddr3_tRAS_msb * 256 + s->sm_ddr3.ddr3_tRAS_lsb) / 697 s->sm_ddr3.ddr3_tCKmin); 698 699 #undef __DDR3_CYCLES 700 } 701 702 static void 703 decode_fbdimm(const struct sysctlnode *node, device_t self, struct spdmem *s) { 704 int dimm_size, cycle_time, bits; 705 706 aprint_naive("\n"); 707 aprint_normal("\n"); 708 aprint_normal_dev(self, "%s", spdmem_basic_types[s->sm_type]); 709 710 /* 711 * FB-DIMM module size calculation is very much like DDR3 712 */ 713 dimm_size = s->sm_fbd.fbdimm_rows + 12 + 714 s->sm_fbd.fbdimm_cols + 9 - 20 - 3; 715 dimm_size = (1 << dimm_size) * (1 << (s->sm_fbd.fbdimm_banks + 2)); 716 717 cycle_time = (1000 * s->sm_fbd.fbdimm_mtb_dividend + 718 (s->sm_fbd.fbdimm_mtb_divisor / 2)) / 719 s->sm_fbd.fbdimm_mtb_divisor; 720 bits = 1 << (s->sm_fbd.fbdimm_dev_width + 2); 721 decode_size_speed(self, node, dimm_size, cycle_time, 2, bits, TRUE, 722 "PC2", 0); 723 724 aprint_verbose_dev(self, 725 "%d rows, %d cols, %d banks, %d.%02dns cycle time\n", 726 s->sm_fbd.fbdimm_rows, s->sm_fbd.fbdimm_cols, 727 1 << (s->sm_fbd.fbdimm_banks + 2), 728 cycle_time / 1000, (cycle_time % 1000 + 5) /10 ); 729 730 #define __FBDIMM_CYCLES(field) (s->sm_fbd.field / s->sm_fbd.fbdimm_tCKmin) 731 732 aprint_verbose_dev(self, LATENCY, __FBDIMM_CYCLES(fbdimm_tAAmin), 733 __FBDIMM_CYCLES(fbdimm_tRCDmin), __FBDIMM_CYCLES(fbdimm_tRPmin), 734 (s->sm_fbd.fbdimm_tRAS_msb * 256 + 735 s->sm_fbd.fbdimm_tRAS_lsb) / 736 s->sm_fbd.fbdimm_tCKmin); 737 738 #undef __FBDIMM_CYCLES 739 740 decode_voltage_refresh(self, s); 741 } 742