1 /* $NetBSD: smc91cxxreg.h,v 1.2 1997/09/02 00:10:58 thorpej Exp $ */ 2 3 /* 4 * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com> 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Gardner Buchanan. 18 * 4. The name of Gardner Buchanan may not be used to endorse or promote 19 * products derived from this software without specific prior written 20 * permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 23 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 24 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 25 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 26 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 27 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 28 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 29 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 30 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 31 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * from FreeBSD Id: if_snreg.h,v 1.4 1996/03/18 15:47:30 gardner Exp 34 */ 35 36 /* 37 * This file contains register information and access macros for 38 * the SMC91xxx chipset. 39 * 40 * Information contained in this file was obtained from the SMC91C92 41 * and SMC91C94 manuals from SMC. You will need one of these in order 42 * to make any meaningful changes to this driver. Information about 43 * obtaining one can be found at http://www.smc.com in the components 44 * division. 45 * 46 * This FreeBSD driver is derived in part from the smc9194 Linux driver 47 * by Erik Stahlman. 48 */ 49 50 51 /* 52 * Wait time for memory to be free. This probably shouldn't be 53 * tuned that much, as waiting for this means nothing else happens 54 * in the system 55 */ 56 #define MEMORY_WAIT_TIME 1000 57 58 59 /* The SMC91xxx uses 16 I/O ports */ 60 #define SMC_IOSIZE 16 61 62 63 /* 64 * A description of the SMC registers is probably in order here, 65 * although for details, the SMC datasheet is invaluable. 66 * The data sheet I (GB) am using is "SMC91C92 Single Chip Ethernet 67 * Controller With RAM", Rev. 12/0/94. Constant definitions I give 68 * here are loosely based on the mnemonic names given to them in the 69 * data sheet, but there are many exceptions. 70 * 71 * Basically, the chip has 4 banks of registers (0 to 3), which 72 * are accessed by writing a number into the BANK_SELECT register 73 * (I also use a SMC_SELECT_BANK macro for this). Registers are 74 * either Byte or Word sized. My constant definitions end in _B 75 * or _W as appropriate. 76 * 77 * The banks are arranged so that for most purposes, bank 2 is all 78 * that is needed for normal run time tasks. 79 */ 80 81 82 /* 83 * Bank Select Register. This also doubles as 84 * a chip identification register. This register 85 * is mapped at the same position in all banks. 86 */ 87 #define BANK_SELECT_REG_W 0x0e 88 #define BSR_DETECT_MASK 0xff00 89 #define BSR_DETECT_VALUE 0x3300 90 91 92 /* 93 * BANK 0 94 */ 95 96 /* 97 * Transmit Control Register controls some aspects of the transmit 98 * behavior of the Ethernet Protocol Handler. 99 */ 100 #define TXMIT_CONTROL_REG_W 0x00 101 102 #define TCR_ENABLE 0x0001 /* if this is 1, we can transmit */ 103 #define TCR_LOOP 0x0002 /* Enable internal analogue loopback */ 104 #define TCR_FORCOL 0x0004 /* Force Collision on next TX */ 105 #define TCR_PAD_ENABLE 0x0080 /* Pad short packets to 64 bytes */ 106 #define TCR_NOCRC 0x0100 /* Do not append CRC */ 107 #define TCR_MON_CSN 0x0400 /* monitors the carrier status */ 108 #define TCR_FDUPLX 0x0800 /* receive packets sent out */ 109 #define TCR_STP_SQET 0x1000 /* stop transmitting if Signal quality error */ 110 #define TCR_EPH_LOOP 0x2000 /* Enable internal digital loopback */ 111 112 113 /* 114 * Status of the last transmitted frame and instantaneous status of 115 * the Ethernet Protocol Handler jumbled together. In auto-release 116 * mode this information is simply discarded after each TX. This info 117 * is copied to the status word of in-memory packets after transmit 118 * where relevent statuses can be checked. 119 */ 120 #define EPH_STATUS_REG_W 0x02 121 122 #define EPHSR_TX_SUC 0x0001 /* Transmit was successful */ 123 #define EPHSR_SNGLCOL 0x0002 /* Single collision occurred */ 124 #define EPHSR_MULCOL 0x0004 /* Multiple Collisions occurred */ 125 #define EPHSR_LTX_MULT 0x0008 /* Transmit was a multicast */ 126 #define EPHSR_16COL 0x0010 /* 16 Collisions occurred, TX disabled */ 127 #define EPHSR_SQET 0x0020 /* SQE Test failed, TX disabled */ 128 #define EPHSR_LTX_BRD 0x0040 /* Transmit was a broadcast */ 129 #define EPHSR_DEFR 0x0080 /* TX deferred due to carrier det. */ 130 #define EPHSR_LATCOL 0x0200 /* Late collision detected, TX disabled */ 131 #define EPHSR_LOST_CAR 0x0400 /* Lost carrier sense, TX disabled */ 132 #define EPHSR_EXC_DEF 0x0800 /* Excessive deferrals in TX >2 MAXETHER 133 * times */ 134 #define EPHSR_CTR_ROL 0x1000 /* Some ECR Counter(s) rolled over */ 135 #define EPHSR_RX_OVRN 0x2000 /* Receiver overrun, packets dropped */ 136 #define EPHSR_LINK_OK 0x4000 /* Link integrity is OK */ 137 #define EPHSR_TXUNRN 0x8000 /* Transmit underrun */ 138 139 140 /* 141 * Receiver Control Register controls some aspects of the receive 142 * behavior of the Ethernet Protocol Handler. 143 */ 144 #define RECV_CONTROL_REG_W 0x04 145 146 #define RCR_RX_ABORT 0x0001 /* Received huge packet */ 147 #define RCR_PROMISC 0x0002 /* enable promiscuous mode */ 148 #define RCR_ALMUL 0x0004 /* receive all multicast packets */ 149 #define RCR_ENABLE 0x0100 /* IFF this is set, we can recieve packets */ 150 #define RCR_STRIP_CRC 0x0200 /* strips CRC */ 151 #define RCR_GAIN_BITS 0x0c00 /* PLL Gain control (for testing) */ 152 #define RCR_FILT_CAR 0x4000 /* Enable 12 bit carrier filter */ 153 #define RCR_SOFTRESET 0x8000 /* Resets the EPH logic */ 154 155 156 /* 157 * TX Statistics counters 158 */ 159 #define COUNTER_REG_W 0x06 160 161 #define ECR_COLN_MASK 0x000f /* Vanilla collisions */ 162 #define ECR_MCOLN_MASK 0x00f0 /* Multiple collisions */ 163 #define ECR_DTX_MASK 0x0f00 /* Deferred transmits */ 164 #define ECR_EXDTX_MASK 0xf000 /* Excessively deferred transmits */ 165 166 167 /* 168 * Memory Information 169 */ 170 #define MEM_INFO_REG_W 0x08 171 172 #define MIR_FREE_MASK 0xff00 /* Free memory pages available */ 173 #define MIR_TOTAL_MASK 0x00ff /* Total memory pages available */ 174 175 176 /* 177 * Memory Configuration 178 */ 179 #define MEM_CFG_REG_W 0x0a 180 181 #define MCR_TXRSV_MASK 0x001f /* Count of pages reserved for transmit */ 182 183 184 /* 185 * Bank 0, Register 0x0c is unused in the SMC91C92 186 */ 187 188 189 /* 190 * BANK 1 191 */ 192 193 /* 194 * Adapter configuration 195 */ 196 #define CONFIG_REG_W 0x00 197 198 #define CR_INT_SEL0 0x0002 /* Interrupt selector */ 199 #define CR_INT_SEL1 0x0004 /* Interrupt selector */ 200 #define CR_DIS_LINK 0x0040 /* Disable 10BaseT Link Test */ 201 #define CR_16BIT 0x0080 /* Bus width */ 202 #define CR_AUI_SELECT 0x0100 /* Use external (AUI) Transceiver */ 203 #define CR_SET_SQLCH 0x0200 /* Squelch level */ 204 #define CR_FULL_STEP 0x0400 /* AUI signalling mode */ 205 #define CR_NOW_WAIT_ST 0x1000 /* Disable bus wait states */ 206 207 208 /* 209 * The contents of this port are used by the adapter 210 * to decode its I/O address. We use it as a varification 211 * that the adapter is detected properly when probing. 212 */ 213 #define BASE_ADDR_REG_W 0x02 /* The selected I/O Base addr. */ 214 215 216 /* 217 * These registers hold the Ethernet MAC address. 218 */ 219 #define IAR_ADDR0_REG_W 0x04 /* My Ethernet address */ 220 #define IAR_ADDR1_REG_W 0x06 /* My Ethernet address */ 221 #define IAR_ADDR2_REG_W 0x08 /* My Ethernet address */ 222 223 224 /* 225 * General purpose register used for talking to the EEPROM. 226 */ 227 #define GENERAL_REG_W 0x0a 228 229 230 /* 231 * Control register used for talking to the EEPROM and 232 * setting some EPH functions. 233 */ 234 #define CONTROL_REG_W 0x0c 235 236 #define CTR_STORE 0x0001 /* Store something to EEPROM */ 237 #define CTR_RELOAD 0x0002 /* Read EEPROM into registers */ 238 #define CTR_EEPROM_SEL 0x0004 /* Select registers for Reload/Store */ 239 #define CTR_TE_ENABLE 0x0020 /* Enable TX Error detection via EPH_INT */ 240 #define CTR_CR_ENABLE 0x0040 /* Enable Counter Rollover via EPH_INT */ 241 #define CTR_LE_ENABLE 0x0080 /* Enable Link Error detection via EPH_INT */ 242 #define CTR_AUTO_RELEASE 0x0800 /* Enable auto release mode for TX */ 243 #define CTR_POWERDOWN 0x2000 /* Enter powerdown mode */ 244 #define CTR_RCV_BAD 0x4000 /* Enable receipt of frames with bad CRC */ 245 246 247 /* 248 * BANK 2 249 */ 250 251 252 /* 253 * Memory Management Unit Control Register 254 * Controls allocation of memory to receive and 255 * transmit functions. 256 */ 257 #define MMU_CMD_REG_W 0x00 258 259 #define MMUCR_BUSY 0x0001 /* MMU busy performing a release */ 260 261 /* 262 * MMU Commands: 263 */ 264 #define MMUCR_NOP 0x0000 /* Do nothing */ 265 #define MMUCR_ALLOC 0x0020 /* Or with number of 256 byte packets - 1 */ 266 #define MMUCR_RESET 0x0040 /* Reset MMU State */ 267 #define MMUCR_REMOVE 0x0060 /* Dequeue (but not free) current RX packet */ 268 #define MMUCR_RELEASE 0x0080 /* Dequeue and free the current RX packet */ 269 #define MMUCR_FREEPKT 0x00a0 /* Release packet in PNR register */ 270 #define MMUCR_ENQUEUE 0x00c0 /* Enqueue the packet for transmit */ 271 #define MMUCR_RESETTX 0x00e0 /* Reset transmit queues */ 272 273 /* 274 * Packet Number at TX Area 275 */ 276 #define PACKET_NUM_REG_B 0x02 277 278 /* 279 * Packet number resulting from MMUCR_ALLOC 280 */ 281 #define ALLOC_RESULT_REG_B 0x03 282 #define ARR_FAILED 0x80 283 284 /* 285 * Transmit and receive queue heads 286 */ 287 #define FIFO_PORTS_REG_W 0x04 288 #define FIFO_REMPTY 0x8000 289 #define FIFO_TEMPTY 0x0080 290 #define FIFO_RX_MASK 0x7f00 291 #define FIFO_TX_MASK 0x007f 292 293 294 /* 295 * The address within the packet for reading/writing. The 296 * PTR_RCV bit is tricky. When PTR_RCV==1, the packet number 297 * to be read is found in the FIFO_PORTS_REG_W, FIFO_RX_MASK. 298 * When PTR_RCV==0, the packet number to be written is found 299 * in the PACKET_NUM_REG_B. 300 */ 301 #define POINTER_REG_W 0x06 302 303 #define PTR_READ 0x2000 /* Intended access mode */ 304 #define PTR_AUTOINC 0x4000 /* Do auto inc after read/write */ 305 #define PTR_RCV 0x8000 /* FIFO_RX is packet, otherwise PNR is packet */ 306 307 /* 308 * Data I/O register to be used in conjunction with 309 * The pointer register to read and write data from the 310 * card. The same register can be used for byte and word 311 * ops. 312 */ 313 #define DATA_REG_W 0x08 314 #define DATA_REG_B 0x08 315 #define DATA_1_REG_B 0x08 316 #define DATA_2_REG_B 0x0a 317 318 319 /* 320 * Sense interrupt status (READ) 321 */ 322 #define INTR_STAT_REG_B 0x0c 323 324 325 /* 326 * Acknowledge interrupt sources (WRITE) 327 */ 328 #define INTR_ACK_REG_B 0x0c 329 330 331 /* 332 * Interrupt mask. Bit set indicates interrupt allowed. 333 */ 334 #define INTR_MASK_REG_B 0x0d 335 336 /* 337 * Interrupts 338 */ 339 #define IM_RCV_INT 0x01 /* A packet has been received */ 340 #define IM_TX_INT 0x02 /* Packet TX complete */ 341 #define IM_TX_EMPTY_INT 0x04 /* No packets left to TX */ 342 #define IM_ALLOC_INT 0x08 /* Memory allocation completed */ 343 #define IM_RX_OVRN_INT 0x10 /* Receiver was overrun */ 344 #define IM_EPH_INT 0x20 /* Misc. EPH conditions (see CONTROL_REG_W) */ 345 #define IM_ERCV_INT 0x40 /* not on SMC9192 */ 346 347 348 /* 349 * BANK 3 350 */ 351 352 353 /* 354 * Multicast subscriptions. 355 * The multicast handling in the SMC90Cxx is quite complicated. A table 356 * of multicast address subscriptions is provided and a clever way of 357 * speeding the search of that table by hashing is implemented in the 358 * hardware. I have ignored this and simply subscribed to all multicasts 359 * and let the kernel deal with the results. 360 */ 361 #define MULTICAST1_REG_W 0x00 362 #define MULTICAST2_REG_W 0x02 363 #define MULTICAST3_REG_W 0x04 364 #define MULTICAST4_REG_W 0x06 365 366 /* 367 * These registers do not exist on SMC9192, or at least 368 * are not documented in the SMC91C92 data sheet. 369 * The REVISION_REG_W register does however seem to work. 370 */ 371 #define MGMT_REG_W 0x08 372 373 #define REVISION_REG_W 0x0a /* (hi: chip id low: rev #) */ 374 #define RR_REV(x) ((x) & 0x0f) 375 #define RR_ID(x) (((x) >> 4) & 0x0f) 376 377 #define ERCV_REG_W 0x0c 378 379 /* 380 * These are constants expected to be found in the 381 * chip id register. 382 */ 383 #define CHIP_9190 3 384 #define CHIP_9194 4 385 #define CHIP_9195 5 386 #define CHIP_91100 7 387 388 389 /* 390 * When packets are stuffed into the card or sucked out of the card 391 * they are set up more or less as follows: 392 * 393 * Addr msbyte lsbyte 394 * 00 SSSSSSSS SSSSSSSS - STATUS-WORD 16 bit TX or RX status 395 * 02 RRRRR - RESERVED (unused) 396 * 02 CCC CCCCCCCC - BYTE COUNT (RX: always even, TX: bit 0 ignored) 397 * 04 DDDDDDDD DDDDDDDD - DESTINATION ADDRESS 398 * 06 DDDDDDDD DDDDDDDD (48 bit Ethernet MAC Address) 399 * 08 DDDDDDDD DDDDDDDD 400 * 0A SSSSSSSS SSSSSSSS - SOURCE ADDRESS 401 * 0C SSSSSSSS SSSSSSSS (48 bit Ethernet MAC Address) 402 * 0E SSSSSSSS SSSSSSSS 403 * 10 PPPPPPPP PPPPPPPP 404 * .. PPPPPPPP PPPPPPPP 405 * C-2 CCCCCCCC - CONTROL BYTE 406 * C-2 PPPPPPPP - Last data byte (If odd length) 407 * 408 * The STATUS_WORD is derived from the EPH_STATUS_REG_W register 409 * during transmit and is composed of another set of bits described 410 * below during receive. 411 */ 412 413 414 /* 415 * Receive status bits. These values are found in the status word 416 * field of a received packet. For receive packets I use the RS_ODDFRAME 417 * to detect whether a frame has an extra byte on it. The CTLB_ODD 418 * bit of the control byte tells the same thing. 419 */ 420 #define RS_MULTICAST 0x0001 /* Packet is multicast */ 421 #define RS_HASH_MASK 0x007e /* Mask of multicast hash value */ 422 #define RS_TOOSHORT 0x0400 /* Frame was a runt, <64 bytes */ 423 #define RS_TOOLONG 0x0800 /* Frame was giant, >1518 */ 424 #define RS_ODDFRAME 0x1000 /* Frame is odd lengthed */ 425 #define RS_BADCRC 0x2000 /* Frame had CRC error */ 426 #define RS_ALGNERR 0x8000 /* Frame had alignment error */ 427 #define RS_ERRORS (RS_ALGNERR | RS_BADCRC | RS_TOOLONG | RS_TOOSHORT) 428 429 #define RLEN_MASK 0x07ff /* Significant length bits in RX length */ 430 431 /* 432 * The control byte has the following significant bits. 433 * For transmit, the CTLB_ODD bit specifies whether an extra byte 434 * is present in the frame. Bit 0 of the byte count field is 435 * ignored. I just pad every frame to even length and forget about 436 * it. 437 */ 438 #define CTLB_CRC 0x10 /* Add CRC for this packet (TX only) */ 439 #define CTLB_ODD 0x20 /* The packet length is ODD */ 440