1 /* $NetBSD: smc91cxx.c,v 1.79 2010/11/13 13:52:02 uebayasi Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com> 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Gardner Buchanan. 48 * 4. The name of Gardner Buchanan may not be used to endorse or promote 49 * products derived from this software without specific prior written 50 * permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 55 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 56 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 57 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 61 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 * from FreeBSD Id: if_sn.c,v 1.4 1996/03/18 15:47:16 gardner Exp 64 */ 65 66 /* 67 * Core driver for the SMC 91Cxx family of Ethernet chips. 68 * 69 * Memory allocation interrupt logic is drived from an SMC 91C90 driver 70 * written for NetBSD/amiga by Michael Hitch. 71 */ 72 73 #include <sys/cdefs.h> 74 __KERNEL_RCSID(0, "$NetBSD: smc91cxx.c,v 1.79 2010/11/13 13:52:02 uebayasi Exp $"); 75 76 #include "opt_inet.h" 77 #include "rnd.h" 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/mbuf.h> 82 #include <sys/syslog.h> 83 #include <sys/socket.h> 84 #include <sys/device.h> 85 #include <sys/kernel.h> 86 #include <sys/malloc.h> 87 #include <sys/ioctl.h> 88 #include <sys/errno.h> 89 #if NRND > 0 90 #include <sys/rnd.h> 91 #endif 92 93 #include <sys/bus.h> 94 #include <sys/intr.h> 95 96 #include <net/if.h> 97 #include <net/if_dl.h> 98 #include <net/if_ether.h> 99 #include <net/if_media.h> 100 101 #ifdef INET 102 #include <netinet/in.h> 103 #include <netinet/if_inarp.h> 104 #include <netinet/in_systm.h> 105 #include <netinet/in_var.h> 106 #include <netinet/ip.h> 107 #endif 108 109 #include <net/bpf.h> 110 #include <net/bpfdesc.h> 111 112 #include <dev/mii/mii.h> 113 #include <dev/mii/miivar.h> 114 #include <dev/mii/mii_bitbang.h> 115 116 #include <dev/ic/smc91cxxreg.h> 117 #include <dev/ic/smc91cxxvar.h> 118 119 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 120 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 121 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 122 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 123 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 124 125 #define bus_space_write_stream_4 bus_space_write_4 126 #define bus_space_read_stream_4 bus_space_read_4 127 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 128 129 /* XXX Hardware padding doesn't work yet(?) */ 130 #define SMC91CXX_SW_PAD 131 132 const char *smc91cxx_idstrs[] = { 133 NULL, /* 0 */ 134 NULL, /* 1 */ 135 NULL, /* 2 */ 136 "SMC91C90/91C92", /* 3 */ 137 "SMC91C94/91C96", /* 4 */ 138 "SMC91C95", /* 5 */ 139 NULL, /* 6 */ 140 "SMC91C100", /* 7 */ 141 "SMC91C100FD", /* 8 */ 142 "SMC91C111", /* 9 */ 143 NULL, /* 10 */ 144 NULL, /* 11 */ 145 NULL, /* 12 */ 146 NULL, /* 13 */ 147 NULL, /* 14 */ 148 NULL, /* 15 */ 149 }; 150 151 /* Supported media types. */ 152 const int smc91cxx_media[] = { 153 IFM_ETHER|IFM_10_T, 154 IFM_ETHER|IFM_10_5, 155 }; 156 #define NSMC91CxxMEDIA (sizeof(smc91cxx_media) / sizeof(smc91cxx_media[0])) 157 158 /* 159 * MII bit-bang glue. 160 */ 161 u_int32_t smc91cxx_mii_bitbang_read(device_t); 162 void smc91cxx_mii_bitbang_write(device_t, u_int32_t); 163 164 const struct mii_bitbang_ops smc91cxx_mii_bitbang_ops = { 165 smc91cxx_mii_bitbang_read, 166 smc91cxx_mii_bitbang_write, 167 { 168 MR_MDO, /* MII_BIT_MDO */ 169 MR_MDI, /* MII_BIT_MDI */ 170 MR_MCLK, /* MII_BIT_MDC */ 171 MR_MDOE, /* MII_BIT_DIR_HOST_PHY */ 172 0, /* MII_BIT_DIR_PHY_HOST */ 173 } 174 }; 175 176 /* MII callbacks */ 177 int smc91cxx_mii_readreg(device_t, int, int); 178 void smc91cxx_mii_writereg(device_t, int, int, int); 179 void smc91cxx_statchg(device_t); 180 void smc91cxx_tick(void *); 181 182 int smc91cxx_mediachange(struct ifnet *); 183 void smc91cxx_mediastatus(struct ifnet *, struct ifmediareq *); 184 185 int smc91cxx_set_media(struct smc91cxx_softc *, int); 186 187 void smc91cxx_init(struct smc91cxx_softc *); 188 void smc91cxx_read(struct smc91cxx_softc *); 189 void smc91cxx_reset(struct smc91cxx_softc *); 190 void smc91cxx_start(struct ifnet *); 191 uint8_t smc91cxx_copy_tx_frame(struct smc91cxx_softc *, struct mbuf *); 192 void smc91cxx_resume(struct smc91cxx_softc *); 193 void smc91cxx_stop(struct smc91cxx_softc *); 194 void smc91cxx_watchdog(struct ifnet *); 195 int smc91cxx_ioctl(struct ifnet *, u_long, void *); 196 197 static inline int ether_cmp(const void *, const void *); 198 static inline int 199 ether_cmp(const void *va, const void *vb) 200 { 201 const u_int8_t *a = va; 202 const u_int8_t *b = vb; 203 204 return ((a[5] != b[5]) || (a[4] != b[4]) || (a[3] != b[3]) || 205 (a[2] != b[2]) || (a[1] != b[1]) || (a[0] != b[0])); 206 } 207 208 static inline void 209 smc91cxx_intr_mask_write(bus_space_tag_t bst, bus_space_handle_t bsh, 210 uint8_t mask) 211 { 212 KDASSERT((mask & IM_ERCV_INT) == 0); 213 #ifdef SMC91CXX_NO_BYTE_WRITE 214 #if BYTE_ORDER == LITTLE_ENDIAN 215 bus_space_write_2(bst, bsh, INTR_STAT_REG_B, mask << 8); 216 #else 217 bus_space_write_2(bst, bsh, INTR_STAT_REG_B, mask); 218 #endif 219 #else 220 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, mask); 221 #endif 222 KDASSERT(!(bus_space_read_1(bst, bsh, INTR_MASK_REG_B) & IM_ERCV_INT)); 223 } 224 225 static inline void 226 smc91cxx_intr_ack_write(bus_space_tag_t bst, bus_space_handle_t bsh, 227 uint8_t mask) 228 { 229 #ifdef SMC91CXX_NO_BYTE_WRITE 230 #if BYTE_ORDER == LITTLE_ENDIAN 231 bus_space_write_2(bst, bsh, INTR_ACK_REG_B, 232 mask | (bus_space_read_2(bst, bsh, INTR_ACK_REG_B) & 0xff00)); 233 #else 234 bus_space_write_2(bst, bsh, INTR_ACK_REG_B, 235 (mask << 8) | (bus_space_read_2(bst, bsh, INTR_ACK_REG_B) & 0xff)); 236 #endif 237 #else 238 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, mask); 239 #endif 240 KDASSERT(!(bus_space_read_1(bst, bsh, INTR_MASK_REG_B) & IM_ERCV_INT)); 241 } 242 243 void 244 smc91cxx_attach(struct smc91cxx_softc *sc, u_int8_t *myea) 245 { 246 struct ifnet *ifp = &sc->sc_ec.ec_if; 247 bus_space_tag_t bst = sc->sc_bst; 248 bus_space_handle_t bsh = sc->sc_bsh; 249 struct ifmedia *ifm = &sc->sc_mii.mii_media; 250 const char *idstr; 251 u_int32_t miicapabilities; 252 u_int16_t tmp; 253 u_int8_t enaddr[ETHER_ADDR_LEN]; 254 int i, aui, mult, scale, memsize; 255 char pbuf[9]; 256 257 tmp = bus_space_read_2(bst, bsh, BANK_SELECT_REG_W); 258 /* check magic number */ 259 if ((tmp & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 260 aprint_error_dev(&sc->sc_dev, "failed to detect chip, bsr=%04x\n", tmp); 261 return; 262 } 263 264 /* Make sure the chip is stopped. */ 265 smc91cxx_stop(sc); 266 267 SMC_SELECT_BANK(sc, 3); 268 tmp = bus_space_read_2(bst, bsh, REVISION_REG_W); 269 sc->sc_chipid = RR_ID(tmp); 270 idstr = smc91cxx_idstrs[sc->sc_chipid]; 271 272 aprint_normal_dev(&sc->sc_dev, ""); 273 if (idstr != NULL) 274 aprint_normal("%s, ", idstr); 275 else 276 aprint_normal("unknown chip id %d, ", sc->sc_chipid); 277 aprint_normal("revision %d, ", RR_REV(tmp)); 278 279 SMC_SELECT_BANK(sc, 0); 280 switch (sc->sc_chipid) { 281 default: 282 mult = MCR_MEM_MULT(bus_space_read_2(bst, bsh, MEM_CFG_REG_W)); 283 scale = MIR_SCALE_91C9x; 284 break; 285 286 case CHIP_91C111: 287 mult = MIR_MULT_91C111; 288 scale = MIR_SCALE_91C111; 289 } 290 memsize = bus_space_read_2(bst, bsh, MEM_INFO_REG_W) & MIR_TOTAL_MASK; 291 if (memsize == 255) memsize++; 292 memsize *= scale * mult; 293 294 format_bytes(pbuf, sizeof(pbuf), memsize); 295 aprint_normal("buffer size: %s\n", pbuf); 296 297 /* Read the station address from the chip. */ 298 SMC_SELECT_BANK(sc, 1); 299 if (myea == NULL) { 300 myea = enaddr; 301 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 302 tmp = bus_space_read_2(bst, bsh, IAR_ADDR0_REG_W + i); 303 myea[i + 1] = (tmp >> 8) & 0xff; 304 myea[i] = tmp & 0xff; 305 } 306 } 307 aprint_normal_dev(&sc->sc_dev, "MAC address %s, ", 308 ether_sprintf(myea)); 309 310 /* Initialize the ifnet structure. */ 311 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 312 ifp->if_softc = sc; 313 ifp->if_start = smc91cxx_start; 314 ifp->if_ioctl = smc91cxx_ioctl; 315 ifp->if_watchdog = smc91cxx_watchdog; 316 ifp->if_flags = 317 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 318 IFQ_SET_READY(&ifp->if_snd); 319 320 /* Attach the interface. */ 321 if_attach(ifp); 322 ether_ifattach(ifp, myea); 323 324 /* 325 * Initialize our media structures and MII info. We will 326 * probe the MII if we are on the SMC91Cxx 327 */ 328 sc->sc_mii.mii_ifp = ifp; 329 sc->sc_mii.mii_readreg = smc91cxx_mii_readreg; 330 sc->sc_mii.mii_writereg = smc91cxx_mii_writereg; 331 sc->sc_mii.mii_statchg = smc91cxx_statchg; 332 ifmedia_init(ifm, IFM_IMASK, smc91cxx_mediachange, smc91cxx_mediastatus); 333 334 SMC_SELECT_BANK(sc, 1); 335 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 336 337 miicapabilities = BMSR_MEDIAMASK|BMSR_ANEG; 338 switch (sc->sc_chipid) { 339 case CHIP_91100: 340 /* 341 * The 91100 does not have full-duplex capabilities, 342 * even if the PHY does. 343 */ 344 miicapabilities &= ~(BMSR_100TXFDX | BMSR_10TFDX); 345 case CHIP_91100FD: 346 case CHIP_91C111: 347 if (tmp & CR_MII_SELECT) { 348 aprint_normal("default media MII"); 349 if (sc->sc_chipid == CHIP_91C111) { 350 aprint_normal(" (%s PHY)\n", (tmp & CR_AUI_SELECT) ? 351 "external" : "internal"); 352 sc->sc_internal_phy = !(tmp & CR_AUI_SELECT); 353 } else 354 aprint_normal("\n"); 355 mii_attach(&sc->sc_dev, &sc->sc_mii, miicapabilities, 356 MII_PHY_ANY, MII_OFFSET_ANY, 0); 357 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 358 ifmedia_add(&sc->sc_mii.mii_media, 359 IFM_ETHER|IFM_NONE, 0, NULL); 360 ifmedia_set(&sc->sc_mii.mii_media, 361 IFM_ETHER|IFM_NONE); 362 } else { 363 ifmedia_set(&sc->sc_mii.mii_media, 364 IFM_ETHER|IFM_AUTO); 365 } 366 sc->sc_flags |= SMC_FLAGS_HAS_MII; 367 break; 368 } else 369 if (sc->sc_chipid == CHIP_91C111) { 370 /* 371 * XXX: Should bring it out of low-power mode 372 */ 373 aprint_normal("EPH interface in low power mode\n"); 374 sc->sc_internal_phy = 0; 375 return; 376 } 377 /*FALLTHROUGH*/ 378 default: 379 aprint_normal("default media %s\n", (aui = (tmp & CR_AUI_SELECT)) ? 380 "AUI" : "UTP"); 381 for (i = 0; i < NSMC91CxxMEDIA; i++) 382 ifmedia_add(ifm, smc91cxx_media[i], 0, NULL); 383 ifmedia_set(ifm, IFM_ETHER | (aui ? IFM_10_5 : IFM_10_T)); 384 break; 385 } 386 387 #if NRND > 0 388 rnd_attach_source(&sc->rnd_source, device_xname(&sc->sc_dev), 389 RND_TYPE_NET, 0); 390 #endif 391 392 callout_init(&sc->sc_mii_callout, 0); 393 394 /* The attach is successful. */ 395 sc->sc_flags |= SMC_FLAGS_ATTACHED; 396 } 397 398 /* 399 * Change media according to request. 400 */ 401 int 402 smc91cxx_mediachange(struct ifnet *ifp) 403 { 404 struct smc91cxx_softc *sc = ifp->if_softc; 405 406 return (smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_media)); 407 } 408 409 int 410 smc91cxx_set_media(struct smc91cxx_softc *sc, int media) 411 { 412 bus_space_tag_t bst = sc->sc_bst; 413 bus_space_handle_t bsh = sc->sc_bsh; 414 u_int16_t tmp; 415 int rc; 416 417 /* 418 * If the interface is not currently powered on, just return. 419 * When it is enabled later, smc91cxx_init() will properly set 420 * up the media for us. 421 */ 422 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) 423 return (0); 424 425 if (IFM_TYPE(media) != IFM_ETHER) 426 return (EINVAL); 427 428 if ((sc->sc_flags & SMC_FLAGS_HAS_MII) == 0 || 429 (rc = mii_mediachg(&sc->sc_mii)) == ENXIO) 430 rc = 0; 431 432 switch (IFM_SUBTYPE(media)) { 433 case IFM_10_T: 434 case IFM_10_5: 435 SMC_SELECT_BANK(sc, 1); 436 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 437 if (IFM_SUBTYPE(media) == IFM_10_5) 438 tmp |= CR_AUI_SELECT; 439 else 440 tmp &= ~CR_AUI_SELECT; 441 bus_space_write_2(bst, bsh, CONFIG_REG_W, tmp); 442 delay(20000); /* XXX is this needed? */ 443 break; 444 445 default: 446 return (EINVAL); 447 } 448 449 return rc; 450 } 451 452 /* 453 * Notify the world which media we're using. 454 */ 455 void 456 smc91cxx_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 457 { 458 struct smc91cxx_softc *sc = ifp->if_softc; 459 bus_space_tag_t bst = sc->sc_bst; 460 bus_space_handle_t bsh = sc->sc_bsh; 461 u_int16_t tmp; 462 463 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) { 464 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 465 ifmr->ifm_status = 0; 466 return; 467 } 468 469 /* 470 * If we have MII, go ask the PHY what's going on. 471 */ 472 if (sc->sc_flags & SMC_FLAGS_HAS_MII) { 473 mii_pollstat(&sc->sc_mii); 474 ifmr->ifm_active = sc->sc_mii.mii_media_active; 475 ifmr->ifm_status = sc->sc_mii.mii_media_status; 476 return; 477 } 478 479 SMC_SELECT_BANK(sc, 1); 480 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 481 ifmr->ifm_active = 482 IFM_ETHER | ((tmp & CR_AUI_SELECT) ? IFM_10_5 : IFM_10_T); 483 } 484 485 /* 486 * Reset and initialize the chip. 487 */ 488 void 489 smc91cxx_init(struct smc91cxx_softc *sc) 490 { 491 struct ifnet *ifp = &sc->sc_ec.ec_if; 492 bus_space_tag_t bst = sc->sc_bst; 493 bus_space_handle_t bsh = sc->sc_bsh; 494 u_int16_t tmp; 495 const u_int8_t *enaddr; 496 int s, i; 497 498 s = splnet(); 499 500 /* 501 * This resets the registers mostly to defaults, but doesn't 502 * affect the EEPROM. After the reset cycle, we pause briefly 503 * for the chip to recover. 504 * 505 * XXX how long are we really supposed to delay? --thorpej 506 */ 507 SMC_SELECT_BANK(sc, 0); 508 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, RCR_SOFTRESET); 509 delay(100); 510 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); 511 delay(200); 512 513 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); 514 515 /* Set the Ethernet address. */ 516 SMC_SELECT_BANK(sc, 1); 517 enaddr = (const u_int8_t *)CLLADDR(ifp->if_sadl); 518 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 519 tmp = enaddr[i + 1] << 8 | enaddr[i]; 520 bus_space_write_2(bst, bsh, IAR_ADDR0_REG_W + i, tmp); 521 } 522 523 /* 524 * Set the control register to automatically release successfully 525 * transmitted packets (making the best use of our limited memory) 526 * and enable the EPH interrupt on certain TX errors. 527 */ 528 bus_space_write_2(bst, bsh, CONTROL_REG_W, (CTR_AUTO_RELEASE | 529 CTR_TE_ENABLE | CTR_CR_ENABLE | CTR_LE_ENABLE)); 530 531 /* 532 * Reset the MMU and wait for it to be un-busy. 533 */ 534 SMC_SELECT_BANK(sc, 2); 535 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RESET); 536 sc->sc_txpacketno = ARR_FAILED; 537 for (;;) { 538 tmp = bus_space_read_2(bst, bsh, MMU_CMD_REG_W); 539 if (tmp == 0xffff) /* card went away! */ 540 return; 541 if ((tmp & MMUCR_BUSY) == 0) 542 break; 543 } 544 545 /* 546 * Disable all interrupts. 547 */ 548 smc91cxx_intr_mask_write(bst, bsh, 0); 549 550 /* 551 * On the 91c111, enable auto-negotiation, and set the LED 552 * status pins to something sane. 553 * XXX: Should be some way for MD code to decide the latter. 554 */ 555 SMC_SELECT_BANK(sc, 0); 556 if (sc->sc_chipid == CHIP_91C111) { 557 bus_space_write_2(bst, bsh, RX_PHY_CONTROL_REG_W, 558 RPC_ANEG | 559 (RPC_LS_LINK_DETECT << RPC_LSA_SHIFT) | 560 (RPC_LS_TXRX << RPC_LSB_SHIFT)); 561 } 562 563 /* 564 * Set current media. 565 */ 566 smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_cur->ifm_media); 567 568 /* 569 * Set the receive filter. We want receive enable and auto 570 * strip of CRC from received packet. If we are in promisc. mode, 571 * then set that bit as well. 572 * 573 * XXX Initialize multicast filter. For now, we just accept 574 * XXX all multicast. 575 */ 576 SMC_SELECT_BANK(sc, 0); 577 578 tmp = RCR_ENABLE | RCR_STRIP_CRC | RCR_ALMUL; 579 if (ifp->if_flags & IFF_PROMISC) 580 tmp |= RCR_PROMISC; 581 582 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, tmp); 583 584 /* 585 * Set transmitter control to "enabled". 586 */ 587 tmp = TCR_ENABLE; 588 589 #ifndef SMC91CXX_SW_PAD 590 /* 591 * Enable hardware padding of transmitted packets. 592 * XXX doesn't work? 593 */ 594 tmp |= TCR_PAD_ENABLE; 595 #endif 596 597 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, tmp); 598 599 /* 600 * Now, enable interrupts. 601 */ 602 SMC_SELECT_BANK(sc, 2); 603 604 sc->sc_intmask = IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT; 605 if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy) { 606 sc->sc_intmask |= IM_MD_INT; 607 } 608 smc91cxx_intr_mask_write(bst, bsh, sc->sc_intmask); 609 610 /* Interface is now running, with no output active. */ 611 ifp->if_flags |= IFF_RUNNING; 612 ifp->if_flags &= ~IFF_OACTIVE; 613 614 if (sc->sc_flags & SMC_FLAGS_HAS_MII) { 615 /* Start the one second clock. */ 616 callout_reset(&sc->sc_mii_callout, hz, smc91cxx_tick, sc); 617 } 618 619 /* 620 * Attempt to start any pending transmission. 621 */ 622 smc91cxx_start(ifp); 623 624 splx(s); 625 } 626 627 /* 628 * Start output on an interface. 629 * Must be called at splnet or interrupt level. 630 */ 631 void 632 smc91cxx_start(struct ifnet *ifp) 633 { 634 struct smc91cxx_softc *sc = ifp->if_softc; 635 bus_space_tag_t bst = sc->sc_bst; 636 bus_space_handle_t bsh = sc->sc_bsh; 637 u_int len; 638 struct mbuf *m; 639 u_int16_t length, npages; 640 u_int16_t oddbyte; 641 u_int8_t packetno; 642 int timo, pad; 643 644 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 645 return; 646 647 again: 648 /* 649 * Peek at the next packet. 650 */ 651 IFQ_POLL(&ifp->if_snd, m); 652 if (m == NULL) 653 return; 654 655 /* 656 * Compute the frame length and set pad to give an overall even 657 * number of bytes. Below, we assume that the packet length 658 * is even. 659 */ 660 for (len = 0; m != NULL; m = m->m_next) 661 len += m->m_len; 662 pad = (len & 1); 663 664 /* 665 * We drop packets that are too large. Perhaps we should 666 * truncate them instead? 667 */ 668 if ((len + pad) > (ETHER_MAX_LEN - ETHER_CRC_LEN)) { 669 printf("%s: large packet discarded\n", device_xname(&sc->sc_dev)); 670 ifp->if_oerrors++; 671 IFQ_DEQUEUE(&ifp->if_snd, m); 672 m_freem(m); 673 goto readcheck; 674 } 675 676 #ifdef SMC91CXX_SW_PAD 677 /* 678 * Not using hardware padding; pad to ETHER_MIN_LEN. 679 */ 680 if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 681 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 682 #endif 683 684 length = pad + len; 685 686 /* 687 * The MMU has a 256 byte page size. The MMU expects us to 688 * ask for "npages - 1". We include space for the status word, 689 * byte count, and control bytes in the allocation request. 690 */ 691 npages = ((length & ~1) + 6) >> 8; 692 693 /* 694 * Now allocate the memory. 695 */ 696 SMC_SELECT_BANK(sc, 2); 697 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ALLOC | npages); 698 699 timo = MEMORY_WAIT_TIME; 700 if (__predict_false((sc->sc_txpacketno & ARR_FAILED) == 0)) { 701 packetno = sc->sc_txpacketno; 702 sc->sc_txpacketno = ARR_FAILED; 703 } else { 704 do { 705 if (bus_space_read_1(bst, bsh, 706 INTR_STAT_REG_B) & IM_ALLOC_INT) 707 break; 708 delay(1); 709 } while (--timo); 710 } 711 712 packetno = bus_space_read_1(bst, bsh, ALLOC_RESULT_REG_B); 713 714 if (packetno & ARR_FAILED || timo == 0) { 715 /* 716 * No transmit memory is available. Record the number 717 * of requestd pages and enable the allocation completion 718 * interrupt. Set up the watchdog timer in case we miss 719 * the interrupt. Mark the interface as active so that 720 * no one else attempts to transmit while we're allocating 721 * memory. 722 */ 723 sc->sc_intmask |= IM_ALLOC_INT; 724 smc91cxx_intr_mask_write(bst, bsh, sc->sc_intmask); 725 ifp->if_timer = 5; 726 ifp->if_flags |= IFF_OACTIVE; 727 728 return; 729 } 730 731 /* 732 * We have a packet number - set the data window. 733 */ 734 bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno); 735 736 /* 737 * Point to the beginning of the packet. 738 */ 739 bus_space_write_2(bst, bsh, POINTER_REG_W, PTR_AUTOINC /* | 0x0000 */); 740 741 /* 742 * Send the packet length (+6 for stats, length, and control bytes) 743 * and the status word (set to zeros). 744 */ 745 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 746 bus_space_write_2(bst, bsh, DATA_REG_W, (length + 6) & 0x7ff); 747 748 /* 749 * Get the packet from the kernel. This will include the Ethernet 750 * frame header, MAC address, etc. 751 */ 752 IFQ_DEQUEUE(&ifp->if_snd, m); 753 754 /* 755 * Push the packet out to the card. 756 */ 757 oddbyte = smc91cxx_copy_tx_frame(sc, m); 758 759 #ifdef SMC91CXX_SW_PAD 760 #ifdef SMC91CXX_NO_BYTE_WRITE 761 #if BYTE_ORDER == LITTLE_ENDIAN 762 if (pad > 1 && (pad & 1)) { 763 bus_space_write_2(bst, bsh, DATA_REG_W, oddbyte << 0); 764 oddbyte = 0; 765 } 766 #else 767 if (pad > 1 && (pad & 1)) { 768 bus_space_write_2(bst, bsh, DATA_REG_W, oddbyte << 8); 769 oddbyte = 0; 770 } 771 #endif 772 #endif 773 774 /* 775 * Push out padding. 776 */ 777 while (pad > 1) { 778 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 779 pad -= 2; 780 } 781 #endif 782 783 #ifdef SMC91CXX_NO_BYTE_WRITE 784 /* 785 * Push out control byte and unused packet byte. The control byte 786 * is 0, meaning the packet is even lengthed and no special 787 * CRC handling is necessary. 788 */ 789 #if BYTE_ORDER == LITTLE_ENDIAN 790 bus_space_write_2(bst, bsh, DATA_REG_W, 791 oddbyte | (pad ? (CTLB_ODD << 8) : 0)); 792 #else 793 bus_space_write_2(bst, bsh, DATA_REG_W, 794 (oddbyte << 8) | (pad ? CTLB_ODD : 0)); 795 #endif 796 #else 797 if (pad) 798 bus_space_write_1(bst, bsh, DATA_REG_B, 0); 799 #endif 800 801 /* 802 * Enable transmit interrupts and let the chip go. Set a watchdog 803 * in case we miss the interrupt. 804 */ 805 sc->sc_intmask |= IM_TX_INT | IM_TX_EMPTY_INT; 806 smc91cxx_intr_mask_write(bst, bsh, sc->sc_intmask); 807 808 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ENQUEUE); 809 810 ifp->if_timer = 5; 811 812 /* Hand off a copy to the bpf. */ 813 bpf_mtap(ifp, m); 814 815 ifp->if_opackets++; 816 m_freem(m); 817 818 readcheck: 819 /* 820 * Check for incoming pcakets. We don't want to overflow the small 821 * RX FIFO. If nothing has arrived, attempt to queue another 822 * transmit packet. 823 */ 824 if (bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & FIFO_REMPTY) 825 goto again; 826 } 827 828 /* 829 * Squirt a (possibly misaligned) mbuf to the device 830 */ 831 uint8_t 832 smc91cxx_copy_tx_frame(struct smc91cxx_softc *sc, struct mbuf *m0) 833 { 834 bus_space_tag_t bst = sc->sc_bst; 835 bus_space_handle_t bsh = sc->sc_bsh; 836 struct mbuf *m; 837 int len, leftover; 838 u_int16_t dbuf; 839 u_int8_t *p; 840 #ifdef DIAGNOSTIC 841 u_int8_t *lim; 842 #endif 843 844 /* start out with no leftover data */ 845 leftover = 0; 846 dbuf = 0; 847 848 /* Process the chain of mbufs */ 849 for (m = m0; m != NULL; m = m->m_next) { 850 /* 851 * Process all of the data in a single mbuf. 852 */ 853 p = mtod(m, u_int8_t *); 854 len = m->m_len; 855 #ifdef DIAGNOSTIC 856 lim = p + len; 857 #endif 858 859 while (len > 0) { 860 if (leftover) { 861 /* 862 * Data left over (from mbuf or realignment). 863 * Buffer the next byte, and write it and 864 * the leftover data out. 865 */ 866 dbuf |= *p++ << 8; 867 len--; 868 bus_space_write_2(bst, bsh, DATA_REG_W, dbuf); 869 leftover = 0; 870 } else if ((long) p & 1) { 871 /* 872 * Misaligned data. Buffer the next byte. 873 */ 874 dbuf = *p++; 875 len--; 876 leftover = 1; 877 } else { 878 /* 879 * Aligned data. This is the case we like. 880 * 881 * Write-region out as much as we can, then 882 * buffer the remaining byte (if any). 883 */ 884 leftover = len & 1; 885 len &= ~1; 886 bus_space_write_multi_stream_2(bst, bsh, 887 DATA_REG_W, (u_int16_t *)p, len >> 1); 888 p += len; 889 890 if (leftover) 891 dbuf = *p++; 892 len = 0; 893 } 894 } 895 if (len < 0) 896 panic("smc91cxx_copy_tx_frame: negative len"); 897 #ifdef DIAGNOSTIC 898 if (p != lim) 899 panic("smc91cxx_copy_tx_frame: p != lim"); 900 #endif 901 } 902 #ifndef SMC91CXX_NO_BYTE_WRITE 903 if (leftover) 904 bus_space_write_1(bst, bsh, DATA_REG_B, dbuf); 905 #endif 906 return dbuf; 907 } 908 909 /* 910 * Interrupt service routine. 911 */ 912 int 913 smc91cxx_intr(void *arg) 914 { 915 struct smc91cxx_softc *sc = arg; 916 struct ifnet *ifp = &sc->sc_ec.ec_if; 917 bus_space_tag_t bst = sc->sc_bst; 918 bus_space_handle_t bsh = sc->sc_bsh; 919 u_int8_t mask, interrupts, status; 920 u_int16_t packetno, tx_status, card_stats; 921 #ifdef SMC91CXX_NO_BYTE_WRITE 922 u_int16_t v; 923 #endif 924 925 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 || 926 !device_is_active(&sc->sc_dev)) 927 return (0); 928 929 SMC_SELECT_BANK(sc, 2); 930 931 /* 932 * Obtain the current interrupt status and mask. 933 */ 934 #ifdef SMC91CXX_NO_BYTE_WRITE 935 v = bus_space_read_2(bst, bsh, INTR_STAT_REG_B); 936 937 /* 938 * Get the set of interrupt which occurred and eliminate any 939 * which are not enabled. 940 */ 941 #if BYTE_ORDER == LITTLE_ENDIAN 942 mask = v >> 8; 943 interrupts = v & 0xff; 944 #else 945 interrupts = v >> 8; 946 mask = v & 0xff; 947 #endif 948 KDASSERT(mask == sc->sc_intmask); 949 #else 950 mask = bus_space_read_1(bst, bsh, INTR_MASK_REG_B); 951 952 /* 953 * Get the set of interrupt which occurred and eliminate any 954 * which are not enabled. 955 */ 956 interrupts = bus_space_read_1(bst, bsh, INTR_STAT_REG_B); 957 #endif 958 status = interrupts & mask; 959 960 /* Ours? */ 961 if (status == 0) 962 return (0); 963 964 /* 965 * It's ours; disable all interrupts while we process them. 966 */ 967 smc91cxx_intr_mask_write(bst, bsh, 0); 968 969 /* 970 * Receive overrun interrupts. 971 */ 972 if (status & IM_RX_OVRN_INT) { 973 smc91cxx_intr_ack_write(bst, bsh, IM_RX_OVRN_INT); 974 ifp->if_ierrors++; 975 } 976 977 /* 978 * Receive interrupts. 979 */ 980 if (status & IM_RCV_INT) { 981 #if 1 /* DIAGNOSTIC */ 982 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 983 if (packetno & FIFO_REMPTY) { 984 aprint_error_dev(&sc->sc_dev, "receive interrupt on empty fifo\n"); 985 goto out; 986 } else 987 #endif 988 smc91cxx_read(sc); 989 } 990 991 /* 992 * Memory allocation interrupts. 993 */ 994 if (status & IM_ALLOC_INT) { 995 /* Disable this interrupt. */ 996 mask &= ~IM_ALLOC_INT; 997 sc->sc_intmask &= ~IM_ALLOC_INT; 998 999 /* 1000 * Save allocated packet number for use in start 1001 */ 1002 packetno = bus_space_read_1(bst, bsh, ALLOC_RESULT_REG_B); 1003 KASSERT(sc->sc_txpacketno & ARR_FAILED); 1004 sc->sc_txpacketno = packetno; 1005 1006 /* 1007 * We can transmit again! 1008 */ 1009 ifp->if_flags &= ~IFF_OACTIVE; 1010 ifp->if_timer = 0; 1011 } 1012 1013 /* 1014 * Transmit complete interrupt. Handle transmission error messages. 1015 * This will only be called on error condition because of AUTO RELEASE 1016 * mode. 1017 */ 1018 if (status & IM_TX_INT) { 1019 smc91cxx_intr_ack_write(bst, bsh, IM_TX_INT); 1020 1021 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & 1022 FIFO_TX_MASK; 1023 1024 /* 1025 * Select this as the packet to read from. 1026 */ 1027 bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno); 1028 1029 /* 1030 * Position the pointer to the beginning of the packet. 1031 */ 1032 bus_space_write_2(bst, bsh, POINTER_REG_W, 1033 PTR_AUTOINC | PTR_READ /* | 0x0000 */); 1034 1035 /* 1036 * Fetch the TX status word. This will be a copy of 1037 * the EPH_STATUS_REG_W at the time of the transmission 1038 * failure. 1039 */ 1040 tx_status = bus_space_read_2(bst, bsh, DATA_REG_W); 1041 1042 if (tx_status & EPHSR_TX_SUC) { 1043 static struct timeval txsuc_last; 1044 static int txsuc_count; 1045 if (ppsratecheck(&txsuc_last, &txsuc_count, 1)) 1046 printf("%s: successful packet caused TX" 1047 " interrupt?!\n", device_xname(&sc->sc_dev)); 1048 } else 1049 ifp->if_oerrors++; 1050 1051 if (tx_status & EPHSR_LATCOL) 1052 ifp->if_collisions++; 1053 1054 /* Disable this interrupt (start will reenable if needed). */ 1055 mask &= ~IM_TX_INT; 1056 sc->sc_intmask &= ~IM_TX_INT; 1057 1058 /* 1059 * Some of these errors disable the transmitter; reenable it. 1060 */ 1061 SMC_SELECT_BANK(sc, 0); 1062 #ifdef SMC91CXX_SW_PAD 1063 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, TCR_ENABLE); 1064 #else 1065 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 1066 TCR_ENABLE | TCR_PAD_ENABLE); 1067 #endif 1068 1069 /* 1070 * Kill the failed packet and wait for the MMU to unbusy. 1071 */ 1072 SMC_SELECT_BANK(sc, 2); 1073 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 1074 /* XXX bound this loop! */ ; 1075 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT); 1076 1077 ifp->if_timer = 0; 1078 } 1079 1080 /* 1081 * Transmit underrun interrupts. We use this opportunity to 1082 * update transmit statistics from the card. 1083 */ 1084 if (status & IM_TX_EMPTY_INT) { 1085 smc91cxx_intr_ack_write(bst, bsh, IM_TX_EMPTY_INT); 1086 1087 /* Disable this interrupt. */ 1088 mask &= ~IM_TX_EMPTY_INT; 1089 sc->sc_intmask &= ~IM_TX_EMPTY_INT; 1090 1091 SMC_SELECT_BANK(sc, 0); 1092 card_stats = bus_space_read_2(bst, bsh, COUNTER_REG_W); 1093 1094 /* Single collisions. */ 1095 ifp->if_collisions += card_stats & ECR_COLN_MASK; 1096 1097 /* Multiple collisions. */ 1098 ifp->if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4; 1099 1100 SMC_SELECT_BANK(sc, 2); 1101 1102 ifp->if_timer = 0; 1103 } 1104 1105 if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy && 1106 (status & IM_MD_INT)) { 1107 /* 1108 * Internal PHY status change 1109 */ 1110 mii_tick(&sc->sc_mii); 1111 } 1112 1113 /* 1114 * Other errors. Reset the interface. 1115 */ 1116 if (status & IM_EPH_INT) { 1117 smc91cxx_stop(sc); 1118 smc91cxx_init(sc); 1119 } 1120 1121 /* 1122 * Attempt to queue more packets for transmission. 1123 */ 1124 smc91cxx_start(ifp); 1125 1126 out: 1127 /* 1128 * Reenable the interrupts we wish to receive now that processing 1129 * is complete. 1130 */ 1131 mask |= sc->sc_intmask; 1132 smc91cxx_intr_mask_write(bst, bsh, mask); 1133 1134 #if NRND > 0 1135 if (status) 1136 rnd_add_uint32(&sc->rnd_source, status); 1137 #endif 1138 1139 return (1); 1140 } 1141 1142 /* 1143 * Read a packet from the card and pass it up to the kernel. 1144 * NOTE! WE EXPECT TO BE IN REGISTER WINDOW 2! 1145 */ 1146 void 1147 smc91cxx_read(struct smc91cxx_softc *sc) 1148 { 1149 struct ifnet *ifp = &sc->sc_ec.ec_if; 1150 bus_space_tag_t bst = sc->sc_bst; 1151 bus_space_handle_t bsh = sc->sc_bsh; 1152 struct ether_header *eh; 1153 struct mbuf *m; 1154 u_int16_t status, packetno, packetlen; 1155 u_int8_t *data; 1156 u_int32_t dr; 1157 1158 again: 1159 /* 1160 * Set data pointer to the beginning of the packet. Since 1161 * PTR_RCV is set, the packet number will be found automatically 1162 * in FIFO_PORTS_REG_W, FIFO_RX_MASK. 1163 */ 1164 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 1165 if (packetno & FIFO_REMPTY) 1166 return; 1167 1168 bus_space_write_2(bst, bsh, POINTER_REG_W, 1169 PTR_READ | PTR_RCV | PTR_AUTOINC /* | 0x0000 */); 1170 1171 /* 1172 * First two words are status and packet length. 1173 */ 1174 if ((sc->sc_flags & SMC_FLAGS_32BIT_READ) == 0) { 1175 status = bus_space_read_2(bst, bsh, DATA_REG_W); 1176 packetlen = bus_space_read_2(bst, bsh, DATA_REG_W); 1177 } else { 1178 dr = bus_space_read_4(bst, bsh, DATA_REG_W); 1179 #if BYTE_ORDER == LITTLE_ENDIAN 1180 status = (u_int16_t)dr; 1181 packetlen = (u_int16_t)(dr >> 16); 1182 #else 1183 packetlen = (u_int16_t)dr; 1184 status = (u_int16_t)(dr >> 16); 1185 #endif 1186 } 1187 1188 packetlen &= RLEN_MASK; 1189 if (packetlen < ETHER_MIN_LEN - ETHER_CRC_LEN + 6 || packetlen > 1534) { 1190 ifp->if_ierrors++; 1191 goto out; 1192 } 1193 1194 /* 1195 * The packet length includes 3 extra words: status, length, 1196 * and an extra word that includes the control byte. 1197 */ 1198 packetlen -= 6; 1199 1200 /* 1201 * Account for receive errors and discard. 1202 */ 1203 if (status & RS_ERRORS) { 1204 ifp->if_ierrors++; 1205 goto out; 1206 } 1207 1208 /* 1209 * Adjust for odd-length packet. 1210 */ 1211 if (status & RS_ODDFRAME) 1212 packetlen++; 1213 1214 /* 1215 * Allocate a header mbuf. 1216 */ 1217 MGETHDR(m, M_DONTWAIT, MT_DATA); 1218 if (m == NULL) 1219 goto out; 1220 m->m_pkthdr.rcvif = ifp; 1221 m->m_pkthdr.len = packetlen; 1222 1223 /* 1224 * Always put the packet in a cluster. 1225 * XXX should chain small mbufs if less than threshold. 1226 */ 1227 MCLGET(m, M_DONTWAIT); 1228 if ((m->m_flags & M_EXT) == 0) { 1229 m_freem(m); 1230 ifp->if_ierrors++; 1231 aprint_error_dev(&sc->sc_dev, "can't allocate cluster for incoming packet\n"); 1232 goto out; 1233 } 1234 1235 /* 1236 * Pull the packet off the interface. Make sure the payload 1237 * is aligned. 1238 */ 1239 if ((sc->sc_flags & SMC_FLAGS_32BIT_READ) == 0) { 1240 m->m_data = (char *) ALIGN(mtod(m, char *) + 1241 sizeof(struct ether_header)) - sizeof(struct ether_header); 1242 1243 eh = mtod(m, struct ether_header *); 1244 data = mtod(m, u_int8_t *); 1245 KASSERT(trunc_page((uintptr_t)data) == trunc_page((uintptr_t)data + packetlen - 1)); 1246 if (packetlen > 1) 1247 bus_space_read_multi_stream_2(bst, bsh, DATA_REG_W, 1248 (u_int16_t *)data, packetlen >> 1); 1249 if (packetlen & 1) { 1250 data += packetlen & ~1; 1251 *data = bus_space_read_1(bst, bsh, DATA_REG_B); 1252 } 1253 } else { 1254 u_int8_t *dp; 1255 1256 m->m_data = (void *) ALIGN(mtod(m, void *)); 1257 eh = mtod(m, struct ether_header *); 1258 dp = data = mtod(m, u_int8_t *); 1259 KASSERT(trunc_page((uintptr_t)data) == trunc_page((uintptr_t)data + packetlen - 1)); 1260 if (packetlen > 3) 1261 bus_space_read_multi_stream_4(bst, bsh, DATA_REG_W, 1262 (u_int32_t *)data, packetlen >> 2); 1263 if (packetlen & 3) { 1264 data += packetlen & ~3; 1265 *((u_int32_t *)data) = 1266 bus_space_read_stream_4(bst, bsh, DATA_REG_W); 1267 } 1268 } 1269 1270 ifp->if_ipackets++; 1271 1272 /* 1273 * Make sure to behave as IFF_SIMPLEX in all cases. 1274 * This is to cope with SMC91C92 (Megahertz XJ10BT), which 1275 * loops back packets to itself on promiscuous mode. 1276 * (should be ensured by chipset configuration) 1277 */ 1278 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1279 /* 1280 * Drop packet looped back from myself. 1281 */ 1282 if (ether_cmp(eh->ether_shost, CLLADDR(ifp->if_sadl)) == 0) { 1283 m_freem(m); 1284 goto out; 1285 } 1286 } 1287 1288 m->m_pkthdr.len = m->m_len = packetlen; 1289 1290 /* 1291 * Hand the packet off to bpf listeners. 1292 */ 1293 bpf_mtap(ifp, m); 1294 1295 (*ifp->if_input)(ifp, m); 1296 1297 out: 1298 /* 1299 * Tell the card to free the memory occupied by this packet. 1300 */ 1301 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 1302 /* XXX bound this loop! */ ; 1303 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RELEASE); 1304 1305 /* 1306 * Check for another packet. 1307 */ 1308 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 1309 if (packetno & FIFO_REMPTY) 1310 return; 1311 goto again; 1312 } 1313 1314 /* 1315 * Process an ioctl request. 1316 */ 1317 int 1318 smc91cxx_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1319 { 1320 struct smc91cxx_softc *sc = ifp->if_softc; 1321 struct ifaddr *ifa = (struct ifaddr *)data; 1322 struct ifreq *ifr = (struct ifreq *)data; 1323 int s, error = 0; 1324 1325 s = splnet(); 1326 1327 switch (cmd) { 1328 case SIOCINITIFADDR: 1329 if ((error = smc91cxx_enable(sc)) != 0) 1330 break; 1331 ifp->if_flags |= IFF_UP; 1332 smc91cxx_init(sc); 1333 switch (ifa->ifa_addr->sa_family) { 1334 #ifdef INET 1335 case AF_INET: 1336 arp_ifinit(ifp, ifa); 1337 break; 1338 #endif 1339 default: 1340 break; 1341 } 1342 break; 1343 1344 1345 case SIOCSIFFLAGS: 1346 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1347 break; 1348 /* XXX re-use ether_ioctl() */ 1349 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 1350 case IFF_RUNNING: 1351 /* 1352 * If interface is marked down and it is running, 1353 * stop it. 1354 */ 1355 smc91cxx_stop(sc); 1356 ifp->if_flags &= ~IFF_RUNNING; 1357 smc91cxx_disable(sc); 1358 break; 1359 case IFF_UP: 1360 /* 1361 * If interface is marked up and it is stopped, 1362 * start it. 1363 */ 1364 if ((error = smc91cxx_enable(sc)) != 0) 1365 break; 1366 smc91cxx_init(sc); 1367 break; 1368 case IFF_UP|IFF_RUNNING: 1369 /* 1370 * Reset the interface to pick up changes in any 1371 * other flags that affect hardware registers. 1372 */ 1373 smc91cxx_reset(sc); 1374 break; 1375 case 0: 1376 break; 1377 } 1378 break; 1379 1380 case SIOCADDMULTI: 1381 case SIOCDELMULTI: 1382 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) { 1383 error = EIO; 1384 break; 1385 } 1386 1387 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1388 /* 1389 * Multicast list has changed; set the hardware 1390 * filter accordingly. 1391 */ 1392 if (ifp->if_flags & IFF_RUNNING) 1393 smc91cxx_reset(sc); 1394 error = 0; 1395 } 1396 break; 1397 1398 case SIOCGIFMEDIA: 1399 case SIOCSIFMEDIA: 1400 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1401 break; 1402 1403 default: 1404 error = ether_ioctl(ifp, cmd, data); 1405 break; 1406 } 1407 1408 splx(s); 1409 return (error); 1410 } 1411 1412 /* 1413 * Reset the interface. 1414 */ 1415 void 1416 smc91cxx_reset(struct smc91cxx_softc *sc) 1417 { 1418 int s; 1419 1420 s = splnet(); 1421 smc91cxx_stop(sc); 1422 smc91cxx_init(sc); 1423 splx(s); 1424 } 1425 1426 /* 1427 * Watchdog timer. 1428 */ 1429 void 1430 smc91cxx_watchdog(struct ifnet *ifp) 1431 { 1432 struct smc91cxx_softc *sc = ifp->if_softc; 1433 1434 log(LOG_ERR, "%s: device timeout\n", device_xname(&sc->sc_dev)); 1435 ifp->if_oerrors++; 1436 smc91cxx_reset(sc); 1437 } 1438 1439 /* 1440 * Stop output on the interface. 1441 */ 1442 void 1443 smc91cxx_stop(struct smc91cxx_softc *sc) 1444 { 1445 bus_space_tag_t bst = sc->sc_bst; 1446 bus_space_handle_t bsh = sc->sc_bsh; 1447 1448 /* 1449 * Clear interrupt mask; disable all interrupts. 1450 */ 1451 SMC_SELECT_BANK(sc, 2); 1452 smc91cxx_intr_mask_write(bst, bsh, 0); 1453 1454 /* 1455 * Disable transmitter and receiver. 1456 */ 1457 SMC_SELECT_BANK(sc, 0); 1458 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); 1459 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); 1460 1461 /* 1462 * Cancel watchdog timer. 1463 */ 1464 sc->sc_ec.ec_if.if_timer = 0; 1465 } 1466 1467 /* 1468 * Enable power on the interface. 1469 */ 1470 int 1471 smc91cxx_enable(struct smc91cxx_softc *sc) 1472 { 1473 1474 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 && sc->sc_enable != NULL) { 1475 if ((*sc->sc_enable)(sc) != 0) { 1476 aprint_error_dev(&sc->sc_dev, "device enable failed\n"); 1477 return (EIO); 1478 } 1479 } 1480 1481 sc->sc_flags |= SMC_FLAGS_ENABLED; 1482 return (0); 1483 } 1484 1485 /* 1486 * Disable power on the interface. 1487 */ 1488 void 1489 smc91cxx_disable(struct smc91cxx_softc *sc) 1490 { 1491 1492 if ((sc->sc_flags & SMC_FLAGS_ENABLED) != 0 && sc->sc_disable != NULL) { 1493 (*sc->sc_disable)(sc); 1494 sc->sc_flags &= ~SMC_FLAGS_ENABLED; 1495 } 1496 } 1497 1498 int 1499 smc91cxx_activate(device_t self, enum devact act) 1500 { 1501 struct smc91cxx_softc *sc = device_private(self); 1502 1503 switch (act) { 1504 case DVACT_DEACTIVATE: 1505 if_deactivate(&sc->sc_ec.ec_if); 1506 return 0; 1507 default: 1508 return EOPNOTSUPP; 1509 } 1510 } 1511 1512 int 1513 smc91cxx_detach(device_t self, int flags) 1514 { 1515 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1516 struct ifnet *ifp = &sc->sc_ec.ec_if; 1517 1518 /* Succeed now if there's no work to do. */ 1519 if ((sc->sc_flags & SMC_FLAGS_ATTACHED) == 0) 1520 return (0); 1521 1522 1523 /* smc91cxx_disable() checks SMC_FLAGS_ENABLED */ 1524 smc91cxx_disable(sc); 1525 1526 /* smc91cxx_attach() never fails */ 1527 1528 /* Delete all media. */ 1529 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1530 1531 #if NRND > 0 1532 rnd_detach_source(&sc->rnd_source); 1533 #endif 1534 ether_ifdetach(ifp); 1535 if_detach(ifp); 1536 1537 return (0); 1538 } 1539 1540 u_int32_t 1541 smc91cxx_mii_bitbang_read(device_t self) 1542 { 1543 struct smc91cxx_softc *sc = (void *) self; 1544 1545 /* We're already in bank 3. */ 1546 return (bus_space_read_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W)); 1547 } 1548 1549 void 1550 smc91cxx_mii_bitbang_write(device_t self, u_int32_t val) 1551 { 1552 struct smc91cxx_softc *sc = (void *) self; 1553 1554 /* We're already in bank 3. */ 1555 bus_space_write_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W, val); 1556 } 1557 1558 int 1559 smc91cxx_mii_readreg(device_t self, int phy, int reg) 1560 { 1561 struct smc91cxx_softc *sc = (void *) self; 1562 int val; 1563 1564 SMC_SELECT_BANK(sc, 3); 1565 1566 val = mii_bitbang_readreg(self, &smc91cxx_mii_bitbang_ops, phy, reg); 1567 1568 SMC_SELECT_BANK(sc, 2); 1569 1570 return (val); 1571 } 1572 1573 void 1574 smc91cxx_mii_writereg(device_t self, int phy, int reg, int val) 1575 { 1576 struct smc91cxx_softc *sc = (void *) self; 1577 1578 SMC_SELECT_BANK(sc, 3); 1579 1580 mii_bitbang_writereg(self, &smc91cxx_mii_bitbang_ops, phy, reg, val); 1581 1582 SMC_SELECT_BANK(sc, 2); 1583 } 1584 1585 void 1586 smc91cxx_statchg(device_t self) 1587 { 1588 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1589 bus_space_tag_t bst = sc->sc_bst; 1590 bus_space_handle_t bsh = sc->sc_bsh; 1591 int mctl; 1592 1593 SMC_SELECT_BANK(sc, 0); 1594 mctl = bus_space_read_2(bst, bsh, TXMIT_CONTROL_REG_W); 1595 if (sc->sc_mii.mii_media_active & IFM_FDX) 1596 mctl |= TCR_SWFDUP; 1597 else 1598 mctl &= ~TCR_SWFDUP; 1599 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, mctl); 1600 SMC_SELECT_BANK(sc, 2); /* back to operating window */ 1601 } 1602 1603 /* 1604 * One second timer, used to tick the MII. 1605 */ 1606 void 1607 smc91cxx_tick(void *arg) 1608 { 1609 struct smc91cxx_softc *sc = arg; 1610 int s; 1611 1612 #ifdef DIAGNOSTIC 1613 if ((sc->sc_flags & SMC_FLAGS_HAS_MII) == 0) 1614 panic("smc91cxx_tick"); 1615 #endif 1616 1617 if (!device_is_active(&sc->sc_dev)) 1618 return; 1619 1620 s = splnet(); 1621 mii_tick(&sc->sc_mii); 1622 splx(s); 1623 1624 callout_reset(&sc->sc_mii_callout, hz, smc91cxx_tick, sc); 1625 } 1626 1627