1 /* $NetBSD: smc91cxx.c,v 1.81 2012/02/12 16:34:11 matt Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com> 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Gardner Buchanan. 48 * 4. The name of Gardner Buchanan may not be used to endorse or promote 49 * products derived from this software without specific prior written 50 * permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 55 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 56 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 57 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 61 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 * from FreeBSD Id: if_sn.c,v 1.4 1996/03/18 15:47:16 gardner Exp 64 */ 65 66 /* 67 * Core driver for the SMC 91Cxx family of Ethernet chips. 68 * 69 * Memory allocation interrupt logic is drived from an SMC 91C90 driver 70 * written for NetBSD/amiga by Michael Hitch. 71 */ 72 73 #include <sys/cdefs.h> 74 __KERNEL_RCSID(0, "$NetBSD: smc91cxx.c,v 1.81 2012/02/12 16:34:11 matt Exp $"); 75 76 #include "opt_inet.h" 77 78 #include <sys/param.h> 79 #include <sys/systm.h> 80 #include <sys/mbuf.h> 81 #include <sys/syslog.h> 82 #include <sys/socket.h> 83 #include <sys/device.h> 84 #include <sys/kernel.h> 85 #include <sys/malloc.h> 86 #include <sys/ioctl.h> 87 #include <sys/errno.h> 88 #include <sys/rnd.h> 89 90 #include <sys/bus.h> 91 #include <sys/intr.h> 92 93 #include <net/if.h> 94 #include <net/if_dl.h> 95 #include <net/if_ether.h> 96 #include <net/if_media.h> 97 98 #ifdef INET 99 #include <netinet/in.h> 100 #include <netinet/if_inarp.h> 101 #include <netinet/in_systm.h> 102 #include <netinet/in_var.h> 103 #include <netinet/ip.h> 104 #endif 105 106 #include <net/bpf.h> 107 #include <net/bpfdesc.h> 108 109 #include <dev/mii/mii.h> 110 #include <dev/mii/miivar.h> 111 #include <dev/mii/mii_bitbang.h> 112 113 #include <dev/ic/smc91cxxreg.h> 114 #include <dev/ic/smc91cxxvar.h> 115 116 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 117 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 118 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 119 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 120 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 121 122 #define bus_space_write_stream_4 bus_space_write_4 123 #define bus_space_read_stream_4 bus_space_read_4 124 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 125 126 /* XXX Hardware padding doesn't work yet(?) */ 127 #define SMC91CXX_SW_PAD 128 129 const char *smc91cxx_idstrs[] = { 130 NULL, /* 0 */ 131 NULL, /* 1 */ 132 NULL, /* 2 */ 133 "SMC91C90/91C92", /* 3 */ 134 "SMC91C94/91C96", /* 4 */ 135 "SMC91C95", /* 5 */ 136 NULL, /* 6 */ 137 "SMC91C100", /* 7 */ 138 "SMC91C100FD", /* 8 */ 139 "SMC91C111", /* 9 */ 140 NULL, /* 10 */ 141 NULL, /* 11 */ 142 NULL, /* 12 */ 143 NULL, /* 13 */ 144 NULL, /* 14 */ 145 NULL, /* 15 */ 146 }; 147 148 /* Supported media types. */ 149 const int smc91cxx_media[] = { 150 IFM_ETHER|IFM_10_T, 151 IFM_ETHER|IFM_10_5, 152 }; 153 #define NSMC91CxxMEDIA (sizeof(smc91cxx_media) / sizeof(smc91cxx_media[0])) 154 155 /* 156 * MII bit-bang glue. 157 */ 158 u_int32_t smc91cxx_mii_bitbang_read(device_t); 159 void smc91cxx_mii_bitbang_write(device_t, u_int32_t); 160 161 const struct mii_bitbang_ops smc91cxx_mii_bitbang_ops = { 162 smc91cxx_mii_bitbang_read, 163 smc91cxx_mii_bitbang_write, 164 { 165 MR_MDO, /* MII_BIT_MDO */ 166 MR_MDI, /* MII_BIT_MDI */ 167 MR_MCLK, /* MII_BIT_MDC */ 168 MR_MDOE, /* MII_BIT_DIR_HOST_PHY */ 169 0, /* MII_BIT_DIR_PHY_HOST */ 170 } 171 }; 172 173 /* MII callbacks */ 174 int smc91cxx_mii_readreg(device_t, int, int); 175 void smc91cxx_mii_writereg(device_t, int, int, int); 176 void smc91cxx_statchg(device_t); 177 void smc91cxx_tick(void *); 178 179 int smc91cxx_mediachange(struct ifnet *); 180 void smc91cxx_mediastatus(struct ifnet *, struct ifmediareq *); 181 182 int smc91cxx_set_media(struct smc91cxx_softc *, int); 183 184 void smc91cxx_init(struct smc91cxx_softc *); 185 void smc91cxx_read(struct smc91cxx_softc *); 186 void smc91cxx_reset(struct smc91cxx_softc *); 187 void smc91cxx_start(struct ifnet *); 188 uint8_t smc91cxx_copy_tx_frame(struct smc91cxx_softc *, struct mbuf *); 189 void smc91cxx_resume(struct smc91cxx_softc *); 190 void smc91cxx_stop(struct smc91cxx_softc *); 191 void smc91cxx_watchdog(struct ifnet *); 192 int smc91cxx_ioctl(struct ifnet *, u_long, void *); 193 194 static inline int ether_cmp(const void *, const void *); 195 static inline int 196 ether_cmp(const void *va, const void *vb) 197 { 198 const u_int8_t *a = va; 199 const u_int8_t *b = vb; 200 201 return ((a[5] != b[5]) || (a[4] != b[4]) || (a[3] != b[3]) || 202 (a[2] != b[2]) || (a[1] != b[1]) || (a[0] != b[0])); 203 } 204 205 static inline void 206 smc91cxx_intr_mask_write(bus_space_tag_t bst, bus_space_handle_t bsh, 207 uint8_t mask) 208 { 209 KDASSERT((mask & IM_ERCV_INT) == 0); 210 #ifdef SMC91CXX_NO_BYTE_WRITE 211 #if BYTE_ORDER == LITTLE_ENDIAN 212 bus_space_write_2(bst, bsh, INTR_STAT_REG_B, mask << 8); 213 #else 214 bus_space_write_2(bst, bsh, INTR_STAT_REG_B, mask); 215 #endif 216 #else 217 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, mask); 218 #endif 219 KDASSERT(!(bus_space_read_1(bst, bsh, INTR_MASK_REG_B) & IM_ERCV_INT)); 220 } 221 222 static inline void 223 smc91cxx_intr_ack_write(bus_space_tag_t bst, bus_space_handle_t bsh, 224 uint8_t mask) 225 { 226 #ifdef SMC91CXX_NO_BYTE_WRITE 227 #if BYTE_ORDER == LITTLE_ENDIAN 228 bus_space_write_2(bst, bsh, INTR_ACK_REG_B, 229 mask | (bus_space_read_2(bst, bsh, INTR_ACK_REG_B) & 0xff00)); 230 #else 231 bus_space_write_2(bst, bsh, INTR_ACK_REG_B, 232 (mask << 8) | (bus_space_read_2(bst, bsh, INTR_ACK_REG_B) & 0xff)); 233 #endif 234 #else 235 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, mask); 236 #endif 237 KDASSERT(!(bus_space_read_1(bst, bsh, INTR_MASK_REG_B) & IM_ERCV_INT)); 238 } 239 240 void 241 smc91cxx_attach(struct smc91cxx_softc *sc, u_int8_t *myea) 242 { 243 struct ifnet *ifp = &sc->sc_ec.ec_if; 244 bus_space_tag_t bst = sc->sc_bst; 245 bus_space_handle_t bsh = sc->sc_bsh; 246 struct ifmedia *ifm = &sc->sc_mii.mii_media; 247 const char *idstr; 248 u_int32_t miicapabilities; 249 u_int16_t tmp; 250 u_int8_t enaddr[ETHER_ADDR_LEN]; 251 int i, aui, mult, scale, memsize; 252 char pbuf[9]; 253 254 tmp = bus_space_read_2(bst, bsh, BANK_SELECT_REG_W); 255 /* check magic number */ 256 if ((tmp & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 257 aprint_error_dev(&sc->sc_dev, "failed to detect chip, bsr=%04x\n", tmp); 258 return; 259 } 260 261 /* Make sure the chip is stopped. */ 262 smc91cxx_stop(sc); 263 264 SMC_SELECT_BANK(sc, 3); 265 tmp = bus_space_read_2(bst, bsh, REVISION_REG_W); 266 sc->sc_chipid = RR_ID(tmp); 267 idstr = smc91cxx_idstrs[sc->sc_chipid]; 268 269 aprint_normal_dev(&sc->sc_dev, ""); 270 if (idstr != NULL) 271 aprint_normal("%s, ", idstr); 272 else 273 aprint_normal("unknown chip id %d, ", sc->sc_chipid); 274 aprint_normal("revision %d, ", RR_REV(tmp)); 275 276 SMC_SELECT_BANK(sc, 0); 277 switch (sc->sc_chipid) { 278 default: 279 mult = MCR_MEM_MULT(bus_space_read_2(bst, bsh, MEM_CFG_REG_W)); 280 scale = MIR_SCALE_91C9x; 281 break; 282 283 case CHIP_91C111: 284 mult = MIR_MULT_91C111; 285 scale = MIR_SCALE_91C111; 286 } 287 memsize = bus_space_read_2(bst, bsh, MEM_INFO_REG_W) & MIR_TOTAL_MASK; 288 if (memsize == 255) memsize++; 289 memsize *= scale * mult; 290 291 format_bytes(pbuf, sizeof(pbuf), memsize); 292 aprint_normal("buffer size: %s\n", pbuf); 293 294 /* Read the station address from the chip. */ 295 SMC_SELECT_BANK(sc, 1); 296 if (myea == NULL) { 297 myea = enaddr; 298 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 299 tmp = bus_space_read_2(bst, bsh, IAR_ADDR0_REG_W + i); 300 myea[i + 1] = (tmp >> 8) & 0xff; 301 myea[i] = tmp & 0xff; 302 } 303 } 304 aprint_normal_dev(&sc->sc_dev, "MAC address %s, ", 305 ether_sprintf(myea)); 306 307 /* Initialize the ifnet structure. */ 308 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 309 ifp->if_softc = sc; 310 ifp->if_start = smc91cxx_start; 311 ifp->if_ioctl = smc91cxx_ioctl; 312 ifp->if_watchdog = smc91cxx_watchdog; 313 ifp->if_flags = 314 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 315 IFQ_SET_READY(&ifp->if_snd); 316 317 /* Attach the interface. */ 318 if_attach(ifp); 319 ether_ifattach(ifp, myea); 320 321 /* 322 * Initialize our media structures and MII info. We will 323 * probe the MII if we are on the SMC91Cxx 324 */ 325 sc->sc_mii.mii_ifp = ifp; 326 sc->sc_mii.mii_readreg = smc91cxx_mii_readreg; 327 sc->sc_mii.mii_writereg = smc91cxx_mii_writereg; 328 sc->sc_mii.mii_statchg = smc91cxx_statchg; 329 ifmedia_init(ifm, IFM_IMASK, smc91cxx_mediachange, smc91cxx_mediastatus); 330 331 SMC_SELECT_BANK(sc, 1); 332 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 333 334 miicapabilities = BMSR_MEDIAMASK|BMSR_ANEG; 335 switch (sc->sc_chipid) { 336 case CHIP_91100: 337 /* 338 * The 91100 does not have full-duplex capabilities, 339 * even if the PHY does. 340 */ 341 miicapabilities &= ~(BMSR_100TXFDX | BMSR_10TFDX); 342 case CHIP_91100FD: 343 case CHIP_91C111: 344 if (tmp & CR_MII_SELECT) { 345 aprint_normal("default media MII"); 346 if (sc->sc_chipid == CHIP_91C111) { 347 aprint_normal(" (%s PHY)\n", (tmp & CR_AUI_SELECT) ? 348 "external" : "internal"); 349 sc->sc_internal_phy = !(tmp & CR_AUI_SELECT); 350 } else 351 aprint_normal("\n"); 352 mii_attach(&sc->sc_dev, &sc->sc_mii, miicapabilities, 353 MII_PHY_ANY, MII_OFFSET_ANY, 0); 354 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 355 ifmedia_add(&sc->sc_mii.mii_media, 356 IFM_ETHER|IFM_NONE, 0, NULL); 357 ifmedia_set(&sc->sc_mii.mii_media, 358 IFM_ETHER|IFM_NONE); 359 } else { 360 ifmedia_set(&sc->sc_mii.mii_media, 361 IFM_ETHER|IFM_AUTO); 362 } 363 sc->sc_flags |= SMC_FLAGS_HAS_MII; 364 break; 365 } else 366 if (sc->sc_chipid == CHIP_91C111) { 367 /* 368 * XXX: Should bring it out of low-power mode 369 */ 370 aprint_normal("EPH interface in low power mode\n"); 371 sc->sc_internal_phy = 0; 372 return; 373 } 374 /*FALLTHROUGH*/ 375 default: 376 aprint_normal("default media %s\n", (aui = (tmp & CR_AUI_SELECT)) ? 377 "AUI" : "UTP"); 378 for (i = 0; i < NSMC91CxxMEDIA; i++) 379 ifmedia_add(ifm, smc91cxx_media[i], 0, NULL); 380 ifmedia_set(ifm, IFM_ETHER | (aui ? IFM_10_5 : IFM_10_T)); 381 break; 382 } 383 384 rnd_attach_source(&sc->rnd_source, device_xname(&sc->sc_dev), 385 RND_TYPE_NET, 0); 386 387 callout_init(&sc->sc_mii_callout, 0); 388 389 /* The attach is successful. */ 390 sc->sc_flags |= SMC_FLAGS_ATTACHED; 391 } 392 393 /* 394 * Change media according to request. 395 */ 396 int 397 smc91cxx_mediachange(struct ifnet *ifp) 398 { 399 struct smc91cxx_softc *sc = ifp->if_softc; 400 401 return (smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_media)); 402 } 403 404 int 405 smc91cxx_set_media(struct smc91cxx_softc *sc, int media) 406 { 407 bus_space_tag_t bst = sc->sc_bst; 408 bus_space_handle_t bsh = sc->sc_bsh; 409 u_int16_t tmp; 410 int rc; 411 412 /* 413 * If the interface is not currently powered on, just return. 414 * When it is enabled later, smc91cxx_init() will properly set 415 * up the media for us. 416 */ 417 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) 418 return (0); 419 420 if (IFM_TYPE(media) != IFM_ETHER) 421 return (EINVAL); 422 423 if ((sc->sc_flags & SMC_FLAGS_HAS_MII) == 0 || 424 (rc = mii_mediachg(&sc->sc_mii)) == ENXIO) 425 rc = 0; 426 427 switch (IFM_SUBTYPE(media)) { 428 case IFM_10_T: 429 case IFM_10_5: 430 SMC_SELECT_BANK(sc, 1); 431 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 432 if (IFM_SUBTYPE(media) == IFM_10_5) 433 tmp |= CR_AUI_SELECT; 434 else 435 tmp &= ~CR_AUI_SELECT; 436 bus_space_write_2(bst, bsh, CONFIG_REG_W, tmp); 437 delay(20000); /* XXX is this needed? */ 438 break; 439 440 default: 441 return (EINVAL); 442 } 443 444 return rc; 445 } 446 447 /* 448 * Notify the world which media we're using. 449 */ 450 void 451 smc91cxx_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 452 { 453 struct smc91cxx_softc *sc = ifp->if_softc; 454 bus_space_tag_t bst = sc->sc_bst; 455 bus_space_handle_t bsh = sc->sc_bsh; 456 u_int16_t tmp; 457 458 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) { 459 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 460 ifmr->ifm_status = 0; 461 return; 462 } 463 464 /* 465 * If we have MII, go ask the PHY what's going on. 466 */ 467 if (sc->sc_flags & SMC_FLAGS_HAS_MII) { 468 mii_pollstat(&sc->sc_mii); 469 ifmr->ifm_active = sc->sc_mii.mii_media_active; 470 ifmr->ifm_status = sc->sc_mii.mii_media_status; 471 return; 472 } 473 474 SMC_SELECT_BANK(sc, 1); 475 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 476 ifmr->ifm_active = 477 IFM_ETHER | ((tmp & CR_AUI_SELECT) ? IFM_10_5 : IFM_10_T); 478 } 479 480 /* 481 * Reset and initialize the chip. 482 */ 483 void 484 smc91cxx_init(struct smc91cxx_softc *sc) 485 { 486 struct ifnet *ifp = &sc->sc_ec.ec_if; 487 bus_space_tag_t bst = sc->sc_bst; 488 bus_space_handle_t bsh = sc->sc_bsh; 489 u_int16_t tmp; 490 const u_int8_t *enaddr; 491 int s, i; 492 493 s = splnet(); 494 495 /* 496 * This resets the registers mostly to defaults, but doesn't 497 * affect the EEPROM. After the reset cycle, we pause briefly 498 * for the chip to recover. 499 * 500 * XXX how long are we really supposed to delay? --thorpej 501 */ 502 SMC_SELECT_BANK(sc, 0); 503 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, RCR_SOFTRESET); 504 delay(100); 505 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); 506 delay(200); 507 508 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); 509 510 /* Set the Ethernet address. */ 511 SMC_SELECT_BANK(sc, 1); 512 enaddr = (const u_int8_t *)CLLADDR(ifp->if_sadl); 513 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 514 tmp = enaddr[i + 1] << 8 | enaddr[i]; 515 bus_space_write_2(bst, bsh, IAR_ADDR0_REG_W + i, tmp); 516 } 517 518 /* 519 * Set the control register to automatically release successfully 520 * transmitted packets (making the best use of our limited memory) 521 * and enable the EPH interrupt on certain TX errors. 522 */ 523 bus_space_write_2(bst, bsh, CONTROL_REG_W, (CTR_AUTO_RELEASE | 524 CTR_TE_ENABLE | CTR_CR_ENABLE | CTR_LE_ENABLE)); 525 526 /* 527 * Reset the MMU and wait for it to be un-busy. 528 */ 529 SMC_SELECT_BANK(sc, 2); 530 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RESET); 531 sc->sc_txpacketno = ARR_FAILED; 532 for (;;) { 533 tmp = bus_space_read_2(bst, bsh, MMU_CMD_REG_W); 534 if (tmp == 0xffff) /* card went away! */ 535 return; 536 if ((tmp & MMUCR_BUSY) == 0) 537 break; 538 } 539 540 /* 541 * Disable all interrupts. 542 */ 543 smc91cxx_intr_mask_write(bst, bsh, 0); 544 545 /* 546 * On the 91c111, enable auto-negotiation, and set the LED 547 * status pins to something sane. 548 * XXX: Should be some way for MD code to decide the latter. 549 */ 550 SMC_SELECT_BANK(sc, 0); 551 if (sc->sc_chipid == CHIP_91C111) { 552 bus_space_write_2(bst, bsh, RX_PHY_CONTROL_REG_W, 553 RPC_ANEG | 554 (RPC_LS_LINK_DETECT << RPC_LSA_SHIFT) | 555 (RPC_LS_TXRX << RPC_LSB_SHIFT)); 556 } 557 558 /* 559 * Set current media. 560 */ 561 smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_cur->ifm_media); 562 563 /* 564 * Set the receive filter. We want receive enable and auto 565 * strip of CRC from received packet. If we are in promisc. mode, 566 * then set that bit as well. 567 * 568 * XXX Initialize multicast filter. For now, we just accept 569 * XXX all multicast. 570 */ 571 SMC_SELECT_BANK(sc, 0); 572 573 tmp = RCR_ENABLE | RCR_STRIP_CRC | RCR_ALMUL; 574 if (ifp->if_flags & IFF_PROMISC) 575 tmp |= RCR_PROMISC; 576 577 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, tmp); 578 579 /* 580 * Set transmitter control to "enabled". 581 */ 582 tmp = TCR_ENABLE; 583 584 #ifndef SMC91CXX_SW_PAD 585 /* 586 * Enable hardware padding of transmitted packets. 587 * XXX doesn't work? 588 */ 589 tmp |= TCR_PAD_ENABLE; 590 #endif 591 592 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, tmp); 593 594 /* 595 * Now, enable interrupts. 596 */ 597 SMC_SELECT_BANK(sc, 2); 598 599 sc->sc_intmask = IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT; 600 if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy) { 601 sc->sc_intmask |= IM_MD_INT; 602 } 603 smc91cxx_intr_mask_write(bst, bsh, sc->sc_intmask); 604 605 /* Interface is now running, with no output active. */ 606 ifp->if_flags |= IFF_RUNNING; 607 ifp->if_flags &= ~IFF_OACTIVE; 608 609 if (sc->sc_flags & SMC_FLAGS_HAS_MII) { 610 /* Start the one second clock. */ 611 callout_reset(&sc->sc_mii_callout, hz, smc91cxx_tick, sc); 612 } 613 614 /* 615 * Attempt to start any pending transmission. 616 */ 617 smc91cxx_start(ifp); 618 619 splx(s); 620 } 621 622 /* 623 * Start output on an interface. 624 * Must be called at splnet or interrupt level. 625 */ 626 void 627 smc91cxx_start(struct ifnet *ifp) 628 { 629 struct smc91cxx_softc *sc = ifp->if_softc; 630 bus_space_tag_t bst = sc->sc_bst; 631 bus_space_handle_t bsh = sc->sc_bsh; 632 u_int len; 633 struct mbuf *m; 634 u_int16_t length, npages; 635 u_int16_t oddbyte; 636 u_int8_t packetno; 637 int timo, pad; 638 639 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 640 return; 641 642 again: 643 /* 644 * Peek at the next packet. 645 */ 646 IFQ_POLL(&ifp->if_snd, m); 647 if (m == NULL) 648 return; 649 650 /* 651 * Compute the frame length and set pad to give an overall even 652 * number of bytes. Below, we assume that the packet length 653 * is even. 654 */ 655 for (len = 0; m != NULL; m = m->m_next) 656 len += m->m_len; 657 pad = (len & 1); 658 659 /* 660 * We drop packets that are too large. Perhaps we should 661 * truncate them instead? 662 */ 663 if ((len + pad) > (ETHER_MAX_LEN - ETHER_CRC_LEN)) { 664 printf("%s: large packet discarded\n", device_xname(&sc->sc_dev)); 665 ifp->if_oerrors++; 666 IFQ_DEQUEUE(&ifp->if_snd, m); 667 m_freem(m); 668 goto readcheck; 669 } 670 671 #ifdef SMC91CXX_SW_PAD 672 /* 673 * Not using hardware padding; pad to ETHER_MIN_LEN. 674 */ 675 if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 676 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 677 #endif 678 679 length = pad + len; 680 681 /* 682 * The MMU has a 256 byte page size. The MMU expects us to 683 * ask for "npages - 1". We include space for the status word, 684 * byte count, and control bytes in the allocation request. 685 */ 686 npages = ((length & ~1) + 6) >> 8; 687 688 /* 689 * Now allocate the memory. 690 */ 691 SMC_SELECT_BANK(sc, 2); 692 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ALLOC | npages); 693 694 timo = MEMORY_WAIT_TIME; 695 if (__predict_false((sc->sc_txpacketno & ARR_FAILED) == 0)) { 696 packetno = sc->sc_txpacketno; 697 sc->sc_txpacketno = ARR_FAILED; 698 } else { 699 do { 700 if (bus_space_read_1(bst, bsh, 701 INTR_STAT_REG_B) & IM_ALLOC_INT) 702 break; 703 delay(1); 704 } while (--timo); 705 } 706 707 packetno = bus_space_read_1(bst, bsh, ALLOC_RESULT_REG_B); 708 709 if (packetno & ARR_FAILED || timo == 0) { 710 /* 711 * No transmit memory is available. Record the number 712 * of requestd pages and enable the allocation completion 713 * interrupt. Set up the watchdog timer in case we miss 714 * the interrupt. Mark the interface as active so that 715 * no one else attempts to transmit while we're allocating 716 * memory. 717 */ 718 sc->sc_intmask |= IM_ALLOC_INT; 719 smc91cxx_intr_mask_write(bst, bsh, sc->sc_intmask); 720 ifp->if_timer = 5; 721 ifp->if_flags |= IFF_OACTIVE; 722 723 return; 724 } 725 726 /* 727 * We have a packet number - set the data window. 728 */ 729 bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno); 730 731 /* 732 * Point to the beginning of the packet. 733 */ 734 bus_space_write_2(bst, bsh, POINTER_REG_W, PTR_AUTOINC /* | 0x0000 */); 735 736 /* 737 * Send the packet length (+6 for stats, length, and control bytes) 738 * and the status word (set to zeros). 739 */ 740 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 741 bus_space_write_2(bst, bsh, DATA_REG_W, (length + 6) & 0x7ff); 742 743 /* 744 * Get the packet from the kernel. This will include the Ethernet 745 * frame header, MAC address, etc. 746 */ 747 IFQ_DEQUEUE(&ifp->if_snd, m); 748 749 /* 750 * Push the packet out to the card. 751 */ 752 oddbyte = smc91cxx_copy_tx_frame(sc, m); 753 754 #ifdef SMC91CXX_SW_PAD 755 #ifdef SMC91CXX_NO_BYTE_WRITE 756 #if BYTE_ORDER == LITTLE_ENDIAN 757 if (pad > 1 && (pad & 1)) { 758 bus_space_write_2(bst, bsh, DATA_REG_W, oddbyte << 0); 759 oddbyte = 0; 760 } 761 #else 762 if (pad > 1 && (pad & 1)) { 763 bus_space_write_2(bst, bsh, DATA_REG_W, oddbyte << 8); 764 oddbyte = 0; 765 } 766 #endif 767 #endif 768 769 /* 770 * Push out padding. 771 */ 772 while (pad > 1) { 773 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 774 pad -= 2; 775 } 776 #endif 777 778 #ifdef SMC91CXX_NO_BYTE_WRITE 779 /* 780 * Push out control byte and unused packet byte. The control byte 781 * is 0, meaning the packet is even lengthed and no special 782 * CRC handling is necessary. 783 */ 784 #if BYTE_ORDER == LITTLE_ENDIAN 785 bus_space_write_2(bst, bsh, DATA_REG_W, 786 oddbyte | (pad ? (CTLB_ODD << 8) : 0)); 787 #else 788 bus_space_write_2(bst, bsh, DATA_REG_W, 789 (oddbyte << 8) | (pad ? CTLB_ODD : 0)); 790 #endif 791 #else 792 if (pad) 793 bus_space_write_1(bst, bsh, DATA_REG_B, 0); 794 #endif 795 796 /* 797 * Enable transmit interrupts and let the chip go. Set a watchdog 798 * in case we miss the interrupt. 799 */ 800 sc->sc_intmask |= IM_TX_INT | IM_TX_EMPTY_INT; 801 smc91cxx_intr_mask_write(bst, bsh, sc->sc_intmask); 802 803 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ENQUEUE); 804 805 ifp->if_timer = 5; 806 807 /* Hand off a copy to the bpf. */ 808 bpf_mtap(ifp, m); 809 810 ifp->if_opackets++; 811 m_freem(m); 812 813 readcheck: 814 /* 815 * Check for incoming pcakets. We don't want to overflow the small 816 * RX FIFO. If nothing has arrived, attempt to queue another 817 * transmit packet. 818 */ 819 if (bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & FIFO_REMPTY) 820 goto again; 821 } 822 823 /* 824 * Squirt a (possibly misaligned) mbuf to the device 825 */ 826 uint8_t 827 smc91cxx_copy_tx_frame(struct smc91cxx_softc *sc, struct mbuf *m0) 828 { 829 bus_space_tag_t bst = sc->sc_bst; 830 bus_space_handle_t bsh = sc->sc_bsh; 831 struct mbuf *m; 832 int len, leftover; 833 u_int16_t dbuf; 834 u_int8_t *p; 835 #ifdef DIAGNOSTIC 836 u_int8_t *lim; 837 #endif 838 839 /* start out with no leftover data */ 840 leftover = 0; 841 dbuf = 0; 842 843 /* Process the chain of mbufs */ 844 for (m = m0; m != NULL; m = m->m_next) { 845 /* 846 * Process all of the data in a single mbuf. 847 */ 848 p = mtod(m, u_int8_t *); 849 len = m->m_len; 850 #ifdef DIAGNOSTIC 851 lim = p + len; 852 #endif 853 854 while (len > 0) { 855 if (leftover) { 856 /* 857 * Data left over (from mbuf or realignment). 858 * Buffer the next byte, and write it and 859 * the leftover data out. 860 */ 861 dbuf |= *p++ << 8; 862 len--; 863 bus_space_write_2(bst, bsh, DATA_REG_W, dbuf); 864 leftover = 0; 865 } else if ((long) p & 1) { 866 /* 867 * Misaligned data. Buffer the next byte. 868 */ 869 dbuf = *p++; 870 len--; 871 leftover = 1; 872 } else { 873 /* 874 * Aligned data. This is the case we like. 875 * 876 * Write-region out as much as we can, then 877 * buffer the remaining byte (if any). 878 */ 879 leftover = len & 1; 880 len &= ~1; 881 bus_space_write_multi_stream_2(bst, bsh, 882 DATA_REG_W, (u_int16_t *)p, len >> 1); 883 p += len; 884 885 if (leftover) 886 dbuf = *p++; 887 len = 0; 888 } 889 } 890 if (len < 0) 891 panic("smc91cxx_copy_tx_frame: negative len"); 892 #ifdef DIAGNOSTIC 893 if (p != lim) 894 panic("smc91cxx_copy_tx_frame: p != lim"); 895 #endif 896 } 897 #ifndef SMC91CXX_NO_BYTE_WRITE 898 if (leftover) 899 bus_space_write_1(bst, bsh, DATA_REG_B, dbuf); 900 #endif 901 return dbuf; 902 } 903 904 /* 905 * Interrupt service routine. 906 */ 907 int 908 smc91cxx_intr(void *arg) 909 { 910 struct smc91cxx_softc *sc = arg; 911 struct ifnet *ifp = &sc->sc_ec.ec_if; 912 bus_space_tag_t bst = sc->sc_bst; 913 bus_space_handle_t bsh = sc->sc_bsh; 914 u_int8_t mask, interrupts, status; 915 u_int16_t packetno, tx_status, card_stats; 916 #ifdef SMC91CXX_NO_BYTE_WRITE 917 u_int16_t v; 918 #endif 919 920 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 || 921 !device_is_active(&sc->sc_dev)) 922 return (0); 923 924 SMC_SELECT_BANK(sc, 2); 925 926 /* 927 * Obtain the current interrupt status and mask. 928 */ 929 #ifdef SMC91CXX_NO_BYTE_WRITE 930 v = bus_space_read_2(bst, bsh, INTR_STAT_REG_B); 931 932 /* 933 * Get the set of interrupt which occurred and eliminate any 934 * which are not enabled. 935 */ 936 #if BYTE_ORDER == LITTLE_ENDIAN 937 mask = v >> 8; 938 interrupts = v & 0xff; 939 #else 940 interrupts = v >> 8; 941 mask = v & 0xff; 942 #endif 943 KDASSERT(mask == sc->sc_intmask); 944 #else 945 mask = bus_space_read_1(bst, bsh, INTR_MASK_REG_B); 946 947 /* 948 * Get the set of interrupt which occurred and eliminate any 949 * which are not enabled. 950 */ 951 interrupts = bus_space_read_1(bst, bsh, INTR_STAT_REG_B); 952 #endif 953 status = interrupts & mask; 954 955 /* Ours? */ 956 if (status == 0) 957 return (0); 958 959 /* 960 * It's ours; disable all interrupts while we process them. 961 */ 962 smc91cxx_intr_mask_write(bst, bsh, 0); 963 964 /* 965 * Receive overrun interrupts. 966 */ 967 if (status & IM_RX_OVRN_INT) { 968 smc91cxx_intr_ack_write(bst, bsh, IM_RX_OVRN_INT); 969 ifp->if_ierrors++; 970 } 971 972 /* 973 * Receive interrupts. 974 */ 975 if (status & IM_RCV_INT) { 976 #if 1 /* DIAGNOSTIC */ 977 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 978 if (packetno & FIFO_REMPTY) { 979 aprint_error_dev(&sc->sc_dev, "receive interrupt on empty fifo\n"); 980 goto out; 981 } else 982 #endif 983 smc91cxx_read(sc); 984 } 985 986 /* 987 * Memory allocation interrupts. 988 */ 989 if (status & IM_ALLOC_INT) { 990 /* Disable this interrupt. */ 991 mask &= ~IM_ALLOC_INT; 992 sc->sc_intmask &= ~IM_ALLOC_INT; 993 994 /* 995 * Save allocated packet number for use in start 996 */ 997 packetno = bus_space_read_1(bst, bsh, ALLOC_RESULT_REG_B); 998 KASSERT(sc->sc_txpacketno & ARR_FAILED); 999 sc->sc_txpacketno = packetno; 1000 1001 /* 1002 * We can transmit again! 1003 */ 1004 ifp->if_flags &= ~IFF_OACTIVE; 1005 ifp->if_timer = 0; 1006 } 1007 1008 /* 1009 * Transmit complete interrupt. Handle transmission error messages. 1010 * This will only be called on error condition because of AUTO RELEASE 1011 * mode. 1012 */ 1013 if (status & IM_TX_INT) { 1014 smc91cxx_intr_ack_write(bst, bsh, IM_TX_INT); 1015 1016 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & 1017 FIFO_TX_MASK; 1018 1019 /* 1020 * Select this as the packet to read from. 1021 */ 1022 bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno); 1023 1024 /* 1025 * Position the pointer to the beginning of the packet. 1026 */ 1027 bus_space_write_2(bst, bsh, POINTER_REG_W, 1028 PTR_AUTOINC | PTR_READ /* | 0x0000 */); 1029 1030 /* 1031 * Fetch the TX status word. This will be a copy of 1032 * the EPH_STATUS_REG_W at the time of the transmission 1033 * failure. 1034 */ 1035 tx_status = bus_space_read_2(bst, bsh, DATA_REG_W); 1036 1037 if (tx_status & EPHSR_TX_SUC) { 1038 static struct timeval txsuc_last; 1039 static int txsuc_count; 1040 if (ppsratecheck(&txsuc_last, &txsuc_count, 1)) 1041 printf("%s: successful packet caused TX" 1042 " interrupt?!\n", device_xname(&sc->sc_dev)); 1043 } else 1044 ifp->if_oerrors++; 1045 1046 if (tx_status & EPHSR_LATCOL) 1047 ifp->if_collisions++; 1048 1049 /* Disable this interrupt (start will reenable if needed). */ 1050 mask &= ~IM_TX_INT; 1051 sc->sc_intmask &= ~IM_TX_INT; 1052 1053 /* 1054 * Some of these errors disable the transmitter; reenable it. 1055 */ 1056 SMC_SELECT_BANK(sc, 0); 1057 #ifdef SMC91CXX_SW_PAD 1058 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, TCR_ENABLE); 1059 #else 1060 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 1061 TCR_ENABLE | TCR_PAD_ENABLE); 1062 #endif 1063 1064 /* 1065 * Kill the failed packet and wait for the MMU to unbusy. 1066 */ 1067 SMC_SELECT_BANK(sc, 2); 1068 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 1069 /* XXX bound this loop! */ ; 1070 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT); 1071 1072 ifp->if_timer = 0; 1073 } 1074 1075 /* 1076 * Transmit underrun interrupts. We use this opportunity to 1077 * update transmit statistics from the card. 1078 */ 1079 if (status & IM_TX_EMPTY_INT) { 1080 smc91cxx_intr_ack_write(bst, bsh, IM_TX_EMPTY_INT); 1081 1082 /* Disable this interrupt. */ 1083 mask &= ~IM_TX_EMPTY_INT; 1084 sc->sc_intmask &= ~IM_TX_EMPTY_INT; 1085 1086 SMC_SELECT_BANK(sc, 0); 1087 card_stats = bus_space_read_2(bst, bsh, COUNTER_REG_W); 1088 1089 /* Single collisions. */ 1090 ifp->if_collisions += card_stats & ECR_COLN_MASK; 1091 1092 /* Multiple collisions. */ 1093 ifp->if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4; 1094 1095 SMC_SELECT_BANK(sc, 2); 1096 1097 ifp->if_timer = 0; 1098 } 1099 1100 if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy && 1101 (status & IM_MD_INT)) { 1102 /* 1103 * Internal PHY status change 1104 */ 1105 mii_tick(&sc->sc_mii); 1106 } 1107 1108 /* 1109 * Other errors. Reset the interface. 1110 */ 1111 if (status & IM_EPH_INT) { 1112 smc91cxx_stop(sc); 1113 smc91cxx_init(sc); 1114 } 1115 1116 /* 1117 * Attempt to queue more packets for transmission. 1118 */ 1119 smc91cxx_start(ifp); 1120 1121 out: 1122 /* 1123 * Reenable the interrupts we wish to receive now that processing 1124 * is complete. 1125 */ 1126 mask |= sc->sc_intmask; 1127 smc91cxx_intr_mask_write(bst, bsh, mask); 1128 1129 if (status) 1130 rnd_add_uint32(&sc->rnd_source, status); 1131 1132 return (1); 1133 } 1134 1135 /* 1136 * Read a packet from the card and pass it up to the kernel. 1137 * NOTE! WE EXPECT TO BE IN REGISTER WINDOW 2! 1138 */ 1139 void 1140 smc91cxx_read(struct smc91cxx_softc *sc) 1141 { 1142 struct ifnet *ifp = &sc->sc_ec.ec_if; 1143 bus_space_tag_t bst = sc->sc_bst; 1144 bus_space_handle_t bsh = sc->sc_bsh; 1145 struct ether_header *eh; 1146 struct mbuf *m; 1147 u_int16_t status, packetno, packetlen; 1148 u_int8_t *data; 1149 u_int32_t dr; 1150 1151 again: 1152 /* 1153 * Set data pointer to the beginning of the packet. Since 1154 * PTR_RCV is set, the packet number will be found automatically 1155 * in FIFO_PORTS_REG_W, FIFO_RX_MASK. 1156 */ 1157 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 1158 if (packetno & FIFO_REMPTY) 1159 return; 1160 1161 bus_space_write_2(bst, bsh, POINTER_REG_W, 1162 PTR_READ | PTR_RCV | PTR_AUTOINC /* | 0x0000 */); 1163 1164 /* 1165 * First two words are status and packet length. 1166 */ 1167 if ((sc->sc_flags & SMC_FLAGS_32BIT_READ) == 0) { 1168 status = bus_space_read_2(bst, bsh, DATA_REG_W); 1169 packetlen = bus_space_read_2(bst, bsh, DATA_REG_W); 1170 } else { 1171 dr = bus_space_read_4(bst, bsh, DATA_REG_W); 1172 #if BYTE_ORDER == LITTLE_ENDIAN 1173 status = (u_int16_t)dr; 1174 packetlen = (u_int16_t)(dr >> 16); 1175 #else 1176 packetlen = (u_int16_t)dr; 1177 status = (u_int16_t)(dr >> 16); 1178 #endif 1179 } 1180 1181 packetlen &= RLEN_MASK; 1182 if (packetlen < ETHER_MIN_LEN - ETHER_CRC_LEN + 6 || packetlen > 1534) { 1183 ifp->if_ierrors++; 1184 goto out; 1185 } 1186 1187 /* 1188 * The packet length includes 3 extra words: status, length, 1189 * and an extra word that includes the control byte. 1190 */ 1191 packetlen -= 6; 1192 1193 /* 1194 * Account for receive errors and discard. 1195 */ 1196 if (status & RS_ERRORS) { 1197 ifp->if_ierrors++; 1198 goto out; 1199 } 1200 1201 /* 1202 * Adjust for odd-length packet. 1203 */ 1204 if (status & RS_ODDFRAME) 1205 packetlen++; 1206 1207 /* 1208 * Allocate a header mbuf. 1209 */ 1210 MGETHDR(m, M_DONTWAIT, MT_DATA); 1211 if (m == NULL) 1212 goto out; 1213 m->m_pkthdr.rcvif = ifp; 1214 m->m_pkthdr.len = packetlen; 1215 1216 /* 1217 * Always put the packet in a cluster. 1218 * XXX should chain small mbufs if less than threshold. 1219 */ 1220 MCLGET(m, M_DONTWAIT); 1221 if ((m->m_flags & M_EXT) == 0) { 1222 m_freem(m); 1223 ifp->if_ierrors++; 1224 aprint_error_dev(&sc->sc_dev, "can't allocate cluster for incoming packet\n"); 1225 goto out; 1226 } 1227 1228 /* 1229 * Pull the packet off the interface. Make sure the payload 1230 * is aligned. 1231 */ 1232 if ((sc->sc_flags & SMC_FLAGS_32BIT_READ) == 0) { 1233 m->m_data = (char *) ALIGN(mtod(m, char *) + 1234 sizeof(struct ether_header)) - sizeof(struct ether_header); 1235 1236 eh = mtod(m, struct ether_header *); 1237 data = mtod(m, u_int8_t *); 1238 KASSERT(trunc_page((uintptr_t)data) == trunc_page((uintptr_t)data + packetlen - 1)); 1239 if (packetlen > 1) 1240 bus_space_read_multi_stream_2(bst, bsh, DATA_REG_W, 1241 (u_int16_t *)data, packetlen >> 1); 1242 if (packetlen & 1) { 1243 data += packetlen & ~1; 1244 *data = bus_space_read_1(bst, bsh, DATA_REG_B); 1245 } 1246 } else { 1247 u_int8_t *dp; 1248 1249 m->m_data = (void *) ALIGN(mtod(m, void *)); 1250 eh = mtod(m, struct ether_header *); 1251 dp = data = mtod(m, u_int8_t *); 1252 KASSERT(trunc_page((uintptr_t)data) == trunc_page((uintptr_t)data + packetlen - 1)); 1253 if (packetlen > 3) 1254 bus_space_read_multi_stream_4(bst, bsh, DATA_REG_W, 1255 (u_int32_t *)data, packetlen >> 2); 1256 if (packetlen & 3) { 1257 data += packetlen & ~3; 1258 *((u_int32_t *)data) = 1259 bus_space_read_stream_4(bst, bsh, DATA_REG_W); 1260 } 1261 } 1262 1263 ifp->if_ipackets++; 1264 1265 /* 1266 * Make sure to behave as IFF_SIMPLEX in all cases. 1267 * This is to cope with SMC91C92 (Megahertz XJ10BT), which 1268 * loops back packets to itself on promiscuous mode. 1269 * (should be ensured by chipset configuration) 1270 */ 1271 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1272 /* 1273 * Drop packet looped back from myself. 1274 */ 1275 if (ether_cmp(eh->ether_shost, CLLADDR(ifp->if_sadl)) == 0) { 1276 m_freem(m); 1277 goto out; 1278 } 1279 } 1280 1281 m->m_pkthdr.len = m->m_len = packetlen; 1282 1283 /* 1284 * Hand the packet off to bpf listeners. 1285 */ 1286 bpf_mtap(ifp, m); 1287 1288 (*ifp->if_input)(ifp, m); 1289 1290 out: 1291 /* 1292 * Tell the card to free the memory occupied by this packet. 1293 */ 1294 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 1295 /* XXX bound this loop! */ ; 1296 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RELEASE); 1297 1298 /* 1299 * Check for another packet. 1300 */ 1301 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 1302 if (packetno & FIFO_REMPTY) 1303 return; 1304 goto again; 1305 } 1306 1307 /* 1308 * Process an ioctl request. 1309 */ 1310 int 1311 smc91cxx_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1312 { 1313 struct smc91cxx_softc *sc = ifp->if_softc; 1314 struct ifaddr *ifa = (struct ifaddr *)data; 1315 struct ifreq *ifr = (struct ifreq *)data; 1316 int s, error = 0; 1317 1318 s = splnet(); 1319 1320 switch (cmd) { 1321 case SIOCINITIFADDR: 1322 if ((error = smc91cxx_enable(sc)) != 0) 1323 break; 1324 ifp->if_flags |= IFF_UP; 1325 smc91cxx_init(sc); 1326 switch (ifa->ifa_addr->sa_family) { 1327 #ifdef INET 1328 case AF_INET: 1329 arp_ifinit(ifp, ifa); 1330 break; 1331 #endif 1332 default: 1333 break; 1334 } 1335 break; 1336 1337 1338 case SIOCSIFFLAGS: 1339 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1340 break; 1341 /* XXX re-use ether_ioctl() */ 1342 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 1343 case IFF_RUNNING: 1344 /* 1345 * If interface is marked down and it is running, 1346 * stop it. 1347 */ 1348 smc91cxx_stop(sc); 1349 ifp->if_flags &= ~IFF_RUNNING; 1350 smc91cxx_disable(sc); 1351 break; 1352 case IFF_UP: 1353 /* 1354 * If interface is marked up and it is stopped, 1355 * start it. 1356 */ 1357 if ((error = smc91cxx_enable(sc)) != 0) 1358 break; 1359 smc91cxx_init(sc); 1360 break; 1361 case IFF_UP|IFF_RUNNING: 1362 /* 1363 * Reset the interface to pick up changes in any 1364 * other flags that affect hardware registers. 1365 */ 1366 smc91cxx_reset(sc); 1367 break; 1368 case 0: 1369 break; 1370 } 1371 break; 1372 1373 case SIOCADDMULTI: 1374 case SIOCDELMULTI: 1375 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) { 1376 error = EIO; 1377 break; 1378 } 1379 1380 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1381 /* 1382 * Multicast list has changed; set the hardware 1383 * filter accordingly. 1384 */ 1385 if (ifp->if_flags & IFF_RUNNING) 1386 smc91cxx_reset(sc); 1387 error = 0; 1388 } 1389 break; 1390 1391 case SIOCGIFMEDIA: 1392 case SIOCSIFMEDIA: 1393 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1394 break; 1395 1396 default: 1397 error = ether_ioctl(ifp, cmd, data); 1398 break; 1399 } 1400 1401 splx(s); 1402 return (error); 1403 } 1404 1405 /* 1406 * Reset the interface. 1407 */ 1408 void 1409 smc91cxx_reset(struct smc91cxx_softc *sc) 1410 { 1411 int s; 1412 1413 s = splnet(); 1414 smc91cxx_stop(sc); 1415 smc91cxx_init(sc); 1416 splx(s); 1417 } 1418 1419 /* 1420 * Watchdog timer. 1421 */ 1422 void 1423 smc91cxx_watchdog(struct ifnet *ifp) 1424 { 1425 struct smc91cxx_softc *sc = ifp->if_softc; 1426 1427 log(LOG_ERR, "%s: device timeout\n", device_xname(&sc->sc_dev)); 1428 ifp->if_oerrors++; 1429 smc91cxx_reset(sc); 1430 } 1431 1432 /* 1433 * Stop output on the interface. 1434 */ 1435 void 1436 smc91cxx_stop(struct smc91cxx_softc *sc) 1437 { 1438 bus_space_tag_t bst = sc->sc_bst; 1439 bus_space_handle_t bsh = sc->sc_bsh; 1440 1441 /* 1442 * Clear interrupt mask; disable all interrupts. 1443 */ 1444 SMC_SELECT_BANK(sc, 2); 1445 smc91cxx_intr_mask_write(bst, bsh, 0); 1446 1447 /* 1448 * Disable transmitter and receiver. 1449 */ 1450 SMC_SELECT_BANK(sc, 0); 1451 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); 1452 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); 1453 1454 /* 1455 * Cancel watchdog timer. 1456 */ 1457 sc->sc_ec.ec_if.if_timer = 0; 1458 } 1459 1460 /* 1461 * Enable power on the interface. 1462 */ 1463 int 1464 smc91cxx_enable(struct smc91cxx_softc *sc) 1465 { 1466 1467 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 && sc->sc_enable != NULL) { 1468 if ((*sc->sc_enable)(sc) != 0) { 1469 aprint_error_dev(&sc->sc_dev, "device enable failed\n"); 1470 return (EIO); 1471 } 1472 } 1473 1474 sc->sc_flags |= SMC_FLAGS_ENABLED; 1475 return (0); 1476 } 1477 1478 /* 1479 * Disable power on the interface. 1480 */ 1481 void 1482 smc91cxx_disable(struct smc91cxx_softc *sc) 1483 { 1484 1485 if ((sc->sc_flags & SMC_FLAGS_ENABLED) != 0 && sc->sc_disable != NULL) { 1486 (*sc->sc_disable)(sc); 1487 sc->sc_flags &= ~SMC_FLAGS_ENABLED; 1488 } 1489 } 1490 1491 int 1492 smc91cxx_activate(device_t self, enum devact act) 1493 { 1494 struct smc91cxx_softc *sc = device_private(self); 1495 1496 switch (act) { 1497 case DVACT_DEACTIVATE: 1498 if_deactivate(&sc->sc_ec.ec_if); 1499 return 0; 1500 default: 1501 return EOPNOTSUPP; 1502 } 1503 } 1504 1505 int 1506 smc91cxx_detach(device_t self, int flags) 1507 { 1508 struct smc91cxx_softc *sc = device_private(self); 1509 struct ifnet *ifp = &sc->sc_ec.ec_if; 1510 1511 /* Succeed now if there's no work to do. */ 1512 if ((sc->sc_flags & SMC_FLAGS_ATTACHED) == 0) 1513 return (0); 1514 1515 1516 /* smc91cxx_disable() checks SMC_FLAGS_ENABLED */ 1517 smc91cxx_disable(sc); 1518 1519 /* smc91cxx_attach() never fails */ 1520 1521 /* Delete all media. */ 1522 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1523 1524 rnd_detach_source(&sc->rnd_source); 1525 1526 ether_ifdetach(ifp); 1527 if_detach(ifp); 1528 1529 return (0); 1530 } 1531 1532 u_int32_t 1533 smc91cxx_mii_bitbang_read(device_t self) 1534 { 1535 struct smc91cxx_softc *sc = device_private(self); 1536 1537 /* We're already in bank 3. */ 1538 return (bus_space_read_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W)); 1539 } 1540 1541 void 1542 smc91cxx_mii_bitbang_write(device_t self, u_int32_t val) 1543 { 1544 struct smc91cxx_softc *sc = device_private(self); 1545 1546 /* We're already in bank 3. */ 1547 bus_space_write_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W, val); 1548 } 1549 1550 int 1551 smc91cxx_mii_readreg(device_t self, int phy, int reg) 1552 { 1553 struct smc91cxx_softc *sc = device_private(self); 1554 int val; 1555 1556 SMC_SELECT_BANK(sc, 3); 1557 1558 val = mii_bitbang_readreg(self, &smc91cxx_mii_bitbang_ops, phy, reg); 1559 1560 SMC_SELECT_BANK(sc, 2); 1561 1562 return (val); 1563 } 1564 1565 void 1566 smc91cxx_mii_writereg(device_t self, int phy, int reg, int val) 1567 { 1568 struct smc91cxx_softc *sc = device_private(self); 1569 1570 SMC_SELECT_BANK(sc, 3); 1571 1572 mii_bitbang_writereg(self, &smc91cxx_mii_bitbang_ops, phy, reg, val); 1573 1574 SMC_SELECT_BANK(sc, 2); 1575 } 1576 1577 void 1578 smc91cxx_statchg(device_t self) 1579 { 1580 struct smc91cxx_softc *sc = device_private(self); 1581 bus_space_tag_t bst = sc->sc_bst; 1582 bus_space_handle_t bsh = sc->sc_bsh; 1583 int mctl; 1584 1585 SMC_SELECT_BANK(sc, 0); 1586 mctl = bus_space_read_2(bst, bsh, TXMIT_CONTROL_REG_W); 1587 if (sc->sc_mii.mii_media_active & IFM_FDX) 1588 mctl |= TCR_SWFDUP; 1589 else 1590 mctl &= ~TCR_SWFDUP; 1591 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, mctl); 1592 SMC_SELECT_BANK(sc, 2); /* back to operating window */ 1593 } 1594 1595 /* 1596 * One second timer, used to tick the MII. 1597 */ 1598 void 1599 smc91cxx_tick(void *arg) 1600 { 1601 struct smc91cxx_softc *sc = arg; 1602 int s; 1603 1604 #ifdef DIAGNOSTIC 1605 if ((sc->sc_flags & SMC_FLAGS_HAS_MII) == 0) 1606 panic("smc91cxx_tick"); 1607 #endif 1608 1609 if (!device_is_active(&sc->sc_dev)) 1610 return; 1611 1612 s = splnet(); 1613 mii_tick(&sc->sc_mii); 1614 splx(s); 1615 1616 callout_reset(&sc->sc_mii_callout, hz, smc91cxx_tick, sc); 1617 } 1618 1619