1 /* $NetBSD: smc91cxx.c,v 1.54 2005/12/24 20:27:30 perry Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com> 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Gardner Buchanan. 55 * 4. The name of Gardner Buchanan may not be used to endorse or promote 56 * products derived from this software without specific prior written 57 * permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 60 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 61 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 63 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 64 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 65 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 66 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 67 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 68 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 69 * 70 * from FreeBSD Id: if_sn.c,v 1.4 1996/03/18 15:47:16 gardner Exp 71 */ 72 73 /* 74 * Core driver for the SMC 91Cxx family of Ethernet chips. 75 * 76 * Memory allocation interrupt logic is drived from an SMC 91C90 driver 77 * written for NetBSD/amiga by Michael Hitch. 78 */ 79 80 #include <sys/cdefs.h> 81 __KERNEL_RCSID(0, "$NetBSD: smc91cxx.c,v 1.54 2005/12/24 20:27:30 perry Exp $"); 82 83 #include "opt_inet.h" 84 #include "opt_ccitt.h" 85 #include "opt_llc.h" 86 #include "opt_ns.h" 87 #include "bpfilter.h" 88 #include "rnd.h" 89 90 #include <sys/param.h> 91 #include <sys/systm.h> 92 #include <sys/mbuf.h> 93 #include <sys/syslog.h> 94 #include <sys/socket.h> 95 #include <sys/device.h> 96 #include <sys/kernel.h> 97 #include <sys/malloc.h> 98 #include <sys/ioctl.h> 99 #include <sys/errno.h> 100 #if NRND > 0 101 #include <sys/rnd.h> 102 #endif 103 104 #include <machine/bus.h> 105 #include <machine/intr.h> 106 107 #include <net/if.h> 108 #include <net/if_dl.h> 109 #include <net/if_ether.h> 110 #include <net/if_media.h> 111 112 #ifdef INET 113 #include <netinet/in.h> 114 #include <netinet/if_inarp.h> 115 #include <netinet/in_systm.h> 116 #include <netinet/in_var.h> 117 #include <netinet/ip.h> 118 #endif 119 120 #ifdef NS 121 #include <netns/ns.h> 122 #include <netns/ns_if.h> 123 #endif 124 125 #if defined(CCITT) && defined(LLC) 126 #include <sys/socketvar.h> 127 #include <netccitt/x25.h> 128 #include <netccitt/pk.h> 129 #include <netccitt/pk_var.h> 130 #include <netccitt/pk_extern.h> 131 #endif 132 133 #if NBPFILTER > 0 134 #include <net/bpf.h> 135 #include <net/bpfdesc.h> 136 #endif 137 138 #include <dev/mii/mii.h> 139 #include <dev/mii/miivar.h> 140 #include <dev/mii/mii_bitbang.h> 141 142 #include <dev/ic/smc91cxxreg.h> 143 #include <dev/ic/smc91cxxvar.h> 144 145 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 146 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 147 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 148 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 149 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 150 151 #define bus_space_write_stream_4 bus_space_write_4 152 #define bus_space_read_stream_4 bus_space_read_4 153 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 154 155 /* XXX Hardware padding doesn't work yet(?) */ 156 #define SMC91CXX_SW_PAD 157 158 const char *smc91cxx_idstrs[] = { 159 NULL, /* 0 */ 160 NULL, /* 1 */ 161 NULL, /* 2 */ 162 "SMC91C90/91C92", /* 3 */ 163 "SMC91C94/91C96", /* 4 */ 164 "SMC91C95", /* 5 */ 165 NULL, /* 6 */ 166 "SMC91C100", /* 7 */ 167 "SMC91C100FD", /* 8 */ 168 "SMC91C111", /* 9 */ 169 NULL, /* 10 */ 170 NULL, /* 11 */ 171 NULL, /* 12 */ 172 NULL, /* 13 */ 173 NULL, /* 14 */ 174 NULL, /* 15 */ 175 }; 176 177 /* Supported media types. */ 178 const int smc91cxx_media[] = { 179 IFM_ETHER|IFM_10_T, 180 IFM_ETHER|IFM_10_5, 181 }; 182 #define NSMC91CxxMEDIA (sizeof(smc91cxx_media) / sizeof(smc91cxx_media[0])) 183 184 /* 185 * MII bit-bang glue. 186 */ 187 u_int32_t smc91cxx_mii_bitbang_read(struct device *); 188 void smc91cxx_mii_bitbang_write(struct device *, u_int32_t); 189 190 const struct mii_bitbang_ops smc91cxx_mii_bitbang_ops = { 191 smc91cxx_mii_bitbang_read, 192 smc91cxx_mii_bitbang_write, 193 { 194 MR_MDO, /* MII_BIT_MDO */ 195 MR_MDI, /* MII_BIT_MDI */ 196 MR_MCLK, /* MII_BIT_MDC */ 197 MR_MDOE, /* MII_BIT_DIR_HOST_PHY */ 198 0, /* MII_BIT_DIR_PHY_HOST */ 199 } 200 }; 201 202 /* MII callbacks */ 203 int smc91cxx_mii_readreg(struct device *, int, int); 204 void smc91cxx_mii_writereg(struct device *, int, int, int); 205 void smc91cxx_statchg(struct device *); 206 void smc91cxx_tick(void *); 207 208 int smc91cxx_mediachange(struct ifnet *); 209 void smc91cxx_mediastatus(struct ifnet *, struct ifmediareq *); 210 211 int smc91cxx_set_media(struct smc91cxx_softc *, int); 212 213 void smc91cxx_init(struct smc91cxx_softc *); 214 void smc91cxx_read(struct smc91cxx_softc *); 215 void smc91cxx_reset(struct smc91cxx_softc *); 216 void smc91cxx_start(struct ifnet *); 217 void smc91cxx_copy_tx_frame(struct smc91cxx_softc *, struct mbuf *); 218 void smc91cxx_resume(struct smc91cxx_softc *); 219 void smc91cxx_stop(struct smc91cxx_softc *); 220 void smc91cxx_watchdog(struct ifnet *); 221 int smc91cxx_ioctl(struct ifnet *, u_long, caddr_t); 222 223 static inline int ether_cmp(void *, void *); 224 static inline int 225 ether_cmp(va, vb) 226 void *va, *vb; 227 { 228 u_int8_t *a = va; 229 u_int8_t *b = vb; 230 231 return ((a[5] != b[5]) || (a[4] != b[4]) || (a[3] != b[3]) || 232 (a[2] != b[2]) || (a[1] != b[1]) || (a[0] != b[0])); 233 } 234 235 void 236 smc91cxx_attach(sc, myea) 237 struct smc91cxx_softc *sc; 238 u_int8_t *myea; 239 { 240 struct ifnet *ifp = &sc->sc_ec.ec_if; 241 bus_space_tag_t bst = sc->sc_bst; 242 bus_space_handle_t bsh = sc->sc_bsh; 243 struct ifmedia *ifm = &sc->sc_mii.mii_media; 244 const char *idstr; 245 u_int32_t miicapabilities; 246 u_int16_t tmp; 247 u_int8_t enaddr[ETHER_ADDR_LEN]; 248 int i, aui, mult, scale, memsize; 249 char pbuf[9]; 250 251 tmp = bus_space_read_2(bst, bsh, BANK_SELECT_REG_W); 252 /* check magic number */ 253 if ((tmp & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 254 aprint_error("%s: failed to detect chip, bsr=%04x\n", 255 sc->sc_dev.dv_xname, tmp); 256 return; 257 } 258 259 /* Make sure the chip is stopped. */ 260 smc91cxx_stop(sc); 261 262 SMC_SELECT_BANK(sc, 3); 263 tmp = bus_space_read_2(bst, bsh, REVISION_REG_W); 264 sc->sc_chipid = RR_ID(tmp); 265 idstr = smc91cxx_idstrs[sc->sc_chipid]; 266 267 aprint_normal("%s: ", sc->sc_dev.dv_xname); 268 if (idstr != NULL) 269 aprint_normal("%s, ", idstr); 270 else 271 aprint_normal("unknown chip id %d, ", sc->sc_chipid); 272 aprint_normal("revision %d, ", RR_REV(tmp)); 273 274 SMC_SELECT_BANK(sc, 0); 275 switch (sc->sc_chipid) { 276 default: 277 mult = MCR_MEM_MULT(bus_space_read_2(bst, bsh, MEM_CFG_REG_W)); 278 scale = MIR_SCALE_91C9x; 279 break; 280 281 case CHIP_91C111: 282 mult = MIR_MULT_91C111; 283 scale = MIR_SCALE_91C111; 284 } 285 memsize = bus_space_read_2(bst, bsh, MEM_INFO_REG_W) & MIR_TOTAL_MASK; 286 if (memsize == 255) memsize++; 287 memsize *= scale * mult; 288 289 format_bytes(pbuf, sizeof(pbuf), memsize); 290 aprint_normal("buffer size: %s\n", pbuf); 291 292 /* Read the station address from the chip. */ 293 SMC_SELECT_BANK(sc, 1); 294 if (myea == NULL) { 295 myea = enaddr; 296 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 297 tmp = bus_space_read_2(bst, bsh, IAR_ADDR0_REG_W + i); 298 myea[i + 1] = (tmp >> 8) & 0xff; 299 myea[i] = tmp & 0xff; 300 } 301 } 302 aprint_normal("%s: MAC address %s, ", sc->sc_dev.dv_xname, 303 ether_sprintf(myea)); 304 305 /* Initialize the ifnet structure. */ 306 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 307 ifp->if_softc = sc; 308 ifp->if_start = smc91cxx_start; 309 ifp->if_ioctl = smc91cxx_ioctl; 310 ifp->if_watchdog = smc91cxx_watchdog; 311 ifp->if_flags = 312 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 313 IFQ_SET_READY(&ifp->if_snd); 314 315 /* Attach the interface. */ 316 if_attach(ifp); 317 ether_ifattach(ifp, myea); 318 319 /* 320 * Initialize our media structures and MII info. We will 321 * probe the MII if we are on the SMC91Cxx 322 */ 323 sc->sc_mii.mii_ifp = ifp; 324 sc->sc_mii.mii_readreg = smc91cxx_mii_readreg; 325 sc->sc_mii.mii_writereg = smc91cxx_mii_writereg; 326 sc->sc_mii.mii_statchg = smc91cxx_statchg; 327 ifmedia_init(ifm, IFM_IMASK, smc91cxx_mediachange, smc91cxx_mediastatus); 328 329 SMC_SELECT_BANK(sc, 1); 330 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 331 332 miicapabilities = BMSR_MEDIAMASK|BMSR_ANEG; 333 switch (sc->sc_chipid) { 334 case CHIP_91100: 335 /* 336 * The 91100 does not have full-duplex capabilities, 337 * even if the PHY does. 338 */ 339 miicapabilities &= ~(BMSR_100TXFDX | BMSR_10TFDX); 340 case CHIP_91100FD: 341 case CHIP_91C111: 342 if (tmp & CR_MII_SELECT) { 343 aprint_normal("default media MII"); 344 if (sc->sc_chipid == CHIP_91C111) { 345 aprint_normal(" (%s PHY)\n", (tmp & CR_AUI_SELECT) ? 346 "external" : "internal"); 347 sc->sc_internal_phy = !(tmp & CR_AUI_SELECT); 348 } else 349 aprint_normal("\n"); 350 mii_attach(&sc->sc_dev, &sc->sc_mii, miicapabilities, 351 MII_PHY_ANY, MII_OFFSET_ANY, 0); 352 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 353 ifmedia_add(&sc->sc_mii.mii_media, 354 IFM_ETHER|IFM_NONE, 0, NULL); 355 ifmedia_set(&sc->sc_mii.mii_media, 356 IFM_ETHER|IFM_NONE); 357 } else { 358 ifmedia_set(&sc->sc_mii.mii_media, 359 IFM_ETHER|IFM_AUTO); 360 } 361 sc->sc_flags |= SMC_FLAGS_HAS_MII; 362 break; 363 } else 364 if (sc->sc_chipid == CHIP_91C111) { 365 /* 366 * XXX: Should bring it out of low-power mode 367 */ 368 aprint_normal("EPH interface in low power mode\n"); 369 sc->sc_internal_phy = 0; 370 return; 371 } 372 /*FALLTHROUGH*/ 373 default: 374 aprint_normal("default media %s\n", (aui = (tmp & CR_AUI_SELECT)) ? 375 "AUI" : "UTP"); 376 for (i = 0; i < NSMC91CxxMEDIA; i++) 377 ifmedia_add(ifm, smc91cxx_media[i], 0, NULL); 378 ifmedia_set(ifm, IFM_ETHER | (aui ? IFM_10_5 : IFM_10_T)); 379 break; 380 } 381 382 #if NRND > 0 383 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 384 RND_TYPE_NET, 0); 385 #endif 386 387 /* The attach is successful. */ 388 sc->sc_flags |= SMC_FLAGS_ATTACHED; 389 } 390 391 /* 392 * Change media according to request. 393 */ 394 int 395 smc91cxx_mediachange(ifp) 396 struct ifnet *ifp; 397 { 398 struct smc91cxx_softc *sc = ifp->if_softc; 399 400 return (smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_media)); 401 } 402 403 int 404 smc91cxx_set_media(sc, media) 405 struct smc91cxx_softc *sc; 406 int media; 407 { 408 bus_space_tag_t bst = sc->sc_bst; 409 bus_space_handle_t bsh = sc->sc_bsh; 410 u_int16_t tmp; 411 412 /* 413 * If the interface is not currently powered on, just return. 414 * When it is enabled later, smc91cxx_init() will properly set 415 * up the media for us. 416 */ 417 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) 418 return (0); 419 420 if (IFM_TYPE(media) != IFM_ETHER) 421 return (EINVAL); 422 423 if (sc->sc_flags & SMC_FLAGS_HAS_MII) 424 return (mii_mediachg(&sc->sc_mii)); 425 426 switch (IFM_SUBTYPE(media)) { 427 case IFM_10_T: 428 case IFM_10_5: 429 SMC_SELECT_BANK(sc, 1); 430 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 431 if (IFM_SUBTYPE(media) == IFM_10_5) 432 tmp |= CR_AUI_SELECT; 433 else 434 tmp &= ~CR_AUI_SELECT; 435 bus_space_write_2(bst, bsh, CONFIG_REG_W, tmp); 436 delay(20000); /* XXX is this needed? */ 437 break; 438 439 default: 440 return (EINVAL); 441 } 442 443 return (0); 444 } 445 446 /* 447 * Notify the world which media we're using. 448 */ 449 void 450 smc91cxx_mediastatus(ifp, ifmr) 451 struct ifnet *ifp; 452 struct ifmediareq *ifmr; 453 { 454 struct smc91cxx_softc *sc = ifp->if_softc; 455 bus_space_tag_t bst = sc->sc_bst; 456 bus_space_handle_t bsh = sc->sc_bsh; 457 u_int16_t tmp; 458 459 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) { 460 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 461 ifmr->ifm_status = 0; 462 return; 463 } 464 465 /* 466 * If we have MII, go ask the PHY what's going on. 467 */ 468 if (sc->sc_flags & SMC_FLAGS_HAS_MII) { 469 mii_pollstat(&sc->sc_mii); 470 ifmr->ifm_active = sc->sc_mii.mii_media_active; 471 ifmr->ifm_status = sc->sc_mii.mii_media_status; 472 return; 473 } 474 475 SMC_SELECT_BANK(sc, 1); 476 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 477 ifmr->ifm_active = 478 IFM_ETHER | ((tmp & CR_AUI_SELECT) ? IFM_10_5 : IFM_10_T); 479 } 480 481 /* 482 * Reset and initialize the chip. 483 */ 484 void 485 smc91cxx_init(sc) 486 struct smc91cxx_softc *sc; 487 { 488 struct ifnet *ifp = &sc->sc_ec.ec_if; 489 bus_space_tag_t bst = sc->sc_bst; 490 bus_space_handle_t bsh = sc->sc_bsh; 491 u_int16_t tmp; 492 u_int8_t *enaddr; 493 int s, i; 494 495 s = splnet(); 496 497 /* 498 * This resets the registers mostly to defaults, but doesn't 499 * affect the EEPROM. After the reset cycle, we pause briefly 500 * for the chip to recover. 501 * 502 * XXX how long are we really supposed to delay? --thorpej 503 */ 504 SMC_SELECT_BANK(sc, 0); 505 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, RCR_SOFTRESET); 506 delay(100); 507 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); 508 delay(200); 509 510 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); 511 512 /* Set the Ethernet address. */ 513 SMC_SELECT_BANK(sc, 1); 514 enaddr = (u_int8_t *)LLADDR(ifp->if_sadl); 515 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 516 tmp = enaddr[i + 1] << 8 | enaddr[i]; 517 bus_space_write_2(bst, bsh, IAR_ADDR0_REG_W + i, tmp); 518 } 519 520 /* 521 * Set the control register to automatically release successfully 522 * transmitted packets (making the best use of our limited memory) 523 * and enable the EPH interrupt on certain TX errors. 524 */ 525 bus_space_write_2(bst, bsh, CONTROL_REG_W, (CTR_AUTO_RELEASE | 526 CTR_TE_ENABLE | CTR_CR_ENABLE | CTR_LE_ENABLE)); 527 528 /* 529 * Reset the MMU and wait for it to be un-busy. 530 */ 531 SMC_SELECT_BANK(sc, 2); 532 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RESET); 533 for (;;) { 534 tmp = bus_space_read_2(bst, bsh, MMU_CMD_REG_W); 535 if (tmp == 0xffff) /* card went away! */ 536 return; 537 if ((tmp & MMUCR_BUSY) == 0) 538 break; 539 } 540 541 /* 542 * Disable all interrupts. 543 */ 544 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0); 545 546 /* 547 * On the 91c111, enable auto-negotiation, and set the LED 548 * status pins to something sane. 549 * XXX: Should be some way for MD code to decide the latter. 550 */ 551 SMC_SELECT_BANK(sc, 0); 552 if (sc->sc_chipid == CHIP_91C111) { 553 bus_space_write_2(bst, bsh, RX_PHY_CONTROL_REG_W, 554 RPC_ANEG | 555 (RPC_LS_LINK_DETECT << RPC_LSA_SHIFT) | 556 (RPC_LS_TXRX << RPC_LSB_SHIFT)); 557 } 558 559 /* 560 * Set current media. 561 */ 562 smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_cur->ifm_media); 563 564 /* 565 * Set the receive filter. We want receive enable and auto 566 * strip of CRC from received packet. If we are in promisc. mode, 567 * then set that bit as well. 568 * 569 * XXX Initialize multicast filter. For now, we just accept 570 * XXX all multicast. 571 */ 572 SMC_SELECT_BANK(sc, 0); 573 574 tmp = RCR_ENABLE | RCR_STRIP_CRC | RCR_ALMUL; 575 if (ifp->if_flags & IFF_PROMISC) 576 tmp |= RCR_PROMISC; 577 578 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, tmp); 579 580 /* 581 * Set transmitter control to "enabled". 582 */ 583 tmp = TCR_ENABLE; 584 585 #ifndef SMC91CXX_SW_PAD 586 /* 587 * Enable hardware padding of transmitted packets. 588 * XXX doesn't work? 589 */ 590 tmp |= TCR_PAD_ENABLE; 591 #endif 592 593 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, tmp); 594 595 /* 596 * Now, enable interrupts. 597 */ 598 SMC_SELECT_BANK(sc, 2); 599 600 if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy) { 601 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 602 IM_EPH_INT | IM_RX_OVRN_INT | 603 IM_RCV_INT | IM_TX_INT | IM_MD_INT); 604 } else { 605 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 606 IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | IM_TX_INT); 607 } 608 609 /* Interface is now running, with no output active. */ 610 ifp->if_flags |= IFF_RUNNING; 611 ifp->if_flags &= ~IFF_OACTIVE; 612 613 if (sc->sc_flags & SMC_FLAGS_HAS_MII) { 614 /* Start the one second clock. */ 615 callout_reset(&sc->sc_mii_callout, hz, smc91cxx_tick, sc); 616 } 617 618 /* 619 * Attempt to start any pending transmission. 620 */ 621 smc91cxx_start(ifp); 622 623 splx(s); 624 } 625 626 /* 627 * Start output on an interface. 628 * Must be called at splnet or interrupt level. 629 */ 630 void 631 smc91cxx_start(ifp) 632 struct ifnet *ifp; 633 { 634 struct smc91cxx_softc *sc = ifp->if_softc; 635 bus_space_tag_t bst = sc->sc_bst; 636 bus_space_handle_t bsh = sc->sc_bsh; 637 u_int len; 638 struct mbuf *m; 639 u_int16_t length, npages; 640 u_int8_t packetno; 641 int timo, pad; 642 643 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 644 return; 645 646 again: 647 /* 648 * Peek at the next packet. 649 */ 650 IFQ_POLL(&ifp->if_snd, m); 651 if (m == NULL) 652 return; 653 654 /* 655 * Compute the frame length and set pad to give an overall even 656 * number of bytes. Below, we assume that the packet length 657 * is even. 658 */ 659 for (len = 0; m != NULL; m = m->m_next) 660 len += m->m_len; 661 pad = (len & 1); 662 663 /* 664 * We drop packets that are too large. Perhaps we should 665 * truncate them instead? 666 */ 667 if ((len + pad) > (ETHER_MAX_LEN - ETHER_CRC_LEN)) { 668 printf("%s: large packet discarded\n", sc->sc_dev.dv_xname); 669 ifp->if_oerrors++; 670 IFQ_DEQUEUE(&ifp->if_snd, m); 671 m_freem(m); 672 goto readcheck; 673 } 674 675 #ifdef SMC91CXX_SW_PAD 676 /* 677 * Not using hardware padding; pad to ETHER_MIN_LEN. 678 */ 679 if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 680 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 681 #endif 682 683 length = pad + len; 684 685 /* 686 * The MMU has a 256 byte page size. The MMU expects us to 687 * ask for "npages - 1". We include space for the status word, 688 * byte count, and control bytes in the allocation request. 689 */ 690 npages = (length + 6) >> 8; 691 692 /* 693 * Now allocate the memory. 694 */ 695 SMC_SELECT_BANK(sc, 2); 696 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ALLOC | npages); 697 698 timo = MEMORY_WAIT_TIME; 699 do { 700 if (bus_space_read_1(bst, bsh, INTR_STAT_REG_B) & IM_ALLOC_INT) 701 break; 702 delay(1); 703 } while (--timo); 704 705 packetno = bus_space_read_1(bst, bsh, ALLOC_RESULT_REG_B); 706 707 if (packetno & ARR_FAILED || timo == 0) { 708 /* 709 * No transmit memory is available. Record the number 710 * of requestd pages and enable the allocation completion 711 * interrupt. Set up the watchdog timer in case we miss 712 * the interrupt. Mark the interface as active so that 713 * no one else attempts to transmit while we're allocating 714 * memory. 715 */ 716 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 717 bus_space_read_1(bst, bsh, INTR_MASK_REG_B) | IM_ALLOC_INT); 718 719 ifp->if_timer = 5; 720 ifp->if_flags |= IFF_OACTIVE; 721 722 return; 723 } 724 725 /* 726 * We have a packet number - set the data window. 727 */ 728 bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno); 729 730 /* 731 * Point to the beginning of the packet. 732 */ 733 bus_space_write_2(bst, bsh, POINTER_REG_W, PTR_AUTOINC /* | 0x0000 */); 734 735 /* 736 * Send the packet length (+6 for stats, length, and control bytes) 737 * and the status word (set to zeros). 738 */ 739 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 740 bus_space_write_2(bst, bsh, DATA_REG_W, (length + 6) & 0x7ff); 741 742 /* 743 * Get the packet from the kernel. This will include the Ethernet 744 * frame header, MAC address, etc. 745 */ 746 IFQ_DEQUEUE(&ifp->if_snd, m); 747 748 /* 749 * Push the packet out to the card. 750 */ 751 smc91cxx_copy_tx_frame(sc, m); 752 753 #ifdef SMC91CXX_SW_PAD 754 /* 755 * Push out padding. 756 */ 757 while (pad > 1) { 758 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 759 pad -= 2; 760 } 761 if (pad) 762 bus_space_write_1(bst, bsh, DATA_REG_B, 0); 763 #endif 764 765 /* 766 * Push out control byte and unused packet byte. The control byte 767 * is 0, meaning the packet is even lengthed and no special 768 * CRC handling is necessary. 769 */ 770 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 771 772 /* 773 * Enable transmit interrupts and let the chip go. Set a watchdog 774 * in case we miss the interrupt. 775 */ 776 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 777 bus_space_read_1(bst, bsh, INTR_MASK_REG_B) | 778 IM_TX_INT | IM_TX_EMPTY_INT); 779 780 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ENQUEUE); 781 782 ifp->if_timer = 5; 783 784 #if NBPFILTER > 0 785 /* Hand off a copy to the bpf. */ 786 if (ifp->if_bpf) 787 bpf_mtap(ifp->if_bpf, m); 788 #endif 789 790 ifp->if_opackets++; 791 m_freem(m); 792 793 readcheck: 794 /* 795 * Check for incoming pcakets. We don't want to overflow the small 796 * RX FIFO. If nothing has arrived, attempt to queue another 797 * transmit packet. 798 */ 799 if (bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & FIFO_REMPTY) 800 goto again; 801 } 802 803 /* 804 * Squirt a (possibly misaligned) mbuf to the device 805 */ 806 void 807 smc91cxx_copy_tx_frame(sc, m0) 808 struct smc91cxx_softc *sc; 809 struct mbuf *m0; 810 { 811 bus_space_tag_t bst = sc->sc_bst; 812 bus_space_handle_t bsh = sc->sc_bsh; 813 struct mbuf *m; 814 int len, leftover; 815 u_int16_t dbuf; 816 u_int8_t *p; 817 #ifdef DIAGNOSTIC 818 u_int8_t *lim; 819 #endif 820 821 /* start out with no leftover data */ 822 leftover = 0; 823 dbuf = 0; 824 825 /* Process the chain of mbufs */ 826 for (m = m0; m != NULL; m = m->m_next) { 827 /* 828 * Process all of the data in a single mbuf. 829 */ 830 p = mtod(m, u_int8_t *); 831 len = m->m_len; 832 #ifdef DIAGNOSTIC 833 lim = p + len; 834 #endif 835 836 while (len > 0) { 837 if (leftover) { 838 /* 839 * Data left over (from mbuf or realignment). 840 * Buffer the next byte, and write it and 841 * the leftover data out. 842 */ 843 dbuf |= *p++ << 8; 844 len--; 845 bus_space_write_2(bst, bsh, DATA_REG_W, dbuf); 846 leftover = 0; 847 } else if ((long) p & 1) { 848 /* 849 * Misaligned data. Buffer the next byte. 850 */ 851 dbuf = *p++; 852 len--; 853 leftover = 1; 854 } else { 855 /* 856 * Aligned data. This is the case we like. 857 * 858 * Write-region out as much as we can, then 859 * buffer the remaining byte (if any). 860 */ 861 leftover = len & 1; 862 len &= ~1; 863 bus_space_write_multi_stream_2(bst, bsh, 864 DATA_REG_W, (u_int16_t *)p, len >> 1); 865 p += len; 866 867 if (leftover) 868 dbuf = *p++; 869 len = 0; 870 } 871 } 872 if (len < 0) 873 panic("smc91cxx_copy_tx_frame: negative len"); 874 #ifdef DIAGNOSTIC 875 if (p != lim) 876 panic("smc91cxx_copy_tx_frame: p != lim"); 877 #endif 878 } 879 if (leftover) 880 bus_space_write_1(bst, bsh, DATA_REG_B, dbuf); 881 } 882 883 /* 884 * Interrupt service routine. 885 */ 886 int 887 smc91cxx_intr(arg) 888 void *arg; 889 { 890 struct smc91cxx_softc *sc = arg; 891 struct ifnet *ifp = &sc->sc_ec.ec_if; 892 bus_space_tag_t bst = sc->sc_bst; 893 bus_space_handle_t bsh = sc->sc_bsh; 894 u_int8_t mask, interrupts, status; 895 u_int16_t packetno, tx_status, card_stats; 896 897 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 || 898 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 899 return (0); 900 901 SMC_SELECT_BANK(sc, 2); 902 903 /* 904 * Obtain the current interrupt mask. 905 */ 906 mask = bus_space_read_1(bst, bsh, INTR_MASK_REG_B); 907 908 /* 909 * Get the set of interrupt which occurred and eliminate any 910 * which are not enabled. 911 */ 912 interrupts = bus_space_read_1(bst, bsh, INTR_STAT_REG_B); 913 status = interrupts & mask; 914 915 /* Ours? */ 916 if (status == 0) 917 return (0); 918 919 /* 920 * It's ours; disable all interrupts while we process them. 921 */ 922 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0); 923 924 /* 925 * Receive overrun interrupts. 926 */ 927 if (status & IM_RX_OVRN_INT) { 928 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, IM_RX_OVRN_INT); 929 ifp->if_ierrors++; 930 } 931 932 /* 933 * Receive interrupts. 934 */ 935 if (status & IM_RCV_INT) { 936 #if 1 /* DIAGNOSTIC */ 937 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 938 if (packetno & FIFO_REMPTY) { 939 printf("%s: receive interrupt on empty fifo\n", 940 sc->sc_dev.dv_xname); 941 goto out; 942 } else 943 #endif 944 smc91cxx_read(sc); 945 } 946 947 /* 948 * Memory allocation interrupts. 949 */ 950 if (status & IM_ALLOC_INT) { 951 /* Disable this interrupt. */ 952 mask &= ~IM_ALLOC_INT; 953 954 /* 955 * Release the just-allocated memory. We will reallocate 956 * it through the normal start logic. 957 */ 958 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 959 /* XXX bound this loop! */ ; 960 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT); 961 962 ifp->if_flags &= ~IFF_OACTIVE; 963 ifp->if_timer = 0; 964 } 965 966 /* 967 * Transmit complete interrupt. Handle transmission error messages. 968 * This will only be called on error condition because of AUTO RELEASE 969 * mode. 970 */ 971 if (status & IM_TX_INT) { 972 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, IM_TX_INT); 973 974 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & 975 FIFO_TX_MASK; 976 977 /* 978 * Select this as the packet to read from. 979 */ 980 bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno); 981 982 /* 983 * Position the pointer to the beginning of the packet. 984 */ 985 bus_space_write_2(bst, bsh, POINTER_REG_W, 986 PTR_AUTOINC | PTR_READ /* | 0x0000 */); 987 988 /* 989 * Fetch the TX status word. This will be a copy of 990 * the EPH_STATUS_REG_W at the time of the transmission 991 * failure. 992 */ 993 tx_status = bus_space_read_2(bst, bsh, DATA_REG_W); 994 995 if (tx_status & EPHSR_TX_SUC) 996 printf("%s: successful packet caused TX interrupt?!\n", 997 sc->sc_dev.dv_xname); 998 else 999 ifp->if_oerrors++; 1000 1001 if (tx_status & EPHSR_LATCOL) 1002 ifp->if_collisions++; 1003 1004 /* 1005 * Some of these errors disable the transmitter; reenable it. 1006 */ 1007 SMC_SELECT_BANK(sc, 0); 1008 #ifdef SMC91CXX_SW_PAD 1009 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, TCR_ENABLE); 1010 #else 1011 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 1012 TCR_ENABLE | TCR_PAD_ENABLE); 1013 #endif 1014 1015 /* 1016 * Kill the failed packet and wait for the MMU to unbusy. 1017 */ 1018 SMC_SELECT_BANK(sc, 2); 1019 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 1020 /* XXX bound this loop! */ ; 1021 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT); 1022 1023 ifp->if_timer = 0; 1024 } 1025 1026 /* 1027 * Transmit underrun interrupts. We use this opportunity to 1028 * update transmit statistics from the card. 1029 */ 1030 if (status & IM_TX_EMPTY_INT) { 1031 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, IM_TX_EMPTY_INT); 1032 1033 /* Disable this interrupt. */ 1034 mask &= ~IM_TX_EMPTY_INT; 1035 1036 SMC_SELECT_BANK(sc, 0); 1037 card_stats = bus_space_read_2(bst, bsh, COUNTER_REG_W); 1038 1039 /* Single collisions. */ 1040 ifp->if_collisions += card_stats & ECR_COLN_MASK; 1041 1042 /* Multiple collisions. */ 1043 ifp->if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4; 1044 1045 SMC_SELECT_BANK(sc, 2); 1046 1047 ifp->if_timer = 0; 1048 } 1049 1050 if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy && 1051 (status & IM_MD_INT)) { 1052 /* 1053 * Internal PHY status change 1054 */ 1055 mii_tick(&sc->sc_mii); 1056 } 1057 1058 /* 1059 * Other errors. Reset the interface. 1060 */ 1061 if (status & IM_EPH_INT) { 1062 smc91cxx_stop(sc); 1063 smc91cxx_init(sc); 1064 } 1065 1066 /* 1067 * Attempt to queue more packets for transmission. 1068 */ 1069 smc91cxx_start(ifp); 1070 1071 out: 1072 /* 1073 * Reenable the interrupts we wish to receive now that processing 1074 * is complete. 1075 */ 1076 mask |= bus_space_read_1(bst, bsh, INTR_MASK_REG_B); 1077 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, mask); 1078 1079 #if NRND > 0 1080 if (status) 1081 rnd_add_uint32(&sc->rnd_source, status); 1082 #endif 1083 1084 return (1); 1085 } 1086 1087 /* 1088 * Read a packet from the card and pass it up to the kernel. 1089 * NOTE! WE EXPECT TO BE IN REGISTER WINDOW 2! 1090 */ 1091 void 1092 smc91cxx_read(sc) 1093 struct smc91cxx_softc *sc; 1094 { 1095 struct ifnet *ifp = &sc->sc_ec.ec_if; 1096 bus_space_tag_t bst = sc->sc_bst; 1097 bus_space_handle_t bsh = sc->sc_bsh; 1098 struct ether_header *eh; 1099 struct mbuf *m; 1100 u_int16_t status, packetno, packetlen; 1101 u_int8_t *data; 1102 u_int32_t dr; 1103 1104 again: 1105 /* 1106 * Set data pointer to the beginning of the packet. Since 1107 * PTR_RCV is set, the packet number will be found automatically 1108 * in FIFO_PORTS_REG_W, FIFO_RX_MASK. 1109 */ 1110 bus_space_write_2(bst, bsh, POINTER_REG_W, 1111 PTR_READ | PTR_RCV | PTR_AUTOINC /* | 0x0000 */); 1112 1113 /* 1114 * First two words are status and packet length. 1115 */ 1116 if ((sc->sc_flags & SMC_FLAGS_32BIT_READ) == 0) { 1117 status = bus_space_read_2(bst, bsh, DATA_REG_W); 1118 packetlen = bus_space_read_2(bst, bsh, DATA_REG_W); 1119 } else { 1120 dr = bus_space_read_4(bst, bsh, DATA_REG_W); 1121 #if BYTE_ORDER == LITTLE_ENDIAN 1122 status = (u_int16_t)dr; 1123 packetlen = (u_int16_t)(dr >> 16); 1124 #else 1125 packetlen = (u_int16_t)dr; 1126 status = (u_int16_t)(dr >> 16); 1127 #endif 1128 } 1129 1130 packetlen &= RLEN_MASK; 1131 1132 /* 1133 * The packet length includes 3 extra words: status, length, 1134 * and an extra word that includes the control byte. 1135 */ 1136 packetlen -= 6; 1137 1138 /* 1139 * Account for receive errors and discard. 1140 */ 1141 if (status & RS_ERRORS) { 1142 ifp->if_ierrors++; 1143 goto out; 1144 } 1145 1146 /* 1147 * Adjust for odd-length packet. 1148 */ 1149 if (status & RS_ODDFRAME) 1150 packetlen++; 1151 1152 /* 1153 * Allocate a header mbuf. 1154 */ 1155 MGETHDR(m, M_DONTWAIT, MT_DATA); 1156 if (m == NULL) 1157 goto out; 1158 m->m_pkthdr.rcvif = ifp; 1159 m->m_pkthdr.len = packetlen; 1160 1161 /* 1162 * Always put the packet in a cluster. 1163 * XXX should chain small mbufs if less than threshold. 1164 */ 1165 MCLGET(m, M_DONTWAIT); 1166 if ((m->m_flags & M_EXT) == 0) { 1167 m_freem(m); 1168 ifp->if_ierrors++; 1169 printf("%s: can't allocate cluster for incoming packet\n", 1170 sc->sc_dev.dv_xname); 1171 goto out; 1172 } 1173 1174 /* 1175 * Pull the packet off the interface. Make sure the payload 1176 * is aligned. 1177 */ 1178 if ((sc->sc_flags & SMC_FLAGS_32BIT_READ) == 0) { 1179 m->m_data = (caddr_t) ALIGN(mtod(m, caddr_t) + 1180 sizeof(struct ether_header)) - sizeof(struct ether_header); 1181 1182 eh = mtod(m, struct ether_header *); 1183 data = mtod(m, u_int8_t *); 1184 if (packetlen > 1) 1185 bus_space_read_multi_stream_2(bst, bsh, DATA_REG_W, 1186 (u_int16_t *)data, packetlen >> 1); 1187 if (packetlen & 1) { 1188 data += packetlen & ~1; 1189 *data = bus_space_read_1(bst, bsh, DATA_REG_B); 1190 } 1191 } else { 1192 u_int8_t *dp; 1193 1194 m->m_data = (caddr_t) ALIGN(mtod(m, caddr_t)); 1195 eh = mtod(m, struct ether_header *); 1196 dp = data = mtod(m, u_int8_t *); 1197 if (packetlen > 3) 1198 bus_space_read_multi_stream_4(bst, bsh, DATA_REG_W, 1199 (u_int32_t *)data, packetlen >> 2); 1200 if (packetlen & 3) { 1201 data += packetlen & ~3; 1202 *((u_int32_t *)data) = 1203 bus_space_read_stream_4(bst, bsh, DATA_REG_W); 1204 } 1205 } 1206 1207 ifp->if_ipackets++; 1208 1209 /* 1210 * Make sure to behave as IFF_SIMPLEX in all cases. 1211 * This is to cope with SMC91C92 (Megahertz XJ10BT), which 1212 * loops back packets to itself on promiscuous mode. 1213 * (should be ensured by chipset configuration) 1214 */ 1215 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1216 /* 1217 * Drop packet looped back from myself. 1218 */ 1219 if (ether_cmp(eh->ether_shost, LLADDR(ifp->if_sadl)) == 0) { 1220 m_freem(m); 1221 goto out; 1222 } 1223 } 1224 1225 m->m_pkthdr.len = m->m_len = packetlen; 1226 1227 #if NBPFILTER > 0 1228 /* 1229 * Hand the packet off to bpf listeners. 1230 */ 1231 if (ifp->if_bpf) 1232 bpf_mtap(ifp->if_bpf, m); 1233 #endif 1234 1235 (*ifp->if_input)(ifp, m); 1236 1237 out: 1238 /* 1239 * Tell the card to free the memory occupied by this packet. 1240 */ 1241 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 1242 /* XXX bound this loop! */ ; 1243 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RELEASE); 1244 1245 /* 1246 * Check for another packet. 1247 */ 1248 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 1249 if (packetno & FIFO_REMPTY) 1250 return; 1251 goto again; 1252 } 1253 1254 /* 1255 * Process an ioctl request. 1256 */ 1257 int 1258 smc91cxx_ioctl(ifp, cmd, data) 1259 struct ifnet *ifp; 1260 u_long cmd; 1261 caddr_t data; 1262 { 1263 struct smc91cxx_softc *sc = ifp->if_softc; 1264 struct ifaddr *ifa = (struct ifaddr *)data; 1265 struct ifreq *ifr = (struct ifreq *)data; 1266 int s, error = 0; 1267 1268 s = splnet(); 1269 1270 switch (cmd) { 1271 case SIOCSIFADDR: 1272 if ((error = smc91cxx_enable(sc)) != 0) 1273 break; 1274 ifp->if_flags |= IFF_UP; 1275 switch (ifa->ifa_addr->sa_family) { 1276 #ifdef INET 1277 case AF_INET: 1278 smc91cxx_init(sc); 1279 arp_ifinit(ifp, ifa); 1280 break; 1281 #endif 1282 #ifdef NS 1283 case AF_NS: 1284 { 1285 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1286 1287 if (ns_nullhost(*ina)) 1288 ina->x_host = 1289 *(union ns_host *)LLADDR(ifp->if_sadl); 1290 else { 1291 memcpy(LLADDR(ifp->if_sadl), ina->x_host.c_host, 1292 ETHER_ADDR_LEN); 1293 } 1294 1295 /* 1296 * Set new address. Reset, because the receiver 1297 * has to be stopped before we can set the new 1298 * MAC address. 1299 */ 1300 smc91cxx_reset(sc); 1301 break; 1302 } 1303 #endif 1304 default: 1305 smc91cxx_init(sc); 1306 break; 1307 } 1308 break; 1309 1310 #if defined(CCITT) && defined(LLC) 1311 case SIOCSIFCONF_X25: 1312 if ((error = smc91cxx_enable(sc)) != 0) 1313 break; 1314 ifp->if_flags |= IFF_UP; 1315 ifa->ifa_rtrequest = cons_rtrequest; /* XXX */ 1316 error = x25_llcglue(PRC_IFUP, ifa->ifa_addr); 1317 if (error == 0) 1318 smc91cxx_init(sc); 1319 break; 1320 #endif 1321 1322 case SIOCSIFFLAGS: 1323 if ((ifp->if_flags & IFF_UP) == 0 && 1324 (ifp->if_flags & IFF_RUNNING) != 0) { 1325 /* 1326 * If interface is marked down and it is running, 1327 * stop it. 1328 */ 1329 smc91cxx_stop(sc); 1330 ifp->if_flags &= ~IFF_RUNNING; 1331 smc91cxx_disable(sc); 1332 } else if ((ifp->if_flags & IFF_UP) != 0 && 1333 (ifp->if_flags & IFF_RUNNING) == 0) { 1334 /* 1335 * If interface is marked up and it is stopped, 1336 * start it. 1337 */ 1338 if ((error = smc91cxx_enable(sc)) != 0) 1339 break; 1340 smc91cxx_init(sc); 1341 } else if ((ifp->if_flags & IFF_UP) != 0) { 1342 /* 1343 * Reset the interface to pick up changes in any 1344 * other flags that affect hardware registers. 1345 */ 1346 smc91cxx_reset(sc); 1347 } 1348 break; 1349 1350 case SIOCADDMULTI: 1351 case SIOCDELMULTI: 1352 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) { 1353 error = EIO; 1354 break; 1355 } 1356 1357 error = (cmd == SIOCADDMULTI) ? 1358 ether_addmulti(ifr, &sc->sc_ec) : 1359 ether_delmulti(ifr, &sc->sc_ec); 1360 if (error == ENETRESET) { 1361 /* 1362 * Multicast list has changed; set the hardware 1363 * filter accordingly. 1364 */ 1365 if (ifp->if_flags & IFF_RUNNING) 1366 smc91cxx_reset(sc); 1367 error = 0; 1368 } 1369 break; 1370 1371 case SIOCGIFMEDIA: 1372 case SIOCSIFMEDIA: 1373 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1374 break; 1375 1376 default: 1377 error = EINVAL; 1378 break; 1379 } 1380 1381 splx(s); 1382 return (error); 1383 } 1384 1385 /* 1386 * Reset the interface. 1387 */ 1388 void 1389 smc91cxx_reset(sc) 1390 struct smc91cxx_softc *sc; 1391 { 1392 int s; 1393 1394 s = splnet(); 1395 smc91cxx_stop(sc); 1396 smc91cxx_init(sc); 1397 splx(s); 1398 } 1399 1400 /* 1401 * Watchdog timer. 1402 */ 1403 void 1404 smc91cxx_watchdog(ifp) 1405 struct ifnet *ifp; 1406 { 1407 struct smc91cxx_softc *sc = ifp->if_softc; 1408 1409 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1410 ifp->if_oerrors++; 1411 smc91cxx_reset(sc); 1412 } 1413 1414 /* 1415 * Stop output on the interface. 1416 */ 1417 void 1418 smc91cxx_stop(sc) 1419 struct smc91cxx_softc *sc; 1420 { 1421 bus_space_tag_t bst = sc->sc_bst; 1422 bus_space_handle_t bsh = sc->sc_bsh; 1423 1424 /* 1425 * Clear interrupt mask; disable all interrupts. 1426 */ 1427 SMC_SELECT_BANK(sc, 2); 1428 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0); 1429 1430 /* 1431 * Disable transmitter and receiver. 1432 */ 1433 SMC_SELECT_BANK(sc, 0); 1434 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); 1435 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); 1436 1437 /* 1438 * Cancel watchdog timer. 1439 */ 1440 sc->sc_ec.ec_if.if_timer = 0; 1441 } 1442 1443 /* 1444 * Enable power on the interface. 1445 */ 1446 int 1447 smc91cxx_enable(sc) 1448 struct smc91cxx_softc *sc; 1449 { 1450 1451 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 && sc->sc_enable != NULL) { 1452 if ((*sc->sc_enable)(sc) != 0) { 1453 printf("%s: device enable failed\n", 1454 sc->sc_dev.dv_xname); 1455 return (EIO); 1456 } 1457 } 1458 1459 sc->sc_flags |= SMC_FLAGS_ENABLED; 1460 return (0); 1461 } 1462 1463 /* 1464 * Disable power on the interface. 1465 */ 1466 void 1467 smc91cxx_disable(sc) 1468 struct smc91cxx_softc *sc; 1469 { 1470 1471 if ((sc->sc_flags & SMC_FLAGS_ENABLED) != 0 && sc->sc_disable != NULL) { 1472 (*sc->sc_disable)(sc); 1473 sc->sc_flags &= ~SMC_FLAGS_ENABLED; 1474 } 1475 } 1476 1477 int 1478 smc91cxx_activate(self, act) 1479 struct device *self; 1480 enum devact act; 1481 { 1482 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1483 int rv = 0, s; 1484 1485 s = splnet(); 1486 switch (act) { 1487 case DVACT_ACTIVATE: 1488 rv = EOPNOTSUPP; 1489 break; 1490 1491 case DVACT_DEACTIVATE: 1492 if_deactivate(&sc->sc_ec.ec_if); 1493 break; 1494 } 1495 splx(s); 1496 return (rv); 1497 } 1498 1499 int 1500 smc91cxx_detach(self, flags) 1501 struct device *self; 1502 int flags; 1503 { 1504 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1505 struct ifnet *ifp = &sc->sc_ec.ec_if; 1506 1507 /* Succeed now if there's no work to do. */ 1508 if ((sc->sc_flags & SMC_FLAGS_ATTACHED) == 0) 1509 return (0); 1510 1511 1512 /* smc91cxx_disable() checks SMC_FLAGS_ENABLED */ 1513 smc91cxx_disable(sc); 1514 1515 /* smc91cxx_attach() never fails */ 1516 1517 /* Delete all media. */ 1518 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1519 1520 #if NRND > 0 1521 rnd_detach_source(&sc->rnd_source); 1522 #endif 1523 ether_ifdetach(ifp); 1524 if_detach(ifp); 1525 1526 return (0); 1527 } 1528 1529 u_int32_t 1530 smc91cxx_mii_bitbang_read(self) 1531 struct device *self; 1532 { 1533 struct smc91cxx_softc *sc = (void *) self; 1534 1535 /* We're already in bank 3. */ 1536 return (bus_space_read_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W)); 1537 } 1538 1539 void 1540 smc91cxx_mii_bitbang_write(self, val) 1541 struct device *self; 1542 u_int32_t val; 1543 { 1544 struct smc91cxx_softc *sc = (void *) self; 1545 1546 /* We're already in bank 3. */ 1547 bus_space_write_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W, val); 1548 } 1549 1550 int 1551 smc91cxx_mii_readreg(self, phy, reg) 1552 struct device *self; 1553 int phy, reg; 1554 { 1555 struct smc91cxx_softc *sc = (void *) self; 1556 int val; 1557 1558 SMC_SELECT_BANK(sc, 3); 1559 1560 val = mii_bitbang_readreg(self, &smc91cxx_mii_bitbang_ops, phy, reg); 1561 1562 SMC_SELECT_BANK(sc, 2); 1563 1564 return (val); 1565 } 1566 1567 void 1568 smc91cxx_mii_writereg(self, phy, reg, val) 1569 struct device *self; 1570 int phy, reg, val; 1571 { 1572 struct smc91cxx_softc *sc = (void *) self; 1573 1574 SMC_SELECT_BANK(sc, 3); 1575 1576 mii_bitbang_writereg(self, &smc91cxx_mii_bitbang_ops, phy, reg, val); 1577 1578 SMC_SELECT_BANK(sc, 2); 1579 } 1580 1581 void 1582 smc91cxx_statchg(self) 1583 struct device *self; 1584 { 1585 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1586 bus_space_tag_t bst = sc->sc_bst; 1587 bus_space_handle_t bsh = sc->sc_bsh; 1588 int mctl; 1589 1590 SMC_SELECT_BANK(sc, 0); 1591 mctl = bus_space_read_2(bst, bsh, TXMIT_CONTROL_REG_W); 1592 if (sc->sc_mii.mii_media_active & IFM_FDX) 1593 mctl |= TCR_SWFDUP; 1594 else 1595 mctl &= ~TCR_SWFDUP; 1596 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, mctl); 1597 SMC_SELECT_BANK(sc, 2); /* back to operating window */ 1598 } 1599 1600 /* 1601 * One second timer, used to tick the MII. 1602 */ 1603 void 1604 smc91cxx_tick(arg) 1605 void *arg; 1606 { 1607 struct smc91cxx_softc *sc = arg; 1608 int s; 1609 1610 #ifdef DIAGNOSTIC 1611 if ((sc->sc_flags & SMC_FLAGS_HAS_MII) == 0) 1612 panic("smc91cxx_tick"); 1613 #endif 1614 1615 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1616 return; 1617 1618 s = splnet(); 1619 mii_tick(&sc->sc_mii); 1620 splx(s); 1621 1622 callout_reset(&sc->sc_mii_callout, hz, smc91cxx_tick, sc); 1623 } 1624 1625