1 /* $NetBSD: smc91cxx.c,v 1.37 2001/11/13 13:14:44 lukem Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com> 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Gardner Buchanan. 55 * 4. The name of Gardner Buchanan may not be used to endorse or promote 56 * products derived from this software without specific prior written 57 * permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 60 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 61 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 63 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 64 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 65 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 66 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 67 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 68 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 69 * 70 * from FreeBSD Id: if_sn.c,v 1.4 1996/03/18 15:47:16 gardner Exp 71 */ 72 73 /* 74 * Core driver for the SMC 91Cxx family of Ethernet chips. 75 * 76 * Memory allocation interrupt logic is drived from an SMC 91C90 driver 77 * written for NetBSD/amiga by Michael Hitch. 78 */ 79 80 #include <sys/cdefs.h> 81 __KERNEL_RCSID(0, "$NetBSD: smc91cxx.c,v 1.37 2001/11/13 13:14:44 lukem Exp $"); 82 83 #include "opt_inet.h" 84 #include "opt_ccitt.h" 85 #include "opt_llc.h" 86 #include "opt_ns.h" 87 #include "bpfilter.h" 88 #include "rnd.h" 89 90 #include <sys/param.h> 91 #include <sys/systm.h> 92 #include <sys/mbuf.h> 93 #include <sys/syslog.h> 94 #include <sys/socket.h> 95 #include <sys/device.h> 96 #include <sys/kernel.h> 97 #include <sys/malloc.h> 98 #include <sys/ioctl.h> 99 #include <sys/errno.h> 100 #if NRND > 0 101 #include <sys/rnd.h> 102 #endif 103 104 #include <machine/bus.h> 105 #include <machine/intr.h> 106 107 #include <net/if.h> 108 #include <net/if_dl.h> 109 #include <net/if_ether.h> 110 #include <net/if_media.h> 111 112 #ifdef INET 113 #include <netinet/in.h> 114 #include <netinet/if_inarp.h> 115 #include <netinet/in_systm.h> 116 #include <netinet/in_var.h> 117 #include <netinet/ip.h> 118 #endif 119 120 #ifdef NS 121 #include <netns/ns.h> 122 #include <netns/ns_if.h> 123 #endif 124 125 #if defined(CCITT) && defined(LLC) 126 #include <sys/socketvar.h> 127 #include <netccitt/x25.h> 128 #include <netccitt/pk.h> 129 #include <netccitt/pk_var.h> 130 #include <netccitt/pk_extern.h> 131 #endif 132 133 #if NBPFILTER > 0 134 #include <net/bpf.h> 135 #include <net/bpfdesc.h> 136 #endif 137 138 #include <dev/mii/mii.h> 139 #include <dev/mii/miivar.h> 140 #include <dev/mii/mii_bitbang.h> 141 142 #include <dev/ic/smc91cxxreg.h> 143 #include <dev/ic/smc91cxxvar.h> 144 145 /* XXX Hardware padding doesn't work yet(?) */ 146 #define SMC91CXX_SW_PAD 147 148 const char *smc91cxx_idstrs[] = { 149 NULL, /* 0 */ 150 NULL, /* 1 */ 151 NULL, /* 2 */ 152 "SMC91C90/91C92", /* 3 */ 153 "SMC91C94", /* 4 */ 154 "SMC91C95", /* 5 */ 155 NULL, /* 6 */ 156 "SMC91C100", /* 7 */ 157 "SMC91C100FD", /* 8 */ 158 NULL, /* 9 */ 159 NULL, /* 10 */ 160 NULL, /* 11 */ 161 NULL, /* 12 */ 162 NULL, /* 13 */ 163 NULL, /* 14 */ 164 NULL, /* 15 */ 165 }; 166 167 /* Supported media types. */ 168 const int smc91cxx_media[] = { 169 IFM_ETHER|IFM_10_T, 170 IFM_ETHER|IFM_10_5, 171 }; 172 #define NSMC91CxxMEDIA (sizeof(smc91cxx_media) / sizeof(smc91cxx_media[0])) 173 174 /* 175 * MII bit-bang glue. 176 */ 177 u_int32_t smc91cxx_mii_bitbang_read __P((struct device *)); 178 void smc91cxx_mii_bitbang_write __P((struct device *, u_int32_t)); 179 180 const struct mii_bitbang_ops smc91cxx_mii_bitbang_ops = { 181 smc91cxx_mii_bitbang_read, 182 smc91cxx_mii_bitbang_write, 183 { 184 MR_MDO, /* MII_BIT_MDO */ 185 MR_MDI, /* MII_BIT_MDI */ 186 MR_MCLK, /* MII_BIT_MDC */ 187 MR_MDOE, /* MII_BIT_DIR_HOST_PHY */ 188 0, /* MII_BIT_DIR_PHY_HOST */ 189 } 190 }; 191 192 /* MII callbacks */ 193 int smc91cxx_mii_readreg __P((struct device *, int, int)); 194 void smc91cxx_mii_writereg __P((struct device *, int, int, int)); 195 void smc91cxx_statchg __P((struct device *)); 196 void smc91cxx_tick __P((void *)); 197 198 int smc91cxx_mediachange __P((struct ifnet *)); 199 void smc91cxx_mediastatus __P((struct ifnet *, struct ifmediareq *)); 200 201 int smc91cxx_set_media __P((struct smc91cxx_softc *, int)); 202 203 void smc91cxx_init __P((struct smc91cxx_softc *)); 204 void smc91cxx_read __P((struct smc91cxx_softc *)); 205 void smc91cxx_reset __P((struct smc91cxx_softc *)); 206 void smc91cxx_start __P((struct ifnet *)); 207 void smc91cxx_resume __P((struct smc91cxx_softc *)); 208 void smc91cxx_stop __P((struct smc91cxx_softc *)); 209 void smc91cxx_watchdog __P((struct ifnet *)); 210 int smc91cxx_ioctl __P((struct ifnet *, u_long, caddr_t)); 211 212 static __inline int ether_cmp __P((void *, void *)); 213 static __inline int 214 ether_cmp(va, vb) 215 void *va, *vb; 216 { 217 u_int8_t *a = va; 218 u_int8_t *b = vb; 219 220 return ((a[5] != b[5]) || (a[4] != b[4]) || (a[3] != b[3]) || 221 (a[2] != b[2]) || (a[1] != b[1]) || (a[0] != b[0])); 222 } 223 224 void 225 smc91cxx_attach(sc, myea) 226 struct smc91cxx_softc *sc; 227 u_int8_t *myea; 228 { 229 struct ifnet *ifp = &sc->sc_ec.ec_if; 230 bus_space_tag_t bst = sc->sc_bst; 231 bus_space_handle_t bsh = sc->sc_bsh; 232 struct ifmedia *ifm = &sc->sc_mii.mii_media; 233 const char *idstr; 234 u_int32_t miicapabilities; 235 u_int16_t tmp; 236 u_int8_t enaddr[ETHER_ADDR_LEN]; 237 int i, aui, mult, memsize; 238 char pbuf[9]; 239 240 /* Make sure the chip is stopped. */ 241 smc91cxx_stop(sc); 242 243 SMC_SELECT_BANK(sc, 3); 244 tmp = bus_space_read_2(bst, bsh, REVISION_REG_W); 245 sc->sc_chipid = RR_ID(tmp); 246 /* check magic number */ 247 if ((tmp & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 248 idstr = NULL; 249 printf("%s: invalid BSR 0x%04x\n", sc->sc_dev.dv_xname, tmp); 250 } else 251 idstr = smc91cxx_idstrs[sc->sc_chipid]; 252 printf("%s: ", sc->sc_dev.dv_xname); 253 if (idstr != NULL) 254 printf("%s, ", idstr); 255 else 256 printf("unknown chip id %d, ", sc->sc_chipid); 257 printf("revision %d, ", RR_REV(tmp)); 258 259 SMC_SELECT_BANK(sc, 0); 260 mult = MCR_MEM_MULT(bus_space_read_2(bst, bsh, MEM_CFG_REG_W)); 261 memsize = bus_space_read_2(bst, bsh, MEM_INFO_REG_W) & MIR_TOTAL_MASK; 262 if (memsize == 255) memsize++; 263 memsize *= 256 * mult; 264 265 format_bytes(pbuf, sizeof(pbuf), memsize); 266 printf("buffer size: %s\n", pbuf); 267 268 /* Read the station address from the chip. */ 269 SMC_SELECT_BANK(sc, 1); 270 if (myea == NULL) { 271 myea = enaddr; 272 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 273 tmp = bus_space_read_2(bst, bsh, IAR_ADDR0_REG_W + i); 274 myea[i + 1] = (tmp >> 8) & 0xff; 275 myea[i] = tmp & 0xff; 276 } 277 } 278 printf("%s: MAC address %s, ", sc->sc_dev.dv_xname, 279 ether_sprintf(myea)); 280 281 /* Initialize the ifnet structure. */ 282 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 283 ifp->if_softc = sc; 284 ifp->if_start = smc91cxx_start; 285 ifp->if_ioctl = smc91cxx_ioctl; 286 ifp->if_watchdog = smc91cxx_watchdog; 287 ifp->if_flags = 288 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 289 IFQ_SET_READY(&ifp->if_snd); 290 291 /* Attach the interface. */ 292 if_attach(ifp); 293 ether_ifattach(ifp, myea); 294 295 /* 296 * Initialize our media structures and MII info. We will 297 * probe the MII if we are on the SMC91Cxx 298 */ 299 sc->sc_mii.mii_ifp = ifp; 300 sc->sc_mii.mii_readreg = smc91cxx_mii_readreg; 301 sc->sc_mii.mii_writereg = smc91cxx_mii_writereg; 302 sc->sc_mii.mii_statchg = smc91cxx_statchg; 303 ifmedia_init(ifm, 0, smc91cxx_mediachange, smc91cxx_mediastatus); 304 305 SMC_SELECT_BANK(sc, 1); 306 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 307 308 miicapabilities = BMSR_MEDIAMASK|BMSR_ANEG; 309 switch (sc->sc_chipid) { 310 case CHIP_91100: 311 /* 312 * The 91100 does not have full-duplex capabilities, 313 * even if the PHY does. 314 */ 315 miicapabilities &= ~(BMSR_100TXFDX | BMSR_10TFDX); 316 case CHIP_91100FD: 317 if (tmp & CR_MII_SELECT) { 318 printf("default media MII\n"); 319 mii_attach(&sc->sc_dev, &sc->sc_mii, miicapabilities, 320 MII_PHY_ANY, MII_OFFSET_ANY, 0); 321 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 322 ifmedia_add(&sc->sc_mii.mii_media, 323 IFM_ETHER|IFM_NONE, 0, NULL); 324 ifmedia_set(&sc->sc_mii.mii_media, 325 IFM_ETHER|IFM_NONE); 326 } else { 327 ifmedia_set(&sc->sc_mii.mii_media, 328 IFM_ETHER|IFM_AUTO); 329 } 330 sc->sc_flags |= SMC_FLAGS_HAS_MII; 331 break; 332 } 333 /*FALLTHROUGH*/ 334 default: 335 printf("default media %s\n", (aui = (tmp & CR_AUI_SELECT)) ? 336 "AUI" : "UTP"); 337 for (i = 0; i < NSMC91CxxMEDIA; i++) 338 ifmedia_add(ifm, smc91cxx_media[i], 0, NULL); 339 ifmedia_set(ifm, IFM_ETHER | (aui ? IFM_10_5 : IFM_10_T)); 340 break; 341 } 342 343 #if NRND > 0 344 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 345 RND_TYPE_NET, 0); 346 #endif 347 348 /* The attach is successful. */ 349 sc->sc_flags |= SMC_FLAGS_ATTACHED; 350 } 351 352 /* 353 * Change media according to request. 354 */ 355 int 356 smc91cxx_mediachange(ifp) 357 struct ifnet *ifp; 358 { 359 struct smc91cxx_softc *sc = ifp->if_softc; 360 361 return (smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_media)); 362 } 363 364 int 365 smc91cxx_set_media(sc, media) 366 struct smc91cxx_softc *sc; 367 int media; 368 { 369 bus_space_tag_t bst = sc->sc_bst; 370 bus_space_handle_t bsh = sc->sc_bsh; 371 u_int16_t tmp; 372 373 /* 374 * If the interface is not currently powered on, just return. 375 * When it is enabled later, smc91cxx_init() will properly set 376 * up the media for us. 377 */ 378 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) 379 return (0); 380 381 if (IFM_TYPE(media) != IFM_ETHER) 382 return (EINVAL); 383 384 if (sc->sc_flags & SMC_FLAGS_HAS_MII) 385 return (mii_mediachg(&sc->sc_mii)); 386 387 switch (IFM_SUBTYPE(media)) { 388 case IFM_10_T: 389 case IFM_10_5: 390 SMC_SELECT_BANK(sc, 1); 391 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 392 if (IFM_SUBTYPE(media) == IFM_10_5) 393 tmp |= CR_AUI_SELECT; 394 else 395 tmp &= ~CR_AUI_SELECT; 396 bus_space_write_2(bst, bsh, CONFIG_REG_W, tmp); 397 delay(20000); /* XXX is this needed? */ 398 break; 399 400 default: 401 return (EINVAL); 402 } 403 404 return (0); 405 } 406 407 /* 408 * Notify the world which media we're using. 409 */ 410 void 411 smc91cxx_mediastatus(ifp, ifmr) 412 struct ifnet *ifp; 413 struct ifmediareq *ifmr; 414 { 415 struct smc91cxx_softc *sc = ifp->if_softc; 416 bus_space_tag_t bst = sc->sc_bst; 417 bus_space_handle_t bsh = sc->sc_bsh; 418 u_int16_t tmp; 419 420 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) { 421 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 422 ifmr->ifm_status = 0; 423 return; 424 } 425 426 /* 427 * If we have MII, go ask the PHY what's going on. 428 */ 429 if (sc->sc_flags & SMC_FLAGS_HAS_MII) { 430 mii_pollstat(&sc->sc_mii); 431 ifmr->ifm_active = sc->sc_mii.mii_media_active; 432 ifmr->ifm_status = sc->sc_mii.mii_media_status; 433 return; 434 } 435 436 SMC_SELECT_BANK(sc, 1); 437 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 438 ifmr->ifm_active = 439 IFM_ETHER | ((tmp & CR_AUI_SELECT) ? IFM_10_5 : IFM_10_T); 440 } 441 442 /* 443 * Reset and initialize the chip. 444 */ 445 void 446 smc91cxx_init(sc) 447 struct smc91cxx_softc *sc; 448 { 449 struct ifnet *ifp = &sc->sc_ec.ec_if; 450 bus_space_tag_t bst = sc->sc_bst; 451 bus_space_handle_t bsh = sc->sc_bsh; 452 u_int16_t tmp; 453 u_int8_t *enaddr; 454 int s, i; 455 456 s = splnet(); 457 458 /* 459 * This resets the registersmostly to defaults, but doesn't 460 * affect the EEPROM. After the reset cycle, we pause briefly 461 * for the chip to recover. 462 * 463 * XXX how long are we really supposed to delay? --thorpej 464 */ 465 SMC_SELECT_BANK(sc, 0); 466 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, RCR_SOFTRESET); 467 delay(100); 468 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); 469 delay(200); 470 471 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); 472 473 /* Set the Ethernet address. */ 474 SMC_SELECT_BANK(sc, 1); 475 enaddr = (u_int8_t *)LLADDR(ifp->if_sadl); 476 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 477 tmp = enaddr[i + 1] << 8 | enaddr[i]; 478 bus_space_write_2(bst, bsh, IAR_ADDR0_REG_W + i, tmp); 479 } 480 481 /* 482 * Set the control register to automatically release successfully 483 * transmitted packets (making the best use of our limited memory) 484 * and enable the EPH interrupt on certain TX errors. 485 */ 486 bus_space_write_2(bst, bsh, CONTROL_REG_W, (CTR_AUTO_RELEASE | 487 CTR_TE_ENABLE | CTR_CR_ENABLE | CTR_LE_ENABLE)); 488 489 /* 490 * Reset the MMU and wait for it to be un-busy. 491 */ 492 SMC_SELECT_BANK(sc, 2); 493 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RESET); 494 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 495 /* XXX bound this loop! */ ; 496 497 /* 498 * Disable all interrupts. 499 */ 500 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0); 501 502 /* 503 * Set current media. 504 */ 505 smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_cur->ifm_media); 506 507 /* 508 * Set the receive filter. We want receive enable and auto 509 * strip of CRC from received packet. If we are in promisc. mode, 510 * then set that bit as well. 511 * 512 * XXX Initialize multicast filter. For now, we just accept 513 * XXX all multicast. 514 */ 515 SMC_SELECT_BANK(sc, 0); 516 517 tmp = RCR_ENABLE | RCR_STRIP_CRC | RCR_ALMUL; 518 if (ifp->if_flags & IFF_PROMISC) 519 tmp |= RCR_PROMISC; 520 521 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, tmp); 522 523 /* 524 * Set transmitter control to "enabled". 525 */ 526 tmp = TCR_ENABLE; 527 528 #ifndef SMC91CXX_SW_PAD 529 /* 530 * Enable hardware padding of transmitted packets. 531 * XXX doesn't work? 532 */ 533 tmp |= TCR_PAD_ENABLE; 534 #endif 535 536 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, tmp); 537 538 /* 539 * Now, enable interrupts. 540 */ 541 SMC_SELECT_BANK(sc, 2); 542 543 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 544 IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | IM_TX_INT); 545 546 /* Interface is now running, with no output active. */ 547 ifp->if_flags |= IFF_RUNNING; 548 ifp->if_flags &= ~IFF_OACTIVE; 549 550 if (sc->sc_flags & SMC_FLAGS_HAS_MII) { 551 /* Start the one second clock. */ 552 callout_reset(&sc->sc_mii_callout, hz, smc91cxx_tick, sc); 553 } 554 555 /* 556 * Attempt to start any pending transmission. 557 */ 558 smc91cxx_start(ifp); 559 560 splx(s); 561 } 562 563 /* 564 * Start output on an interface. 565 * Must be called at splnet or interrupt level. 566 */ 567 void 568 smc91cxx_start(ifp) 569 struct ifnet *ifp; 570 { 571 struct smc91cxx_softc *sc = ifp->if_softc; 572 bus_space_tag_t bst = sc->sc_bst; 573 bus_space_handle_t bsh = sc->sc_bsh; 574 u_int len; 575 struct mbuf *m, *top; 576 u_int16_t length, npages; 577 u_int8_t packetno; 578 int timo, pad; 579 580 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 581 return; 582 583 again: 584 /* 585 * Peek at the next packet. 586 */ 587 IFQ_POLL(&ifp->if_snd, m); 588 if (m == NULL) 589 return; 590 591 /* 592 * Compute the frame length and set pad to give an overall even 593 * number of bytes. Below, we assume that the packet length 594 * is even. 595 */ 596 for (len = 0, top = m; m != NULL; m = m->m_next) 597 len += m->m_len; 598 pad = (len & 1); 599 600 /* 601 * We drop packets that are too large. Perhaps we should 602 * truncate them instead? 603 */ 604 if ((len + pad) > (ETHER_MAX_LEN - ETHER_CRC_LEN)) { 605 printf("%s: large packet discarded\n", sc->sc_dev.dv_xname); 606 ifp->if_oerrors++; 607 IFQ_DEQUEUE(&ifp->if_snd, m); 608 m_freem(m); 609 goto readcheck; 610 } 611 612 #ifdef SMC91CXX_SW_PAD 613 /* 614 * Not using hardware padding; pad to ETHER_MIN_LEN. 615 */ 616 if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 617 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 618 #endif 619 620 length = pad + len; 621 622 /* 623 * The MMU has a 256 byte page size. The MMU expects us to 624 * ask for "npages - 1". We include space for the status word, 625 * byte count, and control bytes in the allocation request. 626 */ 627 npages = (length + 6) >> 8; 628 629 /* 630 * Now allocate the memory. 631 */ 632 SMC_SELECT_BANK(sc, 2); 633 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ALLOC | npages); 634 635 timo = MEMORY_WAIT_TIME; 636 do { 637 if (bus_space_read_1(bst, bsh, INTR_STAT_REG_B) & IM_ALLOC_INT) 638 break; 639 delay(1); 640 } while (--timo); 641 642 packetno = bus_space_read_1(bst, bsh, ALLOC_RESULT_REG_B); 643 644 if (packetno & ARR_FAILED || timo == 0) { 645 /* 646 * No transmit memory is available. Record the number 647 * of requestd pages and enable the allocation completion 648 * interrupt. Set up the watchdog timer in case we miss 649 * the interrupt. Mark the interface as active so that 650 * no one else attempts to transmit while we're allocating 651 * memory. 652 */ 653 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 654 bus_space_read_1(bst, bsh, INTR_MASK_REG_B) | IM_ALLOC_INT); 655 656 ifp->if_timer = 5; 657 ifp->if_flags |= IFF_OACTIVE; 658 659 return; 660 } 661 662 /* 663 * We have a packet number - set the data window. 664 */ 665 bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno); 666 667 /* 668 * Point to the beginning of the packet. 669 */ 670 bus_space_write_2(bst, bsh, POINTER_REG_W, PTR_AUTOINC /* | 0x0000 */); 671 672 /* 673 * Send the packet length (+6 for stats, length, and control bytes) 674 * and the status word (set to zeros). 675 */ 676 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 677 bus_space_write_1(bst, bsh, DATA_REG_B, (length + 6) & 0xff); 678 bus_space_write_1(bst, bsh, DATA_REG_B, ((length + 6) >> 8) & 0xff); 679 680 /* 681 * Get the packet from the kernel. This will include the Ethernet 682 * frame header, MAC address, etc. 683 */ 684 IFQ_DEQUEUE(&ifp->if_snd, m); 685 686 /* 687 * Push the packet out to the card. 688 */ 689 for (top = m; m != NULL; m = m->m_next) { 690 /* Words... */ 691 if (m->m_len > 1) 692 bus_space_write_multi_stream_2(bst, bsh, DATA_REG_W, 693 mtod(m, u_int16_t *), m->m_len >> 1); 694 695 /* ...and the remaining byte, if any. */ 696 if (m->m_len & 1) 697 bus_space_write_1(bst, bsh, DATA_REG_B, 698 *(u_int8_t *)(mtod(m, u_int8_t *) + (m->m_len - 1))); 699 } 700 701 #ifdef SMC91CXX_SW_PAD 702 /* 703 * Push out padding. 704 */ 705 while (pad > 1) { 706 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 707 pad -= 2; 708 } 709 if (pad) 710 bus_space_write_1(bst, bsh, DATA_REG_B, 0); 711 #endif 712 713 /* 714 * Push out control byte and unused packet byte. The control byte 715 * is 0, meaning the packet is even lengthed and no special 716 * CRC handling is necessary. 717 */ 718 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 719 720 /* 721 * Enable transmit interrupts and let the chip go. Set a watchdog 722 * in case we miss the interrupt. 723 */ 724 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 725 bus_space_read_1(bst, bsh, INTR_MASK_REG_B) | 726 IM_TX_INT | IM_TX_EMPTY_INT); 727 728 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ENQUEUE); 729 730 ifp->if_timer = 5; 731 732 #if NBPFILTER > 0 733 /* Hand off a copy to the bpf. */ 734 if (ifp->if_bpf) 735 bpf_mtap(ifp->if_bpf, top); 736 #endif 737 738 ifp->if_opackets++; 739 m_freem(top); 740 741 readcheck: 742 /* 743 * Check for incoming pcakets. We don't want to overflow the small 744 * RX FIFO. If nothing has arrived, attempt to queue another 745 * transmit packet. 746 */ 747 if (bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & FIFO_REMPTY) 748 goto again; 749 } 750 751 /* 752 * Interrupt service routine. 753 */ 754 int 755 smc91cxx_intr(arg) 756 void *arg; 757 { 758 struct smc91cxx_softc *sc = arg; 759 struct ifnet *ifp = &sc->sc_ec.ec_if; 760 bus_space_tag_t bst = sc->sc_bst; 761 bus_space_handle_t bsh = sc->sc_bsh; 762 u_int8_t mask, interrupts, status; 763 u_int16_t packetno, tx_status, card_stats; 764 765 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 || 766 (sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 767 return (0); 768 769 SMC_SELECT_BANK(sc, 2); 770 771 /* 772 * Obtain the current interrupt mask. 773 */ 774 mask = bus_space_read_1(bst, bsh, INTR_MASK_REG_B); 775 776 /* 777 * Get the set of interrupt which occurred and eliminate any 778 * which are not enabled. 779 */ 780 interrupts = bus_space_read_1(bst, bsh, INTR_STAT_REG_B); 781 status = interrupts & mask; 782 783 /* Ours? */ 784 if (status == 0) 785 return (0); 786 787 /* 788 * It's ours; disable all interrupts while we process them. 789 */ 790 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0); 791 792 /* 793 * Receive overrun interrupts. 794 */ 795 if (status & IM_RX_OVRN_INT) { 796 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, IM_RX_OVRN_INT); 797 ifp->if_ierrors++; 798 } 799 800 /* 801 * Receive interrupts. 802 */ 803 if (status & IM_RCV_INT) { 804 #if 1 /* DIAGNOSTIC */ 805 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 806 if (packetno & FIFO_REMPTY) { 807 printf("%s: receive interrupt on empty fifo\n", 808 sc->sc_dev.dv_xname); 809 goto out; 810 } else 811 #endif 812 smc91cxx_read(sc); 813 } 814 815 /* 816 * Memory allocation interrupts. 817 */ 818 if (status & IM_ALLOC_INT) { 819 /* Disable this interrupt. */ 820 mask &= ~IM_ALLOC_INT; 821 822 /* 823 * Release the just-allocated memory. We will reallocate 824 * it through the normal start logic. 825 */ 826 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 827 /* XXX bound this loop! */ ; 828 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT); 829 830 ifp->if_flags &= ~IFF_OACTIVE; 831 ifp->if_timer = 0; 832 } 833 834 /* 835 * Transmit complete interrupt. Handle transmission error messages. 836 * This will only be called on error condition because of AUTO RELEASE 837 * mode. 838 */ 839 if (status & IM_TX_INT) { 840 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, IM_TX_INT); 841 842 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & 843 FIFO_TX_MASK; 844 845 /* 846 * Select this as the packet to read from. 847 */ 848 bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno); 849 850 /* 851 * Position the pointer to the beginning of the packet. 852 */ 853 bus_space_write_2(bst, bsh, POINTER_REG_W, 854 PTR_AUTOINC | PTR_READ /* | 0x0000 */); 855 856 /* 857 * Fetch the TX status word. This will be a copy of 858 * the EPH_STATUS_REG_W at the time of the transmission 859 * failure. 860 */ 861 tx_status = bus_space_read_2(bst, bsh, DATA_REG_W); 862 863 if (tx_status & EPHSR_TX_SUC) 864 printf("%s: successful packet caused TX interrupt?!\n", 865 sc->sc_dev.dv_xname); 866 else 867 ifp->if_oerrors++; 868 869 if (tx_status & EPHSR_LATCOL) 870 ifp->if_collisions++; 871 872 /* 873 * Some of these errors disable the transmitter; reenable it. 874 */ 875 SMC_SELECT_BANK(sc, 0); 876 #ifdef SMC91CXX_SW_PAD 877 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, TCR_ENABLE); 878 #else 879 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 880 TCR_ENABLE | TCR_PAD_ENABLE); 881 #endif 882 883 /* 884 * Kill the failed packet and wait for the MMU to unbusy. 885 */ 886 SMC_SELECT_BANK(sc, 2); 887 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 888 /* XXX bound this loop! */ ; 889 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT); 890 891 ifp->if_timer = 0; 892 } 893 894 /* 895 * Transmit underrun interrupts. We use this opportunity to 896 * update transmit statistics from the card. 897 */ 898 if (status & IM_TX_EMPTY_INT) { 899 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, IM_TX_EMPTY_INT); 900 901 /* Disable this interrupt. */ 902 mask &= ~IM_TX_EMPTY_INT; 903 904 SMC_SELECT_BANK(sc, 0); 905 card_stats = bus_space_read_2(bst, bsh, COUNTER_REG_W); 906 907 /* Single collisions. */ 908 ifp->if_collisions += card_stats & ECR_COLN_MASK; 909 910 /* Multiple collisions. */ 911 ifp->if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4; 912 913 SMC_SELECT_BANK(sc, 2); 914 915 ifp->if_timer = 0; 916 } 917 918 /* 919 * Other errors. Reset the interface. 920 */ 921 if (status & IM_EPH_INT) { 922 smc91cxx_stop(sc); 923 smc91cxx_init(sc); 924 } 925 926 /* 927 * Attempt to queue more packets for transmission. 928 */ 929 smc91cxx_start(ifp); 930 931 out: 932 /* 933 * Reenable the interrupts we wish to receive now that processing 934 * is complete. 935 */ 936 mask |= bus_space_read_1(bst, bsh, INTR_MASK_REG_B); 937 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, mask); 938 939 #if NRND > 0 940 if (status) 941 rnd_add_uint32(&sc->rnd_source, status); 942 #endif 943 944 return (1); 945 } 946 947 /* 948 * Read a packet from the card and pass it up to the kernel. 949 * NOTE! WE EXPECT TO BE IN REGISTER WINDOW 2! 950 */ 951 void 952 smc91cxx_read(sc) 953 struct smc91cxx_softc *sc; 954 { 955 struct ifnet *ifp = &sc->sc_ec.ec_if; 956 bus_space_tag_t bst = sc->sc_bst; 957 bus_space_handle_t bsh = sc->sc_bsh; 958 struct ether_header *eh; 959 struct mbuf *m; 960 u_int16_t status, packetno, packetlen; 961 u_int8_t *data; 962 963 again: 964 /* 965 * Set data pointer to the beginning of the packet. Since 966 * PTR_RCV is set, the packet number will be found automatically 967 * in FIFO_PORTS_REG_W, FIFO_RX_MASK. 968 */ 969 bus_space_write_2(bst, bsh, POINTER_REG_W, 970 PTR_READ | PTR_RCV | PTR_AUTOINC /* | 0x0000 */); 971 972 /* 973 * First two words are status and packet length. 974 */ 975 status = bus_space_read_2(bst, bsh, DATA_REG_W); 976 packetlen = bus_space_read_2(bst, bsh, DATA_REG_W); 977 978 /* 979 * The packet length includes 3 extra words: status, length, 980 * and an extra word that includes the control byte. 981 */ 982 packetlen -= 6; 983 984 /* 985 * Account for receive errors and discard. 986 */ 987 if (status & RS_ERRORS) { 988 ifp->if_ierrors++; 989 goto out; 990 } 991 992 /* 993 * Adjust for odd-length packet. 994 */ 995 if (status & RS_ODDFRAME) 996 packetlen++; 997 998 /* 999 * Allocate a header mbuf. 1000 */ 1001 MGETHDR(m, M_DONTWAIT, MT_DATA); 1002 if (m == NULL) 1003 goto out; 1004 m->m_pkthdr.rcvif = ifp; 1005 m->m_pkthdr.len = packetlen; 1006 1007 /* 1008 * Always put the packet in a cluster. 1009 * XXX should chain small mbufs if less than threshold. 1010 */ 1011 MCLGET(m, M_DONTWAIT); 1012 if ((m->m_flags & M_EXT) == 0) { 1013 m_freem(m); 1014 ifp->if_ierrors++; 1015 printf("%s: can't allocate cluster for incoming packet\n", 1016 sc->sc_dev.dv_xname); 1017 goto out; 1018 } 1019 1020 /* 1021 * Pull the packet off the interface. 1022 */ 1023 eh = mtod(m, struct ether_header *); 1024 data = mtod(m, u_int8_t *); 1025 if (packetlen > 1) 1026 bus_space_read_multi_stream_2(bst, bsh, DATA_REG_W, 1027 (u_int16_t *)data, packetlen >> 1); 1028 if (packetlen & 1) { 1029 data += packetlen & ~1; 1030 *data = bus_space_read_1(bst, bsh, DATA_REG_B); 1031 } 1032 1033 ifp->if_ipackets++; 1034 1035 /* 1036 * Make sure to behave as IFF_SIMPLEX in all cases. 1037 * This is to cope with SMC91C92 (Megahertz XJ10BT), which 1038 * loops back packets to itself on promiscuous mode. 1039 * (should be ensured by chipset configuration) 1040 */ 1041 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1042 /* 1043 * Drop packet looped back from myself. 1044 */ 1045 if (ether_cmp(eh->ether_shost, LLADDR(ifp->if_sadl)) == 0) { 1046 m_freem(m); 1047 goto out; 1048 } 1049 } 1050 1051 #if NBPFILTER > 0 1052 /* 1053 * Hand the packet off to bpf listeners. 1054 */ 1055 if (ifp->if_bpf) 1056 bpf_mtap(ifp->if_bpf, m); 1057 #endif 1058 1059 m->m_pkthdr.len = m->m_len = packetlen; 1060 (*ifp->if_input)(ifp, m); 1061 1062 out: 1063 /* 1064 * Tell the card to free the memory occupied by this packet. 1065 */ 1066 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 1067 /* XXX bound this loop! */ ; 1068 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RELEASE); 1069 1070 /* 1071 * Check for another packet. 1072 */ 1073 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 1074 if (packetno & FIFO_REMPTY) 1075 return; 1076 goto again; 1077 } 1078 1079 /* 1080 * Process an ioctl request. 1081 */ 1082 int 1083 smc91cxx_ioctl(ifp, cmd, data) 1084 struct ifnet *ifp; 1085 u_long cmd; 1086 caddr_t data; 1087 { 1088 struct smc91cxx_softc *sc = ifp->if_softc; 1089 struct ifaddr *ifa = (struct ifaddr *)data; 1090 struct ifreq *ifr = (struct ifreq *)data; 1091 int s, error = 0; 1092 1093 s = splnet(); 1094 1095 switch (cmd) { 1096 case SIOCSIFADDR: 1097 if ((error = smc91cxx_enable(sc)) != 0) 1098 break; 1099 ifp->if_flags |= IFF_UP; 1100 switch (ifa->ifa_addr->sa_family) { 1101 #ifdef INET 1102 case AF_INET: 1103 smc91cxx_init(sc); 1104 arp_ifinit(ifp, ifa); 1105 break; 1106 #endif 1107 #ifdef NS 1108 case AF_NS: 1109 { 1110 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1111 1112 if (ns_nullhost(*ina)) 1113 ina->x_host = 1114 *(union ns_host *)LLADDR(ifp->if_sadl); 1115 else { 1116 memcpy(LLADDR(ifp->if_sadl), ina->x_host.c_host, 1117 ETHER_ADDR_LEN); 1118 } 1119 1120 /* 1121 * Set new address. Reset, because the receiver 1122 * has to be stopped before we can set the new 1123 * MAC address. 1124 */ 1125 smc91cxx_reset(sc); 1126 break; 1127 } 1128 #endif 1129 default: 1130 smc91cxx_init(sc); 1131 break; 1132 } 1133 break; 1134 1135 #if defined(CCITT) && defined(LLC) 1136 case SIOCSIFCONF_X25: 1137 if ((error = smc91cxx_enable(sc)) != 0) 1138 break; 1139 ifp->if_flags |= IFF_UP; 1140 ifa->ifa_rtrequest = cons_rtrequest; /* XXX */ 1141 error = x25_llcglue(PRC_IFUP, ifa->ifa_addr); 1142 if (error == 0) 1143 smc91cxx_init(sc); 1144 break; 1145 #endif 1146 1147 case SIOCSIFFLAGS: 1148 if ((ifp->if_flags & IFF_UP) == 0 && 1149 (ifp->if_flags & IFF_RUNNING) != 0) { 1150 /* 1151 * If interface is marked down and it is running, 1152 * stop it. 1153 */ 1154 smc91cxx_stop(sc); 1155 ifp->if_flags &= ~IFF_RUNNING; 1156 smc91cxx_disable(sc); 1157 } else if ((ifp->if_flags & IFF_UP) != 0 && 1158 (ifp->if_flags & IFF_RUNNING) == 0) { 1159 /* 1160 * If interface is marked up and it is stopped, 1161 * start it. 1162 */ 1163 if ((error = smc91cxx_enable(sc)) != 0) 1164 break; 1165 smc91cxx_init(sc); 1166 } else if ((ifp->if_flags & IFF_UP) != 0) { 1167 /* 1168 * Reset the interface to pick up changes in any 1169 * other flags that affect hardware registers. 1170 */ 1171 smc91cxx_reset(sc); 1172 } 1173 break; 1174 1175 case SIOCADDMULTI: 1176 case SIOCDELMULTI: 1177 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) { 1178 error = EIO; 1179 break; 1180 } 1181 1182 error = (cmd == SIOCADDMULTI) ? 1183 ether_addmulti(ifr, &sc->sc_ec) : 1184 ether_delmulti(ifr, &sc->sc_ec); 1185 if (error == ENETRESET) { 1186 /* 1187 * Multicast list has changed; set the hardware 1188 * filter accordingly. 1189 */ 1190 smc91cxx_reset(sc); 1191 error = 0; 1192 } 1193 break; 1194 1195 case SIOCGIFMEDIA: 1196 case SIOCSIFMEDIA: 1197 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1198 break; 1199 1200 default: 1201 error = EINVAL; 1202 break; 1203 } 1204 1205 splx(s); 1206 return (error); 1207 } 1208 1209 /* 1210 * Reset the interface. 1211 */ 1212 void 1213 smc91cxx_reset(sc) 1214 struct smc91cxx_softc *sc; 1215 { 1216 int s; 1217 1218 s = splnet(); 1219 smc91cxx_stop(sc); 1220 smc91cxx_init(sc); 1221 splx(s); 1222 } 1223 1224 /* 1225 * Watchdog timer. 1226 */ 1227 void 1228 smc91cxx_watchdog(ifp) 1229 struct ifnet *ifp; 1230 { 1231 struct smc91cxx_softc *sc = ifp->if_softc; 1232 1233 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1234 ifp->if_oerrors++; 1235 smc91cxx_reset(sc); 1236 } 1237 1238 /* 1239 * Stop output on the interface. 1240 */ 1241 void 1242 smc91cxx_stop(sc) 1243 struct smc91cxx_softc *sc; 1244 { 1245 bus_space_tag_t bst = sc->sc_bst; 1246 bus_space_handle_t bsh = sc->sc_bsh; 1247 1248 /* 1249 * Clear interrupt mask; disable all interrupts. 1250 */ 1251 SMC_SELECT_BANK(sc, 2); 1252 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0); 1253 1254 /* 1255 * Disable transmitter and receiver. 1256 */ 1257 SMC_SELECT_BANK(sc, 0); 1258 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); 1259 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); 1260 1261 /* 1262 * Cancel watchdog timer. 1263 */ 1264 sc->sc_ec.ec_if.if_timer = 0; 1265 } 1266 1267 /* 1268 * Enable power on the interface. 1269 */ 1270 int 1271 smc91cxx_enable(sc) 1272 struct smc91cxx_softc *sc; 1273 { 1274 1275 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 && sc->sc_enable != NULL) { 1276 if ((*sc->sc_enable)(sc) != 0) { 1277 printf("%s: device enable failed\n", 1278 sc->sc_dev.dv_xname); 1279 return (EIO); 1280 } 1281 } 1282 1283 sc->sc_flags |= SMC_FLAGS_ENABLED; 1284 return (0); 1285 } 1286 1287 /* 1288 * Disable power on the interface. 1289 */ 1290 void 1291 smc91cxx_disable(sc) 1292 struct smc91cxx_softc *sc; 1293 { 1294 1295 if ((sc->sc_flags & SMC_FLAGS_ENABLED) != 0 && sc->sc_disable != NULL) { 1296 (*sc->sc_disable)(sc); 1297 sc->sc_flags &= ~SMC_FLAGS_ENABLED; 1298 } 1299 } 1300 1301 int 1302 smc91cxx_activate(self, act) 1303 struct device *self; 1304 enum devact act; 1305 { 1306 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1307 int rv = 0, s; 1308 1309 s = splnet(); 1310 switch (act) { 1311 case DVACT_ACTIVATE: 1312 rv = EOPNOTSUPP; 1313 break; 1314 1315 case DVACT_DEACTIVATE: 1316 if_deactivate(&sc->sc_ec.ec_if); 1317 break; 1318 } 1319 splx(s); 1320 return (rv); 1321 } 1322 1323 int 1324 smc91cxx_detach(self, flags) 1325 struct device *self; 1326 int flags; 1327 { 1328 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1329 struct ifnet *ifp = &sc->sc_ec.ec_if; 1330 1331 /* Succeed now if there's no work to do. */ 1332 if ((sc->sc_flags & SMC_FLAGS_ATTACHED) == 0) 1333 return (0); 1334 1335 1336 /* smc91cxx_disable() checks SMC_FLAGS_ENABLED */ 1337 smc91cxx_disable(sc); 1338 1339 /* smc91cxx_attach() never fails */ 1340 1341 /* Delete all media. */ 1342 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1343 1344 #if NRND > 0 1345 rnd_detach_source(&sc->rnd_source); 1346 #endif 1347 ether_ifdetach(ifp); 1348 if_detach(ifp); 1349 1350 return (0); 1351 } 1352 1353 u_int32_t 1354 smc91cxx_mii_bitbang_read(self) 1355 struct device *self; 1356 { 1357 struct smc91cxx_softc *sc = (void *) self; 1358 1359 /* We're already in bank 3. */ 1360 return (bus_space_read_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W)); 1361 } 1362 1363 void 1364 smc91cxx_mii_bitbang_write(self, val) 1365 struct device *self; 1366 u_int32_t val; 1367 { 1368 struct smc91cxx_softc *sc = (void *) self; 1369 1370 /* We're already in bank 3. */ 1371 bus_space_write_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W, val); 1372 } 1373 1374 int 1375 smc91cxx_mii_readreg(self, phy, reg) 1376 struct device *self; 1377 int phy, reg; 1378 { 1379 struct smc91cxx_softc *sc = (void *) self; 1380 int val; 1381 1382 SMC_SELECT_BANK(sc, 3); 1383 1384 val = mii_bitbang_readreg(self, &smc91cxx_mii_bitbang_ops, phy, reg); 1385 1386 SMC_SELECT_BANK(sc, 2); 1387 1388 return (val); 1389 } 1390 1391 void 1392 smc91cxx_mii_writereg(self, phy, reg, val) 1393 struct device *self; 1394 int phy, reg, val; 1395 { 1396 struct smc91cxx_softc *sc = (void *) self; 1397 1398 SMC_SELECT_BANK(sc, 3); 1399 1400 mii_bitbang_writereg(self, &smc91cxx_mii_bitbang_ops, phy, reg, val); 1401 1402 SMC_SELECT_BANK(sc, 2); 1403 } 1404 1405 void 1406 smc91cxx_statchg(self) 1407 struct device *self; 1408 { 1409 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1410 bus_space_tag_t bst = sc->sc_bst; 1411 bus_space_handle_t bsh = sc->sc_bsh; 1412 int mctl; 1413 1414 SMC_SELECT_BANK(sc, 0); 1415 mctl = bus_space_read_2(bst, bsh, TXMIT_CONTROL_REG_W); 1416 if (sc->sc_mii.mii_media_active & IFM_FDX) 1417 mctl |= TCR_SWFDUP; 1418 else 1419 mctl &= ~TCR_SWFDUP; 1420 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, mctl); 1421 SMC_SELECT_BANK(sc, 2); /* back to operating window */ 1422 } 1423 1424 /* 1425 * One second timer, used to tick the MII. 1426 */ 1427 void 1428 smc91cxx_tick(arg) 1429 void *arg; 1430 { 1431 struct smc91cxx_softc *sc = arg; 1432 int s; 1433 1434 #ifdef DIAGNOSTIC 1435 if ((sc->sc_flags & SMC_FLAGS_HAS_MII) == 0) 1436 panic("smc91cxx_tick"); 1437 #endif 1438 1439 if ((sc->sc_dev.dv_flags & DVF_ACTIVE) == 0) 1440 return; 1441 1442 s = splnet(); 1443 mii_tick(&sc->sc_mii); 1444 splx(s); 1445 1446 callout_reset(&sc->sc_mii_callout, hz, smc91cxx_tick, sc); 1447 } 1448 1449