1 /* $NetBSD: smc91cxx.c,v 1.63 2007/10/19 12:00:01 ad Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com> 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Gardner Buchanan. 55 * 4. The name of Gardner Buchanan may not be used to endorse or promote 56 * products derived from this software without specific prior written 57 * permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 60 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 61 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 63 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 64 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 65 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 66 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 67 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 68 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 69 * 70 * from FreeBSD Id: if_sn.c,v 1.4 1996/03/18 15:47:16 gardner Exp 71 */ 72 73 /* 74 * Core driver for the SMC 91Cxx family of Ethernet chips. 75 * 76 * Memory allocation interrupt logic is drived from an SMC 91C90 driver 77 * written for NetBSD/amiga by Michael Hitch. 78 */ 79 80 #include <sys/cdefs.h> 81 __KERNEL_RCSID(0, "$NetBSD: smc91cxx.c,v 1.63 2007/10/19 12:00:01 ad Exp $"); 82 83 #include "opt_inet.h" 84 #include "bpfilter.h" 85 #include "rnd.h" 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/mbuf.h> 90 #include <sys/syslog.h> 91 #include <sys/socket.h> 92 #include <sys/device.h> 93 #include <sys/kernel.h> 94 #include <sys/malloc.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #if NRND > 0 98 #include <sys/rnd.h> 99 #endif 100 101 #include <sys/bus.h> 102 #include <sys/intr.h> 103 104 #include <net/if.h> 105 #include <net/if_dl.h> 106 #include <net/if_ether.h> 107 #include <net/if_media.h> 108 109 #ifdef INET 110 #include <netinet/in.h> 111 #include <netinet/if_inarp.h> 112 #include <netinet/in_systm.h> 113 #include <netinet/in_var.h> 114 #include <netinet/ip.h> 115 #endif 116 117 118 119 #if NBPFILTER > 0 120 #include <net/bpf.h> 121 #include <net/bpfdesc.h> 122 #endif 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/miivar.h> 126 #include <dev/mii/mii_bitbang.h> 127 128 #include <dev/ic/smc91cxxreg.h> 129 #include <dev/ic/smc91cxxvar.h> 130 131 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 132 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 133 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 134 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 135 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 136 137 #define bus_space_write_stream_4 bus_space_write_4 138 #define bus_space_read_stream_4 bus_space_read_4 139 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 140 141 /* XXX Hardware padding doesn't work yet(?) */ 142 #define SMC91CXX_SW_PAD 143 144 const char *smc91cxx_idstrs[] = { 145 NULL, /* 0 */ 146 NULL, /* 1 */ 147 NULL, /* 2 */ 148 "SMC91C90/91C92", /* 3 */ 149 "SMC91C94/91C96", /* 4 */ 150 "SMC91C95", /* 5 */ 151 NULL, /* 6 */ 152 "SMC91C100", /* 7 */ 153 "SMC91C100FD", /* 8 */ 154 "SMC91C111", /* 9 */ 155 NULL, /* 10 */ 156 NULL, /* 11 */ 157 NULL, /* 12 */ 158 NULL, /* 13 */ 159 NULL, /* 14 */ 160 NULL, /* 15 */ 161 }; 162 163 /* Supported media types. */ 164 const int smc91cxx_media[] = { 165 IFM_ETHER|IFM_10_T, 166 IFM_ETHER|IFM_10_5, 167 }; 168 #define NSMC91CxxMEDIA (sizeof(smc91cxx_media) / sizeof(smc91cxx_media[0])) 169 170 /* 171 * MII bit-bang glue. 172 */ 173 u_int32_t smc91cxx_mii_bitbang_read(struct device *); 174 void smc91cxx_mii_bitbang_write(struct device *, u_int32_t); 175 176 const struct mii_bitbang_ops smc91cxx_mii_bitbang_ops = { 177 smc91cxx_mii_bitbang_read, 178 smc91cxx_mii_bitbang_write, 179 { 180 MR_MDO, /* MII_BIT_MDO */ 181 MR_MDI, /* MII_BIT_MDI */ 182 MR_MCLK, /* MII_BIT_MDC */ 183 MR_MDOE, /* MII_BIT_DIR_HOST_PHY */ 184 0, /* MII_BIT_DIR_PHY_HOST */ 185 } 186 }; 187 188 /* MII callbacks */ 189 int smc91cxx_mii_readreg(struct device *, int, int); 190 void smc91cxx_mii_writereg(struct device *, int, int, int); 191 void smc91cxx_statchg(struct device *); 192 void smc91cxx_tick(void *); 193 194 int smc91cxx_mediachange(struct ifnet *); 195 void smc91cxx_mediastatus(struct ifnet *, struct ifmediareq *); 196 197 int smc91cxx_set_media(struct smc91cxx_softc *, int); 198 199 void smc91cxx_init(struct smc91cxx_softc *); 200 void smc91cxx_read(struct smc91cxx_softc *); 201 void smc91cxx_reset(struct smc91cxx_softc *); 202 void smc91cxx_start(struct ifnet *); 203 void smc91cxx_copy_tx_frame(struct smc91cxx_softc *, struct mbuf *); 204 void smc91cxx_resume(struct smc91cxx_softc *); 205 void smc91cxx_stop(struct smc91cxx_softc *); 206 void smc91cxx_watchdog(struct ifnet *); 207 int smc91cxx_ioctl(struct ifnet *, u_long, void *); 208 209 static inline int ether_cmp(const void *, const void *); 210 static inline int 211 ether_cmp(va, vb) 212 const void *va, *vb; 213 { 214 const u_int8_t *a = va; 215 const u_int8_t *b = vb; 216 217 return ((a[5] != b[5]) || (a[4] != b[4]) || (a[3] != b[3]) || 218 (a[2] != b[2]) || (a[1] != b[1]) || (a[0] != b[0])); 219 } 220 221 void 222 smc91cxx_attach(sc, myea) 223 struct smc91cxx_softc *sc; 224 u_int8_t *myea; 225 { 226 struct ifnet *ifp = &sc->sc_ec.ec_if; 227 bus_space_tag_t bst = sc->sc_bst; 228 bus_space_handle_t bsh = sc->sc_bsh; 229 struct ifmedia *ifm = &sc->sc_mii.mii_media; 230 const char *idstr; 231 u_int32_t miicapabilities; 232 u_int16_t tmp; 233 u_int8_t enaddr[ETHER_ADDR_LEN]; 234 int i, aui, mult, scale, memsize; 235 char pbuf[9]; 236 237 tmp = bus_space_read_2(bst, bsh, BANK_SELECT_REG_W); 238 /* check magic number */ 239 if ((tmp & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 240 aprint_error("%s: failed to detect chip, bsr=%04x\n", 241 sc->sc_dev.dv_xname, tmp); 242 return; 243 } 244 245 /* Make sure the chip is stopped. */ 246 smc91cxx_stop(sc); 247 248 SMC_SELECT_BANK(sc, 3); 249 tmp = bus_space_read_2(bst, bsh, REVISION_REG_W); 250 sc->sc_chipid = RR_ID(tmp); 251 idstr = smc91cxx_idstrs[sc->sc_chipid]; 252 253 aprint_normal("%s: ", sc->sc_dev.dv_xname); 254 if (idstr != NULL) 255 aprint_normal("%s, ", idstr); 256 else 257 aprint_normal("unknown chip id %d, ", sc->sc_chipid); 258 aprint_normal("revision %d, ", RR_REV(tmp)); 259 260 SMC_SELECT_BANK(sc, 0); 261 switch (sc->sc_chipid) { 262 default: 263 mult = MCR_MEM_MULT(bus_space_read_2(bst, bsh, MEM_CFG_REG_W)); 264 scale = MIR_SCALE_91C9x; 265 break; 266 267 case CHIP_91C111: 268 mult = MIR_MULT_91C111; 269 scale = MIR_SCALE_91C111; 270 } 271 memsize = bus_space_read_2(bst, bsh, MEM_INFO_REG_W) & MIR_TOTAL_MASK; 272 if (memsize == 255) memsize++; 273 memsize *= scale * mult; 274 275 format_bytes(pbuf, sizeof(pbuf), memsize); 276 aprint_normal("buffer size: %s\n", pbuf); 277 278 /* Read the station address from the chip. */ 279 SMC_SELECT_BANK(sc, 1); 280 if (myea == NULL) { 281 myea = enaddr; 282 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 283 tmp = bus_space_read_2(bst, bsh, IAR_ADDR0_REG_W + i); 284 myea[i + 1] = (tmp >> 8) & 0xff; 285 myea[i] = tmp & 0xff; 286 } 287 } 288 aprint_normal("%s: MAC address %s, ", sc->sc_dev.dv_xname, 289 ether_sprintf(myea)); 290 291 /* Initialize the ifnet structure. */ 292 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 293 ifp->if_softc = sc; 294 ifp->if_start = smc91cxx_start; 295 ifp->if_ioctl = smc91cxx_ioctl; 296 ifp->if_watchdog = smc91cxx_watchdog; 297 ifp->if_flags = 298 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 299 IFQ_SET_READY(&ifp->if_snd); 300 301 /* Attach the interface. */ 302 if_attach(ifp); 303 ether_ifattach(ifp, myea); 304 305 /* 306 * Initialize our media structures and MII info. We will 307 * probe the MII if we are on the SMC91Cxx 308 */ 309 sc->sc_mii.mii_ifp = ifp; 310 sc->sc_mii.mii_readreg = smc91cxx_mii_readreg; 311 sc->sc_mii.mii_writereg = smc91cxx_mii_writereg; 312 sc->sc_mii.mii_statchg = smc91cxx_statchg; 313 ifmedia_init(ifm, IFM_IMASK, smc91cxx_mediachange, smc91cxx_mediastatus); 314 315 SMC_SELECT_BANK(sc, 1); 316 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 317 318 miicapabilities = BMSR_MEDIAMASK|BMSR_ANEG; 319 switch (sc->sc_chipid) { 320 case CHIP_91100: 321 /* 322 * The 91100 does not have full-duplex capabilities, 323 * even if the PHY does. 324 */ 325 miicapabilities &= ~(BMSR_100TXFDX | BMSR_10TFDX); 326 case CHIP_91100FD: 327 case CHIP_91C111: 328 if (tmp & CR_MII_SELECT) { 329 aprint_normal("default media MII"); 330 if (sc->sc_chipid == CHIP_91C111) { 331 aprint_normal(" (%s PHY)\n", (tmp & CR_AUI_SELECT) ? 332 "external" : "internal"); 333 sc->sc_internal_phy = !(tmp & CR_AUI_SELECT); 334 } else 335 aprint_normal("\n"); 336 mii_attach(&sc->sc_dev, &sc->sc_mii, miicapabilities, 337 MII_PHY_ANY, MII_OFFSET_ANY, 0); 338 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 339 ifmedia_add(&sc->sc_mii.mii_media, 340 IFM_ETHER|IFM_NONE, 0, NULL); 341 ifmedia_set(&sc->sc_mii.mii_media, 342 IFM_ETHER|IFM_NONE); 343 } else { 344 ifmedia_set(&sc->sc_mii.mii_media, 345 IFM_ETHER|IFM_AUTO); 346 } 347 sc->sc_flags |= SMC_FLAGS_HAS_MII; 348 break; 349 } else 350 if (sc->sc_chipid == CHIP_91C111) { 351 /* 352 * XXX: Should bring it out of low-power mode 353 */ 354 aprint_normal("EPH interface in low power mode\n"); 355 sc->sc_internal_phy = 0; 356 return; 357 } 358 /*FALLTHROUGH*/ 359 default: 360 aprint_normal("default media %s\n", (aui = (tmp & CR_AUI_SELECT)) ? 361 "AUI" : "UTP"); 362 for (i = 0; i < NSMC91CxxMEDIA; i++) 363 ifmedia_add(ifm, smc91cxx_media[i], 0, NULL); 364 ifmedia_set(ifm, IFM_ETHER | (aui ? IFM_10_5 : IFM_10_T)); 365 break; 366 } 367 368 #if NRND > 0 369 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 370 RND_TYPE_NET, 0); 371 #endif 372 373 callout_init(&sc->sc_mii_callout, 0); 374 375 /* The attach is successful. */ 376 sc->sc_flags |= SMC_FLAGS_ATTACHED; 377 } 378 379 /* 380 * Change media according to request. 381 */ 382 int 383 smc91cxx_mediachange(ifp) 384 struct ifnet *ifp; 385 { 386 struct smc91cxx_softc *sc = ifp->if_softc; 387 388 return (smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_media)); 389 } 390 391 int 392 smc91cxx_set_media(sc, media) 393 struct smc91cxx_softc *sc; 394 int media; 395 { 396 bus_space_tag_t bst = sc->sc_bst; 397 bus_space_handle_t bsh = sc->sc_bsh; 398 u_int16_t tmp; 399 400 /* 401 * If the interface is not currently powered on, just return. 402 * When it is enabled later, smc91cxx_init() will properly set 403 * up the media for us. 404 */ 405 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) 406 return (0); 407 408 if (IFM_TYPE(media) != IFM_ETHER) 409 return (EINVAL); 410 411 if (sc->sc_flags & SMC_FLAGS_HAS_MII) 412 return (mii_mediachg(&sc->sc_mii)); 413 414 switch (IFM_SUBTYPE(media)) { 415 case IFM_10_T: 416 case IFM_10_5: 417 SMC_SELECT_BANK(sc, 1); 418 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 419 if (IFM_SUBTYPE(media) == IFM_10_5) 420 tmp |= CR_AUI_SELECT; 421 else 422 tmp &= ~CR_AUI_SELECT; 423 bus_space_write_2(bst, bsh, CONFIG_REG_W, tmp); 424 delay(20000); /* XXX is this needed? */ 425 break; 426 427 default: 428 return (EINVAL); 429 } 430 431 return (0); 432 } 433 434 /* 435 * Notify the world which media we're using. 436 */ 437 void 438 smc91cxx_mediastatus(ifp, ifmr) 439 struct ifnet *ifp; 440 struct ifmediareq *ifmr; 441 { 442 struct smc91cxx_softc *sc = ifp->if_softc; 443 bus_space_tag_t bst = sc->sc_bst; 444 bus_space_handle_t bsh = sc->sc_bsh; 445 u_int16_t tmp; 446 447 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) { 448 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 449 ifmr->ifm_status = 0; 450 return; 451 } 452 453 /* 454 * If we have MII, go ask the PHY what's going on. 455 */ 456 if (sc->sc_flags & SMC_FLAGS_HAS_MII) { 457 mii_pollstat(&sc->sc_mii); 458 ifmr->ifm_active = sc->sc_mii.mii_media_active; 459 ifmr->ifm_status = sc->sc_mii.mii_media_status; 460 return; 461 } 462 463 SMC_SELECT_BANK(sc, 1); 464 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 465 ifmr->ifm_active = 466 IFM_ETHER | ((tmp & CR_AUI_SELECT) ? IFM_10_5 : IFM_10_T); 467 } 468 469 /* 470 * Reset and initialize the chip. 471 */ 472 void 473 smc91cxx_init(sc) 474 struct smc91cxx_softc *sc; 475 { 476 struct ifnet *ifp = &sc->sc_ec.ec_if; 477 bus_space_tag_t bst = sc->sc_bst; 478 bus_space_handle_t bsh = sc->sc_bsh; 479 u_int16_t tmp; 480 const u_int8_t *enaddr; 481 int s, i; 482 483 s = splnet(); 484 485 /* 486 * This resets the registers mostly to defaults, but doesn't 487 * affect the EEPROM. After the reset cycle, we pause briefly 488 * for the chip to recover. 489 * 490 * XXX how long are we really supposed to delay? --thorpej 491 */ 492 SMC_SELECT_BANK(sc, 0); 493 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, RCR_SOFTRESET); 494 delay(100); 495 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); 496 delay(200); 497 498 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); 499 500 /* Set the Ethernet address. */ 501 SMC_SELECT_BANK(sc, 1); 502 enaddr = (const u_int8_t *)CLLADDR(ifp->if_sadl); 503 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 504 tmp = enaddr[i + 1] << 8 | enaddr[i]; 505 bus_space_write_2(bst, bsh, IAR_ADDR0_REG_W + i, tmp); 506 } 507 508 /* 509 * Set the control register to automatically release successfully 510 * transmitted packets (making the best use of our limited memory) 511 * and enable the EPH interrupt on certain TX errors. 512 */ 513 bus_space_write_2(bst, bsh, CONTROL_REG_W, (CTR_AUTO_RELEASE | 514 CTR_TE_ENABLE | CTR_CR_ENABLE | CTR_LE_ENABLE)); 515 516 /* 517 * Reset the MMU and wait for it to be un-busy. 518 */ 519 SMC_SELECT_BANK(sc, 2); 520 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RESET); 521 for (;;) { 522 tmp = bus_space_read_2(bst, bsh, MMU_CMD_REG_W); 523 if (tmp == 0xffff) /* card went away! */ 524 return; 525 if ((tmp & MMUCR_BUSY) == 0) 526 break; 527 } 528 529 /* 530 * Disable all interrupts. 531 */ 532 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0); 533 534 /* 535 * On the 91c111, enable auto-negotiation, and set the LED 536 * status pins to something sane. 537 * XXX: Should be some way for MD code to decide the latter. 538 */ 539 SMC_SELECT_BANK(sc, 0); 540 if (sc->sc_chipid == CHIP_91C111) { 541 bus_space_write_2(bst, bsh, RX_PHY_CONTROL_REG_W, 542 RPC_ANEG | 543 (RPC_LS_LINK_DETECT << RPC_LSA_SHIFT) | 544 (RPC_LS_TXRX << RPC_LSB_SHIFT)); 545 } 546 547 /* 548 * Set current media. 549 */ 550 smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_cur->ifm_media); 551 552 /* 553 * Set the receive filter. We want receive enable and auto 554 * strip of CRC from received packet. If we are in promisc. mode, 555 * then set that bit as well. 556 * 557 * XXX Initialize multicast filter. For now, we just accept 558 * XXX all multicast. 559 */ 560 SMC_SELECT_BANK(sc, 0); 561 562 tmp = RCR_ENABLE | RCR_STRIP_CRC | RCR_ALMUL; 563 if (ifp->if_flags & IFF_PROMISC) 564 tmp |= RCR_PROMISC; 565 566 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, tmp); 567 568 /* 569 * Set transmitter control to "enabled". 570 */ 571 tmp = TCR_ENABLE; 572 573 #ifndef SMC91CXX_SW_PAD 574 /* 575 * Enable hardware padding of transmitted packets. 576 * XXX doesn't work? 577 */ 578 tmp |= TCR_PAD_ENABLE; 579 #endif 580 581 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, tmp); 582 583 /* 584 * Now, enable interrupts. 585 */ 586 SMC_SELECT_BANK(sc, 2); 587 588 if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy) { 589 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 590 IM_EPH_INT | IM_RX_OVRN_INT | 591 IM_RCV_INT | IM_TX_INT | IM_MD_INT); 592 } else { 593 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 594 IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | IM_TX_INT); 595 } 596 597 /* Interface is now running, with no output active. */ 598 ifp->if_flags |= IFF_RUNNING; 599 ifp->if_flags &= ~IFF_OACTIVE; 600 601 if (sc->sc_flags & SMC_FLAGS_HAS_MII) { 602 /* Start the one second clock. */ 603 callout_reset(&sc->sc_mii_callout, hz, smc91cxx_tick, sc); 604 } 605 606 /* 607 * Attempt to start any pending transmission. 608 */ 609 smc91cxx_start(ifp); 610 611 splx(s); 612 } 613 614 /* 615 * Start output on an interface. 616 * Must be called at splnet or interrupt level. 617 */ 618 void 619 smc91cxx_start(ifp) 620 struct ifnet *ifp; 621 { 622 struct smc91cxx_softc *sc = ifp->if_softc; 623 bus_space_tag_t bst = sc->sc_bst; 624 bus_space_handle_t bsh = sc->sc_bsh; 625 u_int len; 626 struct mbuf *m; 627 u_int16_t length, npages; 628 u_int8_t packetno; 629 int timo, pad; 630 631 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 632 return; 633 634 again: 635 /* 636 * Peek at the next packet. 637 */ 638 IFQ_POLL(&ifp->if_snd, m); 639 if (m == NULL) 640 return; 641 642 /* 643 * Compute the frame length and set pad to give an overall even 644 * number of bytes. Below, we assume that the packet length 645 * is even. 646 */ 647 for (len = 0; m != NULL; m = m->m_next) 648 len += m->m_len; 649 pad = (len & 1); 650 651 /* 652 * We drop packets that are too large. Perhaps we should 653 * truncate them instead? 654 */ 655 if ((len + pad) > (ETHER_MAX_LEN - ETHER_CRC_LEN)) { 656 printf("%s: large packet discarded\n", sc->sc_dev.dv_xname); 657 ifp->if_oerrors++; 658 IFQ_DEQUEUE(&ifp->if_snd, m); 659 m_freem(m); 660 goto readcheck; 661 } 662 663 #ifdef SMC91CXX_SW_PAD 664 /* 665 * Not using hardware padding; pad to ETHER_MIN_LEN. 666 */ 667 if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 668 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 669 #endif 670 671 length = pad + len; 672 673 /* 674 * The MMU has a 256 byte page size. The MMU expects us to 675 * ask for "npages - 1". We include space for the status word, 676 * byte count, and control bytes in the allocation request. 677 */ 678 npages = (length + 6) >> 8; 679 680 /* 681 * Now allocate the memory. 682 */ 683 SMC_SELECT_BANK(sc, 2); 684 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ALLOC | npages); 685 686 timo = MEMORY_WAIT_TIME; 687 do { 688 if (bus_space_read_1(bst, bsh, INTR_STAT_REG_B) & IM_ALLOC_INT) 689 break; 690 delay(1); 691 } while (--timo); 692 693 packetno = bus_space_read_1(bst, bsh, ALLOC_RESULT_REG_B); 694 695 if (packetno & ARR_FAILED || timo == 0) { 696 /* 697 * No transmit memory is available. Record the number 698 * of requestd pages and enable the allocation completion 699 * interrupt. Set up the watchdog timer in case we miss 700 * the interrupt. Mark the interface as active so that 701 * no one else attempts to transmit while we're allocating 702 * memory. 703 */ 704 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 705 bus_space_read_1(bst, bsh, INTR_MASK_REG_B) | IM_ALLOC_INT); 706 707 ifp->if_timer = 5; 708 ifp->if_flags |= IFF_OACTIVE; 709 710 return; 711 } 712 713 /* 714 * We have a packet number - set the data window. 715 */ 716 bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno); 717 718 /* 719 * Point to the beginning of the packet. 720 */ 721 bus_space_write_2(bst, bsh, POINTER_REG_W, PTR_AUTOINC /* | 0x0000 */); 722 723 /* 724 * Send the packet length (+6 for stats, length, and control bytes) 725 * and the status word (set to zeros). 726 */ 727 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 728 bus_space_write_2(bst, bsh, DATA_REG_W, (length + 6) & 0x7ff); 729 730 /* 731 * Get the packet from the kernel. This will include the Ethernet 732 * frame header, MAC address, etc. 733 */ 734 IFQ_DEQUEUE(&ifp->if_snd, m); 735 736 /* 737 * Push the packet out to the card. 738 */ 739 smc91cxx_copy_tx_frame(sc, m); 740 741 #ifdef SMC91CXX_SW_PAD 742 /* 743 * Push out padding. 744 */ 745 while (pad > 1) { 746 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 747 pad -= 2; 748 } 749 if (pad) 750 bus_space_write_1(bst, bsh, DATA_REG_B, 0); 751 #endif 752 753 /* 754 * Push out control byte and unused packet byte. The control byte 755 * is 0, meaning the packet is even lengthed and no special 756 * CRC handling is necessary. 757 */ 758 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 759 760 /* 761 * Enable transmit interrupts and let the chip go. Set a watchdog 762 * in case we miss the interrupt. 763 */ 764 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 765 bus_space_read_1(bst, bsh, INTR_MASK_REG_B) | 766 IM_TX_INT | IM_TX_EMPTY_INT); 767 768 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ENQUEUE); 769 770 ifp->if_timer = 5; 771 772 #if NBPFILTER > 0 773 /* Hand off a copy to the bpf. */ 774 if (ifp->if_bpf) 775 bpf_mtap(ifp->if_bpf, m); 776 #endif 777 778 ifp->if_opackets++; 779 m_freem(m); 780 781 readcheck: 782 /* 783 * Check for incoming pcakets. We don't want to overflow the small 784 * RX FIFO. If nothing has arrived, attempt to queue another 785 * transmit packet. 786 */ 787 if (bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & FIFO_REMPTY) 788 goto again; 789 } 790 791 /* 792 * Squirt a (possibly misaligned) mbuf to the device 793 */ 794 void 795 smc91cxx_copy_tx_frame(sc, m0) 796 struct smc91cxx_softc *sc; 797 struct mbuf *m0; 798 { 799 bus_space_tag_t bst = sc->sc_bst; 800 bus_space_handle_t bsh = sc->sc_bsh; 801 struct mbuf *m; 802 int len, leftover; 803 u_int16_t dbuf; 804 u_int8_t *p; 805 #ifdef DIAGNOSTIC 806 u_int8_t *lim; 807 #endif 808 809 /* start out with no leftover data */ 810 leftover = 0; 811 dbuf = 0; 812 813 /* Process the chain of mbufs */ 814 for (m = m0; m != NULL; m = m->m_next) { 815 /* 816 * Process all of the data in a single mbuf. 817 */ 818 p = mtod(m, u_int8_t *); 819 len = m->m_len; 820 #ifdef DIAGNOSTIC 821 lim = p + len; 822 #endif 823 824 while (len > 0) { 825 if (leftover) { 826 /* 827 * Data left over (from mbuf or realignment). 828 * Buffer the next byte, and write it and 829 * the leftover data out. 830 */ 831 dbuf |= *p++ << 8; 832 len--; 833 bus_space_write_2(bst, bsh, DATA_REG_W, dbuf); 834 leftover = 0; 835 } else if ((long) p & 1) { 836 /* 837 * Misaligned data. Buffer the next byte. 838 */ 839 dbuf = *p++; 840 len--; 841 leftover = 1; 842 } else { 843 /* 844 * Aligned data. This is the case we like. 845 * 846 * Write-region out as much as we can, then 847 * buffer the remaining byte (if any). 848 */ 849 leftover = len & 1; 850 len &= ~1; 851 bus_space_write_multi_stream_2(bst, bsh, 852 DATA_REG_W, (u_int16_t *)p, len >> 1); 853 p += len; 854 855 if (leftover) 856 dbuf = *p++; 857 len = 0; 858 } 859 } 860 if (len < 0) 861 panic("smc91cxx_copy_tx_frame: negative len"); 862 #ifdef DIAGNOSTIC 863 if (p != lim) 864 panic("smc91cxx_copy_tx_frame: p != lim"); 865 #endif 866 } 867 if (leftover) 868 bus_space_write_1(bst, bsh, DATA_REG_B, dbuf); 869 } 870 871 /* 872 * Interrupt service routine. 873 */ 874 int 875 smc91cxx_intr(arg) 876 void *arg; 877 { 878 struct smc91cxx_softc *sc = arg; 879 struct ifnet *ifp = &sc->sc_ec.ec_if; 880 bus_space_tag_t bst = sc->sc_bst; 881 bus_space_handle_t bsh = sc->sc_bsh; 882 u_int8_t mask, interrupts, status; 883 u_int16_t packetno, tx_status, card_stats; 884 885 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 || 886 !device_is_active(&sc->sc_dev)) 887 return (0); 888 889 SMC_SELECT_BANK(sc, 2); 890 891 /* 892 * Obtain the current interrupt mask. 893 */ 894 mask = bus_space_read_1(bst, bsh, INTR_MASK_REG_B); 895 896 /* 897 * Get the set of interrupt which occurred and eliminate any 898 * which are not enabled. 899 */ 900 interrupts = bus_space_read_1(bst, bsh, INTR_STAT_REG_B); 901 status = interrupts & mask; 902 903 /* Ours? */ 904 if (status == 0) 905 return (0); 906 907 /* 908 * It's ours; disable all interrupts while we process them. 909 */ 910 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0); 911 912 /* 913 * Receive overrun interrupts. 914 */ 915 if (status & IM_RX_OVRN_INT) { 916 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, IM_RX_OVRN_INT); 917 ifp->if_ierrors++; 918 } 919 920 /* 921 * Receive interrupts. 922 */ 923 if (status & IM_RCV_INT) { 924 #if 1 /* DIAGNOSTIC */ 925 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 926 if (packetno & FIFO_REMPTY) { 927 printf("%s: receive interrupt on empty fifo\n", 928 sc->sc_dev.dv_xname); 929 goto out; 930 } else 931 #endif 932 smc91cxx_read(sc); 933 } 934 935 /* 936 * Memory allocation interrupts. 937 */ 938 if (status & IM_ALLOC_INT) { 939 /* Disable this interrupt. */ 940 mask &= ~IM_ALLOC_INT; 941 942 /* 943 * Release the just-allocated memory. We will reallocate 944 * it through the normal start logic. 945 */ 946 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 947 /* XXX bound this loop! */ ; 948 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT); 949 950 ifp->if_flags &= ~IFF_OACTIVE; 951 ifp->if_timer = 0; 952 } 953 954 /* 955 * Transmit complete interrupt. Handle transmission error messages. 956 * This will only be called on error condition because of AUTO RELEASE 957 * mode. 958 */ 959 if (status & IM_TX_INT) { 960 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, IM_TX_INT); 961 962 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & 963 FIFO_TX_MASK; 964 965 /* 966 * Select this as the packet to read from. 967 */ 968 bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno); 969 970 /* 971 * Position the pointer to the beginning of the packet. 972 */ 973 bus_space_write_2(bst, bsh, POINTER_REG_W, 974 PTR_AUTOINC | PTR_READ /* | 0x0000 */); 975 976 /* 977 * Fetch the TX status word. This will be a copy of 978 * the EPH_STATUS_REG_W at the time of the transmission 979 * failure. 980 */ 981 tx_status = bus_space_read_2(bst, bsh, DATA_REG_W); 982 983 if (tx_status & EPHSR_TX_SUC) 984 printf("%s: successful packet caused TX interrupt?!\n", 985 sc->sc_dev.dv_xname); 986 else 987 ifp->if_oerrors++; 988 989 if (tx_status & EPHSR_LATCOL) 990 ifp->if_collisions++; 991 992 /* 993 * Some of these errors disable the transmitter; reenable it. 994 */ 995 SMC_SELECT_BANK(sc, 0); 996 #ifdef SMC91CXX_SW_PAD 997 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, TCR_ENABLE); 998 #else 999 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 1000 TCR_ENABLE | TCR_PAD_ENABLE); 1001 #endif 1002 1003 /* 1004 * Kill the failed packet and wait for the MMU to unbusy. 1005 */ 1006 SMC_SELECT_BANK(sc, 2); 1007 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 1008 /* XXX bound this loop! */ ; 1009 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT); 1010 1011 ifp->if_timer = 0; 1012 } 1013 1014 /* 1015 * Transmit underrun interrupts. We use this opportunity to 1016 * update transmit statistics from the card. 1017 */ 1018 if (status & IM_TX_EMPTY_INT) { 1019 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, IM_TX_EMPTY_INT); 1020 1021 /* Disable this interrupt. */ 1022 mask &= ~IM_TX_EMPTY_INT; 1023 1024 SMC_SELECT_BANK(sc, 0); 1025 card_stats = bus_space_read_2(bst, bsh, COUNTER_REG_W); 1026 1027 /* Single collisions. */ 1028 ifp->if_collisions += card_stats & ECR_COLN_MASK; 1029 1030 /* Multiple collisions. */ 1031 ifp->if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4; 1032 1033 SMC_SELECT_BANK(sc, 2); 1034 1035 ifp->if_timer = 0; 1036 } 1037 1038 if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy && 1039 (status & IM_MD_INT)) { 1040 /* 1041 * Internal PHY status change 1042 */ 1043 mii_tick(&sc->sc_mii); 1044 } 1045 1046 /* 1047 * Other errors. Reset the interface. 1048 */ 1049 if (status & IM_EPH_INT) { 1050 smc91cxx_stop(sc); 1051 smc91cxx_init(sc); 1052 } 1053 1054 /* 1055 * Attempt to queue more packets for transmission. 1056 */ 1057 smc91cxx_start(ifp); 1058 1059 out: 1060 /* 1061 * Reenable the interrupts we wish to receive now that processing 1062 * is complete. 1063 */ 1064 mask |= bus_space_read_1(bst, bsh, INTR_MASK_REG_B); 1065 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, mask); 1066 1067 #if NRND > 0 1068 if (status) 1069 rnd_add_uint32(&sc->rnd_source, status); 1070 #endif 1071 1072 return (1); 1073 } 1074 1075 /* 1076 * Read a packet from the card and pass it up to the kernel. 1077 * NOTE! WE EXPECT TO BE IN REGISTER WINDOW 2! 1078 */ 1079 void 1080 smc91cxx_read(sc) 1081 struct smc91cxx_softc *sc; 1082 { 1083 struct ifnet *ifp = &sc->sc_ec.ec_if; 1084 bus_space_tag_t bst = sc->sc_bst; 1085 bus_space_handle_t bsh = sc->sc_bsh; 1086 struct ether_header *eh; 1087 struct mbuf *m; 1088 u_int16_t status, packetno, packetlen; 1089 u_int8_t *data; 1090 u_int32_t dr; 1091 1092 again: 1093 /* 1094 * Set data pointer to the beginning of the packet. Since 1095 * PTR_RCV is set, the packet number will be found automatically 1096 * in FIFO_PORTS_REG_W, FIFO_RX_MASK. 1097 */ 1098 bus_space_write_2(bst, bsh, POINTER_REG_W, 1099 PTR_READ | PTR_RCV | PTR_AUTOINC /* | 0x0000 */); 1100 1101 /* 1102 * First two words are status and packet length. 1103 */ 1104 if ((sc->sc_flags & SMC_FLAGS_32BIT_READ) == 0) { 1105 status = bus_space_read_2(bst, bsh, DATA_REG_W); 1106 packetlen = bus_space_read_2(bst, bsh, DATA_REG_W); 1107 } else { 1108 dr = bus_space_read_4(bst, bsh, DATA_REG_W); 1109 #if BYTE_ORDER == LITTLE_ENDIAN 1110 status = (u_int16_t)dr; 1111 packetlen = (u_int16_t)(dr >> 16); 1112 #else 1113 packetlen = (u_int16_t)dr; 1114 status = (u_int16_t)(dr >> 16); 1115 #endif 1116 } 1117 1118 packetlen &= RLEN_MASK; 1119 1120 /* 1121 * The packet length includes 3 extra words: status, length, 1122 * and an extra word that includes the control byte. 1123 */ 1124 packetlen -= 6; 1125 1126 /* 1127 * Account for receive errors and discard. 1128 */ 1129 if (status & RS_ERRORS) { 1130 ifp->if_ierrors++; 1131 goto out; 1132 } 1133 1134 /* 1135 * Adjust for odd-length packet. 1136 */ 1137 if (status & RS_ODDFRAME) 1138 packetlen++; 1139 1140 /* 1141 * Allocate a header mbuf. 1142 */ 1143 MGETHDR(m, M_DONTWAIT, MT_DATA); 1144 if (m == NULL) 1145 goto out; 1146 m->m_pkthdr.rcvif = ifp; 1147 m->m_pkthdr.len = packetlen; 1148 1149 /* 1150 * Always put the packet in a cluster. 1151 * XXX should chain small mbufs if less than threshold. 1152 */ 1153 MCLGET(m, M_DONTWAIT); 1154 if ((m->m_flags & M_EXT) == 0) { 1155 m_freem(m); 1156 ifp->if_ierrors++; 1157 printf("%s: can't allocate cluster for incoming packet\n", 1158 sc->sc_dev.dv_xname); 1159 goto out; 1160 } 1161 1162 /* 1163 * Pull the packet off the interface. Make sure the payload 1164 * is aligned. 1165 */ 1166 if ((sc->sc_flags & SMC_FLAGS_32BIT_READ) == 0) { 1167 m->m_data = (char *) ALIGN(mtod(m, char *) + 1168 sizeof(struct ether_header)) - sizeof(struct ether_header); 1169 1170 eh = mtod(m, struct ether_header *); 1171 data = mtod(m, u_int8_t *); 1172 if (packetlen > 1) 1173 bus_space_read_multi_stream_2(bst, bsh, DATA_REG_W, 1174 (u_int16_t *)data, packetlen >> 1); 1175 if (packetlen & 1) { 1176 data += packetlen & ~1; 1177 *data = bus_space_read_1(bst, bsh, DATA_REG_B); 1178 } 1179 } else { 1180 u_int8_t *dp; 1181 1182 m->m_data = (void *) ALIGN(mtod(m, void *)); 1183 eh = mtod(m, struct ether_header *); 1184 dp = data = mtod(m, u_int8_t *); 1185 if (packetlen > 3) 1186 bus_space_read_multi_stream_4(bst, bsh, DATA_REG_W, 1187 (u_int32_t *)data, packetlen >> 2); 1188 if (packetlen & 3) { 1189 data += packetlen & ~3; 1190 *((u_int32_t *)data) = 1191 bus_space_read_stream_4(bst, bsh, DATA_REG_W); 1192 } 1193 } 1194 1195 ifp->if_ipackets++; 1196 1197 /* 1198 * Make sure to behave as IFF_SIMPLEX in all cases. 1199 * This is to cope with SMC91C92 (Megahertz XJ10BT), which 1200 * loops back packets to itself on promiscuous mode. 1201 * (should be ensured by chipset configuration) 1202 */ 1203 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1204 /* 1205 * Drop packet looped back from myself. 1206 */ 1207 if (ether_cmp(eh->ether_shost, CLLADDR(ifp->if_sadl)) == 0) { 1208 m_freem(m); 1209 goto out; 1210 } 1211 } 1212 1213 m->m_pkthdr.len = m->m_len = packetlen; 1214 1215 #if NBPFILTER > 0 1216 /* 1217 * Hand the packet off to bpf listeners. 1218 */ 1219 if (ifp->if_bpf) 1220 bpf_mtap(ifp->if_bpf, m); 1221 #endif 1222 1223 (*ifp->if_input)(ifp, m); 1224 1225 out: 1226 /* 1227 * Tell the card to free the memory occupied by this packet. 1228 */ 1229 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 1230 /* XXX bound this loop! */ ; 1231 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RELEASE); 1232 1233 /* 1234 * Check for another packet. 1235 */ 1236 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 1237 if (packetno & FIFO_REMPTY) 1238 return; 1239 goto again; 1240 } 1241 1242 /* 1243 * Process an ioctl request. 1244 */ 1245 int 1246 smc91cxx_ioctl(ifp, cmd, data) 1247 struct ifnet *ifp; 1248 u_long cmd; 1249 void *data; 1250 { 1251 struct smc91cxx_softc *sc = ifp->if_softc; 1252 struct ifaddr *ifa = (struct ifaddr *)data; 1253 struct ifreq *ifr = (struct ifreq *)data; 1254 int s, error = 0; 1255 1256 s = splnet(); 1257 1258 switch (cmd) { 1259 case SIOCSIFADDR: 1260 if ((error = smc91cxx_enable(sc)) != 0) 1261 break; 1262 ifp->if_flags |= IFF_UP; 1263 switch (ifa->ifa_addr->sa_family) { 1264 #ifdef INET 1265 case AF_INET: 1266 smc91cxx_init(sc); 1267 arp_ifinit(ifp, ifa); 1268 break; 1269 #endif 1270 default: 1271 smc91cxx_init(sc); 1272 break; 1273 } 1274 break; 1275 1276 1277 case SIOCSIFFLAGS: 1278 if ((ifp->if_flags & IFF_UP) == 0 && 1279 (ifp->if_flags & IFF_RUNNING) != 0) { 1280 /* 1281 * If interface is marked down and it is running, 1282 * stop it. 1283 */ 1284 smc91cxx_stop(sc); 1285 ifp->if_flags &= ~IFF_RUNNING; 1286 smc91cxx_disable(sc); 1287 } else if ((ifp->if_flags & IFF_UP) != 0 && 1288 (ifp->if_flags & IFF_RUNNING) == 0) { 1289 /* 1290 * If interface is marked up and it is stopped, 1291 * start it. 1292 */ 1293 if ((error = smc91cxx_enable(sc)) != 0) 1294 break; 1295 smc91cxx_init(sc); 1296 } else if ((ifp->if_flags & IFF_UP) != 0) { 1297 /* 1298 * Reset the interface to pick up changes in any 1299 * other flags that affect hardware registers. 1300 */ 1301 smc91cxx_reset(sc); 1302 } 1303 break; 1304 1305 case SIOCADDMULTI: 1306 case SIOCDELMULTI: 1307 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) { 1308 error = EIO; 1309 break; 1310 } 1311 1312 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1313 /* 1314 * Multicast list has changed; set the hardware 1315 * filter accordingly. 1316 */ 1317 if (ifp->if_flags & IFF_RUNNING) 1318 smc91cxx_reset(sc); 1319 error = 0; 1320 } 1321 break; 1322 1323 case SIOCGIFMEDIA: 1324 case SIOCSIFMEDIA: 1325 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1326 break; 1327 1328 default: 1329 error = EINVAL; 1330 break; 1331 } 1332 1333 splx(s); 1334 return (error); 1335 } 1336 1337 /* 1338 * Reset the interface. 1339 */ 1340 void 1341 smc91cxx_reset(sc) 1342 struct smc91cxx_softc *sc; 1343 { 1344 int s; 1345 1346 s = splnet(); 1347 smc91cxx_stop(sc); 1348 smc91cxx_init(sc); 1349 splx(s); 1350 } 1351 1352 /* 1353 * Watchdog timer. 1354 */ 1355 void 1356 smc91cxx_watchdog(ifp) 1357 struct ifnet *ifp; 1358 { 1359 struct smc91cxx_softc *sc = ifp->if_softc; 1360 1361 log(LOG_ERR, "%s: device timeout\n", sc->sc_dev.dv_xname); 1362 ifp->if_oerrors++; 1363 smc91cxx_reset(sc); 1364 } 1365 1366 /* 1367 * Stop output on the interface. 1368 */ 1369 void 1370 smc91cxx_stop(sc) 1371 struct smc91cxx_softc *sc; 1372 { 1373 bus_space_tag_t bst = sc->sc_bst; 1374 bus_space_handle_t bsh = sc->sc_bsh; 1375 1376 /* 1377 * Clear interrupt mask; disable all interrupts. 1378 */ 1379 SMC_SELECT_BANK(sc, 2); 1380 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0); 1381 1382 /* 1383 * Disable transmitter and receiver. 1384 */ 1385 SMC_SELECT_BANK(sc, 0); 1386 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); 1387 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); 1388 1389 /* 1390 * Cancel watchdog timer. 1391 */ 1392 sc->sc_ec.ec_if.if_timer = 0; 1393 } 1394 1395 /* 1396 * Enable power on the interface. 1397 */ 1398 int 1399 smc91cxx_enable(sc) 1400 struct smc91cxx_softc *sc; 1401 { 1402 1403 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 && sc->sc_enable != NULL) { 1404 if ((*sc->sc_enable)(sc) != 0) { 1405 printf("%s: device enable failed\n", 1406 sc->sc_dev.dv_xname); 1407 return (EIO); 1408 } 1409 } 1410 1411 sc->sc_flags |= SMC_FLAGS_ENABLED; 1412 return (0); 1413 } 1414 1415 /* 1416 * Disable power on the interface. 1417 */ 1418 void 1419 smc91cxx_disable(sc) 1420 struct smc91cxx_softc *sc; 1421 { 1422 1423 if ((sc->sc_flags & SMC_FLAGS_ENABLED) != 0 && sc->sc_disable != NULL) { 1424 (*sc->sc_disable)(sc); 1425 sc->sc_flags &= ~SMC_FLAGS_ENABLED; 1426 } 1427 } 1428 1429 int 1430 smc91cxx_activate(self, act) 1431 struct device *self; 1432 enum devact act; 1433 { 1434 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1435 int rv = 0, s; 1436 1437 s = splnet(); 1438 switch (act) { 1439 case DVACT_ACTIVATE: 1440 rv = EOPNOTSUPP; 1441 break; 1442 1443 case DVACT_DEACTIVATE: 1444 if_deactivate(&sc->sc_ec.ec_if); 1445 break; 1446 } 1447 splx(s); 1448 return (rv); 1449 } 1450 1451 int 1452 smc91cxx_detach(struct device *self, int flags) 1453 { 1454 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1455 struct ifnet *ifp = &sc->sc_ec.ec_if; 1456 1457 /* Succeed now if there's no work to do. */ 1458 if ((sc->sc_flags & SMC_FLAGS_ATTACHED) == 0) 1459 return (0); 1460 1461 1462 /* smc91cxx_disable() checks SMC_FLAGS_ENABLED */ 1463 smc91cxx_disable(sc); 1464 1465 /* smc91cxx_attach() never fails */ 1466 1467 /* Delete all media. */ 1468 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1469 1470 #if NRND > 0 1471 rnd_detach_source(&sc->rnd_source); 1472 #endif 1473 ether_ifdetach(ifp); 1474 if_detach(ifp); 1475 1476 return (0); 1477 } 1478 1479 u_int32_t 1480 smc91cxx_mii_bitbang_read(self) 1481 struct device *self; 1482 { 1483 struct smc91cxx_softc *sc = (void *) self; 1484 1485 /* We're already in bank 3. */ 1486 return (bus_space_read_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W)); 1487 } 1488 1489 void 1490 smc91cxx_mii_bitbang_write(self, val) 1491 struct device *self; 1492 u_int32_t val; 1493 { 1494 struct smc91cxx_softc *sc = (void *) self; 1495 1496 /* We're already in bank 3. */ 1497 bus_space_write_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W, val); 1498 } 1499 1500 int 1501 smc91cxx_mii_readreg(self, phy, reg) 1502 struct device *self; 1503 int phy, reg; 1504 { 1505 struct smc91cxx_softc *sc = (void *) self; 1506 int val; 1507 1508 SMC_SELECT_BANK(sc, 3); 1509 1510 val = mii_bitbang_readreg(self, &smc91cxx_mii_bitbang_ops, phy, reg); 1511 1512 SMC_SELECT_BANK(sc, 2); 1513 1514 return (val); 1515 } 1516 1517 void 1518 smc91cxx_mii_writereg(self, phy, reg, val) 1519 struct device *self; 1520 int phy, reg, val; 1521 { 1522 struct smc91cxx_softc *sc = (void *) self; 1523 1524 SMC_SELECT_BANK(sc, 3); 1525 1526 mii_bitbang_writereg(self, &smc91cxx_mii_bitbang_ops, phy, reg, val); 1527 1528 SMC_SELECT_BANK(sc, 2); 1529 } 1530 1531 void 1532 smc91cxx_statchg(self) 1533 struct device *self; 1534 { 1535 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1536 bus_space_tag_t bst = sc->sc_bst; 1537 bus_space_handle_t bsh = sc->sc_bsh; 1538 int mctl; 1539 1540 SMC_SELECT_BANK(sc, 0); 1541 mctl = bus_space_read_2(bst, bsh, TXMIT_CONTROL_REG_W); 1542 if (sc->sc_mii.mii_media_active & IFM_FDX) 1543 mctl |= TCR_SWFDUP; 1544 else 1545 mctl &= ~TCR_SWFDUP; 1546 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, mctl); 1547 SMC_SELECT_BANK(sc, 2); /* back to operating window */ 1548 } 1549 1550 /* 1551 * One second timer, used to tick the MII. 1552 */ 1553 void 1554 smc91cxx_tick(arg) 1555 void *arg; 1556 { 1557 struct smc91cxx_softc *sc = arg; 1558 int s; 1559 1560 #ifdef DIAGNOSTIC 1561 if ((sc->sc_flags & SMC_FLAGS_HAS_MII) == 0) 1562 panic("smc91cxx_tick"); 1563 #endif 1564 1565 if (!device_is_active(&sc->sc_dev)) 1566 return; 1567 1568 s = splnet(); 1569 mii_tick(&sc->sc_mii); 1570 splx(s); 1571 1572 callout_reset(&sc->sc_mii_callout, hz, smc91cxx_tick, sc); 1573 } 1574 1575