1 /* $NetBSD: smc91cxx.c,v 1.65 2008/04/08 12:07:27 cegger Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com> 42 * All rights reserved. 43 * 44 * Redistribution and use in source and binary forms, with or without 45 * modification, are permitted provided that the following conditions 46 * are met: 47 * 1. Redistributions of source code must retain the above copyright 48 * notice, this list of conditions and the following disclaimer. 49 * 2. Redistributions in binary form must reproduce the above copyright 50 * notice, this list of conditions and the following disclaimer in the 51 * documentation and/or other materials provided with the distribution. 52 * 3. All advertising materials mentioning features or use of this software 53 * must display the following acknowledgement: 54 * This product includes software developed by Gardner Buchanan. 55 * 4. The name of Gardner Buchanan may not be used to endorse or promote 56 * products derived from this software without specific prior written 57 * permission. 58 * 59 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 60 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 61 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 62 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 63 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 64 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 65 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 66 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 67 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 68 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 69 * 70 * from FreeBSD Id: if_sn.c,v 1.4 1996/03/18 15:47:16 gardner Exp 71 */ 72 73 /* 74 * Core driver for the SMC 91Cxx family of Ethernet chips. 75 * 76 * Memory allocation interrupt logic is drived from an SMC 91C90 driver 77 * written for NetBSD/amiga by Michael Hitch. 78 */ 79 80 #include <sys/cdefs.h> 81 __KERNEL_RCSID(0, "$NetBSD: smc91cxx.c,v 1.65 2008/04/08 12:07:27 cegger Exp $"); 82 83 #include "opt_inet.h" 84 #include "bpfilter.h" 85 #include "rnd.h" 86 87 #include <sys/param.h> 88 #include <sys/systm.h> 89 #include <sys/mbuf.h> 90 #include <sys/syslog.h> 91 #include <sys/socket.h> 92 #include <sys/device.h> 93 #include <sys/kernel.h> 94 #include <sys/malloc.h> 95 #include <sys/ioctl.h> 96 #include <sys/errno.h> 97 #if NRND > 0 98 #include <sys/rnd.h> 99 #endif 100 101 #include <sys/bus.h> 102 #include <sys/intr.h> 103 104 #include <net/if.h> 105 #include <net/if_dl.h> 106 #include <net/if_ether.h> 107 #include <net/if_media.h> 108 109 #ifdef INET 110 #include <netinet/in.h> 111 #include <netinet/if_inarp.h> 112 #include <netinet/in_systm.h> 113 #include <netinet/in_var.h> 114 #include <netinet/ip.h> 115 #endif 116 117 118 119 #if NBPFILTER > 0 120 #include <net/bpf.h> 121 #include <net/bpfdesc.h> 122 #endif 123 124 #include <dev/mii/mii.h> 125 #include <dev/mii/miivar.h> 126 #include <dev/mii/mii_bitbang.h> 127 128 #include <dev/ic/smc91cxxreg.h> 129 #include <dev/ic/smc91cxxvar.h> 130 131 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 132 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 133 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 134 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 135 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 136 137 #define bus_space_write_stream_4 bus_space_write_4 138 #define bus_space_read_stream_4 bus_space_read_4 139 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 140 141 /* XXX Hardware padding doesn't work yet(?) */ 142 #define SMC91CXX_SW_PAD 143 144 const char *smc91cxx_idstrs[] = { 145 NULL, /* 0 */ 146 NULL, /* 1 */ 147 NULL, /* 2 */ 148 "SMC91C90/91C92", /* 3 */ 149 "SMC91C94/91C96", /* 4 */ 150 "SMC91C95", /* 5 */ 151 NULL, /* 6 */ 152 "SMC91C100", /* 7 */ 153 "SMC91C100FD", /* 8 */ 154 "SMC91C111", /* 9 */ 155 NULL, /* 10 */ 156 NULL, /* 11 */ 157 NULL, /* 12 */ 158 NULL, /* 13 */ 159 NULL, /* 14 */ 160 NULL, /* 15 */ 161 }; 162 163 /* Supported media types. */ 164 const int smc91cxx_media[] = { 165 IFM_ETHER|IFM_10_T, 166 IFM_ETHER|IFM_10_5, 167 }; 168 #define NSMC91CxxMEDIA (sizeof(smc91cxx_media) / sizeof(smc91cxx_media[0])) 169 170 /* 171 * MII bit-bang glue. 172 */ 173 u_int32_t smc91cxx_mii_bitbang_read(struct device *); 174 void smc91cxx_mii_bitbang_write(struct device *, u_int32_t); 175 176 const struct mii_bitbang_ops smc91cxx_mii_bitbang_ops = { 177 smc91cxx_mii_bitbang_read, 178 smc91cxx_mii_bitbang_write, 179 { 180 MR_MDO, /* MII_BIT_MDO */ 181 MR_MDI, /* MII_BIT_MDI */ 182 MR_MCLK, /* MII_BIT_MDC */ 183 MR_MDOE, /* MII_BIT_DIR_HOST_PHY */ 184 0, /* MII_BIT_DIR_PHY_HOST */ 185 } 186 }; 187 188 /* MII callbacks */ 189 int smc91cxx_mii_readreg(struct device *, int, int); 190 void smc91cxx_mii_writereg(struct device *, int, int, int); 191 void smc91cxx_statchg(struct device *); 192 void smc91cxx_tick(void *); 193 194 int smc91cxx_mediachange(struct ifnet *); 195 void smc91cxx_mediastatus(struct ifnet *, struct ifmediareq *); 196 197 int smc91cxx_set_media(struct smc91cxx_softc *, int); 198 199 void smc91cxx_init(struct smc91cxx_softc *); 200 void smc91cxx_read(struct smc91cxx_softc *); 201 void smc91cxx_reset(struct smc91cxx_softc *); 202 void smc91cxx_start(struct ifnet *); 203 void smc91cxx_copy_tx_frame(struct smc91cxx_softc *, struct mbuf *); 204 void smc91cxx_resume(struct smc91cxx_softc *); 205 void smc91cxx_stop(struct smc91cxx_softc *); 206 void smc91cxx_watchdog(struct ifnet *); 207 int smc91cxx_ioctl(struct ifnet *, u_long, void *); 208 209 static inline int ether_cmp(const void *, const void *); 210 static inline int 211 ether_cmp(va, vb) 212 const void *va, *vb; 213 { 214 const u_int8_t *a = va; 215 const u_int8_t *b = vb; 216 217 return ((a[5] != b[5]) || (a[4] != b[4]) || (a[3] != b[3]) || 218 (a[2] != b[2]) || (a[1] != b[1]) || (a[0] != b[0])); 219 } 220 221 void 222 smc91cxx_attach(sc, myea) 223 struct smc91cxx_softc *sc; 224 u_int8_t *myea; 225 { 226 struct ifnet *ifp = &sc->sc_ec.ec_if; 227 bus_space_tag_t bst = sc->sc_bst; 228 bus_space_handle_t bsh = sc->sc_bsh; 229 struct ifmedia *ifm = &sc->sc_mii.mii_media; 230 const char *idstr; 231 u_int32_t miicapabilities; 232 u_int16_t tmp; 233 u_int8_t enaddr[ETHER_ADDR_LEN]; 234 int i, aui, mult, scale, memsize; 235 char pbuf[9]; 236 237 tmp = bus_space_read_2(bst, bsh, BANK_SELECT_REG_W); 238 /* check magic number */ 239 if ((tmp & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 240 aprint_error_dev(&sc->sc_dev, "failed to detect chip, bsr=%04x\n", tmp); 241 return; 242 } 243 244 /* Make sure the chip is stopped. */ 245 smc91cxx_stop(sc); 246 247 SMC_SELECT_BANK(sc, 3); 248 tmp = bus_space_read_2(bst, bsh, REVISION_REG_W); 249 sc->sc_chipid = RR_ID(tmp); 250 idstr = smc91cxx_idstrs[sc->sc_chipid]; 251 252 aprint_normal_dev(&sc->sc_dev, ""); 253 if (idstr != NULL) 254 aprint_normal("%s, ", idstr); 255 else 256 aprint_normal("unknown chip id %d, ", sc->sc_chipid); 257 aprint_normal("revision %d, ", RR_REV(tmp)); 258 259 SMC_SELECT_BANK(sc, 0); 260 switch (sc->sc_chipid) { 261 default: 262 mult = MCR_MEM_MULT(bus_space_read_2(bst, bsh, MEM_CFG_REG_W)); 263 scale = MIR_SCALE_91C9x; 264 break; 265 266 case CHIP_91C111: 267 mult = MIR_MULT_91C111; 268 scale = MIR_SCALE_91C111; 269 } 270 memsize = bus_space_read_2(bst, bsh, MEM_INFO_REG_W) & MIR_TOTAL_MASK; 271 if (memsize == 255) memsize++; 272 memsize *= scale * mult; 273 274 format_bytes(pbuf, sizeof(pbuf), memsize); 275 aprint_normal("buffer size: %s\n", pbuf); 276 277 /* Read the station address from the chip. */ 278 SMC_SELECT_BANK(sc, 1); 279 if (myea == NULL) { 280 myea = enaddr; 281 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 282 tmp = bus_space_read_2(bst, bsh, IAR_ADDR0_REG_W + i); 283 myea[i + 1] = (tmp >> 8) & 0xff; 284 myea[i] = tmp & 0xff; 285 } 286 } 287 aprint_normal_dev(&sc->sc_dev, "MAC address %s, ", 288 ether_sprintf(myea)); 289 290 /* Initialize the ifnet structure. */ 291 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 292 ifp->if_softc = sc; 293 ifp->if_start = smc91cxx_start; 294 ifp->if_ioctl = smc91cxx_ioctl; 295 ifp->if_watchdog = smc91cxx_watchdog; 296 ifp->if_flags = 297 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 298 IFQ_SET_READY(&ifp->if_snd); 299 300 /* Attach the interface. */ 301 if_attach(ifp); 302 ether_ifattach(ifp, myea); 303 304 /* 305 * Initialize our media structures and MII info. We will 306 * probe the MII if we are on the SMC91Cxx 307 */ 308 sc->sc_mii.mii_ifp = ifp; 309 sc->sc_mii.mii_readreg = smc91cxx_mii_readreg; 310 sc->sc_mii.mii_writereg = smc91cxx_mii_writereg; 311 sc->sc_mii.mii_statchg = smc91cxx_statchg; 312 ifmedia_init(ifm, IFM_IMASK, smc91cxx_mediachange, smc91cxx_mediastatus); 313 314 SMC_SELECT_BANK(sc, 1); 315 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 316 317 miicapabilities = BMSR_MEDIAMASK|BMSR_ANEG; 318 switch (sc->sc_chipid) { 319 case CHIP_91100: 320 /* 321 * The 91100 does not have full-duplex capabilities, 322 * even if the PHY does. 323 */ 324 miicapabilities &= ~(BMSR_100TXFDX | BMSR_10TFDX); 325 case CHIP_91100FD: 326 case CHIP_91C111: 327 if (tmp & CR_MII_SELECT) { 328 aprint_normal("default media MII"); 329 if (sc->sc_chipid == CHIP_91C111) { 330 aprint_normal(" (%s PHY)\n", (tmp & CR_AUI_SELECT) ? 331 "external" : "internal"); 332 sc->sc_internal_phy = !(tmp & CR_AUI_SELECT); 333 } else 334 aprint_normal("\n"); 335 mii_attach(&sc->sc_dev, &sc->sc_mii, miicapabilities, 336 MII_PHY_ANY, MII_OFFSET_ANY, 0); 337 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 338 ifmedia_add(&sc->sc_mii.mii_media, 339 IFM_ETHER|IFM_NONE, 0, NULL); 340 ifmedia_set(&sc->sc_mii.mii_media, 341 IFM_ETHER|IFM_NONE); 342 } else { 343 ifmedia_set(&sc->sc_mii.mii_media, 344 IFM_ETHER|IFM_AUTO); 345 } 346 sc->sc_flags |= SMC_FLAGS_HAS_MII; 347 break; 348 } else 349 if (sc->sc_chipid == CHIP_91C111) { 350 /* 351 * XXX: Should bring it out of low-power mode 352 */ 353 aprint_normal("EPH interface in low power mode\n"); 354 sc->sc_internal_phy = 0; 355 return; 356 } 357 /*FALLTHROUGH*/ 358 default: 359 aprint_normal("default media %s\n", (aui = (tmp & CR_AUI_SELECT)) ? 360 "AUI" : "UTP"); 361 for (i = 0; i < NSMC91CxxMEDIA; i++) 362 ifmedia_add(ifm, smc91cxx_media[i], 0, NULL); 363 ifmedia_set(ifm, IFM_ETHER | (aui ? IFM_10_5 : IFM_10_T)); 364 break; 365 } 366 367 #if NRND > 0 368 rnd_attach_source(&sc->rnd_source, device_xname(&sc->sc_dev), 369 RND_TYPE_NET, 0); 370 #endif 371 372 callout_init(&sc->sc_mii_callout, 0); 373 374 /* The attach is successful. */ 375 sc->sc_flags |= SMC_FLAGS_ATTACHED; 376 } 377 378 /* 379 * Change media according to request. 380 */ 381 int 382 smc91cxx_mediachange(ifp) 383 struct ifnet *ifp; 384 { 385 struct smc91cxx_softc *sc = ifp->if_softc; 386 387 return (smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_media)); 388 } 389 390 int 391 smc91cxx_set_media(sc, media) 392 struct smc91cxx_softc *sc; 393 int media; 394 { 395 bus_space_tag_t bst = sc->sc_bst; 396 bus_space_handle_t bsh = sc->sc_bsh; 397 u_int16_t tmp; 398 int rc; 399 400 /* 401 * If the interface is not currently powered on, just return. 402 * When it is enabled later, smc91cxx_init() will properly set 403 * up the media for us. 404 */ 405 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) 406 return (0); 407 408 if (IFM_TYPE(media) != IFM_ETHER) 409 return (EINVAL); 410 411 if ((sc->sc_flags & SMC_FLAGS_HAS_MII) == 0 || 412 (rc = mii_mediachg(&sc->sc_mii)) == ENXIO) 413 rc = 0; 414 415 switch (IFM_SUBTYPE(media)) { 416 case IFM_10_T: 417 case IFM_10_5: 418 SMC_SELECT_BANK(sc, 1); 419 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 420 if (IFM_SUBTYPE(media) == IFM_10_5) 421 tmp |= CR_AUI_SELECT; 422 else 423 tmp &= ~CR_AUI_SELECT; 424 bus_space_write_2(bst, bsh, CONFIG_REG_W, tmp); 425 delay(20000); /* XXX is this needed? */ 426 break; 427 428 default: 429 return (EINVAL); 430 } 431 432 return rc; 433 } 434 435 /* 436 * Notify the world which media we're using. 437 */ 438 void 439 smc91cxx_mediastatus(ifp, ifmr) 440 struct ifnet *ifp; 441 struct ifmediareq *ifmr; 442 { 443 struct smc91cxx_softc *sc = ifp->if_softc; 444 bus_space_tag_t bst = sc->sc_bst; 445 bus_space_handle_t bsh = sc->sc_bsh; 446 u_int16_t tmp; 447 448 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) { 449 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 450 ifmr->ifm_status = 0; 451 return; 452 } 453 454 /* 455 * If we have MII, go ask the PHY what's going on. 456 */ 457 if (sc->sc_flags & SMC_FLAGS_HAS_MII) { 458 mii_pollstat(&sc->sc_mii); 459 ifmr->ifm_active = sc->sc_mii.mii_media_active; 460 ifmr->ifm_status = sc->sc_mii.mii_media_status; 461 return; 462 } 463 464 SMC_SELECT_BANK(sc, 1); 465 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 466 ifmr->ifm_active = 467 IFM_ETHER | ((tmp & CR_AUI_SELECT) ? IFM_10_5 : IFM_10_T); 468 } 469 470 /* 471 * Reset and initialize the chip. 472 */ 473 void 474 smc91cxx_init(sc) 475 struct smc91cxx_softc *sc; 476 { 477 struct ifnet *ifp = &sc->sc_ec.ec_if; 478 bus_space_tag_t bst = sc->sc_bst; 479 bus_space_handle_t bsh = sc->sc_bsh; 480 u_int16_t tmp; 481 const u_int8_t *enaddr; 482 int s, i; 483 484 s = splnet(); 485 486 /* 487 * This resets the registers mostly to defaults, but doesn't 488 * affect the EEPROM. After the reset cycle, we pause briefly 489 * for the chip to recover. 490 * 491 * XXX how long are we really supposed to delay? --thorpej 492 */ 493 SMC_SELECT_BANK(sc, 0); 494 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, RCR_SOFTRESET); 495 delay(100); 496 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); 497 delay(200); 498 499 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); 500 501 /* Set the Ethernet address. */ 502 SMC_SELECT_BANK(sc, 1); 503 enaddr = (const u_int8_t *)CLLADDR(ifp->if_sadl); 504 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 505 tmp = enaddr[i + 1] << 8 | enaddr[i]; 506 bus_space_write_2(bst, bsh, IAR_ADDR0_REG_W + i, tmp); 507 } 508 509 /* 510 * Set the control register to automatically release successfully 511 * transmitted packets (making the best use of our limited memory) 512 * and enable the EPH interrupt on certain TX errors. 513 */ 514 bus_space_write_2(bst, bsh, CONTROL_REG_W, (CTR_AUTO_RELEASE | 515 CTR_TE_ENABLE | CTR_CR_ENABLE | CTR_LE_ENABLE)); 516 517 /* 518 * Reset the MMU and wait for it to be un-busy. 519 */ 520 SMC_SELECT_BANK(sc, 2); 521 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RESET); 522 for (;;) { 523 tmp = bus_space_read_2(bst, bsh, MMU_CMD_REG_W); 524 if (tmp == 0xffff) /* card went away! */ 525 return; 526 if ((tmp & MMUCR_BUSY) == 0) 527 break; 528 } 529 530 /* 531 * Disable all interrupts. 532 */ 533 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0); 534 535 /* 536 * On the 91c111, enable auto-negotiation, and set the LED 537 * status pins to something sane. 538 * XXX: Should be some way for MD code to decide the latter. 539 */ 540 SMC_SELECT_BANK(sc, 0); 541 if (sc->sc_chipid == CHIP_91C111) { 542 bus_space_write_2(bst, bsh, RX_PHY_CONTROL_REG_W, 543 RPC_ANEG | 544 (RPC_LS_LINK_DETECT << RPC_LSA_SHIFT) | 545 (RPC_LS_TXRX << RPC_LSB_SHIFT)); 546 } 547 548 /* 549 * Set current media. 550 */ 551 smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_cur->ifm_media); 552 553 /* 554 * Set the receive filter. We want receive enable and auto 555 * strip of CRC from received packet. If we are in promisc. mode, 556 * then set that bit as well. 557 * 558 * XXX Initialize multicast filter. For now, we just accept 559 * XXX all multicast. 560 */ 561 SMC_SELECT_BANK(sc, 0); 562 563 tmp = RCR_ENABLE | RCR_STRIP_CRC | RCR_ALMUL; 564 if (ifp->if_flags & IFF_PROMISC) 565 tmp |= RCR_PROMISC; 566 567 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, tmp); 568 569 /* 570 * Set transmitter control to "enabled". 571 */ 572 tmp = TCR_ENABLE; 573 574 #ifndef SMC91CXX_SW_PAD 575 /* 576 * Enable hardware padding of transmitted packets. 577 * XXX doesn't work? 578 */ 579 tmp |= TCR_PAD_ENABLE; 580 #endif 581 582 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, tmp); 583 584 /* 585 * Now, enable interrupts. 586 */ 587 SMC_SELECT_BANK(sc, 2); 588 589 if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy) { 590 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 591 IM_EPH_INT | IM_RX_OVRN_INT | 592 IM_RCV_INT | IM_TX_INT | IM_MD_INT); 593 } else { 594 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 595 IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT | IM_TX_INT); 596 } 597 598 /* Interface is now running, with no output active. */ 599 ifp->if_flags |= IFF_RUNNING; 600 ifp->if_flags &= ~IFF_OACTIVE; 601 602 if (sc->sc_flags & SMC_FLAGS_HAS_MII) { 603 /* Start the one second clock. */ 604 callout_reset(&sc->sc_mii_callout, hz, smc91cxx_tick, sc); 605 } 606 607 /* 608 * Attempt to start any pending transmission. 609 */ 610 smc91cxx_start(ifp); 611 612 splx(s); 613 } 614 615 /* 616 * Start output on an interface. 617 * Must be called at splnet or interrupt level. 618 */ 619 void 620 smc91cxx_start(ifp) 621 struct ifnet *ifp; 622 { 623 struct smc91cxx_softc *sc = ifp->if_softc; 624 bus_space_tag_t bst = sc->sc_bst; 625 bus_space_handle_t bsh = sc->sc_bsh; 626 u_int len; 627 struct mbuf *m; 628 u_int16_t length, npages; 629 u_int8_t packetno; 630 int timo, pad; 631 632 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 633 return; 634 635 again: 636 /* 637 * Peek at the next packet. 638 */ 639 IFQ_POLL(&ifp->if_snd, m); 640 if (m == NULL) 641 return; 642 643 /* 644 * Compute the frame length and set pad to give an overall even 645 * number of bytes. Below, we assume that the packet length 646 * is even. 647 */ 648 for (len = 0; m != NULL; m = m->m_next) 649 len += m->m_len; 650 pad = (len & 1); 651 652 /* 653 * We drop packets that are too large. Perhaps we should 654 * truncate them instead? 655 */ 656 if ((len + pad) > (ETHER_MAX_LEN - ETHER_CRC_LEN)) { 657 printf("%s: large packet discarded\n", device_xname(&sc->sc_dev)); 658 ifp->if_oerrors++; 659 IFQ_DEQUEUE(&ifp->if_snd, m); 660 m_freem(m); 661 goto readcheck; 662 } 663 664 #ifdef SMC91CXX_SW_PAD 665 /* 666 * Not using hardware padding; pad to ETHER_MIN_LEN. 667 */ 668 if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 669 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 670 #endif 671 672 length = pad + len; 673 674 /* 675 * The MMU has a 256 byte page size. The MMU expects us to 676 * ask for "npages - 1". We include space for the status word, 677 * byte count, and control bytes in the allocation request. 678 */ 679 npages = (length + 6) >> 8; 680 681 /* 682 * Now allocate the memory. 683 */ 684 SMC_SELECT_BANK(sc, 2); 685 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ALLOC | npages); 686 687 timo = MEMORY_WAIT_TIME; 688 do { 689 if (bus_space_read_1(bst, bsh, INTR_STAT_REG_B) & IM_ALLOC_INT) 690 break; 691 delay(1); 692 } while (--timo); 693 694 packetno = bus_space_read_1(bst, bsh, ALLOC_RESULT_REG_B); 695 696 if (packetno & ARR_FAILED || timo == 0) { 697 /* 698 * No transmit memory is available. Record the number 699 * of requestd pages and enable the allocation completion 700 * interrupt. Set up the watchdog timer in case we miss 701 * the interrupt. Mark the interface as active so that 702 * no one else attempts to transmit while we're allocating 703 * memory. 704 */ 705 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 706 bus_space_read_1(bst, bsh, INTR_MASK_REG_B) | IM_ALLOC_INT); 707 708 ifp->if_timer = 5; 709 ifp->if_flags |= IFF_OACTIVE; 710 711 return; 712 } 713 714 /* 715 * We have a packet number - set the data window. 716 */ 717 bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno); 718 719 /* 720 * Point to the beginning of the packet. 721 */ 722 bus_space_write_2(bst, bsh, POINTER_REG_W, PTR_AUTOINC /* | 0x0000 */); 723 724 /* 725 * Send the packet length (+6 for stats, length, and control bytes) 726 * and the status word (set to zeros). 727 */ 728 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 729 bus_space_write_2(bst, bsh, DATA_REG_W, (length + 6) & 0x7ff); 730 731 /* 732 * Get the packet from the kernel. This will include the Ethernet 733 * frame header, MAC address, etc. 734 */ 735 IFQ_DEQUEUE(&ifp->if_snd, m); 736 737 /* 738 * Push the packet out to the card. 739 */ 740 smc91cxx_copy_tx_frame(sc, m); 741 742 #ifdef SMC91CXX_SW_PAD 743 /* 744 * Push out padding. 745 */ 746 while (pad > 1) { 747 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 748 pad -= 2; 749 } 750 if (pad) 751 bus_space_write_1(bst, bsh, DATA_REG_B, 0); 752 #endif 753 754 /* 755 * Push out control byte and unused packet byte. The control byte 756 * is 0, meaning the packet is even lengthed and no special 757 * CRC handling is necessary. 758 */ 759 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 760 761 /* 762 * Enable transmit interrupts and let the chip go. Set a watchdog 763 * in case we miss the interrupt. 764 */ 765 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 766 bus_space_read_1(bst, bsh, INTR_MASK_REG_B) | 767 IM_TX_INT | IM_TX_EMPTY_INT); 768 769 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ENQUEUE); 770 771 ifp->if_timer = 5; 772 773 #if NBPFILTER > 0 774 /* Hand off a copy to the bpf. */ 775 if (ifp->if_bpf) 776 bpf_mtap(ifp->if_bpf, m); 777 #endif 778 779 ifp->if_opackets++; 780 m_freem(m); 781 782 readcheck: 783 /* 784 * Check for incoming pcakets. We don't want to overflow the small 785 * RX FIFO. If nothing has arrived, attempt to queue another 786 * transmit packet. 787 */ 788 if (bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & FIFO_REMPTY) 789 goto again; 790 } 791 792 /* 793 * Squirt a (possibly misaligned) mbuf to the device 794 */ 795 void 796 smc91cxx_copy_tx_frame(sc, m0) 797 struct smc91cxx_softc *sc; 798 struct mbuf *m0; 799 { 800 bus_space_tag_t bst = sc->sc_bst; 801 bus_space_handle_t bsh = sc->sc_bsh; 802 struct mbuf *m; 803 int len, leftover; 804 u_int16_t dbuf; 805 u_int8_t *p; 806 #ifdef DIAGNOSTIC 807 u_int8_t *lim; 808 #endif 809 810 /* start out with no leftover data */ 811 leftover = 0; 812 dbuf = 0; 813 814 /* Process the chain of mbufs */ 815 for (m = m0; m != NULL; m = m->m_next) { 816 /* 817 * Process all of the data in a single mbuf. 818 */ 819 p = mtod(m, u_int8_t *); 820 len = m->m_len; 821 #ifdef DIAGNOSTIC 822 lim = p + len; 823 #endif 824 825 while (len > 0) { 826 if (leftover) { 827 /* 828 * Data left over (from mbuf or realignment). 829 * Buffer the next byte, and write it and 830 * the leftover data out. 831 */ 832 dbuf |= *p++ << 8; 833 len--; 834 bus_space_write_2(bst, bsh, DATA_REG_W, dbuf); 835 leftover = 0; 836 } else if ((long) p & 1) { 837 /* 838 * Misaligned data. Buffer the next byte. 839 */ 840 dbuf = *p++; 841 len--; 842 leftover = 1; 843 } else { 844 /* 845 * Aligned data. This is the case we like. 846 * 847 * Write-region out as much as we can, then 848 * buffer the remaining byte (if any). 849 */ 850 leftover = len & 1; 851 len &= ~1; 852 bus_space_write_multi_stream_2(bst, bsh, 853 DATA_REG_W, (u_int16_t *)p, len >> 1); 854 p += len; 855 856 if (leftover) 857 dbuf = *p++; 858 len = 0; 859 } 860 } 861 if (len < 0) 862 panic("smc91cxx_copy_tx_frame: negative len"); 863 #ifdef DIAGNOSTIC 864 if (p != lim) 865 panic("smc91cxx_copy_tx_frame: p != lim"); 866 #endif 867 } 868 if (leftover) 869 bus_space_write_1(bst, bsh, DATA_REG_B, dbuf); 870 } 871 872 /* 873 * Interrupt service routine. 874 */ 875 int 876 smc91cxx_intr(arg) 877 void *arg; 878 { 879 struct smc91cxx_softc *sc = arg; 880 struct ifnet *ifp = &sc->sc_ec.ec_if; 881 bus_space_tag_t bst = sc->sc_bst; 882 bus_space_handle_t bsh = sc->sc_bsh; 883 u_int8_t mask, interrupts, status; 884 u_int16_t packetno, tx_status, card_stats; 885 886 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 || 887 !device_is_active(&sc->sc_dev)) 888 return (0); 889 890 SMC_SELECT_BANK(sc, 2); 891 892 /* 893 * Obtain the current interrupt mask. 894 */ 895 mask = bus_space_read_1(bst, bsh, INTR_MASK_REG_B); 896 897 /* 898 * Get the set of interrupt which occurred and eliminate any 899 * which are not enabled. 900 */ 901 interrupts = bus_space_read_1(bst, bsh, INTR_STAT_REG_B); 902 status = interrupts & mask; 903 904 /* Ours? */ 905 if (status == 0) 906 return (0); 907 908 /* 909 * It's ours; disable all interrupts while we process them. 910 */ 911 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0); 912 913 /* 914 * Receive overrun interrupts. 915 */ 916 if (status & IM_RX_OVRN_INT) { 917 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, IM_RX_OVRN_INT); 918 ifp->if_ierrors++; 919 } 920 921 /* 922 * Receive interrupts. 923 */ 924 if (status & IM_RCV_INT) { 925 #if 1 /* DIAGNOSTIC */ 926 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 927 if (packetno & FIFO_REMPTY) { 928 aprint_error_dev(&sc->sc_dev, "receive interrupt on empty fifo\n"); 929 goto out; 930 } else 931 #endif 932 smc91cxx_read(sc); 933 } 934 935 /* 936 * Memory allocation interrupts. 937 */ 938 if (status & IM_ALLOC_INT) { 939 /* Disable this interrupt. */ 940 mask &= ~IM_ALLOC_INT; 941 942 /* 943 * Release the just-allocated memory. We will reallocate 944 * it through the normal start logic. 945 */ 946 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 947 /* XXX bound this loop! */ ; 948 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT); 949 950 ifp->if_flags &= ~IFF_OACTIVE; 951 ifp->if_timer = 0; 952 } 953 954 /* 955 * Transmit complete interrupt. Handle transmission error messages. 956 * This will only be called on error condition because of AUTO RELEASE 957 * mode. 958 */ 959 if (status & IM_TX_INT) { 960 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, IM_TX_INT); 961 962 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & 963 FIFO_TX_MASK; 964 965 /* 966 * Select this as the packet to read from. 967 */ 968 bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno); 969 970 /* 971 * Position the pointer to the beginning of the packet. 972 */ 973 bus_space_write_2(bst, bsh, POINTER_REG_W, 974 PTR_AUTOINC | PTR_READ /* | 0x0000 */); 975 976 /* 977 * Fetch the TX status word. This will be a copy of 978 * the EPH_STATUS_REG_W at the time of the transmission 979 * failure. 980 */ 981 tx_status = bus_space_read_2(bst, bsh, DATA_REG_W); 982 983 if (tx_status & EPHSR_TX_SUC) 984 printf("%s: successful packet caused TX interrupt?!\n", 985 device_xname(&sc->sc_dev)); 986 else 987 ifp->if_oerrors++; 988 989 if (tx_status & EPHSR_LATCOL) 990 ifp->if_collisions++; 991 992 /* 993 * Some of these errors disable the transmitter; reenable it. 994 */ 995 SMC_SELECT_BANK(sc, 0); 996 #ifdef SMC91CXX_SW_PAD 997 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, TCR_ENABLE); 998 #else 999 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 1000 TCR_ENABLE | TCR_PAD_ENABLE); 1001 #endif 1002 1003 /* 1004 * Kill the failed packet and wait for the MMU to unbusy. 1005 */ 1006 SMC_SELECT_BANK(sc, 2); 1007 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 1008 /* XXX bound this loop! */ ; 1009 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT); 1010 1011 ifp->if_timer = 0; 1012 } 1013 1014 /* 1015 * Transmit underrun interrupts. We use this opportunity to 1016 * update transmit statistics from the card. 1017 */ 1018 if (status & IM_TX_EMPTY_INT) { 1019 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, IM_TX_EMPTY_INT); 1020 1021 /* Disable this interrupt. */ 1022 mask &= ~IM_TX_EMPTY_INT; 1023 1024 SMC_SELECT_BANK(sc, 0); 1025 card_stats = bus_space_read_2(bst, bsh, COUNTER_REG_W); 1026 1027 /* Single collisions. */ 1028 ifp->if_collisions += card_stats & ECR_COLN_MASK; 1029 1030 /* Multiple collisions. */ 1031 ifp->if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4; 1032 1033 SMC_SELECT_BANK(sc, 2); 1034 1035 ifp->if_timer = 0; 1036 } 1037 1038 if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy && 1039 (status & IM_MD_INT)) { 1040 /* 1041 * Internal PHY status change 1042 */ 1043 mii_tick(&sc->sc_mii); 1044 } 1045 1046 /* 1047 * Other errors. Reset the interface. 1048 */ 1049 if (status & IM_EPH_INT) { 1050 smc91cxx_stop(sc); 1051 smc91cxx_init(sc); 1052 } 1053 1054 /* 1055 * Attempt to queue more packets for transmission. 1056 */ 1057 smc91cxx_start(ifp); 1058 1059 out: 1060 /* 1061 * Reenable the interrupts we wish to receive now that processing 1062 * is complete. 1063 */ 1064 mask |= bus_space_read_1(bst, bsh, INTR_MASK_REG_B); 1065 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, mask); 1066 1067 #if NRND > 0 1068 if (status) 1069 rnd_add_uint32(&sc->rnd_source, status); 1070 #endif 1071 1072 return (1); 1073 } 1074 1075 /* 1076 * Read a packet from the card and pass it up to the kernel. 1077 * NOTE! WE EXPECT TO BE IN REGISTER WINDOW 2! 1078 */ 1079 void 1080 smc91cxx_read(sc) 1081 struct smc91cxx_softc *sc; 1082 { 1083 struct ifnet *ifp = &sc->sc_ec.ec_if; 1084 bus_space_tag_t bst = sc->sc_bst; 1085 bus_space_handle_t bsh = sc->sc_bsh; 1086 struct ether_header *eh; 1087 struct mbuf *m; 1088 u_int16_t status, packetno, packetlen; 1089 u_int8_t *data; 1090 u_int32_t dr; 1091 1092 again: 1093 /* 1094 * Set data pointer to the beginning of the packet. Since 1095 * PTR_RCV is set, the packet number will be found automatically 1096 * in FIFO_PORTS_REG_W, FIFO_RX_MASK. 1097 */ 1098 bus_space_write_2(bst, bsh, POINTER_REG_W, 1099 PTR_READ | PTR_RCV | PTR_AUTOINC /* | 0x0000 */); 1100 1101 /* 1102 * First two words are status and packet length. 1103 */ 1104 if ((sc->sc_flags & SMC_FLAGS_32BIT_READ) == 0) { 1105 status = bus_space_read_2(bst, bsh, DATA_REG_W); 1106 packetlen = bus_space_read_2(bst, bsh, DATA_REG_W); 1107 } else { 1108 dr = bus_space_read_4(bst, bsh, DATA_REG_W); 1109 #if BYTE_ORDER == LITTLE_ENDIAN 1110 status = (u_int16_t)dr; 1111 packetlen = (u_int16_t)(dr >> 16); 1112 #else 1113 packetlen = (u_int16_t)dr; 1114 status = (u_int16_t)(dr >> 16); 1115 #endif 1116 } 1117 1118 packetlen &= RLEN_MASK; 1119 1120 /* 1121 * The packet length includes 3 extra words: status, length, 1122 * and an extra word that includes the control byte. 1123 */ 1124 packetlen -= 6; 1125 1126 /* 1127 * Account for receive errors and discard. 1128 */ 1129 if (status & RS_ERRORS) { 1130 ifp->if_ierrors++; 1131 goto out; 1132 } 1133 1134 /* 1135 * Adjust for odd-length packet. 1136 */ 1137 if (status & RS_ODDFRAME) 1138 packetlen++; 1139 1140 /* 1141 * Allocate a header mbuf. 1142 */ 1143 MGETHDR(m, M_DONTWAIT, MT_DATA); 1144 if (m == NULL) 1145 goto out; 1146 m->m_pkthdr.rcvif = ifp; 1147 m->m_pkthdr.len = packetlen; 1148 1149 /* 1150 * Always put the packet in a cluster. 1151 * XXX should chain small mbufs if less than threshold. 1152 */ 1153 MCLGET(m, M_DONTWAIT); 1154 if ((m->m_flags & M_EXT) == 0) { 1155 m_freem(m); 1156 ifp->if_ierrors++; 1157 aprint_error_dev(&sc->sc_dev, "can't allocate cluster for incoming packet\n"); 1158 goto out; 1159 } 1160 1161 /* 1162 * Pull the packet off the interface. Make sure the payload 1163 * is aligned. 1164 */ 1165 if ((sc->sc_flags & SMC_FLAGS_32BIT_READ) == 0) { 1166 m->m_data = (char *) ALIGN(mtod(m, char *) + 1167 sizeof(struct ether_header)) - sizeof(struct ether_header); 1168 1169 eh = mtod(m, struct ether_header *); 1170 data = mtod(m, u_int8_t *); 1171 if (packetlen > 1) 1172 bus_space_read_multi_stream_2(bst, bsh, DATA_REG_W, 1173 (u_int16_t *)data, packetlen >> 1); 1174 if (packetlen & 1) { 1175 data += packetlen & ~1; 1176 *data = bus_space_read_1(bst, bsh, DATA_REG_B); 1177 } 1178 } else { 1179 u_int8_t *dp; 1180 1181 m->m_data = (void *) ALIGN(mtod(m, void *)); 1182 eh = mtod(m, struct ether_header *); 1183 dp = data = mtod(m, u_int8_t *); 1184 if (packetlen > 3) 1185 bus_space_read_multi_stream_4(bst, bsh, DATA_REG_W, 1186 (u_int32_t *)data, packetlen >> 2); 1187 if (packetlen & 3) { 1188 data += packetlen & ~3; 1189 *((u_int32_t *)data) = 1190 bus_space_read_stream_4(bst, bsh, DATA_REG_W); 1191 } 1192 } 1193 1194 ifp->if_ipackets++; 1195 1196 /* 1197 * Make sure to behave as IFF_SIMPLEX in all cases. 1198 * This is to cope with SMC91C92 (Megahertz XJ10BT), which 1199 * loops back packets to itself on promiscuous mode. 1200 * (should be ensured by chipset configuration) 1201 */ 1202 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1203 /* 1204 * Drop packet looped back from myself. 1205 */ 1206 if (ether_cmp(eh->ether_shost, CLLADDR(ifp->if_sadl)) == 0) { 1207 m_freem(m); 1208 goto out; 1209 } 1210 } 1211 1212 m->m_pkthdr.len = m->m_len = packetlen; 1213 1214 #if NBPFILTER > 0 1215 /* 1216 * Hand the packet off to bpf listeners. 1217 */ 1218 if (ifp->if_bpf) 1219 bpf_mtap(ifp->if_bpf, m); 1220 #endif 1221 1222 (*ifp->if_input)(ifp, m); 1223 1224 out: 1225 /* 1226 * Tell the card to free the memory occupied by this packet. 1227 */ 1228 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 1229 /* XXX bound this loop! */ ; 1230 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RELEASE); 1231 1232 /* 1233 * Check for another packet. 1234 */ 1235 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 1236 if (packetno & FIFO_REMPTY) 1237 return; 1238 goto again; 1239 } 1240 1241 /* 1242 * Process an ioctl request. 1243 */ 1244 int 1245 smc91cxx_ioctl(ifp, cmd, data) 1246 struct ifnet *ifp; 1247 u_long cmd; 1248 void *data; 1249 { 1250 struct smc91cxx_softc *sc = ifp->if_softc; 1251 struct ifaddr *ifa = (struct ifaddr *)data; 1252 struct ifreq *ifr = (struct ifreq *)data; 1253 int s, error = 0; 1254 1255 s = splnet(); 1256 1257 switch (cmd) { 1258 case SIOCSIFADDR: 1259 if ((error = smc91cxx_enable(sc)) != 0) 1260 break; 1261 ifp->if_flags |= IFF_UP; 1262 switch (ifa->ifa_addr->sa_family) { 1263 #ifdef INET 1264 case AF_INET: 1265 smc91cxx_init(sc); 1266 arp_ifinit(ifp, ifa); 1267 break; 1268 #endif 1269 default: 1270 smc91cxx_init(sc); 1271 break; 1272 } 1273 break; 1274 1275 1276 case SIOCSIFFLAGS: 1277 if ((ifp->if_flags & IFF_UP) == 0 && 1278 (ifp->if_flags & IFF_RUNNING) != 0) { 1279 /* 1280 * If interface is marked down and it is running, 1281 * stop it. 1282 */ 1283 smc91cxx_stop(sc); 1284 ifp->if_flags &= ~IFF_RUNNING; 1285 smc91cxx_disable(sc); 1286 } else if ((ifp->if_flags & IFF_UP) != 0 && 1287 (ifp->if_flags & IFF_RUNNING) == 0) { 1288 /* 1289 * If interface is marked up and it is stopped, 1290 * start it. 1291 */ 1292 if ((error = smc91cxx_enable(sc)) != 0) 1293 break; 1294 smc91cxx_init(sc); 1295 } else if ((ifp->if_flags & IFF_UP) != 0) { 1296 /* 1297 * Reset the interface to pick up changes in any 1298 * other flags that affect hardware registers. 1299 */ 1300 smc91cxx_reset(sc); 1301 } 1302 break; 1303 1304 case SIOCADDMULTI: 1305 case SIOCDELMULTI: 1306 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) { 1307 error = EIO; 1308 break; 1309 } 1310 1311 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1312 /* 1313 * Multicast list has changed; set the hardware 1314 * filter accordingly. 1315 */ 1316 if (ifp->if_flags & IFF_RUNNING) 1317 smc91cxx_reset(sc); 1318 error = 0; 1319 } 1320 break; 1321 1322 case SIOCGIFMEDIA: 1323 case SIOCSIFMEDIA: 1324 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1325 break; 1326 1327 default: 1328 error = EINVAL; 1329 break; 1330 } 1331 1332 splx(s); 1333 return (error); 1334 } 1335 1336 /* 1337 * Reset the interface. 1338 */ 1339 void 1340 smc91cxx_reset(sc) 1341 struct smc91cxx_softc *sc; 1342 { 1343 int s; 1344 1345 s = splnet(); 1346 smc91cxx_stop(sc); 1347 smc91cxx_init(sc); 1348 splx(s); 1349 } 1350 1351 /* 1352 * Watchdog timer. 1353 */ 1354 void 1355 smc91cxx_watchdog(ifp) 1356 struct ifnet *ifp; 1357 { 1358 struct smc91cxx_softc *sc = ifp->if_softc; 1359 1360 log(LOG_ERR, "%s: device timeout\n", device_xname(&sc->sc_dev)); 1361 ifp->if_oerrors++; 1362 smc91cxx_reset(sc); 1363 } 1364 1365 /* 1366 * Stop output on the interface. 1367 */ 1368 void 1369 smc91cxx_stop(sc) 1370 struct smc91cxx_softc *sc; 1371 { 1372 bus_space_tag_t bst = sc->sc_bst; 1373 bus_space_handle_t bsh = sc->sc_bsh; 1374 1375 /* 1376 * Clear interrupt mask; disable all interrupts. 1377 */ 1378 SMC_SELECT_BANK(sc, 2); 1379 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, 0); 1380 1381 /* 1382 * Disable transmitter and receiver. 1383 */ 1384 SMC_SELECT_BANK(sc, 0); 1385 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); 1386 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); 1387 1388 /* 1389 * Cancel watchdog timer. 1390 */ 1391 sc->sc_ec.ec_if.if_timer = 0; 1392 } 1393 1394 /* 1395 * Enable power on the interface. 1396 */ 1397 int 1398 smc91cxx_enable(sc) 1399 struct smc91cxx_softc *sc; 1400 { 1401 1402 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 && sc->sc_enable != NULL) { 1403 if ((*sc->sc_enable)(sc) != 0) { 1404 aprint_error_dev(&sc->sc_dev, "device enable failed\n"); 1405 return (EIO); 1406 } 1407 } 1408 1409 sc->sc_flags |= SMC_FLAGS_ENABLED; 1410 return (0); 1411 } 1412 1413 /* 1414 * Disable power on the interface. 1415 */ 1416 void 1417 smc91cxx_disable(sc) 1418 struct smc91cxx_softc *sc; 1419 { 1420 1421 if ((sc->sc_flags & SMC_FLAGS_ENABLED) != 0 && sc->sc_disable != NULL) { 1422 (*sc->sc_disable)(sc); 1423 sc->sc_flags &= ~SMC_FLAGS_ENABLED; 1424 } 1425 } 1426 1427 int 1428 smc91cxx_activate(self, act) 1429 struct device *self; 1430 enum devact act; 1431 { 1432 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1433 int rv = 0, s; 1434 1435 s = splnet(); 1436 switch (act) { 1437 case DVACT_ACTIVATE: 1438 rv = EOPNOTSUPP; 1439 break; 1440 1441 case DVACT_DEACTIVATE: 1442 if_deactivate(&sc->sc_ec.ec_if); 1443 break; 1444 } 1445 splx(s); 1446 return (rv); 1447 } 1448 1449 int 1450 smc91cxx_detach(struct device *self, int flags) 1451 { 1452 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1453 struct ifnet *ifp = &sc->sc_ec.ec_if; 1454 1455 /* Succeed now if there's no work to do. */ 1456 if ((sc->sc_flags & SMC_FLAGS_ATTACHED) == 0) 1457 return (0); 1458 1459 1460 /* smc91cxx_disable() checks SMC_FLAGS_ENABLED */ 1461 smc91cxx_disable(sc); 1462 1463 /* smc91cxx_attach() never fails */ 1464 1465 /* Delete all media. */ 1466 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1467 1468 #if NRND > 0 1469 rnd_detach_source(&sc->rnd_source); 1470 #endif 1471 ether_ifdetach(ifp); 1472 if_detach(ifp); 1473 1474 return (0); 1475 } 1476 1477 u_int32_t 1478 smc91cxx_mii_bitbang_read(self) 1479 struct device *self; 1480 { 1481 struct smc91cxx_softc *sc = (void *) self; 1482 1483 /* We're already in bank 3. */ 1484 return (bus_space_read_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W)); 1485 } 1486 1487 void 1488 smc91cxx_mii_bitbang_write(self, val) 1489 struct device *self; 1490 u_int32_t val; 1491 { 1492 struct smc91cxx_softc *sc = (void *) self; 1493 1494 /* We're already in bank 3. */ 1495 bus_space_write_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W, val); 1496 } 1497 1498 int 1499 smc91cxx_mii_readreg(self, phy, reg) 1500 struct device *self; 1501 int phy, reg; 1502 { 1503 struct smc91cxx_softc *sc = (void *) self; 1504 int val; 1505 1506 SMC_SELECT_BANK(sc, 3); 1507 1508 val = mii_bitbang_readreg(self, &smc91cxx_mii_bitbang_ops, phy, reg); 1509 1510 SMC_SELECT_BANK(sc, 2); 1511 1512 return (val); 1513 } 1514 1515 void 1516 smc91cxx_mii_writereg(self, phy, reg, val) 1517 struct device *self; 1518 int phy, reg, val; 1519 { 1520 struct smc91cxx_softc *sc = (void *) self; 1521 1522 SMC_SELECT_BANK(sc, 3); 1523 1524 mii_bitbang_writereg(self, &smc91cxx_mii_bitbang_ops, phy, reg, val); 1525 1526 SMC_SELECT_BANK(sc, 2); 1527 } 1528 1529 void 1530 smc91cxx_statchg(self) 1531 struct device *self; 1532 { 1533 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1534 bus_space_tag_t bst = sc->sc_bst; 1535 bus_space_handle_t bsh = sc->sc_bsh; 1536 int mctl; 1537 1538 SMC_SELECT_BANK(sc, 0); 1539 mctl = bus_space_read_2(bst, bsh, TXMIT_CONTROL_REG_W); 1540 if (sc->sc_mii.mii_media_active & IFM_FDX) 1541 mctl |= TCR_SWFDUP; 1542 else 1543 mctl &= ~TCR_SWFDUP; 1544 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, mctl); 1545 SMC_SELECT_BANK(sc, 2); /* back to operating window */ 1546 } 1547 1548 /* 1549 * One second timer, used to tick the MII. 1550 */ 1551 void 1552 smc91cxx_tick(arg) 1553 void *arg; 1554 { 1555 struct smc91cxx_softc *sc = arg; 1556 int s; 1557 1558 #ifdef DIAGNOSTIC 1559 if ((sc->sc_flags & SMC_FLAGS_HAS_MII) == 0) 1560 panic("smc91cxx_tick"); 1561 #endif 1562 1563 if (!device_is_active(&sc->sc_dev)) 1564 return; 1565 1566 s = splnet(); 1567 mii_tick(&sc->sc_mii); 1568 splx(s); 1569 1570 callout_reset(&sc->sc_mii_callout, hz, smc91cxx_tick, sc); 1571 } 1572 1573