1 /* $NetBSD: smc91cxx.c,v 1.77 2010/01/19 22:06:25 pooka Exp $ */ 2 3 /*- 4 * Copyright (c) 1997 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Copyright (c) 1996 Gardner Buchanan <gbuchanan@shl.com> 35 * All rights reserved. 36 * 37 * Redistribution and use in source and binary forms, with or without 38 * modification, are permitted provided that the following conditions 39 * are met: 40 * 1. Redistributions of source code must retain the above copyright 41 * notice, this list of conditions and the following disclaimer. 42 * 2. Redistributions in binary form must reproduce the above copyright 43 * notice, this list of conditions and the following disclaimer in the 44 * documentation and/or other materials provided with the distribution. 45 * 3. All advertising materials mentioning features or use of this software 46 * must display the following acknowledgement: 47 * This product includes software developed by Gardner Buchanan. 48 * 4. The name of Gardner Buchanan may not be used to endorse or promote 49 * products derived from this software without specific prior written 50 * permission. 51 * 52 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 53 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 54 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 55 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 56 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 57 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 58 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 59 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 60 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 61 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 62 * 63 * from FreeBSD Id: if_sn.c,v 1.4 1996/03/18 15:47:16 gardner Exp 64 */ 65 66 /* 67 * Core driver for the SMC 91Cxx family of Ethernet chips. 68 * 69 * Memory allocation interrupt logic is drived from an SMC 91C90 driver 70 * written for NetBSD/amiga by Michael Hitch. 71 */ 72 73 #include <sys/cdefs.h> 74 __KERNEL_RCSID(0, "$NetBSD: smc91cxx.c,v 1.77 2010/01/19 22:06:25 pooka Exp $"); 75 76 #include "opt_inet.h" 77 #include "rnd.h" 78 79 #include <sys/param.h> 80 #include <sys/systm.h> 81 #include <sys/mbuf.h> 82 #include <sys/syslog.h> 83 #include <sys/socket.h> 84 #include <sys/device.h> 85 #include <sys/kernel.h> 86 #include <sys/malloc.h> 87 #include <sys/ioctl.h> 88 #include <sys/errno.h> 89 #if NRND > 0 90 #include <sys/rnd.h> 91 #endif 92 93 #include <sys/bus.h> 94 #include <sys/intr.h> 95 96 #include <uvm/uvm_extern.h> 97 98 #include <net/if.h> 99 #include <net/if_dl.h> 100 #include <net/if_ether.h> 101 #include <net/if_media.h> 102 103 #ifdef INET 104 #include <netinet/in.h> 105 #include <netinet/if_inarp.h> 106 #include <netinet/in_systm.h> 107 #include <netinet/in_var.h> 108 #include <netinet/ip.h> 109 #endif 110 111 #include <net/bpf.h> 112 #include <net/bpfdesc.h> 113 114 #include <dev/mii/mii.h> 115 #include <dev/mii/miivar.h> 116 #include <dev/mii/mii_bitbang.h> 117 118 #include <dev/ic/smc91cxxreg.h> 119 #include <dev/ic/smc91cxxvar.h> 120 121 #ifndef __BUS_SPACE_HAS_STREAM_METHODS 122 #define bus_space_write_multi_stream_2 bus_space_write_multi_2 123 #define bus_space_write_multi_stream_4 bus_space_write_multi_4 124 #define bus_space_read_multi_stream_2 bus_space_read_multi_2 125 #define bus_space_read_multi_stream_4 bus_space_read_multi_4 126 127 #define bus_space_write_stream_4 bus_space_write_4 128 #define bus_space_read_stream_4 bus_space_read_4 129 #endif /* __BUS_SPACE_HAS_STREAM_METHODS */ 130 131 /* XXX Hardware padding doesn't work yet(?) */ 132 #define SMC91CXX_SW_PAD 133 134 const char *smc91cxx_idstrs[] = { 135 NULL, /* 0 */ 136 NULL, /* 1 */ 137 NULL, /* 2 */ 138 "SMC91C90/91C92", /* 3 */ 139 "SMC91C94/91C96", /* 4 */ 140 "SMC91C95", /* 5 */ 141 NULL, /* 6 */ 142 "SMC91C100", /* 7 */ 143 "SMC91C100FD", /* 8 */ 144 "SMC91C111", /* 9 */ 145 NULL, /* 10 */ 146 NULL, /* 11 */ 147 NULL, /* 12 */ 148 NULL, /* 13 */ 149 NULL, /* 14 */ 150 NULL, /* 15 */ 151 }; 152 153 /* Supported media types. */ 154 const int smc91cxx_media[] = { 155 IFM_ETHER|IFM_10_T, 156 IFM_ETHER|IFM_10_5, 157 }; 158 #define NSMC91CxxMEDIA (sizeof(smc91cxx_media) / sizeof(smc91cxx_media[0])) 159 160 /* 161 * MII bit-bang glue. 162 */ 163 u_int32_t smc91cxx_mii_bitbang_read(device_t); 164 void smc91cxx_mii_bitbang_write(device_t, u_int32_t); 165 166 const struct mii_bitbang_ops smc91cxx_mii_bitbang_ops = { 167 smc91cxx_mii_bitbang_read, 168 smc91cxx_mii_bitbang_write, 169 { 170 MR_MDO, /* MII_BIT_MDO */ 171 MR_MDI, /* MII_BIT_MDI */ 172 MR_MCLK, /* MII_BIT_MDC */ 173 MR_MDOE, /* MII_BIT_DIR_HOST_PHY */ 174 0, /* MII_BIT_DIR_PHY_HOST */ 175 } 176 }; 177 178 /* MII callbacks */ 179 int smc91cxx_mii_readreg(device_t, int, int); 180 void smc91cxx_mii_writereg(device_t, int, int, int); 181 void smc91cxx_statchg(device_t); 182 void smc91cxx_tick(void *); 183 184 int smc91cxx_mediachange(struct ifnet *); 185 void smc91cxx_mediastatus(struct ifnet *, struct ifmediareq *); 186 187 int smc91cxx_set_media(struct smc91cxx_softc *, int); 188 189 void smc91cxx_init(struct smc91cxx_softc *); 190 void smc91cxx_read(struct smc91cxx_softc *); 191 void smc91cxx_reset(struct smc91cxx_softc *); 192 void smc91cxx_start(struct ifnet *); 193 uint8_t smc91cxx_copy_tx_frame(struct smc91cxx_softc *, struct mbuf *); 194 void smc91cxx_resume(struct smc91cxx_softc *); 195 void smc91cxx_stop(struct smc91cxx_softc *); 196 void smc91cxx_watchdog(struct ifnet *); 197 int smc91cxx_ioctl(struct ifnet *, u_long, void *); 198 199 static inline int ether_cmp(const void *, const void *); 200 static inline int 201 ether_cmp(const void *va, const void *vb) 202 { 203 const u_int8_t *a = va; 204 const u_int8_t *b = vb; 205 206 return ((a[5] != b[5]) || (a[4] != b[4]) || (a[3] != b[3]) || 207 (a[2] != b[2]) || (a[1] != b[1]) || (a[0] != b[0])); 208 } 209 210 static inline void 211 smc91cxx_intr_mask_write(bus_space_tag_t bst, bus_space_handle_t bsh, 212 uint8_t mask) 213 { 214 KDASSERT((mask & IM_ERCV_INT) == 0); 215 #ifdef SMC91CXX_NO_BYTE_WRITE 216 #if BYTE_ORDER == LITTLE_ENDIAN 217 bus_space_write_2(bst, bsh, INTR_STAT_REG_B, mask << 8); 218 #else 219 bus_space_write_2(bst, bsh, INTR_STAT_REG_B, mask); 220 #endif 221 #else 222 bus_space_write_1(bst, bsh, INTR_MASK_REG_B, mask); 223 #endif 224 KDASSERT(!(bus_space_read_1(bst, bsh, INTR_MASK_REG_B) & IM_ERCV_INT)); 225 } 226 227 static inline void 228 smc91cxx_intr_ack_write(bus_space_tag_t bst, bus_space_handle_t bsh, 229 uint8_t mask) 230 { 231 #ifdef SMC91CXX_NO_BYTE_WRITE 232 #if BYTE_ORDER == LITTLE_ENDIAN 233 bus_space_write_2(bst, bsh, INTR_ACK_REG_B, 234 mask | (bus_space_read_2(bst, bsh, INTR_ACK_REG_B) & 0xff00)); 235 #else 236 bus_space_write_2(bst, bsh, INTR_ACK_REG_B, 237 (mask << 8) | (bus_space_read_2(bst, bsh, INTR_ACK_REG_B) & 0xff)); 238 #endif 239 #else 240 bus_space_write_1(bst, bsh, INTR_ACK_REG_B, mask); 241 #endif 242 KDASSERT(!(bus_space_read_1(bst, bsh, INTR_MASK_REG_B) & IM_ERCV_INT)); 243 } 244 245 void 246 smc91cxx_attach(struct smc91cxx_softc *sc, u_int8_t *myea) 247 { 248 struct ifnet *ifp = &sc->sc_ec.ec_if; 249 bus_space_tag_t bst = sc->sc_bst; 250 bus_space_handle_t bsh = sc->sc_bsh; 251 struct ifmedia *ifm = &sc->sc_mii.mii_media; 252 const char *idstr; 253 u_int32_t miicapabilities; 254 u_int16_t tmp; 255 u_int8_t enaddr[ETHER_ADDR_LEN]; 256 int i, aui, mult, scale, memsize; 257 char pbuf[9]; 258 259 tmp = bus_space_read_2(bst, bsh, BANK_SELECT_REG_W); 260 /* check magic number */ 261 if ((tmp & BSR_DETECT_MASK) != BSR_DETECT_VALUE) { 262 aprint_error_dev(&sc->sc_dev, "failed to detect chip, bsr=%04x\n", tmp); 263 return; 264 } 265 266 /* Make sure the chip is stopped. */ 267 smc91cxx_stop(sc); 268 269 SMC_SELECT_BANK(sc, 3); 270 tmp = bus_space_read_2(bst, bsh, REVISION_REG_W); 271 sc->sc_chipid = RR_ID(tmp); 272 idstr = smc91cxx_idstrs[sc->sc_chipid]; 273 274 aprint_normal_dev(&sc->sc_dev, ""); 275 if (idstr != NULL) 276 aprint_normal("%s, ", idstr); 277 else 278 aprint_normal("unknown chip id %d, ", sc->sc_chipid); 279 aprint_normal("revision %d, ", RR_REV(tmp)); 280 281 SMC_SELECT_BANK(sc, 0); 282 switch (sc->sc_chipid) { 283 default: 284 mult = MCR_MEM_MULT(bus_space_read_2(bst, bsh, MEM_CFG_REG_W)); 285 scale = MIR_SCALE_91C9x; 286 break; 287 288 case CHIP_91C111: 289 mult = MIR_MULT_91C111; 290 scale = MIR_SCALE_91C111; 291 } 292 memsize = bus_space_read_2(bst, bsh, MEM_INFO_REG_W) & MIR_TOTAL_MASK; 293 if (memsize == 255) memsize++; 294 memsize *= scale * mult; 295 296 format_bytes(pbuf, sizeof(pbuf), memsize); 297 aprint_normal("buffer size: %s\n", pbuf); 298 299 /* Read the station address from the chip. */ 300 SMC_SELECT_BANK(sc, 1); 301 if (myea == NULL) { 302 myea = enaddr; 303 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 304 tmp = bus_space_read_2(bst, bsh, IAR_ADDR0_REG_W + i); 305 myea[i + 1] = (tmp >> 8) & 0xff; 306 myea[i] = tmp & 0xff; 307 } 308 } 309 aprint_normal_dev(&sc->sc_dev, "MAC address %s, ", 310 ether_sprintf(myea)); 311 312 /* Initialize the ifnet structure. */ 313 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 314 ifp->if_softc = sc; 315 ifp->if_start = smc91cxx_start; 316 ifp->if_ioctl = smc91cxx_ioctl; 317 ifp->if_watchdog = smc91cxx_watchdog; 318 ifp->if_flags = 319 IFF_BROADCAST | IFF_SIMPLEX | IFF_NOTRAILERS | IFF_MULTICAST; 320 IFQ_SET_READY(&ifp->if_snd); 321 322 /* Attach the interface. */ 323 if_attach(ifp); 324 ether_ifattach(ifp, myea); 325 326 /* 327 * Initialize our media structures and MII info. We will 328 * probe the MII if we are on the SMC91Cxx 329 */ 330 sc->sc_mii.mii_ifp = ifp; 331 sc->sc_mii.mii_readreg = smc91cxx_mii_readreg; 332 sc->sc_mii.mii_writereg = smc91cxx_mii_writereg; 333 sc->sc_mii.mii_statchg = smc91cxx_statchg; 334 ifmedia_init(ifm, IFM_IMASK, smc91cxx_mediachange, smc91cxx_mediastatus); 335 336 SMC_SELECT_BANK(sc, 1); 337 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 338 339 miicapabilities = BMSR_MEDIAMASK|BMSR_ANEG; 340 switch (sc->sc_chipid) { 341 case CHIP_91100: 342 /* 343 * The 91100 does not have full-duplex capabilities, 344 * even if the PHY does. 345 */ 346 miicapabilities &= ~(BMSR_100TXFDX | BMSR_10TFDX); 347 case CHIP_91100FD: 348 case CHIP_91C111: 349 if (tmp & CR_MII_SELECT) { 350 aprint_normal("default media MII"); 351 if (sc->sc_chipid == CHIP_91C111) { 352 aprint_normal(" (%s PHY)\n", (tmp & CR_AUI_SELECT) ? 353 "external" : "internal"); 354 sc->sc_internal_phy = !(tmp & CR_AUI_SELECT); 355 } else 356 aprint_normal("\n"); 357 mii_attach(&sc->sc_dev, &sc->sc_mii, miicapabilities, 358 MII_PHY_ANY, MII_OFFSET_ANY, 0); 359 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 360 ifmedia_add(&sc->sc_mii.mii_media, 361 IFM_ETHER|IFM_NONE, 0, NULL); 362 ifmedia_set(&sc->sc_mii.mii_media, 363 IFM_ETHER|IFM_NONE); 364 } else { 365 ifmedia_set(&sc->sc_mii.mii_media, 366 IFM_ETHER|IFM_AUTO); 367 } 368 sc->sc_flags |= SMC_FLAGS_HAS_MII; 369 break; 370 } else 371 if (sc->sc_chipid == CHIP_91C111) { 372 /* 373 * XXX: Should bring it out of low-power mode 374 */ 375 aprint_normal("EPH interface in low power mode\n"); 376 sc->sc_internal_phy = 0; 377 return; 378 } 379 /*FALLTHROUGH*/ 380 default: 381 aprint_normal("default media %s\n", (aui = (tmp & CR_AUI_SELECT)) ? 382 "AUI" : "UTP"); 383 for (i = 0; i < NSMC91CxxMEDIA; i++) 384 ifmedia_add(ifm, smc91cxx_media[i], 0, NULL); 385 ifmedia_set(ifm, IFM_ETHER | (aui ? IFM_10_5 : IFM_10_T)); 386 break; 387 } 388 389 #if NRND > 0 390 rnd_attach_source(&sc->rnd_source, device_xname(&sc->sc_dev), 391 RND_TYPE_NET, 0); 392 #endif 393 394 callout_init(&sc->sc_mii_callout, 0); 395 396 /* The attach is successful. */ 397 sc->sc_flags |= SMC_FLAGS_ATTACHED; 398 } 399 400 /* 401 * Change media according to request. 402 */ 403 int 404 smc91cxx_mediachange(struct ifnet *ifp) 405 { 406 struct smc91cxx_softc *sc = ifp->if_softc; 407 408 return (smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_media)); 409 } 410 411 int 412 smc91cxx_set_media(struct smc91cxx_softc *sc, int media) 413 { 414 bus_space_tag_t bst = sc->sc_bst; 415 bus_space_handle_t bsh = sc->sc_bsh; 416 u_int16_t tmp; 417 int rc; 418 419 /* 420 * If the interface is not currently powered on, just return. 421 * When it is enabled later, smc91cxx_init() will properly set 422 * up the media for us. 423 */ 424 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) 425 return (0); 426 427 if (IFM_TYPE(media) != IFM_ETHER) 428 return (EINVAL); 429 430 if ((sc->sc_flags & SMC_FLAGS_HAS_MII) == 0 || 431 (rc = mii_mediachg(&sc->sc_mii)) == ENXIO) 432 rc = 0; 433 434 switch (IFM_SUBTYPE(media)) { 435 case IFM_10_T: 436 case IFM_10_5: 437 SMC_SELECT_BANK(sc, 1); 438 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 439 if (IFM_SUBTYPE(media) == IFM_10_5) 440 tmp |= CR_AUI_SELECT; 441 else 442 tmp &= ~CR_AUI_SELECT; 443 bus_space_write_2(bst, bsh, CONFIG_REG_W, tmp); 444 delay(20000); /* XXX is this needed? */ 445 break; 446 447 default: 448 return (EINVAL); 449 } 450 451 return rc; 452 } 453 454 /* 455 * Notify the world which media we're using. 456 */ 457 void 458 smc91cxx_mediastatus(struct ifnet *ifp, struct ifmediareq *ifmr) 459 { 460 struct smc91cxx_softc *sc = ifp->if_softc; 461 bus_space_tag_t bst = sc->sc_bst; 462 bus_space_handle_t bsh = sc->sc_bsh; 463 u_int16_t tmp; 464 465 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) { 466 ifmr->ifm_active = IFM_ETHER | IFM_NONE; 467 ifmr->ifm_status = 0; 468 return; 469 } 470 471 /* 472 * If we have MII, go ask the PHY what's going on. 473 */ 474 if (sc->sc_flags & SMC_FLAGS_HAS_MII) { 475 mii_pollstat(&sc->sc_mii); 476 ifmr->ifm_active = sc->sc_mii.mii_media_active; 477 ifmr->ifm_status = sc->sc_mii.mii_media_status; 478 return; 479 } 480 481 SMC_SELECT_BANK(sc, 1); 482 tmp = bus_space_read_2(bst, bsh, CONFIG_REG_W); 483 ifmr->ifm_active = 484 IFM_ETHER | ((tmp & CR_AUI_SELECT) ? IFM_10_5 : IFM_10_T); 485 } 486 487 /* 488 * Reset and initialize the chip. 489 */ 490 void 491 smc91cxx_init(struct smc91cxx_softc *sc) 492 { 493 struct ifnet *ifp = &sc->sc_ec.ec_if; 494 bus_space_tag_t bst = sc->sc_bst; 495 bus_space_handle_t bsh = sc->sc_bsh; 496 u_int16_t tmp; 497 const u_int8_t *enaddr; 498 int s, i; 499 500 s = splnet(); 501 502 /* 503 * This resets the registers mostly to defaults, but doesn't 504 * affect the EEPROM. After the reset cycle, we pause briefly 505 * for the chip to recover. 506 * 507 * XXX how long are we really supposed to delay? --thorpej 508 */ 509 SMC_SELECT_BANK(sc, 0); 510 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, RCR_SOFTRESET); 511 delay(100); 512 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); 513 delay(200); 514 515 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); 516 517 /* Set the Ethernet address. */ 518 SMC_SELECT_BANK(sc, 1); 519 enaddr = (const u_int8_t *)CLLADDR(ifp->if_sadl); 520 for (i = 0; i < ETHER_ADDR_LEN; i += 2) { 521 tmp = enaddr[i + 1] << 8 | enaddr[i]; 522 bus_space_write_2(bst, bsh, IAR_ADDR0_REG_W + i, tmp); 523 } 524 525 /* 526 * Set the control register to automatically release successfully 527 * transmitted packets (making the best use of our limited memory) 528 * and enable the EPH interrupt on certain TX errors. 529 */ 530 bus_space_write_2(bst, bsh, CONTROL_REG_W, (CTR_AUTO_RELEASE | 531 CTR_TE_ENABLE | CTR_CR_ENABLE | CTR_LE_ENABLE)); 532 533 /* 534 * Reset the MMU and wait for it to be un-busy. 535 */ 536 SMC_SELECT_BANK(sc, 2); 537 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RESET); 538 sc->sc_txpacketno = ARR_FAILED; 539 for (;;) { 540 tmp = bus_space_read_2(bst, bsh, MMU_CMD_REG_W); 541 if (tmp == 0xffff) /* card went away! */ 542 return; 543 if ((tmp & MMUCR_BUSY) == 0) 544 break; 545 } 546 547 /* 548 * Disable all interrupts. 549 */ 550 smc91cxx_intr_mask_write(bst, bsh, 0); 551 552 /* 553 * On the 91c111, enable auto-negotiation, and set the LED 554 * status pins to something sane. 555 * XXX: Should be some way for MD code to decide the latter. 556 */ 557 SMC_SELECT_BANK(sc, 0); 558 if (sc->sc_chipid == CHIP_91C111) { 559 bus_space_write_2(bst, bsh, RX_PHY_CONTROL_REG_W, 560 RPC_ANEG | 561 (RPC_LS_LINK_DETECT << RPC_LSA_SHIFT) | 562 (RPC_LS_TXRX << RPC_LSB_SHIFT)); 563 } 564 565 /* 566 * Set current media. 567 */ 568 smc91cxx_set_media(sc, sc->sc_mii.mii_media.ifm_cur->ifm_media); 569 570 /* 571 * Set the receive filter. We want receive enable and auto 572 * strip of CRC from received packet. If we are in promisc. mode, 573 * then set that bit as well. 574 * 575 * XXX Initialize multicast filter. For now, we just accept 576 * XXX all multicast. 577 */ 578 SMC_SELECT_BANK(sc, 0); 579 580 tmp = RCR_ENABLE | RCR_STRIP_CRC | RCR_ALMUL; 581 if (ifp->if_flags & IFF_PROMISC) 582 tmp |= RCR_PROMISC; 583 584 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, tmp); 585 586 /* 587 * Set transmitter control to "enabled". 588 */ 589 tmp = TCR_ENABLE; 590 591 #ifndef SMC91CXX_SW_PAD 592 /* 593 * Enable hardware padding of transmitted packets. 594 * XXX doesn't work? 595 */ 596 tmp |= TCR_PAD_ENABLE; 597 #endif 598 599 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, tmp); 600 601 /* 602 * Now, enable interrupts. 603 */ 604 SMC_SELECT_BANK(sc, 2); 605 606 sc->sc_intmask = IM_EPH_INT | IM_RX_OVRN_INT | IM_RCV_INT; 607 if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy) { 608 sc->sc_intmask |= IM_MD_INT; 609 } 610 smc91cxx_intr_mask_write(bst, bsh, sc->sc_intmask); 611 612 /* Interface is now running, with no output active. */ 613 ifp->if_flags |= IFF_RUNNING; 614 ifp->if_flags &= ~IFF_OACTIVE; 615 616 if (sc->sc_flags & SMC_FLAGS_HAS_MII) { 617 /* Start the one second clock. */ 618 callout_reset(&sc->sc_mii_callout, hz, smc91cxx_tick, sc); 619 } 620 621 /* 622 * Attempt to start any pending transmission. 623 */ 624 smc91cxx_start(ifp); 625 626 splx(s); 627 } 628 629 /* 630 * Start output on an interface. 631 * Must be called at splnet or interrupt level. 632 */ 633 void 634 smc91cxx_start(struct ifnet *ifp) 635 { 636 struct smc91cxx_softc *sc = ifp->if_softc; 637 bus_space_tag_t bst = sc->sc_bst; 638 bus_space_handle_t bsh = sc->sc_bsh; 639 u_int len; 640 struct mbuf *m; 641 u_int16_t length, npages; 642 u_int16_t oddbyte; 643 u_int8_t packetno; 644 int timo, pad; 645 646 if ((ifp->if_flags & (IFF_RUNNING|IFF_OACTIVE)) != IFF_RUNNING) 647 return; 648 649 again: 650 /* 651 * Peek at the next packet. 652 */ 653 IFQ_POLL(&ifp->if_snd, m); 654 if (m == NULL) 655 return; 656 657 /* 658 * Compute the frame length and set pad to give an overall even 659 * number of bytes. Below, we assume that the packet length 660 * is even. 661 */ 662 for (len = 0; m != NULL; m = m->m_next) 663 len += m->m_len; 664 pad = (len & 1); 665 666 /* 667 * We drop packets that are too large. Perhaps we should 668 * truncate them instead? 669 */ 670 if ((len + pad) > (ETHER_MAX_LEN - ETHER_CRC_LEN)) { 671 printf("%s: large packet discarded\n", device_xname(&sc->sc_dev)); 672 ifp->if_oerrors++; 673 IFQ_DEQUEUE(&ifp->if_snd, m); 674 m_freem(m); 675 goto readcheck; 676 } 677 678 #ifdef SMC91CXX_SW_PAD 679 /* 680 * Not using hardware padding; pad to ETHER_MIN_LEN. 681 */ 682 if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 683 pad = ETHER_MIN_LEN - ETHER_CRC_LEN - len; 684 #endif 685 686 length = pad + len; 687 688 /* 689 * The MMU has a 256 byte page size. The MMU expects us to 690 * ask for "npages - 1". We include space for the status word, 691 * byte count, and control bytes in the allocation request. 692 */ 693 npages = ((length & ~1) + 6) >> 8; 694 695 /* 696 * Now allocate the memory. 697 */ 698 SMC_SELECT_BANK(sc, 2); 699 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ALLOC | npages); 700 701 timo = MEMORY_WAIT_TIME; 702 if (__predict_false((sc->sc_txpacketno & ARR_FAILED) == 0)) { 703 packetno = sc->sc_txpacketno; 704 sc->sc_txpacketno = ARR_FAILED; 705 } else { 706 do { 707 if (bus_space_read_1(bst, bsh, 708 INTR_STAT_REG_B) & IM_ALLOC_INT) 709 break; 710 delay(1); 711 } while (--timo); 712 } 713 714 packetno = bus_space_read_1(bst, bsh, ALLOC_RESULT_REG_B); 715 716 if (packetno & ARR_FAILED || timo == 0) { 717 /* 718 * No transmit memory is available. Record the number 719 * of requestd pages and enable the allocation completion 720 * interrupt. Set up the watchdog timer in case we miss 721 * the interrupt. Mark the interface as active so that 722 * no one else attempts to transmit while we're allocating 723 * memory. 724 */ 725 sc->sc_intmask |= IM_ALLOC_INT; 726 smc91cxx_intr_mask_write(bst, bsh, sc->sc_intmask); 727 ifp->if_timer = 5; 728 ifp->if_flags |= IFF_OACTIVE; 729 730 return; 731 } 732 733 /* 734 * We have a packet number - set the data window. 735 */ 736 bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno); 737 738 /* 739 * Point to the beginning of the packet. 740 */ 741 bus_space_write_2(bst, bsh, POINTER_REG_W, PTR_AUTOINC /* | 0x0000 */); 742 743 /* 744 * Send the packet length (+6 for stats, length, and control bytes) 745 * and the status word (set to zeros). 746 */ 747 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 748 bus_space_write_2(bst, bsh, DATA_REG_W, (length + 6) & 0x7ff); 749 750 /* 751 * Get the packet from the kernel. This will include the Ethernet 752 * frame header, MAC address, etc. 753 */ 754 IFQ_DEQUEUE(&ifp->if_snd, m); 755 756 /* 757 * Push the packet out to the card. 758 */ 759 oddbyte = smc91cxx_copy_tx_frame(sc, m); 760 761 #ifdef SMC91CXX_SW_PAD 762 #ifdef SMC91CXX_NO_BYTE_WRITE 763 #if BYTE_ORDER == LITTLE_ENDIAN 764 if (pad > 1 && (pad & 1)) { 765 bus_space_write_2(bst, bsh, DATA_REG_W, oddbyte << 0); 766 oddbyte = 0; 767 } 768 #else 769 if (pad > 1 && (pad & 1)) { 770 bus_space_write_2(bst, bsh, DATA_REG_W, oddbyte << 8); 771 oddbyte = 0; 772 } 773 #endif 774 #endif 775 776 /* 777 * Push out padding. 778 */ 779 while (pad > 1) { 780 bus_space_write_2(bst, bsh, DATA_REG_W, 0); 781 pad -= 2; 782 } 783 #endif 784 785 #ifdef SMC91CXX_NO_BYTE_WRITE 786 /* 787 * Push out control byte and unused packet byte. The control byte 788 * is 0, meaning the packet is even lengthed and no special 789 * CRC handling is necessary. 790 */ 791 #if BYTE_ORDER == LITTLE_ENDIAN 792 bus_space_write_2(bst, bsh, DATA_REG_W, 793 oddbyte | (pad ? (CTLB_ODD << 8) : 0)); 794 #else 795 bus_space_write_2(bst, bsh, DATA_REG_W, 796 (oddbyte << 8) | (pad ? CTLB_ODD : 0)); 797 #endif 798 #else 799 if (pad) 800 bus_space_write_1(bst, bsh, DATA_REG_B, 0); 801 #endif 802 803 /* 804 * Enable transmit interrupts and let the chip go. Set a watchdog 805 * in case we miss the interrupt. 806 */ 807 sc->sc_intmask |= IM_TX_INT | IM_TX_EMPTY_INT; 808 smc91cxx_intr_mask_write(bst, bsh, sc->sc_intmask); 809 810 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_ENQUEUE); 811 812 ifp->if_timer = 5; 813 814 /* Hand off a copy to the bpf. */ 815 if (ifp->if_bpf) 816 bpf_ops->bpf_mtap(ifp->if_bpf, m); 817 818 ifp->if_opackets++; 819 m_freem(m); 820 821 readcheck: 822 /* 823 * Check for incoming pcakets. We don't want to overflow the small 824 * RX FIFO. If nothing has arrived, attempt to queue another 825 * transmit packet. 826 */ 827 if (bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & FIFO_REMPTY) 828 goto again; 829 } 830 831 /* 832 * Squirt a (possibly misaligned) mbuf to the device 833 */ 834 uint8_t 835 smc91cxx_copy_tx_frame(struct smc91cxx_softc *sc, struct mbuf *m0) 836 { 837 bus_space_tag_t bst = sc->sc_bst; 838 bus_space_handle_t bsh = sc->sc_bsh; 839 struct mbuf *m; 840 int len, leftover; 841 u_int16_t dbuf; 842 u_int8_t *p; 843 #ifdef DIAGNOSTIC 844 u_int8_t *lim; 845 #endif 846 847 /* start out with no leftover data */ 848 leftover = 0; 849 dbuf = 0; 850 851 /* Process the chain of mbufs */ 852 for (m = m0; m != NULL; m = m->m_next) { 853 /* 854 * Process all of the data in a single mbuf. 855 */ 856 p = mtod(m, u_int8_t *); 857 len = m->m_len; 858 #ifdef DIAGNOSTIC 859 lim = p + len; 860 #endif 861 862 while (len > 0) { 863 if (leftover) { 864 /* 865 * Data left over (from mbuf or realignment). 866 * Buffer the next byte, and write it and 867 * the leftover data out. 868 */ 869 dbuf |= *p++ << 8; 870 len--; 871 bus_space_write_2(bst, bsh, DATA_REG_W, dbuf); 872 leftover = 0; 873 } else if ((long) p & 1) { 874 /* 875 * Misaligned data. Buffer the next byte. 876 */ 877 dbuf = *p++; 878 len--; 879 leftover = 1; 880 } else { 881 /* 882 * Aligned data. This is the case we like. 883 * 884 * Write-region out as much as we can, then 885 * buffer the remaining byte (if any). 886 */ 887 leftover = len & 1; 888 len &= ~1; 889 bus_space_write_multi_stream_2(bst, bsh, 890 DATA_REG_W, (u_int16_t *)p, len >> 1); 891 p += len; 892 893 if (leftover) 894 dbuf = *p++; 895 len = 0; 896 } 897 } 898 if (len < 0) 899 panic("smc91cxx_copy_tx_frame: negative len"); 900 #ifdef DIAGNOSTIC 901 if (p != lim) 902 panic("smc91cxx_copy_tx_frame: p != lim"); 903 #endif 904 } 905 #ifndef SMC91CXX_NO_BYTE_WRITE 906 if (leftover) 907 bus_space_write_1(bst, bsh, DATA_REG_B, dbuf); 908 #endif 909 return dbuf; 910 } 911 912 /* 913 * Interrupt service routine. 914 */ 915 int 916 smc91cxx_intr(void *arg) 917 { 918 struct smc91cxx_softc *sc = arg; 919 struct ifnet *ifp = &sc->sc_ec.ec_if; 920 bus_space_tag_t bst = sc->sc_bst; 921 bus_space_handle_t bsh = sc->sc_bsh; 922 u_int8_t mask, interrupts, status; 923 u_int16_t packetno, tx_status, card_stats; 924 #ifdef SMC91CXX_NO_BYTE_WRITE 925 u_int16_t v; 926 #endif 927 928 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 || 929 !device_is_active(&sc->sc_dev)) 930 return (0); 931 932 SMC_SELECT_BANK(sc, 2); 933 934 /* 935 * Obtain the current interrupt status and mask. 936 */ 937 #ifdef SMC91CXX_NO_BYTE_WRITE 938 v = bus_space_read_2(bst, bsh, INTR_STAT_REG_B); 939 940 /* 941 * Get the set of interrupt which occurred and eliminate any 942 * which are not enabled. 943 */ 944 #if BYTE_ORDER == LITTLE_ENDIAN 945 mask = v >> 8; 946 interrupts = v & 0xff; 947 #else 948 interrupts = v >> 8; 949 mask = v & 0xff; 950 #endif 951 KDASSERT(mask == sc->sc_intmask); 952 #else 953 mask = bus_space_read_1(bst, bsh, INTR_MASK_REG_B); 954 955 /* 956 * Get the set of interrupt which occurred and eliminate any 957 * which are not enabled. 958 */ 959 interrupts = bus_space_read_1(bst, bsh, INTR_STAT_REG_B); 960 #endif 961 status = interrupts & mask; 962 963 /* Ours? */ 964 if (status == 0) 965 return (0); 966 967 /* 968 * It's ours; disable all interrupts while we process them. 969 */ 970 smc91cxx_intr_mask_write(bst, bsh, 0); 971 972 /* 973 * Receive overrun interrupts. 974 */ 975 if (status & IM_RX_OVRN_INT) { 976 smc91cxx_intr_ack_write(bst, bsh, IM_RX_OVRN_INT); 977 ifp->if_ierrors++; 978 } 979 980 /* 981 * Receive interrupts. 982 */ 983 if (status & IM_RCV_INT) { 984 #if 1 /* DIAGNOSTIC */ 985 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 986 if (packetno & FIFO_REMPTY) { 987 aprint_error_dev(&sc->sc_dev, "receive interrupt on empty fifo\n"); 988 goto out; 989 } else 990 #endif 991 smc91cxx_read(sc); 992 } 993 994 /* 995 * Memory allocation interrupts. 996 */ 997 if (status & IM_ALLOC_INT) { 998 /* Disable this interrupt. */ 999 mask &= ~IM_ALLOC_INT; 1000 sc->sc_intmask &= ~IM_ALLOC_INT; 1001 1002 /* 1003 * Save allocated packet number for use in start 1004 */ 1005 packetno = bus_space_read_1(bst, bsh, ALLOC_RESULT_REG_B); 1006 KASSERT(sc->sc_txpacketno & ARR_FAILED); 1007 sc->sc_txpacketno = packetno; 1008 1009 /* 1010 * We can transmit again! 1011 */ 1012 ifp->if_flags &= ~IFF_OACTIVE; 1013 ifp->if_timer = 0; 1014 } 1015 1016 /* 1017 * Transmit complete interrupt. Handle transmission error messages. 1018 * This will only be called on error condition because of AUTO RELEASE 1019 * mode. 1020 */ 1021 if (status & IM_TX_INT) { 1022 smc91cxx_intr_ack_write(bst, bsh, IM_TX_INT); 1023 1024 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W) & 1025 FIFO_TX_MASK; 1026 1027 /* 1028 * Select this as the packet to read from. 1029 */ 1030 bus_space_write_1(bst, bsh, PACKET_NUM_REG_B, packetno); 1031 1032 /* 1033 * Position the pointer to the beginning of the packet. 1034 */ 1035 bus_space_write_2(bst, bsh, POINTER_REG_W, 1036 PTR_AUTOINC | PTR_READ /* | 0x0000 */); 1037 1038 /* 1039 * Fetch the TX status word. This will be a copy of 1040 * the EPH_STATUS_REG_W at the time of the transmission 1041 * failure. 1042 */ 1043 tx_status = bus_space_read_2(bst, bsh, DATA_REG_W); 1044 1045 if (tx_status & EPHSR_TX_SUC) { 1046 static struct timeval txsuc_last; 1047 static int txsuc_count; 1048 if (ppsratecheck(&txsuc_last, &txsuc_count, 1)) 1049 printf("%s: successful packet caused TX" 1050 " interrupt?!\n", device_xname(&sc->sc_dev)); 1051 } else 1052 ifp->if_oerrors++; 1053 1054 if (tx_status & EPHSR_LATCOL) 1055 ifp->if_collisions++; 1056 1057 /* Disable this interrupt (start will reenable if needed). */ 1058 mask &= ~IM_TX_INT; 1059 sc->sc_intmask &= ~IM_TX_INT; 1060 1061 /* 1062 * Some of these errors disable the transmitter; reenable it. 1063 */ 1064 SMC_SELECT_BANK(sc, 0); 1065 #ifdef SMC91CXX_SW_PAD 1066 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, TCR_ENABLE); 1067 #else 1068 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 1069 TCR_ENABLE | TCR_PAD_ENABLE); 1070 #endif 1071 1072 /* 1073 * Kill the failed packet and wait for the MMU to unbusy. 1074 */ 1075 SMC_SELECT_BANK(sc, 2); 1076 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 1077 /* XXX bound this loop! */ ; 1078 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_FREEPKT); 1079 1080 ifp->if_timer = 0; 1081 } 1082 1083 /* 1084 * Transmit underrun interrupts. We use this opportunity to 1085 * update transmit statistics from the card. 1086 */ 1087 if (status & IM_TX_EMPTY_INT) { 1088 smc91cxx_intr_ack_write(bst, bsh, IM_TX_EMPTY_INT); 1089 1090 /* Disable this interrupt. */ 1091 mask &= ~IM_TX_EMPTY_INT; 1092 sc->sc_intmask &= ~IM_TX_EMPTY_INT; 1093 1094 SMC_SELECT_BANK(sc, 0); 1095 card_stats = bus_space_read_2(bst, bsh, COUNTER_REG_W); 1096 1097 /* Single collisions. */ 1098 ifp->if_collisions += card_stats & ECR_COLN_MASK; 1099 1100 /* Multiple collisions. */ 1101 ifp->if_collisions += (card_stats & ECR_MCOLN_MASK) >> 4; 1102 1103 SMC_SELECT_BANK(sc, 2); 1104 1105 ifp->if_timer = 0; 1106 } 1107 1108 if (sc->sc_chipid == CHIP_91C111 && sc->sc_internal_phy && 1109 (status & IM_MD_INT)) { 1110 /* 1111 * Internal PHY status change 1112 */ 1113 mii_tick(&sc->sc_mii); 1114 } 1115 1116 /* 1117 * Other errors. Reset the interface. 1118 */ 1119 if (status & IM_EPH_INT) { 1120 smc91cxx_stop(sc); 1121 smc91cxx_init(sc); 1122 } 1123 1124 /* 1125 * Attempt to queue more packets for transmission. 1126 */ 1127 smc91cxx_start(ifp); 1128 1129 out: 1130 /* 1131 * Reenable the interrupts we wish to receive now that processing 1132 * is complete. 1133 */ 1134 mask |= sc->sc_intmask; 1135 smc91cxx_intr_mask_write(bst, bsh, mask); 1136 1137 #if NRND > 0 1138 if (status) 1139 rnd_add_uint32(&sc->rnd_source, status); 1140 #endif 1141 1142 return (1); 1143 } 1144 1145 /* 1146 * Read a packet from the card and pass it up to the kernel. 1147 * NOTE! WE EXPECT TO BE IN REGISTER WINDOW 2! 1148 */ 1149 void 1150 smc91cxx_read(struct smc91cxx_softc *sc) 1151 { 1152 struct ifnet *ifp = &sc->sc_ec.ec_if; 1153 bus_space_tag_t bst = sc->sc_bst; 1154 bus_space_handle_t bsh = sc->sc_bsh; 1155 struct ether_header *eh; 1156 struct mbuf *m; 1157 u_int16_t status, packetno, packetlen; 1158 u_int8_t *data; 1159 u_int32_t dr; 1160 1161 again: 1162 /* 1163 * Set data pointer to the beginning of the packet. Since 1164 * PTR_RCV is set, the packet number will be found automatically 1165 * in FIFO_PORTS_REG_W, FIFO_RX_MASK. 1166 */ 1167 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 1168 if (packetno & FIFO_REMPTY) 1169 return; 1170 1171 bus_space_write_2(bst, bsh, POINTER_REG_W, 1172 PTR_READ | PTR_RCV | PTR_AUTOINC /* | 0x0000 */); 1173 1174 /* 1175 * First two words are status and packet length. 1176 */ 1177 if ((sc->sc_flags & SMC_FLAGS_32BIT_READ) == 0) { 1178 status = bus_space_read_2(bst, bsh, DATA_REG_W); 1179 packetlen = bus_space_read_2(bst, bsh, DATA_REG_W); 1180 } else { 1181 dr = bus_space_read_4(bst, bsh, DATA_REG_W); 1182 #if BYTE_ORDER == LITTLE_ENDIAN 1183 status = (u_int16_t)dr; 1184 packetlen = (u_int16_t)(dr >> 16); 1185 #else 1186 packetlen = (u_int16_t)dr; 1187 status = (u_int16_t)(dr >> 16); 1188 #endif 1189 } 1190 1191 packetlen &= RLEN_MASK; 1192 if (packetlen < ETHER_MIN_LEN - ETHER_CRC_LEN + 6 || packetlen > 1534) { 1193 ifp->if_ierrors++; 1194 goto out; 1195 } 1196 1197 /* 1198 * The packet length includes 3 extra words: status, length, 1199 * and an extra word that includes the control byte. 1200 */ 1201 packetlen -= 6; 1202 1203 /* 1204 * Account for receive errors and discard. 1205 */ 1206 if (status & RS_ERRORS) { 1207 ifp->if_ierrors++; 1208 goto out; 1209 } 1210 1211 /* 1212 * Adjust for odd-length packet. 1213 */ 1214 if (status & RS_ODDFRAME) 1215 packetlen++; 1216 1217 /* 1218 * Allocate a header mbuf. 1219 */ 1220 MGETHDR(m, M_DONTWAIT, MT_DATA); 1221 if (m == NULL) 1222 goto out; 1223 m->m_pkthdr.rcvif = ifp; 1224 m->m_pkthdr.len = packetlen; 1225 1226 /* 1227 * Always put the packet in a cluster. 1228 * XXX should chain small mbufs if less than threshold. 1229 */ 1230 MCLGET(m, M_DONTWAIT); 1231 if ((m->m_flags & M_EXT) == 0) { 1232 m_freem(m); 1233 ifp->if_ierrors++; 1234 aprint_error_dev(&sc->sc_dev, "can't allocate cluster for incoming packet\n"); 1235 goto out; 1236 } 1237 1238 /* 1239 * Pull the packet off the interface. Make sure the payload 1240 * is aligned. 1241 */ 1242 if ((sc->sc_flags & SMC_FLAGS_32BIT_READ) == 0) { 1243 m->m_data = (char *) ALIGN(mtod(m, char *) + 1244 sizeof(struct ether_header)) - sizeof(struct ether_header); 1245 1246 eh = mtod(m, struct ether_header *); 1247 data = mtod(m, u_int8_t *); 1248 KASSERT(trunc_page((uintptr_t)data) == trunc_page((uintptr_t)data + packetlen - 1)); 1249 if (packetlen > 1) 1250 bus_space_read_multi_stream_2(bst, bsh, DATA_REG_W, 1251 (u_int16_t *)data, packetlen >> 1); 1252 if (packetlen & 1) { 1253 data += packetlen & ~1; 1254 *data = bus_space_read_1(bst, bsh, DATA_REG_B); 1255 } 1256 } else { 1257 u_int8_t *dp; 1258 1259 m->m_data = (void *) ALIGN(mtod(m, void *)); 1260 eh = mtod(m, struct ether_header *); 1261 dp = data = mtod(m, u_int8_t *); 1262 KASSERT(trunc_page((uintptr_t)data) == trunc_page((uintptr_t)data + packetlen - 1)); 1263 if (packetlen > 3) 1264 bus_space_read_multi_stream_4(bst, bsh, DATA_REG_W, 1265 (u_int32_t *)data, packetlen >> 2); 1266 if (packetlen & 3) { 1267 data += packetlen & ~3; 1268 *((u_int32_t *)data) = 1269 bus_space_read_stream_4(bst, bsh, DATA_REG_W); 1270 } 1271 } 1272 1273 ifp->if_ipackets++; 1274 1275 /* 1276 * Make sure to behave as IFF_SIMPLEX in all cases. 1277 * This is to cope with SMC91C92 (Megahertz XJ10BT), which 1278 * loops back packets to itself on promiscuous mode. 1279 * (should be ensured by chipset configuration) 1280 */ 1281 if ((ifp->if_flags & IFF_PROMISC) != 0) { 1282 /* 1283 * Drop packet looped back from myself. 1284 */ 1285 if (ether_cmp(eh->ether_shost, CLLADDR(ifp->if_sadl)) == 0) { 1286 m_freem(m); 1287 goto out; 1288 } 1289 } 1290 1291 m->m_pkthdr.len = m->m_len = packetlen; 1292 1293 /* 1294 * Hand the packet off to bpf listeners. 1295 */ 1296 if (ifp->if_bpf) 1297 bpf_ops->bpf_mtap(ifp->if_bpf, m); 1298 1299 (*ifp->if_input)(ifp, m); 1300 1301 out: 1302 /* 1303 * Tell the card to free the memory occupied by this packet. 1304 */ 1305 while (bus_space_read_2(bst, bsh, MMU_CMD_REG_W) & MMUCR_BUSY) 1306 /* XXX bound this loop! */ ; 1307 bus_space_write_2(bst, bsh, MMU_CMD_REG_W, MMUCR_RELEASE); 1308 1309 /* 1310 * Check for another packet. 1311 */ 1312 packetno = bus_space_read_2(bst, bsh, FIFO_PORTS_REG_W); 1313 if (packetno & FIFO_REMPTY) 1314 return; 1315 goto again; 1316 } 1317 1318 /* 1319 * Process an ioctl request. 1320 */ 1321 int 1322 smc91cxx_ioctl(struct ifnet *ifp, u_long cmd, void *data) 1323 { 1324 struct smc91cxx_softc *sc = ifp->if_softc; 1325 struct ifaddr *ifa = (struct ifaddr *)data; 1326 struct ifreq *ifr = (struct ifreq *)data; 1327 int s, error = 0; 1328 1329 s = splnet(); 1330 1331 switch (cmd) { 1332 case SIOCINITIFADDR: 1333 if ((error = smc91cxx_enable(sc)) != 0) 1334 break; 1335 ifp->if_flags |= IFF_UP; 1336 smc91cxx_init(sc); 1337 switch (ifa->ifa_addr->sa_family) { 1338 #ifdef INET 1339 case AF_INET: 1340 arp_ifinit(ifp, ifa); 1341 break; 1342 #endif 1343 default: 1344 break; 1345 } 1346 break; 1347 1348 1349 case SIOCSIFFLAGS: 1350 if ((error = ifioctl_common(ifp, cmd, data)) != 0) 1351 break; 1352 /* XXX re-use ether_ioctl() */ 1353 switch (ifp->if_flags & (IFF_UP|IFF_RUNNING)) { 1354 case IFF_RUNNING: 1355 /* 1356 * If interface is marked down and it is running, 1357 * stop it. 1358 */ 1359 smc91cxx_stop(sc); 1360 ifp->if_flags &= ~IFF_RUNNING; 1361 smc91cxx_disable(sc); 1362 break; 1363 case IFF_UP: 1364 /* 1365 * If interface is marked up and it is stopped, 1366 * start it. 1367 */ 1368 if ((error = smc91cxx_enable(sc)) != 0) 1369 break; 1370 smc91cxx_init(sc); 1371 break; 1372 case IFF_UP|IFF_RUNNING: 1373 /* 1374 * Reset the interface to pick up changes in any 1375 * other flags that affect hardware registers. 1376 */ 1377 smc91cxx_reset(sc); 1378 break; 1379 case 0: 1380 break; 1381 } 1382 break; 1383 1384 case SIOCADDMULTI: 1385 case SIOCDELMULTI: 1386 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0) { 1387 error = EIO; 1388 break; 1389 } 1390 1391 if ((error = ether_ioctl(ifp, cmd, data)) == ENETRESET) { 1392 /* 1393 * Multicast list has changed; set the hardware 1394 * filter accordingly. 1395 */ 1396 if (ifp->if_flags & IFF_RUNNING) 1397 smc91cxx_reset(sc); 1398 error = 0; 1399 } 1400 break; 1401 1402 case SIOCGIFMEDIA: 1403 case SIOCSIFMEDIA: 1404 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 1405 break; 1406 1407 default: 1408 error = ether_ioctl(ifp, cmd, data); 1409 break; 1410 } 1411 1412 splx(s); 1413 return (error); 1414 } 1415 1416 /* 1417 * Reset the interface. 1418 */ 1419 void 1420 smc91cxx_reset(struct smc91cxx_softc *sc) 1421 { 1422 int s; 1423 1424 s = splnet(); 1425 smc91cxx_stop(sc); 1426 smc91cxx_init(sc); 1427 splx(s); 1428 } 1429 1430 /* 1431 * Watchdog timer. 1432 */ 1433 void 1434 smc91cxx_watchdog(struct ifnet *ifp) 1435 { 1436 struct smc91cxx_softc *sc = ifp->if_softc; 1437 1438 log(LOG_ERR, "%s: device timeout\n", device_xname(&sc->sc_dev)); 1439 ifp->if_oerrors++; 1440 smc91cxx_reset(sc); 1441 } 1442 1443 /* 1444 * Stop output on the interface. 1445 */ 1446 void 1447 smc91cxx_stop(struct smc91cxx_softc *sc) 1448 { 1449 bus_space_tag_t bst = sc->sc_bst; 1450 bus_space_handle_t bsh = sc->sc_bsh; 1451 1452 /* 1453 * Clear interrupt mask; disable all interrupts. 1454 */ 1455 SMC_SELECT_BANK(sc, 2); 1456 smc91cxx_intr_mask_write(bst, bsh, 0); 1457 1458 /* 1459 * Disable transmitter and receiver. 1460 */ 1461 SMC_SELECT_BANK(sc, 0); 1462 bus_space_write_2(bst, bsh, RECV_CONTROL_REG_W, 0); 1463 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, 0); 1464 1465 /* 1466 * Cancel watchdog timer. 1467 */ 1468 sc->sc_ec.ec_if.if_timer = 0; 1469 } 1470 1471 /* 1472 * Enable power on the interface. 1473 */ 1474 int 1475 smc91cxx_enable(struct smc91cxx_softc *sc) 1476 { 1477 1478 if ((sc->sc_flags & SMC_FLAGS_ENABLED) == 0 && sc->sc_enable != NULL) { 1479 if ((*sc->sc_enable)(sc) != 0) { 1480 aprint_error_dev(&sc->sc_dev, "device enable failed\n"); 1481 return (EIO); 1482 } 1483 } 1484 1485 sc->sc_flags |= SMC_FLAGS_ENABLED; 1486 return (0); 1487 } 1488 1489 /* 1490 * Disable power on the interface. 1491 */ 1492 void 1493 smc91cxx_disable(struct smc91cxx_softc *sc) 1494 { 1495 1496 if ((sc->sc_flags & SMC_FLAGS_ENABLED) != 0 && sc->sc_disable != NULL) { 1497 (*sc->sc_disable)(sc); 1498 sc->sc_flags &= ~SMC_FLAGS_ENABLED; 1499 } 1500 } 1501 1502 int 1503 smc91cxx_activate(device_t self, enum devact act) 1504 { 1505 struct smc91cxx_softc *sc = device_private(self); 1506 1507 switch (act) { 1508 case DVACT_DEACTIVATE: 1509 if_deactivate(&sc->sc_ec.ec_if); 1510 return 0; 1511 default: 1512 return EOPNOTSUPP; 1513 } 1514 } 1515 1516 int 1517 smc91cxx_detach(device_t self, int flags) 1518 { 1519 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1520 struct ifnet *ifp = &sc->sc_ec.ec_if; 1521 1522 /* Succeed now if there's no work to do. */ 1523 if ((sc->sc_flags & SMC_FLAGS_ATTACHED) == 0) 1524 return (0); 1525 1526 1527 /* smc91cxx_disable() checks SMC_FLAGS_ENABLED */ 1528 smc91cxx_disable(sc); 1529 1530 /* smc91cxx_attach() never fails */ 1531 1532 /* Delete all media. */ 1533 ifmedia_delete_instance(&sc->sc_mii.mii_media, IFM_INST_ANY); 1534 1535 #if NRND > 0 1536 rnd_detach_source(&sc->rnd_source); 1537 #endif 1538 ether_ifdetach(ifp); 1539 if_detach(ifp); 1540 1541 return (0); 1542 } 1543 1544 u_int32_t 1545 smc91cxx_mii_bitbang_read(device_t self) 1546 { 1547 struct smc91cxx_softc *sc = (void *) self; 1548 1549 /* We're already in bank 3. */ 1550 return (bus_space_read_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W)); 1551 } 1552 1553 void 1554 smc91cxx_mii_bitbang_write(device_t self, u_int32_t val) 1555 { 1556 struct smc91cxx_softc *sc = (void *) self; 1557 1558 /* We're already in bank 3. */ 1559 bus_space_write_2(sc->sc_bst, sc->sc_bsh, MGMT_REG_W, val); 1560 } 1561 1562 int 1563 smc91cxx_mii_readreg(device_t self, int phy, int reg) 1564 { 1565 struct smc91cxx_softc *sc = (void *) self; 1566 int val; 1567 1568 SMC_SELECT_BANK(sc, 3); 1569 1570 val = mii_bitbang_readreg(self, &smc91cxx_mii_bitbang_ops, phy, reg); 1571 1572 SMC_SELECT_BANK(sc, 2); 1573 1574 return (val); 1575 } 1576 1577 void 1578 smc91cxx_mii_writereg(device_t self, int phy, int reg, int val) 1579 { 1580 struct smc91cxx_softc *sc = (void *) self; 1581 1582 SMC_SELECT_BANK(sc, 3); 1583 1584 mii_bitbang_writereg(self, &smc91cxx_mii_bitbang_ops, phy, reg, val); 1585 1586 SMC_SELECT_BANK(sc, 2); 1587 } 1588 1589 void 1590 smc91cxx_statchg(device_t self) 1591 { 1592 struct smc91cxx_softc *sc = (struct smc91cxx_softc *)self; 1593 bus_space_tag_t bst = sc->sc_bst; 1594 bus_space_handle_t bsh = sc->sc_bsh; 1595 int mctl; 1596 1597 SMC_SELECT_BANK(sc, 0); 1598 mctl = bus_space_read_2(bst, bsh, TXMIT_CONTROL_REG_W); 1599 if (sc->sc_mii.mii_media_active & IFM_FDX) 1600 mctl |= TCR_SWFDUP; 1601 else 1602 mctl &= ~TCR_SWFDUP; 1603 bus_space_write_2(bst, bsh, TXMIT_CONTROL_REG_W, mctl); 1604 SMC_SELECT_BANK(sc, 2); /* back to operating window */ 1605 } 1606 1607 /* 1608 * One second timer, used to tick the MII. 1609 */ 1610 void 1611 smc91cxx_tick(void *arg) 1612 { 1613 struct smc91cxx_softc *sc = arg; 1614 int s; 1615 1616 #ifdef DIAGNOSTIC 1617 if ((sc->sc_flags & SMC_FLAGS_HAS_MII) == 0) 1618 panic("smc91cxx_tick"); 1619 #endif 1620 1621 if (!device_is_active(&sc->sc_dev)) 1622 return; 1623 1624 s = splnet(); 1625 mii_tick(&sc->sc_mii); 1626 splx(s); 1627 1628 callout_reset(&sc->sc_mii_callout, hz, smc91cxx_tick, sc); 1629 } 1630 1631