1 /* $NetBSD: smc83c170.c,v 1.74 2008/04/28 20:23:51 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Device driver for the Standard Microsystems Corp. 83C170 35 * Ethernet PCI Integrated Controller (EPIC/100). 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: smc83c170.c,v 1.74 2008/04/28 20:23:51 martin Exp $"); 40 41 #include "bpfilter.h" 42 43 #include <sys/param.h> 44 #include <sys/systm.h> 45 #include <sys/callout.h> 46 #include <sys/mbuf.h> 47 #include <sys/malloc.h> 48 #include <sys/kernel.h> 49 #include <sys/socket.h> 50 #include <sys/ioctl.h> 51 #include <sys/errno.h> 52 #include <sys/device.h> 53 54 #include <uvm/uvm_extern.h> 55 56 #include <net/if.h> 57 #include <net/if_dl.h> 58 #include <net/if_media.h> 59 #include <net/if_ether.h> 60 61 #if NBPFILTER > 0 62 #include <net/bpf.h> 63 #endif 64 65 #include <sys/bus.h> 66 #include <sys/intr.h> 67 68 #include <dev/mii/miivar.h> 69 #include <dev/mii/lxtphyreg.h> 70 71 #include <dev/ic/smc83c170reg.h> 72 #include <dev/ic/smc83c170var.h> 73 74 void epic_start(struct ifnet *); 75 void epic_watchdog(struct ifnet *); 76 int epic_ioctl(struct ifnet *, u_long, void *); 77 int epic_init(struct ifnet *); 78 void epic_stop(struct ifnet *, int); 79 80 void epic_shutdown(void *); 81 82 void epic_reset(struct epic_softc *); 83 void epic_rxdrain(struct epic_softc *); 84 int epic_add_rxbuf(struct epic_softc *, int); 85 void epic_read_eeprom(struct epic_softc *, int, int, uint16_t *); 86 void epic_set_mchash(struct epic_softc *); 87 void epic_fixup_clock_source(struct epic_softc *); 88 int epic_mii_read(struct device *, int, int); 89 void epic_mii_write(struct device *, int, int, int); 90 int epic_mii_wait(struct epic_softc *, uint32_t); 91 void epic_tick(void *); 92 93 void epic_statchg(struct device *); 94 int epic_mediachange(struct ifnet *); 95 96 #define INTMASK (INTSTAT_FATAL_INT | INTSTAT_TXU | \ 97 INTSTAT_TXC | INTSTAT_RXE | INTSTAT_RQE | INTSTAT_RCC) 98 99 int epic_copy_small = 0; 100 101 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 102 103 /* 104 * Attach an EPIC interface to the system. 105 */ 106 void 107 epic_attach(sc) 108 struct epic_softc *sc; 109 { 110 bus_space_tag_t st = sc->sc_st; 111 bus_space_handle_t sh = sc->sc_sh; 112 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 113 int rseg, error, miiflags; 114 u_int i; 115 bus_dma_segment_t seg; 116 uint8_t enaddr[ETHER_ADDR_LEN], devname[12 + 1]; 117 uint16_t myea[ETHER_ADDR_LEN / 2], mydevname[6]; 118 char *nullbuf; 119 120 callout_init(&sc->sc_mii_callout, 0); 121 122 /* 123 * Allocate the control data structures, and create and load the 124 * DMA map for it. 125 */ 126 if ((error = bus_dmamem_alloc(sc->sc_dmat, 127 sizeof(struct epic_control_data) + ETHER_PAD_LEN, PAGE_SIZE, 0, 128 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 129 aprint_error_dev(&sc->sc_dev, 130 "unable to allocate control data, error = %d\n", 131 error); 132 goto fail_0; 133 } 134 135 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 136 sizeof(struct epic_control_data) + ETHER_PAD_LEN, 137 (void **)&sc->sc_control_data, 138 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 139 aprint_error_dev(&sc->sc_dev, "unable to map control data, error = %d\n", error); 140 goto fail_1; 141 } 142 nullbuf = 143 (char *)sc->sc_control_data + sizeof(struct epic_control_data); 144 memset(nullbuf, 0, ETHER_PAD_LEN); 145 146 if ((error = bus_dmamap_create(sc->sc_dmat, 147 sizeof(struct epic_control_data), 1, 148 sizeof(struct epic_control_data), 0, BUS_DMA_NOWAIT, 149 &sc->sc_cddmamap)) != 0) { 150 aprint_error_dev(&sc->sc_dev, "unable to create control data DMA map, " 151 "error = %d\n", error); 152 goto fail_2; 153 } 154 155 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 156 sc->sc_control_data, sizeof(struct epic_control_data), NULL, 157 BUS_DMA_NOWAIT)) != 0) { 158 aprint_error_dev(&sc->sc_dev, 159 "unable to load control data DMA map, error = %d\n", 160 error); 161 goto fail_3; 162 } 163 164 /* 165 * Create the transmit buffer DMA maps. 166 */ 167 for (i = 0; i < EPIC_NTXDESC; i++) { 168 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 169 EPIC_NFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 170 &EPIC_DSTX(sc, i)->ds_dmamap)) != 0) { 171 aprint_error_dev(&sc->sc_dev, "unable to create tx DMA map %d, " 172 "error = %d\n", i, error); 173 goto fail_4; 174 } 175 } 176 177 /* 178 * Create the receive buffer DMA maps. 179 */ 180 for (i = 0; i < EPIC_NRXDESC; i++) { 181 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 182 MCLBYTES, 0, BUS_DMA_NOWAIT, 183 &EPIC_DSRX(sc, i)->ds_dmamap)) != 0) { 184 aprint_error_dev(&sc->sc_dev, "unable to create rx DMA map %d, " 185 "error = %d\n", i, error); 186 goto fail_5; 187 } 188 EPIC_DSRX(sc, i)->ds_mbuf = NULL; 189 } 190 191 /* 192 * create and map the pad buffer 193 */ 194 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_PAD_LEN, 1, 195 ETHER_PAD_LEN, 0, BUS_DMA_NOWAIT,&sc->sc_nulldmamap)) != 0) { 196 aprint_error_dev(&sc->sc_dev, "unable to create pad buffer DMA map, " 197 "error = %d\n", error); 198 goto fail_5; 199 } 200 201 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_nulldmamap, 202 nullbuf, ETHER_PAD_LEN, NULL, BUS_DMA_NOWAIT)) != 0) { 203 aprint_error_dev(&sc->sc_dev, "unable to load pad buffer DMA map, " 204 "error = %d\n", error); 205 goto fail_6; 206 } 207 bus_dmamap_sync(sc->sc_dmat, sc->sc_nulldmamap, 0, ETHER_PAD_LEN, 208 BUS_DMASYNC_PREWRITE); 209 210 /* 211 * Bring the chip out of low-power mode and reset it to a known state. 212 */ 213 bus_space_write_4(st, sh, EPIC_GENCTL, 0); 214 epic_reset(sc); 215 216 /* 217 * Read the Ethernet address from the EEPROM. 218 */ 219 epic_read_eeprom(sc, 0, __arraycount(myea), myea); 220 for (i = 0; i < __arraycount(myea); i++) { 221 enaddr[i * 2] = myea[i] & 0xff; 222 enaddr[i * 2 + 1] = myea[i] >> 8; 223 } 224 225 /* 226 * ...and the device name. 227 */ 228 epic_read_eeprom(sc, 0x2c, __arraycount(mydevname), mydevname); 229 for (i = 0; i < __arraycount(mydevname); i++) { 230 devname[i * 2] = mydevname[i] & 0xff; 231 devname[i * 2 + 1] = mydevname[i] >> 8; 232 } 233 234 devname[sizeof(mydevname)] = '\0'; 235 for (i = sizeof(mydevname) ; i > 0; i--) { 236 if (devname[i - 1] == ' ') 237 devname[i - 1] = '\0'; 238 else 239 break; 240 } 241 242 aprint_normal_dev(&sc->sc_dev, "%s, Ethernet address %s\n", 243 devname, ether_sprintf(enaddr)); 244 245 miiflags = 0; 246 if (sc->sc_hwflags & EPIC_HAS_MII_FIBER) 247 miiflags |= MIIF_HAVEFIBER; 248 249 /* 250 * Initialize our media structures and probe the MII. 251 */ 252 sc->sc_mii.mii_ifp = ifp; 253 sc->sc_mii.mii_readreg = epic_mii_read; 254 sc->sc_mii.mii_writereg = epic_mii_write; 255 sc->sc_mii.mii_statchg = epic_statchg; 256 257 sc->sc_ethercom.ec_mii = &sc->sc_mii; 258 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, epic_mediachange, 259 ether_mediastatus); 260 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 261 MII_OFFSET_ANY, miiflags); 262 if (LIST_EMPTY(&sc->sc_mii.mii_phys)) { 263 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 264 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 265 } else 266 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 267 268 if (sc->sc_hwflags & EPIC_HAS_BNC) { 269 /* use the next free media instance */ 270 sc->sc_serinst = sc->sc_mii.mii_instance++; 271 ifmedia_add(&sc->sc_mii.mii_media, 272 IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, 273 sc->sc_serinst), 274 0, NULL); 275 aprint_normal_dev(&sc->sc_dev, "10base2/BNC\n"); 276 } else 277 sc->sc_serinst = -1; 278 279 strlcpy(ifp->if_xname, device_xname(&sc->sc_dev), IFNAMSIZ); 280 ifp->if_softc = sc; 281 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 282 ifp->if_ioctl = epic_ioctl; 283 ifp->if_start = epic_start; 284 ifp->if_watchdog = epic_watchdog; 285 ifp->if_init = epic_init; 286 ifp->if_stop = epic_stop; 287 IFQ_SET_READY(&ifp->if_snd); 288 289 /* 290 * We can support 802.1Q VLAN-sized frames. 291 */ 292 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 293 294 /* 295 * Attach the interface. 296 */ 297 if_attach(ifp); 298 ether_ifattach(ifp, enaddr); 299 300 /* 301 * Make sure the interface is shutdown during reboot. 302 */ 303 sc->sc_sdhook = shutdownhook_establish(epic_shutdown, sc); 304 if (sc->sc_sdhook == NULL) 305 aprint_error_dev(&sc->sc_dev, "WARNING: unable to establish shutdown hook\n"); 306 return; 307 308 /* 309 * Free any resources we've allocated during the failed attach 310 * attempt. Do this in reverse order and fall through. 311 */ 312 fail_6: 313 bus_dmamap_destroy(sc->sc_dmat, sc->sc_nulldmamap); 314 fail_5: 315 for (i = 0; i < EPIC_NRXDESC; i++) { 316 if (EPIC_DSRX(sc, i)->ds_dmamap != NULL) 317 bus_dmamap_destroy(sc->sc_dmat, 318 EPIC_DSRX(sc, i)->ds_dmamap); 319 } 320 fail_4: 321 for (i = 0; i < EPIC_NTXDESC; i++) { 322 if (EPIC_DSTX(sc, i)->ds_dmamap != NULL) 323 bus_dmamap_destroy(sc->sc_dmat, 324 EPIC_DSTX(sc, i)->ds_dmamap); 325 } 326 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 327 fail_3: 328 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 329 fail_2: 330 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 331 sizeof(struct epic_control_data)); 332 fail_1: 333 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 334 fail_0: 335 return; 336 } 337 338 /* 339 * Shutdown hook. Make sure the interface is stopped at reboot. 340 */ 341 void 342 epic_shutdown(arg) 343 void *arg; 344 { 345 struct epic_softc *sc = arg; 346 347 epic_stop(&sc->sc_ethercom.ec_if, 1); 348 } 349 350 /* 351 * Start packet transmission on the interface. 352 * [ifnet interface function] 353 */ 354 void 355 epic_start(ifp) 356 struct ifnet *ifp; 357 { 358 struct epic_softc *sc = ifp->if_softc; 359 struct mbuf *m0, *m; 360 struct epic_txdesc *txd; 361 struct epic_descsoft *ds; 362 struct epic_fraglist *fr; 363 bus_dmamap_t dmamap; 364 int error, firsttx, nexttx, opending, seg; 365 u_int len; 366 367 /* 368 * Remember the previous txpending and the first transmit 369 * descriptor we use. 370 */ 371 opending = sc->sc_txpending; 372 firsttx = EPIC_NEXTTX(sc->sc_txlast); 373 374 /* 375 * Loop through the send queue, setting up transmit descriptors 376 * until we drain the queue, or use up all available transmit 377 * descriptors. 378 */ 379 while (sc->sc_txpending < EPIC_NTXDESC) { 380 /* 381 * Grab a packet off the queue. 382 */ 383 IFQ_POLL(&ifp->if_snd, m0); 384 if (m0 == NULL) 385 break; 386 m = NULL; 387 388 /* 389 * Get the last and next available transmit descriptor. 390 */ 391 nexttx = EPIC_NEXTTX(sc->sc_txlast); 392 txd = EPIC_CDTX(sc, nexttx); 393 fr = EPIC_CDFL(sc, nexttx); 394 ds = EPIC_DSTX(sc, nexttx); 395 dmamap = ds->ds_dmamap; 396 397 /* 398 * Load the DMA map. If this fails, the packet either 399 * didn't fit in the alloted number of frags, or we were 400 * short on resources. In this case, we'll copy and try 401 * again. 402 */ 403 if ((error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 404 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 || 405 (m0->m_pkthdr.len < ETHER_PAD_LEN && 406 dmamap-> dm_nsegs == EPIC_NFRAGS)) { 407 if (error == 0) 408 bus_dmamap_unload(sc->sc_dmat, dmamap); 409 410 MGETHDR(m, M_DONTWAIT, MT_DATA); 411 if (m == NULL) { 412 aprint_error_dev(&sc->sc_dev, "unable to allocate Tx mbuf\n"); 413 break; 414 } 415 if (m0->m_pkthdr.len > MHLEN) { 416 MCLGET(m, M_DONTWAIT); 417 if ((m->m_flags & M_EXT) == 0) { 418 aprint_error_dev(&sc->sc_dev, "unable to allocate Tx " 419 "cluster\n"); 420 m_freem(m); 421 break; 422 } 423 } 424 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 425 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 426 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 427 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 428 if (error) { 429 aprint_error_dev(&sc->sc_dev, "unable to load Tx buffer, " 430 "error = %d\n", error); 431 break; 432 } 433 } 434 IFQ_DEQUEUE(&ifp->if_snd, m0); 435 if (m != NULL) { 436 m_freem(m0); 437 m0 = m; 438 } 439 440 /* Initialize the fraglist. */ 441 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 442 fr->ef_frags[seg].ef_addr = 443 dmamap->dm_segs[seg].ds_addr; 444 fr->ef_frags[seg].ef_length = 445 dmamap->dm_segs[seg].ds_len; 446 } 447 len = m0->m_pkthdr.len; 448 if (len < ETHER_PAD_LEN) { 449 fr->ef_frags[seg].ef_addr = sc->sc_nulldma; 450 fr->ef_frags[seg].ef_length = ETHER_PAD_LEN - len; 451 len = ETHER_PAD_LEN; 452 seg++; 453 } 454 fr->ef_nfrags = seg; 455 456 EPIC_CDFLSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE); 457 458 /* Sync the DMA map. */ 459 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 460 BUS_DMASYNC_PREWRITE); 461 462 /* 463 * Store a pointer to the packet so we can free it later. 464 */ 465 ds->ds_mbuf = m0; 466 467 /* 468 * Fill in the transmit descriptor. 469 */ 470 txd->et_control = ET_TXCTL_LASTDESC | ET_TXCTL_FRAGLIST; 471 472 /* 473 * If this is the first descriptor we're enqueueing, 474 * don't give it to the EPIC yet. That could cause 475 * a race condition. We'll do it below. 476 */ 477 if (nexttx == firsttx) 478 txd->et_txstatus = TXSTAT_TXLENGTH(len); 479 else 480 txd->et_txstatus = 481 TXSTAT_TXLENGTH(len) | ET_TXSTAT_OWNER; 482 483 EPIC_CDTXSYNC(sc, nexttx, 484 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 485 486 /* Advance the tx pointer. */ 487 sc->sc_txpending++; 488 sc->sc_txlast = nexttx; 489 490 #if NBPFILTER > 0 491 /* 492 * Pass the packet to any BPF listeners. 493 */ 494 if (ifp->if_bpf) 495 bpf_mtap(ifp->if_bpf, m0); 496 #endif 497 } 498 499 if (sc->sc_txpending == EPIC_NTXDESC) { 500 /* No more slots left; notify upper layer. */ 501 ifp->if_flags |= IFF_OACTIVE; 502 } 503 504 if (sc->sc_txpending != opending) { 505 /* 506 * We enqueued packets. If the transmitter was idle, 507 * reset the txdirty pointer. 508 */ 509 if (opending == 0) 510 sc->sc_txdirty = firsttx; 511 512 /* 513 * Cause a transmit interrupt to happen on the 514 * last packet we enqueued. 515 */ 516 EPIC_CDTX(sc, sc->sc_txlast)->et_control |= ET_TXCTL_IAF; 517 EPIC_CDTXSYNC(sc, sc->sc_txlast, 518 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 519 520 /* 521 * The entire packet chain is set up. Give the 522 * first descriptor to the EPIC now. 523 */ 524 EPIC_CDTX(sc, firsttx)->et_txstatus |= ET_TXSTAT_OWNER; 525 EPIC_CDTXSYNC(sc, firsttx, 526 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 527 528 /* Start the transmitter. */ 529 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 530 COMMAND_TXQUEUED); 531 532 /* Set a watchdog timer in case the chip flakes out. */ 533 ifp->if_timer = 5; 534 } 535 } 536 537 /* 538 * Watchdog timer handler. 539 * [ifnet interface function] 540 */ 541 void 542 epic_watchdog(ifp) 543 struct ifnet *ifp; 544 { 545 struct epic_softc *sc = ifp->if_softc; 546 547 printf("%s: device timeout\n", device_xname(&sc->sc_dev)); 548 ifp->if_oerrors++; 549 550 (void) epic_init(ifp); 551 } 552 553 /* 554 * Handle control requests from the operator. 555 * [ifnet interface function] 556 */ 557 int 558 epic_ioctl(ifp, cmd, data) 559 struct ifnet *ifp; 560 u_long cmd; 561 void *data; 562 { 563 struct epic_softc *sc = ifp->if_softc; 564 int s, error; 565 566 s = splnet(); 567 568 error = ether_ioctl(ifp, cmd, data); 569 if (error == ENETRESET) { 570 /* 571 * Multicast list has changed; set the hardware filter 572 * accordingly. Update our idea of the current media; 573 * epic_set_mchash() needs to know what it is. 574 */ 575 if (ifp->if_flags & IFF_RUNNING) { 576 mii_pollstat(&sc->sc_mii); 577 epic_set_mchash(sc); 578 } 579 error = 0; 580 } 581 582 splx(s); 583 return (error); 584 } 585 586 /* 587 * Interrupt handler. 588 */ 589 int 590 epic_intr(arg) 591 void *arg; 592 { 593 struct epic_softc *sc = arg; 594 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 595 struct epic_rxdesc *rxd; 596 struct epic_txdesc *txd; 597 struct epic_descsoft *ds; 598 struct mbuf *m; 599 uint32_t intstat, rxstatus, txstatus; 600 int i, claimed = 0; 601 u_int len; 602 603 top: 604 /* 605 * Get the interrupt status from the EPIC. 606 */ 607 intstat = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT); 608 if ((intstat & INTSTAT_INT_ACTV) == 0) 609 return (claimed); 610 611 claimed = 1; 612 613 /* 614 * Acknowledge the interrupt. 615 */ 616 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT, 617 intstat & INTMASK); 618 619 /* 620 * Check for receive interrupts. 621 */ 622 if (intstat & (INTSTAT_RCC | INTSTAT_RXE | INTSTAT_RQE)) { 623 for (i = sc->sc_rxptr;; i = EPIC_NEXTRX(i)) { 624 rxd = EPIC_CDRX(sc, i); 625 ds = EPIC_DSRX(sc, i); 626 627 EPIC_CDRXSYNC(sc, i, 628 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 629 630 rxstatus = rxd->er_rxstatus; 631 if (rxstatus & ER_RXSTAT_OWNER) { 632 /* 633 * We have processed all of the 634 * receive buffers. 635 */ 636 break; 637 } 638 639 /* 640 * Make sure the packet arrived intact. If an error 641 * occurred, update stats and reset the descriptor. 642 * The buffer will be reused the next time the 643 * descriptor comes up in the ring. 644 */ 645 if ((rxstatus & ER_RXSTAT_PKTINTACT) == 0) { 646 if (rxstatus & ER_RXSTAT_CRCERROR) 647 aprint_error_dev(&sc->sc_dev, "CRC error\n"); 648 if (rxstatus & ER_RXSTAT_ALIGNERROR) 649 aprint_error_dev(&sc->sc_dev, "alignment error\n"); 650 ifp->if_ierrors++; 651 EPIC_INIT_RXDESC(sc, i); 652 continue; 653 } 654 655 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 656 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 657 658 /* 659 * The EPIC includes the CRC with every packet; 660 * trim it. 661 */ 662 len = RXSTAT_RXLENGTH(rxstatus) - ETHER_CRC_LEN; 663 664 if (len < sizeof(struct ether_header)) { 665 /* 666 * Runt packet; drop it now. 667 */ 668 ifp->if_ierrors++; 669 EPIC_INIT_RXDESC(sc, i); 670 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 671 ds->ds_dmamap->dm_mapsize, 672 BUS_DMASYNC_PREREAD); 673 continue; 674 } 675 676 /* 677 * If the packet is small enough to fit in a 678 * single header mbuf, allocate one and copy 679 * the data into it. This greatly reduces 680 * memory consumption when we receive lots 681 * of small packets. 682 * 683 * Otherwise, we add a new buffer to the receive 684 * chain. If this fails, we drop the packet and 685 * recycle the old buffer. 686 */ 687 if (epic_copy_small != 0 && len <= MHLEN) { 688 MGETHDR(m, M_DONTWAIT, MT_DATA); 689 if (m == NULL) 690 goto dropit; 691 memcpy(mtod(m, void *), 692 mtod(ds->ds_mbuf, void *), len); 693 EPIC_INIT_RXDESC(sc, i); 694 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 695 ds->ds_dmamap->dm_mapsize, 696 BUS_DMASYNC_PREREAD); 697 } else { 698 m = ds->ds_mbuf; 699 if (epic_add_rxbuf(sc, i) != 0) { 700 dropit: 701 ifp->if_ierrors++; 702 EPIC_INIT_RXDESC(sc, i); 703 bus_dmamap_sync(sc->sc_dmat, 704 ds->ds_dmamap, 0, 705 ds->ds_dmamap->dm_mapsize, 706 BUS_DMASYNC_PREREAD); 707 continue; 708 } 709 } 710 711 m->m_pkthdr.rcvif = ifp; 712 m->m_pkthdr.len = m->m_len = len; 713 714 #if NBPFILTER > 0 715 /* 716 * Pass this up to any BPF listeners, but only 717 * pass it up the stack if it's for us. 718 */ 719 if (ifp->if_bpf) 720 bpf_mtap(ifp->if_bpf, m); 721 #endif 722 723 /* Pass it on. */ 724 (*ifp->if_input)(ifp, m); 725 ifp->if_ipackets++; 726 } 727 728 /* Update the receive pointer. */ 729 sc->sc_rxptr = i; 730 731 /* 732 * Check for receive queue underflow. 733 */ 734 if (intstat & INTSTAT_RQE) { 735 aprint_error_dev(&sc->sc_dev, "receiver queue empty\n"); 736 /* 737 * Ring is already built; just restart the 738 * receiver. 739 */ 740 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_PRCDAR, 741 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 742 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 743 COMMAND_RXQUEUED | COMMAND_START_RX); 744 } 745 } 746 747 /* 748 * Check for transmission complete interrupts. 749 */ 750 if (intstat & (INTSTAT_TXC | INTSTAT_TXU)) { 751 ifp->if_flags &= ~IFF_OACTIVE; 752 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 753 i = EPIC_NEXTTX(i), sc->sc_txpending--) { 754 txd = EPIC_CDTX(sc, i); 755 ds = EPIC_DSTX(sc, i); 756 757 EPIC_CDTXSYNC(sc, i, 758 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 759 760 txstatus = txd->et_txstatus; 761 if (txstatus & ET_TXSTAT_OWNER) 762 break; 763 764 EPIC_CDFLSYNC(sc, i, BUS_DMASYNC_POSTWRITE); 765 766 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 767 0, ds->ds_dmamap->dm_mapsize, 768 BUS_DMASYNC_POSTWRITE); 769 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 770 m_freem(ds->ds_mbuf); 771 ds->ds_mbuf = NULL; 772 773 /* 774 * Check for errors and collisions. 775 */ 776 if ((txstatus & ET_TXSTAT_PACKETTX) == 0) 777 ifp->if_oerrors++; 778 else 779 ifp->if_opackets++; 780 ifp->if_collisions += 781 TXSTAT_COLLISIONS(txstatus); 782 if (txstatus & ET_TXSTAT_CARSENSELOST) 783 aprint_error_dev(&sc->sc_dev, "lost carrier\n"); 784 } 785 786 /* Update the dirty transmit buffer pointer. */ 787 sc->sc_txdirty = i; 788 789 /* 790 * Cancel the watchdog timer if there are no pending 791 * transmissions. 792 */ 793 if (sc->sc_txpending == 0) 794 ifp->if_timer = 0; 795 796 /* 797 * Kick the transmitter after a DMA underrun. 798 */ 799 if (intstat & INTSTAT_TXU) { 800 aprint_error_dev(&sc->sc_dev, "transmit underrun\n"); 801 bus_space_write_4(sc->sc_st, sc->sc_sh, 802 EPIC_COMMAND, COMMAND_TXUGO); 803 if (sc->sc_txpending) 804 bus_space_write_4(sc->sc_st, sc->sc_sh, 805 EPIC_COMMAND, COMMAND_TXQUEUED); 806 } 807 808 /* 809 * Try to get more packets going. 810 */ 811 epic_start(ifp); 812 } 813 814 /* 815 * Check for fatal interrupts. 816 */ 817 if (intstat & INTSTAT_FATAL_INT) { 818 if (intstat & INTSTAT_PTA) 819 aprint_error_dev(&sc->sc_dev, "PCI target abort error\n"); 820 else if (intstat & INTSTAT_PMA) 821 aprint_error_dev(&sc->sc_dev, "PCI master abort error\n"); 822 else if (intstat & INTSTAT_APE) 823 aprint_error_dev(&sc->sc_dev, "PCI address parity error\n"); 824 else if (intstat & INTSTAT_DPE) 825 aprint_error_dev(&sc->sc_dev, "PCI data parity error\n"); 826 else 827 aprint_error_dev(&sc->sc_dev, "unknown fatal error\n"); 828 (void) epic_init(ifp); 829 } 830 831 /* 832 * Check for more interrupts. 833 */ 834 goto top; 835 } 836 837 /* 838 * One second timer, used to tick the MII. 839 */ 840 void 841 epic_tick(arg) 842 void *arg; 843 { 844 struct epic_softc *sc = arg; 845 int s; 846 847 s = splnet(); 848 mii_tick(&sc->sc_mii); 849 splx(s); 850 851 callout_reset(&sc->sc_mii_callout, hz, epic_tick, sc); 852 } 853 854 /* 855 * Fixup the clock source on the EPIC. 856 */ 857 void 858 epic_fixup_clock_source(sc) 859 struct epic_softc *sc; 860 { 861 int i; 862 863 /* 864 * According to SMC Application Note 7-15, the EPIC's clock 865 * source is incorrect following a reset. This manifests itself 866 * as failure to recognize when host software has written to 867 * a register on the EPIC. The appnote recommends issuing at 868 * least 16 consecutive writes to the CLOCK TEST bit to correctly 869 * configure the clock source. 870 */ 871 for (i = 0; i < 16; i++) 872 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TEST, 873 TEST_CLOCKTEST); 874 } 875 876 /* 877 * Perform a soft reset on the EPIC. 878 */ 879 void 880 epic_reset(sc) 881 struct epic_softc *sc; 882 { 883 884 epic_fixup_clock_source(sc); 885 886 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, 0); 887 delay(100); 888 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, GENCTL_SOFTRESET); 889 delay(100); 890 891 epic_fixup_clock_source(sc); 892 } 893 894 /* 895 * Initialize the interface. Must be called at splnet(). 896 */ 897 int 898 epic_init(ifp) 899 struct ifnet *ifp; 900 { 901 struct epic_softc *sc = ifp->if_softc; 902 bus_space_tag_t st = sc->sc_st; 903 bus_space_handle_t sh = sc->sc_sh; 904 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 905 struct epic_txdesc *txd; 906 struct epic_descsoft *ds; 907 uint32_t genctl, reg0; 908 int i, error = 0; 909 910 /* 911 * Cancel any pending I/O. 912 */ 913 epic_stop(ifp, 0); 914 915 /* 916 * Reset the EPIC to a known state. 917 */ 918 epic_reset(sc); 919 920 /* 921 * Magical mystery initialization. 922 */ 923 bus_space_write_4(st, sh, EPIC_TXTEST, 0); 924 925 /* 926 * Initialize the EPIC genctl register: 927 * 928 * - 64 byte receive FIFO threshold 929 * - automatic advance to next receive frame 930 */ 931 genctl = GENCTL_RX_FIFO_THRESH0 | GENCTL_ONECOPY; 932 #if BYTE_ORDER == BIG_ENDIAN 933 genctl |= GENCTL_BIG_ENDIAN; 934 #endif 935 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 936 937 /* 938 * Reset the MII bus and PHY. 939 */ 940 reg0 = bus_space_read_4(st, sh, EPIC_NVCTL); 941 bus_space_write_4(st, sh, EPIC_NVCTL, reg0 | NVCTL_GPIO1 | NVCTL_GPOE1); 942 bus_space_write_4(st, sh, EPIC_MIICFG, MIICFG_ENASER); 943 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_RESET_PHY); 944 delay(100); 945 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 946 delay(1000); 947 bus_space_write_4(st, sh, EPIC_NVCTL, reg0); 948 949 /* 950 * Initialize Ethernet address. 951 */ 952 reg0 = enaddr[1] << 8 | enaddr[0]; 953 bus_space_write_4(st, sh, EPIC_LAN0, reg0); 954 reg0 = enaddr[3] << 8 | enaddr[2]; 955 bus_space_write_4(st, sh, EPIC_LAN1, reg0); 956 reg0 = enaddr[5] << 8 | enaddr[4]; 957 bus_space_write_4(st, sh, EPIC_LAN2, reg0); 958 959 /* 960 * Initialize receive control. Remember the external buffer 961 * size setting. 962 */ 963 reg0 = bus_space_read_4(st, sh, EPIC_RXCON) & 964 (RXCON_EXTBUFSIZESEL1 | RXCON_EXTBUFSIZESEL0); 965 reg0 |= (RXCON_RXMULTICAST | RXCON_RXBROADCAST); 966 if (ifp->if_flags & IFF_PROMISC) 967 reg0 |= RXCON_PROMISCMODE; 968 bus_space_write_4(st, sh, EPIC_RXCON, reg0); 969 970 /* Set the current media. */ 971 if ((error = epic_mediachange(ifp)) != 0) 972 goto out; 973 974 /* Set up the multicast hash table. */ 975 epic_set_mchash(sc); 976 977 /* 978 * Initialize the transmit descriptor ring. txlast is initialized 979 * to the end of the list so that it will wrap around to the first 980 * descriptor when the first packet is transmitted. 981 */ 982 for (i = 0; i < EPIC_NTXDESC; i++) { 983 txd = EPIC_CDTX(sc, i); 984 memset(txd, 0, sizeof(struct epic_txdesc)); 985 txd->et_bufaddr = EPIC_CDFLADDR(sc, i); 986 txd->et_nextdesc = EPIC_CDTXADDR(sc, EPIC_NEXTTX(i)); 987 EPIC_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 988 } 989 sc->sc_txpending = 0; 990 sc->sc_txdirty = 0; 991 sc->sc_txlast = EPIC_NTXDESC - 1; 992 993 /* 994 * Initialize the receive descriptor ring. 995 */ 996 for (i = 0; i < EPIC_NRXDESC; i++) { 997 ds = EPIC_DSRX(sc, i); 998 if (ds->ds_mbuf == NULL) { 999 if ((error = epic_add_rxbuf(sc, i)) != 0) { 1000 aprint_error_dev(&sc->sc_dev, "unable to allocate or map rx " 1001 "buffer %d error = %d\n", 1002 i, error); 1003 /* 1004 * XXX Should attempt to run with fewer receive 1005 * XXX buffers instead of just failing. 1006 */ 1007 epic_rxdrain(sc); 1008 goto out; 1009 } 1010 } else 1011 EPIC_INIT_RXDESC(sc, i); 1012 } 1013 sc->sc_rxptr = 0; 1014 1015 /* 1016 * Initialize the interrupt mask and enable interrupts. 1017 */ 1018 bus_space_write_4(st, sh, EPIC_INTMASK, INTMASK); 1019 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_INTENA); 1020 1021 /* 1022 * Give the transmit and receive rings to the EPIC. 1023 */ 1024 bus_space_write_4(st, sh, EPIC_PTCDAR, 1025 EPIC_CDTXADDR(sc, EPIC_NEXTTX(sc->sc_txlast))); 1026 bus_space_write_4(st, sh, EPIC_PRCDAR, 1027 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 1028 1029 /* 1030 * Set the EPIC in motion. 1031 */ 1032 bus_space_write_4(st, sh, EPIC_COMMAND, 1033 COMMAND_RXQUEUED | COMMAND_START_RX); 1034 1035 /* 1036 * ...all done! 1037 */ 1038 ifp->if_flags |= IFF_RUNNING; 1039 ifp->if_flags &= ~IFF_OACTIVE; 1040 1041 /* 1042 * Start the one second clock. 1043 */ 1044 callout_reset(&sc->sc_mii_callout, hz, epic_tick, sc); 1045 1046 /* 1047 * Attempt to start output on the interface. 1048 */ 1049 epic_start(ifp); 1050 1051 out: 1052 if (error) 1053 aprint_error_dev(&sc->sc_dev, "interface not running\n"); 1054 return (error); 1055 } 1056 1057 /* 1058 * Drain the receive queue. 1059 */ 1060 void 1061 epic_rxdrain(sc) 1062 struct epic_softc *sc; 1063 { 1064 struct epic_descsoft *ds; 1065 int i; 1066 1067 for (i = 0; i < EPIC_NRXDESC; i++) { 1068 ds = EPIC_DSRX(sc, i); 1069 if (ds->ds_mbuf != NULL) { 1070 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1071 m_freem(ds->ds_mbuf); 1072 ds->ds_mbuf = NULL; 1073 } 1074 } 1075 } 1076 1077 /* 1078 * Stop transmission on the interface. 1079 */ 1080 void 1081 epic_stop(ifp, disable) 1082 struct ifnet *ifp; 1083 int disable; 1084 { 1085 struct epic_softc *sc = ifp->if_softc; 1086 bus_space_tag_t st = sc->sc_st; 1087 bus_space_handle_t sh = sc->sc_sh; 1088 struct epic_descsoft *ds; 1089 uint32_t reg; 1090 int i; 1091 1092 /* 1093 * Stop the one second clock. 1094 */ 1095 callout_stop(&sc->sc_mii_callout); 1096 1097 /* Down the MII. */ 1098 mii_down(&sc->sc_mii); 1099 1100 /* Paranoia... */ 1101 epic_fixup_clock_source(sc); 1102 1103 /* 1104 * Disable interrupts. 1105 */ 1106 reg = bus_space_read_4(st, sh, EPIC_GENCTL); 1107 bus_space_write_4(st, sh, EPIC_GENCTL, reg & ~GENCTL_INTENA); 1108 bus_space_write_4(st, sh, EPIC_INTMASK, 0); 1109 1110 /* 1111 * Stop the DMA engine and take the receiver off-line. 1112 */ 1113 bus_space_write_4(st, sh, EPIC_COMMAND, COMMAND_STOP_RDMA | 1114 COMMAND_STOP_TDMA | COMMAND_STOP_RX); 1115 1116 /* 1117 * Release any queued transmit buffers. 1118 */ 1119 for (i = 0; i < EPIC_NTXDESC; i++) { 1120 ds = EPIC_DSTX(sc, i); 1121 if (ds->ds_mbuf != NULL) { 1122 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1123 m_freem(ds->ds_mbuf); 1124 ds->ds_mbuf = NULL; 1125 } 1126 } 1127 1128 /* 1129 * Mark the interface down and cancel the watchdog timer. 1130 */ 1131 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1132 ifp->if_timer = 0; 1133 1134 if (disable) 1135 epic_rxdrain(sc); 1136 } 1137 1138 /* 1139 * Read the EPIC Serial EEPROM. 1140 */ 1141 void 1142 epic_read_eeprom(sc, word, wordcnt, data) 1143 struct epic_softc *sc; 1144 int word, wordcnt; 1145 uint16_t *data; 1146 { 1147 bus_space_tag_t st = sc->sc_st; 1148 bus_space_handle_t sh = sc->sc_sh; 1149 uint16_t reg; 1150 int i, x; 1151 1152 #define EEPROM_WAIT_READY(st, sh) \ 1153 while ((bus_space_read_4((st), (sh), EPIC_EECTL) & EECTL_EERDY) == 0) \ 1154 /* nothing */ 1155 1156 /* 1157 * Enable the EEPROM. 1158 */ 1159 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1160 EEPROM_WAIT_READY(st, sh); 1161 1162 for (i = 0; i < wordcnt; i++) { 1163 /* Send CHIP SELECT for one clock tick. */ 1164 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE|EECTL_EECS); 1165 EEPROM_WAIT_READY(st, sh); 1166 1167 /* Shift in the READ opcode. */ 1168 for (x = 3; x > 0; x--) { 1169 reg = EECTL_ENABLE|EECTL_EECS; 1170 if (EPIC_EEPROM_OPC_READ & (1 << (x - 1))) 1171 reg |= EECTL_EEDI; 1172 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1173 EEPROM_WAIT_READY(st, sh); 1174 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1175 EEPROM_WAIT_READY(st, sh); 1176 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1177 EEPROM_WAIT_READY(st, sh); 1178 } 1179 1180 /* Shift in address. */ 1181 for (x = 6; x > 0; x--) { 1182 reg = EECTL_ENABLE|EECTL_EECS; 1183 if ((word + i) & (1 << (x - 1))) 1184 reg |= EECTL_EEDI; 1185 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1186 EEPROM_WAIT_READY(st, sh); 1187 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1188 EEPROM_WAIT_READY(st, sh); 1189 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1190 EEPROM_WAIT_READY(st, sh); 1191 } 1192 1193 /* Shift out data. */ 1194 reg = EECTL_ENABLE|EECTL_EECS; 1195 data[i] = 0; 1196 for (x = 16; x > 0; x--) { 1197 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1198 EEPROM_WAIT_READY(st, sh); 1199 if (bus_space_read_4(st, sh, EPIC_EECTL) & EECTL_EEDO) 1200 data[i] |= (1 << (x - 1)); 1201 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1202 EEPROM_WAIT_READY(st, sh); 1203 } 1204 1205 /* Clear CHIP SELECT. */ 1206 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1207 EEPROM_WAIT_READY(st, sh); 1208 } 1209 1210 /* 1211 * Disable the EEPROM. 1212 */ 1213 bus_space_write_4(st, sh, EPIC_EECTL, 0); 1214 1215 #undef EEPROM_WAIT_READY 1216 } 1217 1218 /* 1219 * Add a receive buffer to the indicated descriptor. 1220 */ 1221 int 1222 epic_add_rxbuf(sc, idx) 1223 struct epic_softc *sc; 1224 int idx; 1225 { 1226 struct epic_descsoft *ds = EPIC_DSRX(sc, idx); 1227 struct mbuf *m; 1228 int error; 1229 1230 MGETHDR(m, M_DONTWAIT, MT_DATA); 1231 if (m == NULL) 1232 return (ENOBUFS); 1233 1234 MCLGET(m, M_DONTWAIT); 1235 if ((m->m_flags & M_EXT) == 0) { 1236 m_freem(m); 1237 return (ENOBUFS); 1238 } 1239 1240 if (ds->ds_mbuf != NULL) 1241 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1242 1243 ds->ds_mbuf = m; 1244 1245 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1246 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1247 BUS_DMA_READ|BUS_DMA_NOWAIT); 1248 if (error) { 1249 aprint_error_dev(&sc->sc_dev, "can't load rx DMA map %d, error = %d\n", 1250 idx, error); 1251 panic("epic_add_rxbuf"); /* XXX */ 1252 } 1253 1254 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1255 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1256 1257 EPIC_INIT_RXDESC(sc, idx); 1258 1259 return (0); 1260 } 1261 1262 /* 1263 * Set the EPIC multicast hash table. 1264 * 1265 * NOTE: We rely on a recently-updated mii_media_active here! 1266 */ 1267 void 1268 epic_set_mchash(sc) 1269 struct epic_softc *sc; 1270 { 1271 struct ethercom *ec = &sc->sc_ethercom; 1272 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1273 struct ether_multi *enm; 1274 struct ether_multistep step; 1275 uint32_t hash, mchash[4]; 1276 1277 /* 1278 * Set up the multicast address filter by passing all multicast 1279 * addresses through a CRC generator, and then using the low-order 1280 * 6 bits as an index into the 64 bit multicast hash table (only 1281 * the lower 16 bits of each 32 bit multicast hash register are 1282 * valid). The high order bits select the register, while the 1283 * rest of the bits select the bit within the register. 1284 */ 1285 1286 if (ifp->if_flags & IFF_PROMISC) 1287 goto allmulti; 1288 1289 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_10_T) { 1290 /* XXX hardware bug in 10Mbps mode. */ 1291 goto allmulti; 1292 } 1293 1294 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0; 1295 1296 ETHER_FIRST_MULTI(step, ec, enm); 1297 while (enm != NULL) { 1298 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1299 /* 1300 * We must listen to a range of multicast addresses. 1301 * For now, just accept all multicasts, rather than 1302 * trying to set only those filter bits needed to match 1303 * the range. (At this time, the only use of address 1304 * ranges is for IP multicast routing, for which the 1305 * range is big enough to require all bits set.) 1306 */ 1307 goto allmulti; 1308 } 1309 1310 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1311 hash >>= 26; 1312 1313 /* Set the corresponding bit in the hash table. */ 1314 mchash[hash >> 4] |= 1 << (hash & 0xf); 1315 1316 ETHER_NEXT_MULTI(step, enm); 1317 } 1318 1319 ifp->if_flags &= ~IFF_ALLMULTI; 1320 goto sethash; 1321 1322 allmulti: 1323 ifp->if_flags |= IFF_ALLMULTI; 1324 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0xffff; 1325 1326 sethash: 1327 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC0, mchash[0]); 1328 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC1, mchash[1]); 1329 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC2, mchash[2]); 1330 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC3, mchash[3]); 1331 } 1332 1333 /* 1334 * Wait for the MII to become ready. 1335 */ 1336 int 1337 epic_mii_wait(sc, rw) 1338 struct epic_softc *sc; 1339 uint32_t rw; 1340 { 1341 int i; 1342 1343 for (i = 0; i < 50; i++) { 1344 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL) & rw) 1345 == 0) 1346 break; 1347 delay(2); 1348 } 1349 if (i == 50) { 1350 aprint_error_dev(&sc->sc_dev, "MII timed out\n"); 1351 return (1); 1352 } 1353 1354 return (0); 1355 } 1356 1357 /* 1358 * Read from the MII. 1359 */ 1360 int 1361 epic_mii_read(self, phy, reg) 1362 struct device *self; 1363 int phy, reg; 1364 { 1365 struct epic_softc *sc = (struct epic_softc *)self; 1366 1367 if (epic_mii_wait(sc, MMCTL_WRITE)) 1368 return (0); 1369 1370 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1371 MMCTL_ARG(phy, reg, MMCTL_READ)); 1372 1373 if (epic_mii_wait(sc, MMCTL_READ)) 1374 return (0); 1375 1376 return (bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA) & 1377 MMDATA_MASK); 1378 } 1379 1380 /* 1381 * Write to the MII. 1382 */ 1383 void 1384 epic_mii_write(self, phy, reg, val) 1385 struct device *self; 1386 int phy, reg, val; 1387 { 1388 struct epic_softc *sc = (struct epic_softc *)self; 1389 1390 if (epic_mii_wait(sc, MMCTL_WRITE)) 1391 return; 1392 1393 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA, val); 1394 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1395 MMCTL_ARG(phy, reg, MMCTL_WRITE)); 1396 } 1397 1398 /* 1399 * Callback from PHY when media changes. 1400 */ 1401 void 1402 epic_statchg(self) 1403 struct device *self; 1404 { 1405 struct epic_softc *sc = (struct epic_softc *)self; 1406 uint32_t txcon, miicfg; 1407 1408 /* 1409 * Update loopback bits in TXCON to reflect duplex mode. 1410 */ 1411 txcon = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_TXCON); 1412 if (sc->sc_mii.mii_media_active & IFM_FDX) 1413 txcon |= (TXCON_LOOPBACK_D1|TXCON_LOOPBACK_D2); 1414 else 1415 txcon &= ~(TXCON_LOOPBACK_D1|TXCON_LOOPBACK_D2); 1416 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TXCON, txcon); 1417 1418 /* On some cards we need manualy set fullduplex led */ 1419 if (sc->sc_hwflags & EPIC_DUPLEXLED_ON_694) { 1420 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1421 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) 1422 miicfg |= MIICFG_ENABLE; 1423 else 1424 miicfg &= ~MIICFG_ENABLE; 1425 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1426 } 1427 1428 /* 1429 * There is a multicast filter bug in 10Mbps mode. Kick the 1430 * multicast filter in case the speed changed. 1431 */ 1432 epic_set_mchash(sc); 1433 } 1434 1435 /* 1436 * Callback from ifmedia to request new media setting. 1437 * 1438 * XXX Looks to me like some of this complexity should move into 1439 * XXX one or two custom PHY drivers. --dyoung 1440 */ 1441 int 1442 epic_mediachange(ifp) 1443 struct ifnet *ifp; 1444 { 1445 struct epic_softc *sc = ifp->if_softc; 1446 struct mii_data *mii = &sc->sc_mii; 1447 struct ifmedia *ifm = &mii->mii_media; 1448 int media = ifm->ifm_cur->ifm_media; 1449 uint32_t miicfg; 1450 struct mii_softc *miisc; 1451 int cfg, rc; 1452 1453 if ((ifp->if_flags & IFF_UP) == 0) 1454 return (0); 1455 1456 if (IFM_INST(media) != sc->sc_serinst) { 1457 /* If we're not selecting serial interface, select MII mode */ 1458 #ifdef EPICMEDIADEBUG 1459 printf("%s: parallel mode\n", ifp->if_xname); 1460 #endif 1461 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1462 miicfg &= ~MIICFG_SERMODEENA; 1463 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1464 } 1465 1466 if ((rc = mii_mediachg(mii)) == ENXIO) 1467 rc = 0; 1468 1469 if (IFM_INST(media) == sc->sc_serinst) { 1470 /* select serial interface */ 1471 #ifdef EPICMEDIADEBUG 1472 printf("%s: serial mode\n", ifp->if_xname); 1473 #endif 1474 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1475 miicfg |= (MIICFG_SERMODEENA | MIICFG_ENABLE); 1476 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1477 1478 /* There is no driver to fill this */ 1479 mii->mii_media_active = media; 1480 mii->mii_media_status = 0; 1481 1482 epic_statchg(&sc->sc_dev); 1483 return (0); 1484 } 1485 1486 /* Lookup selected PHY */ 1487 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 1488 if (IFM_INST(media) == miisc->mii_inst) 1489 break; 1490 } 1491 if (!miisc) { 1492 printf("epic_mediachange: can't happen\n"); /* ??? panic */ 1493 return (0); 1494 } 1495 #ifdef EPICMEDIADEBUG 1496 printf("%s: using phy %s\n", ifp->if_xname, 1497 device_xname(&miisc->mii_dev)); 1498 #endif 1499 1500 if (miisc->mii_flags & MIIF_HAVEFIBER) { 1501 /* XXX XXX assume it's a Level1 - should check */ 1502 1503 /* We have to powerup fiber transceivers */ 1504 cfg = PHY_READ(miisc, MII_LXTPHY_CONFIG); 1505 if (IFM_SUBTYPE(media) == IFM_100_FX) { 1506 #ifdef EPICMEDIADEBUG 1507 printf("%s: power up fiber\n", ifp->if_xname); 1508 #endif 1509 cfg |= (CONFIG_LEDC1 | CONFIG_LEDC0); 1510 } else { 1511 #ifdef EPICMEDIADEBUG 1512 printf("%s: power down fiber\n", ifp->if_xname); 1513 #endif 1514 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0); 1515 } 1516 PHY_WRITE(miisc, MII_LXTPHY_CONFIG, cfg); 1517 } 1518 1519 return rc; 1520 } 1521