1 /* $NetBSD: smc83c170.c,v 1.78 2010/01/19 22:06:25 pooka Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 21 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 22 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 23 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 24 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 * POSSIBILITY OF SUCH DAMAGE. 31 */ 32 33 /* 34 * Device driver for the Standard Microsystems Corp. 83C170 35 * Ethernet PCI Integrated Controller (EPIC/100). 36 */ 37 38 #include <sys/cdefs.h> 39 __KERNEL_RCSID(0, "$NetBSD: smc83c170.c,v 1.78 2010/01/19 22:06:25 pooka Exp $"); 40 41 42 #include <sys/param.h> 43 #include <sys/systm.h> 44 #include <sys/callout.h> 45 #include <sys/mbuf.h> 46 #include <sys/malloc.h> 47 #include <sys/kernel.h> 48 #include <sys/socket.h> 49 #include <sys/ioctl.h> 50 #include <sys/errno.h> 51 #include <sys/device.h> 52 53 #include <uvm/uvm_extern.h> 54 55 #include <net/if.h> 56 #include <net/if_dl.h> 57 #include <net/if_media.h> 58 #include <net/if_ether.h> 59 60 #include <net/bpf.h> 61 62 #include <sys/bus.h> 63 #include <sys/intr.h> 64 65 #include <dev/mii/miivar.h> 66 #include <dev/mii/lxtphyreg.h> 67 68 #include <dev/ic/smc83c170reg.h> 69 #include <dev/ic/smc83c170var.h> 70 71 void epic_start(struct ifnet *); 72 void epic_watchdog(struct ifnet *); 73 int epic_ioctl(struct ifnet *, u_long, void *); 74 int epic_init(struct ifnet *); 75 void epic_stop(struct ifnet *, int); 76 77 bool epic_shutdown(device_t, int); 78 79 void epic_reset(struct epic_softc *); 80 void epic_rxdrain(struct epic_softc *); 81 int epic_add_rxbuf(struct epic_softc *, int); 82 void epic_read_eeprom(struct epic_softc *, int, int, uint16_t *); 83 void epic_set_mchash(struct epic_softc *); 84 void epic_fixup_clock_source(struct epic_softc *); 85 int epic_mii_read(device_t, int, int); 86 void epic_mii_write(device_t, int, int, int); 87 int epic_mii_wait(struct epic_softc *, uint32_t); 88 void epic_tick(void *); 89 90 void epic_statchg(device_t); 91 int epic_mediachange(struct ifnet *); 92 93 #define INTMASK (INTSTAT_FATAL_INT | INTSTAT_TXU | \ 94 INTSTAT_TXC | INTSTAT_RXE | INTSTAT_RQE | INTSTAT_RCC) 95 96 int epic_copy_small = 0; 97 98 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 99 100 /* 101 * Attach an EPIC interface to the system. 102 */ 103 void 104 epic_attach(struct epic_softc *sc) 105 { 106 bus_space_tag_t st = sc->sc_st; 107 bus_space_handle_t sh = sc->sc_sh; 108 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 109 int rseg, error, miiflags; 110 u_int i; 111 bus_dma_segment_t seg; 112 uint8_t enaddr[ETHER_ADDR_LEN], devname[12 + 1]; 113 uint16_t myea[ETHER_ADDR_LEN / 2], mydevname[6]; 114 char *nullbuf; 115 116 callout_init(&sc->sc_mii_callout, 0); 117 118 /* 119 * Allocate the control data structures, and create and load the 120 * DMA map for it. 121 */ 122 if ((error = bus_dmamem_alloc(sc->sc_dmat, 123 sizeof(struct epic_control_data) + ETHER_PAD_LEN, PAGE_SIZE, 0, 124 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 125 aprint_error_dev(sc->sc_dev, 126 "unable to allocate control data, error = %d\n", error); 127 goto fail_0; 128 } 129 130 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 131 sizeof(struct epic_control_data) + ETHER_PAD_LEN, 132 (void **)&sc->sc_control_data, 133 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 134 aprint_error_dev(sc->sc_dev, 135 "unable to map control data, error = %d\n", error); 136 goto fail_1; 137 } 138 nullbuf = 139 (char *)sc->sc_control_data + sizeof(struct epic_control_data); 140 memset(nullbuf, 0, ETHER_PAD_LEN); 141 142 if ((error = bus_dmamap_create(sc->sc_dmat, 143 sizeof(struct epic_control_data), 1, 144 sizeof(struct epic_control_data), 0, BUS_DMA_NOWAIT, 145 &sc->sc_cddmamap)) != 0) { 146 aprint_error_dev(sc->sc_dev, 147 "unable to create control data DMA map, error = %d\n", 148 error); 149 goto fail_2; 150 } 151 152 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 153 sc->sc_control_data, sizeof(struct epic_control_data), NULL, 154 BUS_DMA_NOWAIT)) != 0) { 155 aprint_error_dev(sc->sc_dev, 156 "unable to load control data DMA map, error = %d\n", 157 error); 158 goto fail_3; 159 } 160 161 /* 162 * Create the transmit buffer DMA maps. 163 */ 164 for (i = 0; i < EPIC_NTXDESC; i++) { 165 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 166 EPIC_NFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 167 &EPIC_DSTX(sc, i)->ds_dmamap)) != 0) { 168 aprint_error_dev(sc->sc_dev, 169 "unable to create tx DMA map %d, error = %d\n", 170 i, error); 171 goto fail_4; 172 } 173 } 174 175 /* 176 * Create the receive buffer DMA maps. 177 */ 178 for (i = 0; i < EPIC_NRXDESC; i++) { 179 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 180 MCLBYTES, 0, BUS_DMA_NOWAIT, 181 &EPIC_DSRX(sc, i)->ds_dmamap)) != 0) { 182 aprint_error_dev(sc->sc_dev, 183 "unable to create rx DMA map %d, error = %d\n", 184 i, error); 185 goto fail_5; 186 } 187 EPIC_DSRX(sc, i)->ds_mbuf = NULL; 188 } 189 190 /* 191 * create and map the pad buffer 192 */ 193 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_PAD_LEN, 1, 194 ETHER_PAD_LEN, 0, BUS_DMA_NOWAIT,&sc->sc_nulldmamap)) != 0) { 195 aprint_error_dev(sc->sc_dev, 196 "unable to create pad buffer DMA map, error = %d\n", error); 197 goto fail_5; 198 } 199 200 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_nulldmamap, 201 nullbuf, ETHER_PAD_LEN, NULL, BUS_DMA_NOWAIT)) != 0) { 202 aprint_error_dev(sc->sc_dev, 203 "unable to load pad buffer DMA map, error = %d\n", error); 204 goto fail_6; 205 } 206 bus_dmamap_sync(sc->sc_dmat, sc->sc_nulldmamap, 0, ETHER_PAD_LEN, 207 BUS_DMASYNC_PREWRITE); 208 209 /* 210 * Bring the chip out of low-power mode and reset it to a known state. 211 */ 212 bus_space_write_4(st, sh, EPIC_GENCTL, 0); 213 epic_reset(sc); 214 215 /* 216 * Read the Ethernet address from the EEPROM. 217 */ 218 epic_read_eeprom(sc, 0, __arraycount(myea), myea); 219 for (i = 0; i < __arraycount(myea); i++) { 220 enaddr[i * 2] = myea[i] & 0xff; 221 enaddr[i * 2 + 1] = myea[i] >> 8; 222 } 223 224 /* 225 * ...and the device name. 226 */ 227 epic_read_eeprom(sc, 0x2c, __arraycount(mydevname), mydevname); 228 for (i = 0; i < __arraycount(mydevname); i++) { 229 devname[i * 2] = mydevname[i] & 0xff; 230 devname[i * 2 + 1] = mydevname[i] >> 8; 231 } 232 233 devname[sizeof(mydevname)] = '\0'; 234 for (i = sizeof(mydevname) ; i > 0; i--) { 235 if (devname[i - 1] == ' ') 236 devname[i - 1] = '\0'; 237 else 238 break; 239 } 240 241 aprint_normal_dev(sc->sc_dev, "%s, Ethernet address %s\n", 242 devname, ether_sprintf(enaddr)); 243 244 miiflags = 0; 245 if (sc->sc_hwflags & EPIC_HAS_MII_FIBER) 246 miiflags |= MIIF_HAVEFIBER; 247 248 /* 249 * Initialize our media structures and probe the MII. 250 */ 251 sc->sc_mii.mii_ifp = ifp; 252 sc->sc_mii.mii_readreg = epic_mii_read; 253 sc->sc_mii.mii_writereg = epic_mii_write; 254 sc->sc_mii.mii_statchg = epic_statchg; 255 256 sc->sc_ethercom.ec_mii = &sc->sc_mii; 257 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, epic_mediachange, 258 ether_mediastatus); 259 mii_attach(sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 260 MII_OFFSET_ANY, miiflags); 261 if (LIST_EMPTY(&sc->sc_mii.mii_phys)) { 262 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 263 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 264 } else 265 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 266 267 if (sc->sc_hwflags & EPIC_HAS_BNC) { 268 /* use the next free media instance */ 269 sc->sc_serinst = sc->sc_mii.mii_instance++; 270 ifmedia_add(&sc->sc_mii.mii_media, 271 IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, sc->sc_serinst), 272 0, NULL); 273 aprint_normal_dev(sc->sc_dev, "10base2/BNC\n"); 274 } else 275 sc->sc_serinst = -1; 276 277 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 278 ifp->if_softc = sc; 279 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 280 ifp->if_ioctl = epic_ioctl; 281 ifp->if_start = epic_start; 282 ifp->if_watchdog = epic_watchdog; 283 ifp->if_init = epic_init; 284 ifp->if_stop = epic_stop; 285 IFQ_SET_READY(&ifp->if_snd); 286 287 /* 288 * We can support 802.1Q VLAN-sized frames. 289 */ 290 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 291 292 /* 293 * Attach the interface. 294 */ 295 if_attach(ifp); 296 ether_ifattach(ifp, enaddr); 297 298 /* 299 * Make sure the interface is shutdown during reboot. 300 */ 301 if (pmf_device_register1(sc->sc_dev, NULL, NULL, epic_shutdown)) 302 pmf_class_network_register(sc->sc_dev, ifp); 303 else 304 aprint_error_dev(sc->sc_dev, 305 "couldn't establish power handler\n"); 306 307 return; 308 309 /* 310 * Free any resources we've allocated during the failed attach 311 * attempt. Do this in reverse order and fall through. 312 */ 313 fail_6: 314 bus_dmamap_destroy(sc->sc_dmat, sc->sc_nulldmamap); 315 fail_5: 316 for (i = 0; i < EPIC_NRXDESC; i++) { 317 if (EPIC_DSRX(sc, i)->ds_dmamap != NULL) 318 bus_dmamap_destroy(sc->sc_dmat, 319 EPIC_DSRX(sc, i)->ds_dmamap); 320 } 321 fail_4: 322 for (i = 0; i < EPIC_NTXDESC; i++) { 323 if (EPIC_DSTX(sc, i)->ds_dmamap != NULL) 324 bus_dmamap_destroy(sc->sc_dmat, 325 EPIC_DSTX(sc, i)->ds_dmamap); 326 } 327 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 328 fail_3: 329 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 330 fail_2: 331 bus_dmamem_unmap(sc->sc_dmat, (void *)sc->sc_control_data, 332 sizeof(struct epic_control_data)); 333 fail_1: 334 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 335 fail_0: 336 return; 337 } 338 339 /* 340 * Shutdown hook. Make sure the interface is stopped at reboot. 341 */ 342 bool 343 epic_shutdown(device_t self, int howto) 344 { 345 struct epic_softc *sc = device_private(self); 346 347 epic_stop(&sc->sc_ethercom.ec_if, 1); 348 349 return true; 350 } 351 352 /* 353 * Start packet transmission on the interface. 354 * [ifnet interface function] 355 */ 356 void 357 epic_start(struct ifnet *ifp) 358 { 359 struct epic_softc *sc = ifp->if_softc; 360 struct mbuf *m0, *m; 361 struct epic_txdesc *txd; 362 struct epic_descsoft *ds; 363 struct epic_fraglist *fr; 364 bus_dmamap_t dmamap; 365 int error, firsttx, nexttx, opending, seg; 366 u_int len; 367 368 /* 369 * Remember the previous txpending and the first transmit 370 * descriptor we use. 371 */ 372 opending = sc->sc_txpending; 373 firsttx = EPIC_NEXTTX(sc->sc_txlast); 374 375 /* 376 * Loop through the send queue, setting up transmit descriptors 377 * until we drain the queue, or use up all available transmit 378 * descriptors. 379 */ 380 while (sc->sc_txpending < EPIC_NTXDESC) { 381 /* 382 * Grab a packet off the queue. 383 */ 384 IFQ_POLL(&ifp->if_snd, m0); 385 if (m0 == NULL) 386 break; 387 m = NULL; 388 389 /* 390 * Get the last and next available transmit descriptor. 391 */ 392 nexttx = EPIC_NEXTTX(sc->sc_txlast); 393 txd = EPIC_CDTX(sc, nexttx); 394 fr = EPIC_CDFL(sc, nexttx); 395 ds = EPIC_DSTX(sc, nexttx); 396 dmamap = ds->ds_dmamap; 397 398 /* 399 * Load the DMA map. If this fails, the packet either 400 * didn't fit in the alloted number of frags, or we were 401 * short on resources. In this case, we'll copy and try 402 * again. 403 */ 404 if ((error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 405 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 || 406 (m0->m_pkthdr.len < ETHER_PAD_LEN && 407 dmamap-> dm_nsegs == EPIC_NFRAGS)) { 408 if (error == 0) 409 bus_dmamap_unload(sc->sc_dmat, dmamap); 410 411 MGETHDR(m, M_DONTWAIT, MT_DATA); 412 if (m == NULL) { 413 printf("%s: unable to allocate Tx mbuf\n", 414 device_xname(sc->sc_dev)); 415 break; 416 } 417 if (m0->m_pkthdr.len > MHLEN) { 418 MCLGET(m, M_DONTWAIT); 419 if ((m->m_flags & M_EXT) == 0) { 420 printf("%s: unable to allocate Tx " 421 "cluster\n", 422 device_xname(sc->sc_dev)); 423 m_freem(m); 424 break; 425 } 426 } 427 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, void *)); 428 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 429 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 430 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 431 if (error) { 432 printf("%s: unable to load Tx buffer, " 433 "error = %d\n", device_xname(sc->sc_dev), 434 error); 435 break; 436 } 437 } 438 IFQ_DEQUEUE(&ifp->if_snd, m0); 439 if (m != NULL) { 440 m_freem(m0); 441 m0 = m; 442 } 443 444 /* Initialize the fraglist. */ 445 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 446 fr->ef_frags[seg].ef_addr = 447 dmamap->dm_segs[seg].ds_addr; 448 fr->ef_frags[seg].ef_length = 449 dmamap->dm_segs[seg].ds_len; 450 } 451 len = m0->m_pkthdr.len; 452 if (len < ETHER_PAD_LEN) { 453 fr->ef_frags[seg].ef_addr = sc->sc_nulldma; 454 fr->ef_frags[seg].ef_length = ETHER_PAD_LEN - len; 455 len = ETHER_PAD_LEN; 456 seg++; 457 } 458 fr->ef_nfrags = seg; 459 460 EPIC_CDFLSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE); 461 462 /* Sync the DMA map. */ 463 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 464 BUS_DMASYNC_PREWRITE); 465 466 /* 467 * Store a pointer to the packet so we can free it later. 468 */ 469 ds->ds_mbuf = m0; 470 471 /* 472 * Fill in the transmit descriptor. 473 */ 474 txd->et_control = ET_TXCTL_LASTDESC | ET_TXCTL_FRAGLIST; 475 476 /* 477 * If this is the first descriptor we're enqueueing, 478 * don't give it to the EPIC yet. That could cause 479 * a race condition. We'll do it below. 480 */ 481 if (nexttx == firsttx) 482 txd->et_txstatus = TXSTAT_TXLENGTH(len); 483 else 484 txd->et_txstatus = 485 TXSTAT_TXLENGTH(len) | ET_TXSTAT_OWNER; 486 487 EPIC_CDTXSYNC(sc, nexttx, 488 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 489 490 /* Advance the tx pointer. */ 491 sc->sc_txpending++; 492 sc->sc_txlast = nexttx; 493 494 /* 495 * Pass the packet to any BPF listeners. 496 */ 497 if (ifp->if_bpf) 498 bpf_ops->bpf_mtap(ifp->if_bpf, m0); 499 } 500 501 if (sc->sc_txpending == EPIC_NTXDESC) { 502 /* No more slots left; notify upper layer. */ 503 ifp->if_flags |= IFF_OACTIVE; 504 } 505 506 if (sc->sc_txpending != opending) { 507 /* 508 * We enqueued packets. If the transmitter was idle, 509 * reset the txdirty pointer. 510 */ 511 if (opending == 0) 512 sc->sc_txdirty = firsttx; 513 514 /* 515 * Cause a transmit interrupt to happen on the 516 * last packet we enqueued. 517 */ 518 EPIC_CDTX(sc, sc->sc_txlast)->et_control |= ET_TXCTL_IAF; 519 EPIC_CDTXSYNC(sc, sc->sc_txlast, 520 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 521 522 /* 523 * The entire packet chain is set up. Give the 524 * first descriptor to the EPIC now. 525 */ 526 EPIC_CDTX(sc, firsttx)->et_txstatus |= ET_TXSTAT_OWNER; 527 EPIC_CDTXSYNC(sc, firsttx, 528 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 529 530 /* Start the transmitter. */ 531 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 532 COMMAND_TXQUEUED); 533 534 /* Set a watchdog timer in case the chip flakes out. */ 535 ifp->if_timer = 5; 536 } 537 } 538 539 /* 540 * Watchdog timer handler. 541 * [ifnet interface function] 542 */ 543 void 544 epic_watchdog(struct ifnet *ifp) 545 { 546 struct epic_softc *sc = ifp->if_softc; 547 548 printf("%s: device timeout\n", device_xname(sc->sc_dev)); 549 ifp->if_oerrors++; 550 551 (void)epic_init(ifp); 552 } 553 554 /* 555 * Handle control requests from the operator. 556 * [ifnet interface function] 557 */ 558 int 559 epic_ioctl(struct ifnet *ifp, u_long cmd, void *data) 560 { 561 struct epic_softc *sc = ifp->if_softc; 562 int s, error; 563 564 s = splnet(); 565 566 error = ether_ioctl(ifp, cmd, data); 567 if (error == ENETRESET) { 568 /* 569 * Multicast list has changed; set the hardware filter 570 * accordingly. Update our idea of the current media; 571 * epic_set_mchash() needs to know what it is. 572 */ 573 if (ifp->if_flags & IFF_RUNNING) { 574 mii_pollstat(&sc->sc_mii); 575 epic_set_mchash(sc); 576 } 577 error = 0; 578 } 579 580 splx(s); 581 return error; 582 } 583 584 /* 585 * Interrupt handler. 586 */ 587 int 588 epic_intr(void *arg) 589 { 590 struct epic_softc *sc = arg; 591 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 592 struct epic_rxdesc *rxd; 593 struct epic_txdesc *txd; 594 struct epic_descsoft *ds; 595 struct mbuf *m; 596 uint32_t intstat, rxstatus, txstatus; 597 int i, claimed = 0; 598 u_int len; 599 600 top: 601 /* 602 * Get the interrupt status from the EPIC. 603 */ 604 intstat = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT); 605 if ((intstat & INTSTAT_INT_ACTV) == 0) 606 return claimed; 607 608 claimed = 1; 609 610 /* 611 * Acknowledge the interrupt. 612 */ 613 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT, 614 intstat & INTMASK); 615 616 /* 617 * Check for receive interrupts. 618 */ 619 if (intstat & (INTSTAT_RCC | INTSTAT_RXE | INTSTAT_RQE)) { 620 for (i = sc->sc_rxptr;; i = EPIC_NEXTRX(i)) { 621 rxd = EPIC_CDRX(sc, i); 622 ds = EPIC_DSRX(sc, i); 623 624 EPIC_CDRXSYNC(sc, i, 625 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 626 627 rxstatus = rxd->er_rxstatus; 628 if (rxstatus & ER_RXSTAT_OWNER) { 629 /* 630 * We have processed all of the 631 * receive buffers. 632 */ 633 break; 634 } 635 636 /* 637 * Make sure the packet arrived intact. If an error 638 * occurred, update stats and reset the descriptor. 639 * The buffer will be reused the next time the 640 * descriptor comes up in the ring. 641 */ 642 if ((rxstatus & ER_RXSTAT_PKTINTACT) == 0) { 643 if (rxstatus & ER_RXSTAT_CRCERROR) 644 printf("%s: CRC error\n", 645 device_xname(sc->sc_dev)); 646 if (rxstatus & ER_RXSTAT_ALIGNERROR) 647 printf("%s: alignment error\n", 648 device_xname(sc->sc_dev)); 649 ifp->if_ierrors++; 650 EPIC_INIT_RXDESC(sc, i); 651 continue; 652 } 653 654 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 655 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 656 657 /* 658 * The EPIC includes the CRC with every packet; 659 * trim it. 660 */ 661 len = RXSTAT_RXLENGTH(rxstatus) - ETHER_CRC_LEN; 662 663 if (len < sizeof(struct ether_header)) { 664 /* 665 * Runt packet; drop it now. 666 */ 667 ifp->if_ierrors++; 668 EPIC_INIT_RXDESC(sc, i); 669 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 670 ds->ds_dmamap->dm_mapsize, 671 BUS_DMASYNC_PREREAD); 672 continue; 673 } 674 675 /* 676 * If the packet is small enough to fit in a 677 * single header mbuf, allocate one and copy 678 * the data into it. This greatly reduces 679 * memory consumption when we receive lots 680 * of small packets. 681 * 682 * Otherwise, we add a new buffer to the receive 683 * chain. If this fails, we drop the packet and 684 * recycle the old buffer. 685 */ 686 if (epic_copy_small != 0 && len <= MHLEN) { 687 MGETHDR(m, M_DONTWAIT, MT_DATA); 688 if (m == NULL) 689 goto dropit; 690 memcpy(mtod(m, void *), 691 mtod(ds->ds_mbuf, void *), len); 692 EPIC_INIT_RXDESC(sc, i); 693 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 694 ds->ds_dmamap->dm_mapsize, 695 BUS_DMASYNC_PREREAD); 696 } else { 697 m = ds->ds_mbuf; 698 if (epic_add_rxbuf(sc, i) != 0) { 699 dropit: 700 ifp->if_ierrors++; 701 EPIC_INIT_RXDESC(sc, i); 702 bus_dmamap_sync(sc->sc_dmat, 703 ds->ds_dmamap, 0, 704 ds->ds_dmamap->dm_mapsize, 705 BUS_DMASYNC_PREREAD); 706 continue; 707 } 708 } 709 710 m->m_pkthdr.rcvif = ifp; 711 m->m_pkthdr.len = m->m_len = len; 712 713 /* 714 * Pass this up to any BPF listeners, but only 715 * pass it up the stack if it's for us. 716 */ 717 if (ifp->if_bpf) 718 bpf_ops->bpf_mtap(ifp->if_bpf, m); 719 720 /* Pass it on. */ 721 (*ifp->if_input)(ifp, m); 722 ifp->if_ipackets++; 723 } 724 725 /* Update the receive pointer. */ 726 sc->sc_rxptr = i; 727 728 /* 729 * Check for receive queue underflow. 730 */ 731 if (intstat & INTSTAT_RQE) { 732 printf("%s: receiver queue empty\n", 733 device_xname(sc->sc_dev)); 734 /* 735 * Ring is already built; just restart the 736 * receiver. 737 */ 738 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_PRCDAR, 739 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 740 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 741 COMMAND_RXQUEUED | COMMAND_START_RX); 742 } 743 } 744 745 /* 746 * Check for transmission complete interrupts. 747 */ 748 if (intstat & (INTSTAT_TXC | INTSTAT_TXU)) { 749 ifp->if_flags &= ~IFF_OACTIVE; 750 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 751 i = EPIC_NEXTTX(i), sc->sc_txpending--) { 752 txd = EPIC_CDTX(sc, i); 753 ds = EPIC_DSTX(sc, i); 754 755 EPIC_CDTXSYNC(sc, i, 756 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 757 758 txstatus = txd->et_txstatus; 759 if (txstatus & ET_TXSTAT_OWNER) 760 break; 761 762 EPIC_CDFLSYNC(sc, i, BUS_DMASYNC_POSTWRITE); 763 764 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 765 0, ds->ds_dmamap->dm_mapsize, 766 BUS_DMASYNC_POSTWRITE); 767 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 768 m_freem(ds->ds_mbuf); 769 ds->ds_mbuf = NULL; 770 771 /* 772 * Check for errors and collisions. 773 */ 774 if ((txstatus & ET_TXSTAT_PACKETTX) == 0) 775 ifp->if_oerrors++; 776 else 777 ifp->if_opackets++; 778 ifp->if_collisions += 779 TXSTAT_COLLISIONS(txstatus); 780 if (txstatus & ET_TXSTAT_CARSENSELOST) 781 printf("%s: lost carrier\n", 782 device_xname(sc->sc_dev)); 783 } 784 785 /* Update the dirty transmit buffer pointer. */ 786 sc->sc_txdirty = i; 787 788 /* 789 * Cancel the watchdog timer if there are no pending 790 * transmissions. 791 */ 792 if (sc->sc_txpending == 0) 793 ifp->if_timer = 0; 794 795 /* 796 * Kick the transmitter after a DMA underrun. 797 */ 798 if (intstat & INTSTAT_TXU) { 799 printf("%s: transmit underrun\n", 800 device_xname(sc->sc_dev)); 801 bus_space_write_4(sc->sc_st, sc->sc_sh, 802 EPIC_COMMAND, COMMAND_TXUGO); 803 if (sc->sc_txpending) 804 bus_space_write_4(sc->sc_st, sc->sc_sh, 805 EPIC_COMMAND, COMMAND_TXQUEUED); 806 } 807 808 /* 809 * Try to get more packets going. 810 */ 811 epic_start(ifp); 812 } 813 814 /* 815 * Check for fatal interrupts. 816 */ 817 if (intstat & INTSTAT_FATAL_INT) { 818 if (intstat & INTSTAT_PTA) 819 printf("%s: PCI target abort error\n", 820 device_xname(sc->sc_dev)); 821 else if (intstat & INTSTAT_PMA) 822 printf("%s: PCI master abort error\n", 823 device_xname(sc->sc_dev)); 824 else if (intstat & INTSTAT_APE) 825 printf("%s: PCI address parity error\n", 826 device_xname(sc->sc_dev)); 827 else if (intstat & INTSTAT_DPE) 828 printf("%s: PCI data parity error\n", 829 device_xname(sc->sc_dev)); 830 else 831 printf("%s: unknown fatal error\n", 832 device_xname(sc->sc_dev)); 833 (void)epic_init(ifp); 834 } 835 836 /* 837 * Check for more interrupts. 838 */ 839 goto top; 840 } 841 842 /* 843 * One second timer, used to tick the MII. 844 */ 845 void 846 epic_tick(void *arg) 847 { 848 struct epic_softc *sc = arg; 849 int s; 850 851 s = splnet(); 852 mii_tick(&sc->sc_mii); 853 splx(s); 854 855 callout_reset(&sc->sc_mii_callout, hz, epic_tick, sc); 856 } 857 858 /* 859 * Fixup the clock source on the EPIC. 860 */ 861 void 862 epic_fixup_clock_source(struct epic_softc *sc) 863 { 864 int i; 865 866 /* 867 * According to SMC Application Note 7-15, the EPIC's clock 868 * source is incorrect following a reset. This manifests itself 869 * as failure to recognize when host software has written to 870 * a register on the EPIC. The appnote recommends issuing at 871 * least 16 consecutive writes to the CLOCK TEST bit to correctly 872 * configure the clock source. 873 */ 874 for (i = 0; i < 16; i++) 875 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TEST, 876 TEST_CLOCKTEST); 877 } 878 879 /* 880 * Perform a soft reset on the EPIC. 881 */ 882 void 883 epic_reset(struct epic_softc *sc) 884 { 885 886 epic_fixup_clock_source(sc); 887 888 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, 0); 889 delay(100); 890 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, GENCTL_SOFTRESET); 891 delay(100); 892 893 epic_fixup_clock_source(sc); 894 } 895 896 /* 897 * Initialize the interface. Must be called at splnet(). 898 */ 899 int 900 epic_init(struct ifnet *ifp) 901 { 902 struct epic_softc *sc = ifp->if_softc; 903 bus_space_tag_t st = sc->sc_st; 904 bus_space_handle_t sh = sc->sc_sh; 905 const uint8_t *enaddr = CLLADDR(ifp->if_sadl); 906 struct epic_txdesc *txd; 907 struct epic_descsoft *ds; 908 uint32_t genctl, reg0; 909 int i, error = 0; 910 911 /* 912 * Cancel any pending I/O. 913 */ 914 epic_stop(ifp, 0); 915 916 /* 917 * Reset the EPIC to a known state. 918 */ 919 epic_reset(sc); 920 921 /* 922 * Magical mystery initialization. 923 */ 924 bus_space_write_4(st, sh, EPIC_TXTEST, 0); 925 926 /* 927 * Initialize the EPIC genctl register: 928 * 929 * - 64 byte receive FIFO threshold 930 * - automatic advance to next receive frame 931 */ 932 genctl = GENCTL_RX_FIFO_THRESH0 | GENCTL_ONECOPY; 933 #if BYTE_ORDER == BIG_ENDIAN 934 genctl |= GENCTL_BIG_ENDIAN; 935 #endif 936 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 937 938 /* 939 * Reset the MII bus and PHY. 940 */ 941 reg0 = bus_space_read_4(st, sh, EPIC_NVCTL); 942 bus_space_write_4(st, sh, EPIC_NVCTL, reg0 | NVCTL_GPIO1 | NVCTL_GPOE1); 943 bus_space_write_4(st, sh, EPIC_MIICFG, MIICFG_ENASER); 944 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_RESET_PHY); 945 delay(100); 946 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 947 delay(1000); 948 bus_space_write_4(st, sh, EPIC_NVCTL, reg0); 949 950 /* 951 * Initialize Ethernet address. 952 */ 953 reg0 = enaddr[1] << 8 | enaddr[0]; 954 bus_space_write_4(st, sh, EPIC_LAN0, reg0); 955 reg0 = enaddr[3] << 8 | enaddr[2]; 956 bus_space_write_4(st, sh, EPIC_LAN1, reg0); 957 reg0 = enaddr[5] << 8 | enaddr[4]; 958 bus_space_write_4(st, sh, EPIC_LAN2, reg0); 959 960 /* 961 * Initialize receive control. Remember the external buffer 962 * size setting. 963 */ 964 reg0 = bus_space_read_4(st, sh, EPIC_RXCON) & 965 (RXCON_EXTBUFSIZESEL1 | RXCON_EXTBUFSIZESEL0); 966 reg0 |= (RXCON_RXMULTICAST | RXCON_RXBROADCAST); 967 if (ifp->if_flags & IFF_PROMISC) 968 reg0 |= RXCON_PROMISCMODE; 969 bus_space_write_4(st, sh, EPIC_RXCON, reg0); 970 971 /* Set the current media. */ 972 if ((error = epic_mediachange(ifp)) != 0) 973 goto out; 974 975 /* Set up the multicast hash table. */ 976 epic_set_mchash(sc); 977 978 /* 979 * Initialize the transmit descriptor ring. txlast is initialized 980 * to the end of the list so that it will wrap around to the first 981 * descriptor when the first packet is transmitted. 982 */ 983 for (i = 0; i < EPIC_NTXDESC; i++) { 984 txd = EPIC_CDTX(sc, i); 985 memset(txd, 0, sizeof(struct epic_txdesc)); 986 txd->et_bufaddr = EPIC_CDFLADDR(sc, i); 987 txd->et_nextdesc = EPIC_CDTXADDR(sc, EPIC_NEXTTX(i)); 988 EPIC_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 989 } 990 sc->sc_txpending = 0; 991 sc->sc_txdirty = 0; 992 sc->sc_txlast = EPIC_NTXDESC - 1; 993 994 /* 995 * Initialize the receive descriptor ring. 996 */ 997 for (i = 0; i < EPIC_NRXDESC; i++) { 998 ds = EPIC_DSRX(sc, i); 999 if (ds->ds_mbuf == NULL) { 1000 if ((error = epic_add_rxbuf(sc, i)) != 0) { 1001 printf("%s: unable to allocate or map rx " 1002 "buffer %d error = %d\n", 1003 device_xname(sc->sc_dev), i, error); 1004 /* 1005 * XXX Should attempt to run with fewer receive 1006 * XXX buffers instead of just failing. 1007 */ 1008 epic_rxdrain(sc); 1009 goto out; 1010 } 1011 } else 1012 EPIC_INIT_RXDESC(sc, i); 1013 } 1014 sc->sc_rxptr = 0; 1015 1016 /* 1017 * Initialize the interrupt mask and enable interrupts. 1018 */ 1019 bus_space_write_4(st, sh, EPIC_INTMASK, INTMASK); 1020 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_INTENA); 1021 1022 /* 1023 * Give the transmit and receive rings to the EPIC. 1024 */ 1025 bus_space_write_4(st, sh, EPIC_PTCDAR, 1026 EPIC_CDTXADDR(sc, EPIC_NEXTTX(sc->sc_txlast))); 1027 bus_space_write_4(st, sh, EPIC_PRCDAR, 1028 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 1029 1030 /* 1031 * Set the EPIC in motion. 1032 */ 1033 bus_space_write_4(st, sh, EPIC_COMMAND, 1034 COMMAND_RXQUEUED | COMMAND_START_RX); 1035 1036 /* 1037 * ...all done! 1038 */ 1039 ifp->if_flags |= IFF_RUNNING; 1040 ifp->if_flags &= ~IFF_OACTIVE; 1041 1042 /* 1043 * Start the one second clock. 1044 */ 1045 callout_reset(&sc->sc_mii_callout, hz, epic_tick, sc); 1046 1047 /* 1048 * Attempt to start output on the interface. 1049 */ 1050 epic_start(ifp); 1051 1052 out: 1053 if (error) 1054 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1055 return error; 1056 } 1057 1058 /* 1059 * Drain the receive queue. 1060 */ 1061 void 1062 epic_rxdrain(struct epic_softc *sc) 1063 { 1064 struct epic_descsoft *ds; 1065 int i; 1066 1067 for (i = 0; i < EPIC_NRXDESC; i++) { 1068 ds = EPIC_DSRX(sc, i); 1069 if (ds->ds_mbuf != NULL) { 1070 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1071 m_freem(ds->ds_mbuf); 1072 ds->ds_mbuf = NULL; 1073 } 1074 } 1075 } 1076 1077 /* 1078 * Stop transmission on the interface. 1079 */ 1080 void 1081 epic_stop(struct ifnet *ifp, int disable) 1082 { 1083 struct epic_softc *sc = ifp->if_softc; 1084 bus_space_tag_t st = sc->sc_st; 1085 bus_space_handle_t sh = sc->sc_sh; 1086 struct epic_descsoft *ds; 1087 uint32_t reg; 1088 int i; 1089 1090 /* 1091 * Stop the one second clock. 1092 */ 1093 callout_stop(&sc->sc_mii_callout); 1094 1095 /* Down the MII. */ 1096 mii_down(&sc->sc_mii); 1097 1098 /* Paranoia... */ 1099 epic_fixup_clock_source(sc); 1100 1101 /* 1102 * Disable interrupts. 1103 */ 1104 reg = bus_space_read_4(st, sh, EPIC_GENCTL); 1105 bus_space_write_4(st, sh, EPIC_GENCTL, reg & ~GENCTL_INTENA); 1106 bus_space_write_4(st, sh, EPIC_INTMASK, 0); 1107 1108 /* 1109 * Stop the DMA engine and take the receiver off-line. 1110 */ 1111 bus_space_write_4(st, sh, EPIC_COMMAND, COMMAND_STOP_RDMA | 1112 COMMAND_STOP_TDMA | COMMAND_STOP_RX); 1113 1114 /* 1115 * Release any queued transmit buffers. 1116 */ 1117 for (i = 0; i < EPIC_NTXDESC; i++) { 1118 ds = EPIC_DSTX(sc, i); 1119 if (ds->ds_mbuf != NULL) { 1120 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1121 m_freem(ds->ds_mbuf); 1122 ds->ds_mbuf = NULL; 1123 } 1124 } 1125 1126 /* 1127 * Mark the interface down and cancel the watchdog timer. 1128 */ 1129 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1130 ifp->if_timer = 0; 1131 1132 if (disable) 1133 epic_rxdrain(sc); 1134 } 1135 1136 /* 1137 * Read the EPIC Serial EEPROM. 1138 */ 1139 void 1140 epic_read_eeprom(struct epic_softc *sc, int word, int wordcnt, uint16_t *data) 1141 { 1142 bus_space_tag_t st = sc->sc_st; 1143 bus_space_handle_t sh = sc->sc_sh; 1144 uint16_t reg; 1145 int i, x; 1146 1147 #define EEPROM_WAIT_READY(st, sh) \ 1148 while ((bus_space_read_4((st), (sh), EPIC_EECTL) & EECTL_EERDY) == 0) \ 1149 /* nothing */ 1150 1151 /* 1152 * Enable the EEPROM. 1153 */ 1154 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1155 EEPROM_WAIT_READY(st, sh); 1156 1157 for (i = 0; i < wordcnt; i++) { 1158 /* Send CHIP SELECT for one clock tick. */ 1159 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE|EECTL_EECS); 1160 EEPROM_WAIT_READY(st, sh); 1161 1162 /* Shift in the READ opcode. */ 1163 for (x = 3; x > 0; x--) { 1164 reg = EECTL_ENABLE|EECTL_EECS; 1165 if (EPIC_EEPROM_OPC_READ & (1 << (x - 1))) 1166 reg |= EECTL_EEDI; 1167 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1168 EEPROM_WAIT_READY(st, sh); 1169 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1170 EEPROM_WAIT_READY(st, sh); 1171 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1172 EEPROM_WAIT_READY(st, sh); 1173 } 1174 1175 /* Shift in address. */ 1176 for (x = 6; x > 0; x--) { 1177 reg = EECTL_ENABLE|EECTL_EECS; 1178 if ((word + i) & (1 << (x - 1))) 1179 reg |= EECTL_EEDI; 1180 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1181 EEPROM_WAIT_READY(st, sh); 1182 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1183 EEPROM_WAIT_READY(st, sh); 1184 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1185 EEPROM_WAIT_READY(st, sh); 1186 } 1187 1188 /* Shift out data. */ 1189 reg = EECTL_ENABLE|EECTL_EECS; 1190 data[i] = 0; 1191 for (x = 16; x > 0; x--) { 1192 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1193 EEPROM_WAIT_READY(st, sh); 1194 if (bus_space_read_4(st, sh, EPIC_EECTL) & EECTL_EEDO) 1195 data[i] |= (1 << (x - 1)); 1196 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1197 EEPROM_WAIT_READY(st, sh); 1198 } 1199 1200 /* Clear CHIP SELECT. */ 1201 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1202 EEPROM_WAIT_READY(st, sh); 1203 } 1204 1205 /* 1206 * Disable the EEPROM. 1207 */ 1208 bus_space_write_4(st, sh, EPIC_EECTL, 0); 1209 1210 #undef EEPROM_WAIT_READY 1211 } 1212 1213 /* 1214 * Add a receive buffer to the indicated descriptor. 1215 */ 1216 int 1217 epic_add_rxbuf(struct epic_softc *sc, int idx) 1218 { 1219 struct epic_descsoft *ds = EPIC_DSRX(sc, idx); 1220 struct mbuf *m; 1221 int error; 1222 1223 MGETHDR(m, M_DONTWAIT, MT_DATA); 1224 if (m == NULL) 1225 return ENOBUFS; 1226 1227 MCLGET(m, M_DONTWAIT); 1228 if ((m->m_flags & M_EXT) == 0) { 1229 m_freem(m); 1230 return ENOBUFS; 1231 } 1232 1233 if (ds->ds_mbuf != NULL) 1234 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1235 1236 ds->ds_mbuf = m; 1237 1238 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1239 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1240 BUS_DMA_READ|BUS_DMA_NOWAIT); 1241 if (error) { 1242 printf("%s: can't load rx DMA map %d, error = %d\n", 1243 device_xname(sc->sc_dev), idx, error); 1244 panic("%s", __func__); /* XXX */ 1245 } 1246 1247 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1248 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1249 1250 EPIC_INIT_RXDESC(sc, idx); 1251 1252 return 0; 1253 } 1254 1255 /* 1256 * Set the EPIC multicast hash table. 1257 * 1258 * NOTE: We rely on a recently-updated mii_media_active here! 1259 */ 1260 void 1261 epic_set_mchash(struct epic_softc *sc) 1262 { 1263 struct ethercom *ec = &sc->sc_ethercom; 1264 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1265 struct ether_multi *enm; 1266 struct ether_multistep step; 1267 uint32_t hash, mchash[4]; 1268 1269 /* 1270 * Set up the multicast address filter by passing all multicast 1271 * addresses through a CRC generator, and then using the low-order 1272 * 6 bits as an index into the 64 bit multicast hash table (only 1273 * the lower 16 bits of each 32 bit multicast hash register are 1274 * valid). The high order bits select the register, while the 1275 * rest of the bits select the bit within the register. 1276 */ 1277 1278 if (ifp->if_flags & IFF_PROMISC) 1279 goto allmulti; 1280 1281 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_10_T) { 1282 /* XXX hardware bug in 10Mbps mode. */ 1283 goto allmulti; 1284 } 1285 1286 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0; 1287 1288 ETHER_FIRST_MULTI(step, ec, enm); 1289 while (enm != NULL) { 1290 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1291 /* 1292 * We must listen to a range of multicast addresses. 1293 * For now, just accept all multicasts, rather than 1294 * trying to set only those filter bits needed to match 1295 * the range. (At this time, the only use of address 1296 * ranges is for IP multicast routing, for which the 1297 * range is big enough to require all bits set.) 1298 */ 1299 goto allmulti; 1300 } 1301 1302 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1303 hash >>= 26; 1304 1305 /* Set the corresponding bit in the hash table. */ 1306 mchash[hash >> 4] |= 1 << (hash & 0xf); 1307 1308 ETHER_NEXT_MULTI(step, enm); 1309 } 1310 1311 ifp->if_flags &= ~IFF_ALLMULTI; 1312 goto sethash; 1313 1314 allmulti: 1315 ifp->if_flags |= IFF_ALLMULTI; 1316 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0xffff; 1317 1318 sethash: 1319 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC0, mchash[0]); 1320 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC1, mchash[1]); 1321 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC2, mchash[2]); 1322 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC3, mchash[3]); 1323 } 1324 1325 /* 1326 * Wait for the MII to become ready. 1327 */ 1328 int 1329 epic_mii_wait(struct epic_softc *sc, uint32_t rw) 1330 { 1331 int i; 1332 1333 for (i = 0; i < 50; i++) { 1334 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL) & rw) 1335 == 0) 1336 break; 1337 delay(2); 1338 } 1339 if (i == 50) { 1340 printf("%s: MII timed out\n", device_xname(sc->sc_dev)); 1341 return 1; 1342 } 1343 1344 return 0; 1345 } 1346 1347 /* 1348 * Read from the MII. 1349 */ 1350 int 1351 epic_mii_read(device_t self, int phy, int reg) 1352 { 1353 struct epic_softc *sc = device_private(self); 1354 1355 if (epic_mii_wait(sc, MMCTL_WRITE)) 1356 return 0; 1357 1358 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1359 MMCTL_ARG(phy, reg, MMCTL_READ)); 1360 1361 if (epic_mii_wait(sc, MMCTL_READ)) 1362 return 0; 1363 1364 return bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA) & 1365 MMDATA_MASK; 1366 } 1367 1368 /* 1369 * Write to the MII. 1370 */ 1371 void 1372 epic_mii_write(device_t self, int phy, int reg, int val) 1373 { 1374 struct epic_softc *sc = device_private(self); 1375 1376 if (epic_mii_wait(sc, MMCTL_WRITE)) 1377 return; 1378 1379 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA, val); 1380 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1381 MMCTL_ARG(phy, reg, MMCTL_WRITE)); 1382 } 1383 1384 /* 1385 * Callback from PHY when media changes. 1386 */ 1387 void 1388 epic_statchg(device_t self) 1389 { 1390 struct epic_softc *sc = device_private(self); 1391 uint32_t txcon, miicfg; 1392 1393 /* 1394 * Update loopback bits in TXCON to reflect duplex mode. 1395 */ 1396 txcon = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_TXCON); 1397 if (sc->sc_mii.mii_media_active & IFM_FDX) 1398 txcon |= (TXCON_LOOPBACK_D1|TXCON_LOOPBACK_D2); 1399 else 1400 txcon &= ~(TXCON_LOOPBACK_D1|TXCON_LOOPBACK_D2); 1401 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TXCON, txcon); 1402 1403 /* On some cards we need manualy set fullduplex led */ 1404 if (sc->sc_hwflags & EPIC_DUPLEXLED_ON_694) { 1405 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1406 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) 1407 miicfg |= MIICFG_ENABLE; 1408 else 1409 miicfg &= ~MIICFG_ENABLE; 1410 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1411 } 1412 1413 /* 1414 * There is a multicast filter bug in 10Mbps mode. Kick the 1415 * multicast filter in case the speed changed. 1416 */ 1417 epic_set_mchash(sc); 1418 } 1419 1420 /* 1421 * Callback from ifmedia to request new media setting. 1422 * 1423 * XXX Looks to me like some of this complexity should move into 1424 * XXX one or two custom PHY drivers. --dyoung 1425 */ 1426 int 1427 epic_mediachange(struct ifnet *ifp) 1428 { 1429 struct epic_softc *sc = ifp->if_softc; 1430 struct mii_data *mii = &sc->sc_mii; 1431 struct ifmedia *ifm = &mii->mii_media; 1432 int media = ifm->ifm_cur->ifm_media; 1433 uint32_t miicfg; 1434 struct mii_softc *miisc; 1435 int cfg, rc; 1436 1437 if ((ifp->if_flags & IFF_UP) == 0) 1438 return 0; 1439 1440 if (IFM_INST(media) != sc->sc_serinst) { 1441 /* If we're not selecting serial interface, select MII mode */ 1442 #ifdef EPICMEDIADEBUG 1443 printf("%s: parallel mode\n", ifp->if_xname); 1444 #endif 1445 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1446 miicfg &= ~MIICFG_SERMODEENA; 1447 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1448 } 1449 1450 if ((rc = mii_mediachg(mii)) == ENXIO) 1451 rc = 0; 1452 1453 if (IFM_INST(media) == sc->sc_serinst) { 1454 /* select serial interface */ 1455 #ifdef EPICMEDIADEBUG 1456 printf("%s: serial mode\n", ifp->if_xname); 1457 #endif 1458 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1459 miicfg |= (MIICFG_SERMODEENA | MIICFG_ENABLE); 1460 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1461 1462 /* There is no driver to fill this */ 1463 mii->mii_media_active = media; 1464 mii->mii_media_status = 0; 1465 1466 epic_statchg(sc->sc_dev); 1467 return 0; 1468 } 1469 1470 /* Lookup selected PHY */ 1471 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 1472 if (IFM_INST(media) == miisc->mii_inst) 1473 break; 1474 } 1475 if (!miisc) { 1476 printf("%s: can't happen\n", __func__); /* ??? panic */ 1477 return 0; 1478 } 1479 #ifdef EPICMEDIADEBUG 1480 printf("%s: using phy %s\n", ifp->if_xname, 1481 device_xname(miisc->mii_dev)); 1482 #endif 1483 1484 if (miisc->mii_flags & MIIF_HAVEFIBER) { 1485 /* XXX XXX assume it's a Level1 - should check */ 1486 1487 /* We have to powerup fiber transceivers */ 1488 cfg = PHY_READ(miisc, MII_LXTPHY_CONFIG); 1489 if (IFM_SUBTYPE(media) == IFM_100_FX) { 1490 #ifdef EPICMEDIADEBUG 1491 printf("%s: power up fiber\n", ifp->if_xname); 1492 #endif 1493 cfg |= (CONFIG_LEDC1 | CONFIG_LEDC0); 1494 } else { 1495 #ifdef EPICMEDIADEBUG 1496 printf("%s: power down fiber\n", ifp->if_xname); 1497 #endif 1498 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0); 1499 } 1500 PHY_WRITE(miisc, MII_LXTPHY_CONFIG, cfg); 1501 } 1502 1503 return rc; 1504 } 1505