1 /* $NetBSD: smc83c170.c,v 1.56 2004/10/30 18:08:40 thorpej Exp $ */ 2 3 /*- 4 * Copyright (c) 1998, 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Jason R. Thorpe of the Numerical Aerospace Simulation Facility, 9 * NASA Ames Research Center. 10 * 11 * Redistribution and use in source and binary forms, with or without 12 * modification, are permitted provided that the following conditions 13 * are met: 14 * 1. Redistributions of source code must retain the above copyright 15 * notice, this list of conditions and the following disclaimer. 16 * 2. Redistributions in binary form must reproduce the above copyright 17 * notice, this list of conditions and the following disclaimer in the 18 * documentation and/or other materials provided with the distribution. 19 * 3. All advertising materials mentioning features or use of this software 20 * must display the following acknowledgement: 21 * This product includes software developed by the NetBSD 22 * Foundation, Inc. and its contributors. 23 * 4. Neither the name of The NetBSD Foundation nor the names of its 24 * contributors may be used to endorse or promote products derived 25 * from this software without specific prior written permission. 26 * 27 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 28 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 29 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 30 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 31 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 32 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 33 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 34 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 35 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 36 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 37 * POSSIBILITY OF SUCH DAMAGE. 38 */ 39 40 /* 41 * Device driver for the Standard Microsystems Corp. 83C170 42 * Ethernet PCI Integrated Controller (EPIC/100). 43 */ 44 45 #include <sys/cdefs.h> 46 __KERNEL_RCSID(0, "$NetBSD: smc83c170.c,v 1.56 2004/10/30 18:08:40 thorpej Exp $"); 47 48 #include "bpfilter.h" 49 50 #include <sys/param.h> 51 #include <sys/systm.h> 52 #include <sys/callout.h> 53 #include <sys/mbuf.h> 54 #include <sys/malloc.h> 55 #include <sys/kernel.h> 56 #include <sys/socket.h> 57 #include <sys/ioctl.h> 58 #include <sys/errno.h> 59 #include <sys/device.h> 60 61 #include <uvm/uvm_extern.h> 62 63 #include <net/if.h> 64 #include <net/if_dl.h> 65 #include <net/if_media.h> 66 #include <net/if_ether.h> 67 68 #if NBPFILTER > 0 69 #include <net/bpf.h> 70 #endif 71 72 #include <machine/bus.h> 73 #include <machine/intr.h> 74 75 #include <dev/mii/miivar.h> 76 #include <dev/mii/lxtphyreg.h> 77 78 #include <dev/ic/smc83c170reg.h> 79 #include <dev/ic/smc83c170var.h> 80 81 void epic_start __P((struct ifnet *)); 82 void epic_watchdog __P((struct ifnet *)); 83 int epic_ioctl __P((struct ifnet *, u_long, caddr_t)); 84 int epic_init __P((struct ifnet *)); 85 void epic_stop __P((struct ifnet *, int)); 86 87 void epic_shutdown __P((void *)); 88 89 void epic_reset __P((struct epic_softc *)); 90 void epic_rxdrain __P((struct epic_softc *)); 91 int epic_add_rxbuf __P((struct epic_softc *, int)); 92 void epic_read_eeprom __P((struct epic_softc *, int, int, u_int16_t *)); 93 void epic_set_mchash __P((struct epic_softc *)); 94 void epic_fixup_clock_source __P((struct epic_softc *)); 95 int epic_mii_read __P((struct device *, int, int)); 96 void epic_mii_write __P((struct device *, int, int, int)); 97 int epic_mii_wait __P((struct epic_softc *, u_int32_t)); 98 void epic_tick __P((void *)); 99 100 void epic_statchg __P((struct device *)); 101 int epic_mediachange __P((struct ifnet *)); 102 void epic_mediastatus __P((struct ifnet *, struct ifmediareq *)); 103 104 #define INTMASK (INTSTAT_FATAL_INT | INTSTAT_TXU | \ 105 INTSTAT_TXC | INTSTAT_RXE | INTSTAT_RQE | INTSTAT_RCC) 106 107 int epic_copy_small = 0; 108 109 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 110 111 /* 112 * Attach an EPIC interface to the system. 113 */ 114 void 115 epic_attach(sc) 116 struct epic_softc *sc; 117 { 118 bus_space_tag_t st = sc->sc_st; 119 bus_space_handle_t sh = sc->sc_sh; 120 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 121 int rseg, error, miiflags; 122 u_int i; 123 bus_dma_segment_t seg; 124 u_int8_t enaddr[ETHER_ADDR_LEN], devname[12 + 1]; 125 u_int16_t myea[ETHER_ADDR_LEN / 2], mydevname[6]; 126 char *nullbuf; 127 128 callout_init(&sc->sc_mii_callout); 129 130 /* 131 * Allocate the control data structures, and create and load the 132 * DMA map for it. 133 */ 134 if ((error = bus_dmamem_alloc(sc->sc_dmat, 135 sizeof(struct epic_control_data) + ETHER_PAD_LEN, PAGE_SIZE, 0, 136 &seg, 1, &rseg, BUS_DMA_NOWAIT)) != 0) { 137 aprint_error( 138 "%s: unable to allocate control data, error = %d\n", 139 sc->sc_dev.dv_xname, error); 140 goto fail_0; 141 } 142 143 if ((error = bus_dmamem_map(sc->sc_dmat, &seg, rseg, 144 sizeof(struct epic_control_data) + ETHER_PAD_LEN, 145 (caddr_t *)&sc->sc_control_data, 146 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 147 aprint_error("%s: unable to map control data, error = %d\n", 148 sc->sc_dev.dv_xname, error); 149 goto fail_1; 150 } 151 nullbuf = 152 (char *)sc->sc_control_data + sizeof(struct epic_control_data); 153 memset(nullbuf, 0, ETHER_PAD_LEN); 154 155 if ((error = bus_dmamap_create(sc->sc_dmat, 156 sizeof(struct epic_control_data), 1, 157 sizeof(struct epic_control_data), 0, BUS_DMA_NOWAIT, 158 &sc->sc_cddmamap)) != 0) { 159 aprint_error("%s: unable to create control data DMA map, " 160 "error = %d\n", sc->sc_dev.dv_xname, error); 161 goto fail_2; 162 } 163 164 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_cddmamap, 165 sc->sc_control_data, sizeof(struct epic_control_data), NULL, 166 BUS_DMA_NOWAIT)) != 0) { 167 aprint_error( 168 "%s: unable to load control data DMA map, error = %d\n", 169 sc->sc_dev.dv_xname, error); 170 goto fail_3; 171 } 172 173 /* 174 * Create the transmit buffer DMA maps. 175 */ 176 for (i = 0; i < EPIC_NTXDESC; i++) { 177 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 178 EPIC_NFRAGS, MCLBYTES, 0, BUS_DMA_NOWAIT, 179 &EPIC_DSTX(sc, i)->ds_dmamap)) != 0) { 180 aprint_error("%s: unable to create tx DMA map %d, " 181 "error = %d\n", sc->sc_dev.dv_xname, i, error); 182 goto fail_4; 183 } 184 } 185 186 /* 187 * Create the receive buffer DMA maps. 188 */ 189 for (i = 0; i < EPIC_NRXDESC; i++) { 190 if ((error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, 191 MCLBYTES, 0, BUS_DMA_NOWAIT, 192 &EPIC_DSRX(sc, i)->ds_dmamap)) != 0) { 193 aprint_error("%s: unable to create rx DMA map %d, " 194 "error = %d\n", sc->sc_dev.dv_xname, i, error); 195 goto fail_5; 196 } 197 EPIC_DSRX(sc, i)->ds_mbuf = NULL; 198 } 199 200 /* 201 * create and map the pad buffer 202 */ 203 if ((error = bus_dmamap_create(sc->sc_dmat, ETHER_PAD_LEN, 1, 204 ETHER_PAD_LEN, 0, BUS_DMA_NOWAIT,&sc->sc_nulldmamap)) != 0) { 205 printf("%s: unable to create pad buffer DMA map, " 206 "error = %d\n", sc->sc_dev.dv_xname, error); 207 goto fail_5; 208 } 209 210 if ((error = bus_dmamap_load(sc->sc_dmat, sc->sc_nulldmamap, 211 nullbuf, ETHER_PAD_LEN, NULL, BUS_DMA_NOWAIT)) != 0) { 212 printf("%s: unable to load pad buffer DMA map, " 213 "error = %d\n", sc->sc_dev.dv_xname, error); 214 goto fail_6; 215 } 216 bus_dmamap_sync(sc->sc_dmat, sc->sc_nulldmamap, 0, ETHER_PAD_LEN, 217 BUS_DMASYNC_PREWRITE); 218 219 /* 220 * Bring the chip out of low-power mode and reset it to a known state. 221 */ 222 bus_space_write_4(st, sh, EPIC_GENCTL, 0); 223 epic_reset(sc); 224 225 /* 226 * Read the Ethernet address from the EEPROM. 227 */ 228 epic_read_eeprom(sc, 0, (sizeof(myea) / sizeof(myea[0])), myea); 229 for (i = 0; i < sizeof(myea)/ sizeof(myea[0]); i++) { 230 enaddr[i * 2] = myea[i] & 0xff; 231 enaddr[i * 2 + 1] = myea[i] >> 8; 232 } 233 234 /* 235 * ...and the device name. 236 */ 237 epic_read_eeprom(sc, 0x2c, (sizeof(mydevname) / sizeof(mydevname[0])), 238 mydevname); 239 for (i = 0; i < sizeof(mydevname) / sizeof(mydevname[0]); i++) { 240 devname[i * 2] = mydevname[i] & 0xff; 241 devname[i * 2 + 1] = mydevname[i] >> 8; 242 } 243 244 devname[sizeof(mydevname)] = '\0'; 245 for (i = sizeof(mydevname) - 1; i >= 0; i--) { 246 if (devname[i] == ' ') 247 devname[i] = '\0'; 248 else 249 break; 250 } 251 252 aprint_normal("%s: %s, Ethernet address %s\n", sc->sc_dev.dv_xname, 253 devname, ether_sprintf(enaddr)); 254 255 miiflags = 0; 256 if (sc->sc_hwflags & EPIC_HAS_MII_FIBER) 257 miiflags |= MIIF_HAVEFIBER; 258 259 /* 260 * Initialize our media structures and probe the MII. 261 */ 262 sc->sc_mii.mii_ifp = ifp; 263 sc->sc_mii.mii_readreg = epic_mii_read; 264 sc->sc_mii.mii_writereg = epic_mii_write; 265 sc->sc_mii.mii_statchg = epic_statchg; 266 ifmedia_init(&sc->sc_mii.mii_media, IFM_IMASK, epic_mediachange, 267 epic_mediastatus); 268 mii_attach(&sc->sc_dev, &sc->sc_mii, 0xffffffff, MII_PHY_ANY, 269 MII_OFFSET_ANY, miiflags); 270 if (LIST_FIRST(&sc->sc_mii.mii_phys) == NULL) { 271 ifmedia_add(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 272 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_NONE); 273 } else 274 ifmedia_set(&sc->sc_mii.mii_media, IFM_ETHER|IFM_AUTO); 275 276 if (sc->sc_hwflags & EPIC_HAS_BNC) { 277 /* use the next free media instance */ 278 sc->sc_serinst = sc->sc_mii.mii_instance++; 279 ifmedia_add(&sc->sc_mii.mii_media, 280 IFM_MAKEWORD(IFM_ETHER, IFM_10_2, 0, 281 sc->sc_serinst), 282 0, NULL); 283 aprint_normal("%s: 10base2/BNC\n", sc->sc_dev.dv_xname); 284 } else 285 sc->sc_serinst = -1; 286 287 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 288 ifp->if_softc = sc; 289 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 290 ifp->if_ioctl = epic_ioctl; 291 ifp->if_start = epic_start; 292 ifp->if_watchdog = epic_watchdog; 293 ifp->if_init = epic_init; 294 ifp->if_stop = epic_stop; 295 IFQ_SET_READY(&ifp->if_snd); 296 297 /* 298 * We can support 802.1Q VLAN-sized frames. 299 */ 300 sc->sc_ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 301 302 /* 303 * Attach the interface. 304 */ 305 if_attach(ifp); 306 ether_ifattach(ifp, enaddr); 307 308 /* 309 * Make sure the interface is shutdown during reboot. 310 */ 311 sc->sc_sdhook = shutdownhook_establish(epic_shutdown, sc); 312 if (sc->sc_sdhook == NULL) 313 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 314 sc->sc_dev.dv_xname); 315 return; 316 317 /* 318 * Free any resources we've allocated during the failed attach 319 * attempt. Do this in reverse order and fall through. 320 */ 321 fail_6: 322 bus_dmamap_destroy(sc->sc_dmat, sc->sc_nulldmamap); 323 fail_5: 324 for (i = 0; i < EPIC_NRXDESC; i++) { 325 if (EPIC_DSRX(sc, i)->ds_dmamap != NULL) 326 bus_dmamap_destroy(sc->sc_dmat, 327 EPIC_DSRX(sc, i)->ds_dmamap); 328 } 329 fail_4: 330 for (i = 0; i < EPIC_NTXDESC; i++) { 331 if (EPIC_DSTX(sc, i)->ds_dmamap != NULL) 332 bus_dmamap_destroy(sc->sc_dmat, 333 EPIC_DSTX(sc, i)->ds_dmamap); 334 } 335 bus_dmamap_unload(sc->sc_dmat, sc->sc_cddmamap); 336 fail_3: 337 bus_dmamap_destroy(sc->sc_dmat, sc->sc_cddmamap); 338 fail_2: 339 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->sc_control_data, 340 sizeof(struct epic_control_data)); 341 fail_1: 342 bus_dmamem_free(sc->sc_dmat, &seg, rseg); 343 fail_0: 344 return; 345 } 346 347 /* 348 * Shutdown hook. Make sure the interface is stopped at reboot. 349 */ 350 void 351 epic_shutdown(arg) 352 void *arg; 353 { 354 struct epic_softc *sc = arg; 355 356 epic_stop(&sc->sc_ethercom.ec_if, 1); 357 } 358 359 /* 360 * Start packet transmission on the interface. 361 * [ifnet interface function] 362 */ 363 void 364 epic_start(ifp) 365 struct ifnet *ifp; 366 { 367 struct epic_softc *sc = ifp->if_softc; 368 struct mbuf *m0, *m; 369 struct epic_txdesc *txd; 370 struct epic_descsoft *ds; 371 struct epic_fraglist *fr; 372 bus_dmamap_t dmamap; 373 int error, firsttx, nexttx, opending, seg; 374 u_int len; 375 376 /* 377 * Remember the previous txpending and the first transmit 378 * descriptor we use. 379 */ 380 opending = sc->sc_txpending; 381 firsttx = EPIC_NEXTTX(sc->sc_txlast); 382 383 /* 384 * Loop through the send queue, setting up transmit descriptors 385 * until we drain the queue, or use up all available transmit 386 * descriptors. 387 */ 388 while (sc->sc_txpending < EPIC_NTXDESC) { 389 /* 390 * Grab a packet off the queue. 391 */ 392 IFQ_POLL(&ifp->if_snd, m0); 393 if (m0 == NULL) 394 break; 395 m = NULL; 396 397 /* 398 * Get the last and next available transmit descriptor. 399 */ 400 nexttx = EPIC_NEXTTX(sc->sc_txlast); 401 txd = EPIC_CDTX(sc, nexttx); 402 fr = EPIC_CDFL(sc, nexttx); 403 ds = EPIC_DSTX(sc, nexttx); 404 dmamap = ds->ds_dmamap; 405 406 /* 407 * Load the DMA map. If this fails, the packet either 408 * didn't fit in the alloted number of frags, or we were 409 * short on resources. In this case, we'll copy and try 410 * again. 411 */ 412 if ((error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, m0, 413 BUS_DMA_WRITE|BUS_DMA_NOWAIT)) != 0 || 414 (m0->m_pkthdr.len < ETHER_PAD_LEN && 415 dmamap-> dm_nsegs == EPIC_NFRAGS)) { 416 if (error == 0) 417 bus_dmamap_unload(sc->sc_dmat, dmamap); 418 419 MGETHDR(m, M_DONTWAIT, MT_DATA); 420 if (m == NULL) { 421 printf("%s: unable to allocate Tx mbuf\n", 422 sc->sc_dev.dv_xname); 423 break; 424 } 425 if (m0->m_pkthdr.len > MHLEN) { 426 MCLGET(m, M_DONTWAIT); 427 if ((m->m_flags & M_EXT) == 0) { 428 printf("%s: unable to allocate Tx " 429 "cluster\n", sc->sc_dev.dv_xname); 430 m_freem(m); 431 break; 432 } 433 } 434 m_copydata(m0, 0, m0->m_pkthdr.len, mtod(m, caddr_t)); 435 m->m_pkthdr.len = m->m_len = m0->m_pkthdr.len; 436 error = bus_dmamap_load_mbuf(sc->sc_dmat, dmamap, 437 m, BUS_DMA_WRITE|BUS_DMA_NOWAIT); 438 if (error) { 439 printf("%s: unable to load Tx buffer, " 440 "error = %d\n", sc->sc_dev.dv_xname, error); 441 break; 442 } 443 } 444 IFQ_DEQUEUE(&ifp->if_snd, m0); 445 if (m != NULL) { 446 m_freem(m0); 447 m0 = m; 448 } 449 450 /* Initialize the fraglist. */ 451 for (seg = 0; seg < dmamap->dm_nsegs; seg++) { 452 fr->ef_frags[seg].ef_addr = 453 dmamap->dm_segs[seg].ds_addr; 454 fr->ef_frags[seg].ef_length = 455 dmamap->dm_segs[seg].ds_len; 456 } 457 len = m0->m_pkthdr.len; 458 if (len < ETHER_PAD_LEN) { 459 fr->ef_frags[seg].ef_addr = sc->sc_nulldma; 460 fr->ef_frags[seg].ef_length = ETHER_PAD_LEN - len; 461 len = ETHER_PAD_LEN; 462 seg++; 463 } 464 fr->ef_nfrags = seg; 465 466 EPIC_CDFLSYNC(sc, nexttx, BUS_DMASYNC_PREWRITE); 467 468 /* Sync the DMA map. */ 469 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 470 BUS_DMASYNC_PREWRITE); 471 472 /* 473 * Store a pointer to the packet so we can free it later. 474 */ 475 ds->ds_mbuf = m0; 476 477 /* 478 * Fill in the transmit descriptor. 479 */ 480 txd->et_control = ET_TXCTL_LASTDESC | ET_TXCTL_FRAGLIST; 481 482 /* 483 * If this is the first descriptor we're enqueueing, 484 * don't give it to the EPIC yet. That could cause 485 * a race condition. We'll do it below. 486 */ 487 if (nexttx == firsttx) 488 txd->et_txstatus = TXSTAT_TXLENGTH(len); 489 else 490 txd->et_txstatus = 491 TXSTAT_TXLENGTH(len) | ET_TXSTAT_OWNER; 492 493 EPIC_CDTXSYNC(sc, nexttx, 494 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 495 496 /* Advance the tx pointer. */ 497 sc->sc_txpending++; 498 sc->sc_txlast = nexttx; 499 500 #if NBPFILTER > 0 501 /* 502 * Pass the packet to any BPF listeners. 503 */ 504 if (ifp->if_bpf) 505 bpf_mtap(ifp->if_bpf, m0); 506 #endif 507 } 508 509 if (sc->sc_txpending == EPIC_NTXDESC) { 510 /* No more slots left; notify upper layer. */ 511 ifp->if_flags |= IFF_OACTIVE; 512 } 513 514 if (sc->sc_txpending != opending) { 515 /* 516 * We enqueued packets. If the transmitter was idle, 517 * reset the txdirty pointer. 518 */ 519 if (opending == 0) 520 sc->sc_txdirty = firsttx; 521 522 /* 523 * Cause a transmit interrupt to happen on the 524 * last packet we enqueued. 525 */ 526 EPIC_CDTX(sc, sc->sc_txlast)->et_control |= ET_TXCTL_IAF; 527 EPIC_CDTXSYNC(sc, sc->sc_txlast, 528 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 529 530 /* 531 * The entire packet chain is set up. Give the 532 * first descriptor to the EPIC now. 533 */ 534 EPIC_CDTX(sc, firsttx)->et_txstatus |= ET_TXSTAT_OWNER; 535 EPIC_CDTXSYNC(sc, firsttx, 536 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 537 538 /* Start the transmitter. */ 539 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 540 COMMAND_TXQUEUED); 541 542 /* Set a watchdog timer in case the chip flakes out. */ 543 ifp->if_timer = 5; 544 } 545 } 546 547 /* 548 * Watchdog timer handler. 549 * [ifnet interface function] 550 */ 551 void 552 epic_watchdog(ifp) 553 struct ifnet *ifp; 554 { 555 struct epic_softc *sc = ifp->if_softc; 556 557 printf("%s: device timeout\n", sc->sc_dev.dv_xname); 558 ifp->if_oerrors++; 559 560 (void) epic_init(ifp); 561 } 562 563 /* 564 * Handle control requests from the operator. 565 * [ifnet interface function] 566 */ 567 int 568 epic_ioctl(ifp, cmd, data) 569 struct ifnet *ifp; 570 u_long cmd; 571 caddr_t data; 572 { 573 struct epic_softc *sc = ifp->if_softc; 574 struct ifreq *ifr = (struct ifreq *)data; 575 int s, error; 576 577 s = splnet(); 578 579 switch (cmd) { 580 case SIOCSIFMEDIA: 581 case SIOCGIFMEDIA: 582 error = ifmedia_ioctl(ifp, ifr, &sc->sc_mii.mii_media, cmd); 583 break; 584 585 default: 586 error = ether_ioctl(ifp, cmd, data); 587 if (error == ENETRESET) { 588 /* 589 * Multicast list has changed; set the hardware filter 590 * accordingly. Update our idea of the current media; 591 * epic_set_mchash() needs to know what it is. 592 */ 593 if (ifp->if_flags & IFF_RUNNING) { 594 mii_pollstat(&sc->sc_mii); 595 epic_set_mchash(sc); 596 } 597 error = 0; 598 } 599 break; 600 } 601 602 splx(s); 603 return (error); 604 } 605 606 /* 607 * Interrupt handler. 608 */ 609 int 610 epic_intr(arg) 611 void *arg; 612 { 613 struct epic_softc *sc = arg; 614 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 615 struct epic_rxdesc *rxd; 616 struct epic_txdesc *txd; 617 struct epic_descsoft *ds; 618 struct mbuf *m; 619 u_int32_t intstat, rxstatus, txstatus; 620 int i, claimed = 0; 621 u_int len; 622 623 top: 624 /* 625 * Get the interrupt status from the EPIC. 626 */ 627 intstat = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT); 628 if ((intstat & INTSTAT_INT_ACTV) == 0) 629 return (claimed); 630 631 claimed = 1; 632 633 /* 634 * Acknowledge the interrupt. 635 */ 636 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_INTSTAT, 637 intstat & INTMASK); 638 639 /* 640 * Check for receive interrupts. 641 */ 642 if (intstat & (INTSTAT_RCC | INTSTAT_RXE | INTSTAT_RQE)) { 643 for (i = sc->sc_rxptr;; i = EPIC_NEXTRX(i)) { 644 rxd = EPIC_CDRX(sc, i); 645 ds = EPIC_DSRX(sc, i); 646 647 EPIC_CDRXSYNC(sc, i, 648 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 649 650 rxstatus = rxd->er_rxstatus; 651 if (rxstatus & ER_RXSTAT_OWNER) { 652 /* 653 * We have processed all of the 654 * receive buffers. 655 */ 656 break; 657 } 658 659 /* 660 * Make sure the packet arrived intact. If an error 661 * occurred, update stats and reset the descriptor. 662 * The buffer will be reused the next time the 663 * descriptor comes up in the ring. 664 */ 665 if ((rxstatus & ER_RXSTAT_PKTINTACT) == 0) { 666 if (rxstatus & ER_RXSTAT_CRCERROR) 667 printf("%s: CRC error\n", 668 sc->sc_dev.dv_xname); 669 if (rxstatus & ER_RXSTAT_ALIGNERROR) 670 printf("%s: alignment error\n", 671 sc->sc_dev.dv_xname); 672 ifp->if_ierrors++; 673 EPIC_INIT_RXDESC(sc, i); 674 continue; 675 } 676 677 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 678 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 679 680 /* 681 * The EPIC includes the CRC with every packet. 682 */ 683 len = RXSTAT_RXLENGTH(rxstatus); 684 685 if (len < sizeof(struct ether_header)) { 686 /* 687 * Runt packet; drop it now. 688 */ 689 ifp->if_ierrors++; 690 EPIC_INIT_RXDESC(sc, i); 691 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 692 ds->ds_dmamap->dm_mapsize, 693 BUS_DMASYNC_PREREAD); 694 continue; 695 } 696 697 /* 698 * If the packet is small enough to fit in a 699 * single header mbuf, allocate one and copy 700 * the data into it. This greatly reduces 701 * memory consumption when we receive lots 702 * of small packets. 703 * 704 * Otherwise, we add a new buffer to the receive 705 * chain. If this fails, we drop the packet and 706 * recycle the old buffer. 707 */ 708 if (epic_copy_small != 0 && len <= MHLEN) { 709 MGETHDR(m, M_DONTWAIT, MT_DATA); 710 if (m == NULL) 711 goto dropit; 712 memcpy(mtod(m, caddr_t), 713 mtod(ds->ds_mbuf, caddr_t), len); 714 EPIC_INIT_RXDESC(sc, i); 715 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 716 ds->ds_dmamap->dm_mapsize, 717 BUS_DMASYNC_PREREAD); 718 } else { 719 m = ds->ds_mbuf; 720 if (epic_add_rxbuf(sc, i) != 0) { 721 dropit: 722 ifp->if_ierrors++; 723 EPIC_INIT_RXDESC(sc, i); 724 bus_dmamap_sync(sc->sc_dmat, 725 ds->ds_dmamap, 0, 726 ds->ds_dmamap->dm_mapsize, 727 BUS_DMASYNC_PREREAD); 728 continue; 729 } 730 } 731 732 m->m_flags |= M_HASFCS; 733 m->m_pkthdr.rcvif = ifp; 734 m->m_pkthdr.len = m->m_len = len; 735 736 #if NBPFILTER > 0 737 /* 738 * Pass this up to any BPF listeners, but only 739 * pass it up the stack if its for us. 740 */ 741 if (ifp->if_bpf) 742 bpf_mtap(ifp->if_bpf, m); 743 #endif 744 745 /* Pass it on. */ 746 (*ifp->if_input)(ifp, m); 747 ifp->if_ipackets++; 748 } 749 750 /* Update the receive pointer. */ 751 sc->sc_rxptr = i; 752 753 /* 754 * Check for receive queue underflow. 755 */ 756 if (intstat & INTSTAT_RQE) { 757 printf("%s: receiver queue empty\n", 758 sc->sc_dev.dv_xname); 759 /* 760 * Ring is already built; just restart the 761 * receiver. 762 */ 763 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_PRCDAR, 764 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 765 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_COMMAND, 766 COMMAND_RXQUEUED | COMMAND_START_RX); 767 } 768 } 769 770 /* 771 * Check for transmission complete interrupts. 772 */ 773 if (intstat & (INTSTAT_TXC | INTSTAT_TXU)) { 774 ifp->if_flags &= ~IFF_OACTIVE; 775 for (i = sc->sc_txdirty; sc->sc_txpending != 0; 776 i = EPIC_NEXTTX(i), sc->sc_txpending--) { 777 txd = EPIC_CDTX(sc, i); 778 ds = EPIC_DSTX(sc, i); 779 780 EPIC_CDTXSYNC(sc, i, 781 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 782 783 txstatus = txd->et_txstatus; 784 if (txstatus & ET_TXSTAT_OWNER) 785 break; 786 787 EPIC_CDFLSYNC(sc, i, BUS_DMASYNC_POSTWRITE); 788 789 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 790 0, ds->ds_dmamap->dm_mapsize, 791 BUS_DMASYNC_POSTWRITE); 792 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 793 m_freem(ds->ds_mbuf); 794 ds->ds_mbuf = NULL; 795 796 /* 797 * Check for errors and collisions. 798 */ 799 if ((txstatus & ET_TXSTAT_PACKETTX) == 0) 800 ifp->if_oerrors++; 801 else 802 ifp->if_opackets++; 803 ifp->if_collisions += 804 TXSTAT_COLLISIONS(txstatus); 805 if (txstatus & ET_TXSTAT_CARSENSELOST) 806 printf("%s: lost carrier\n", 807 sc->sc_dev.dv_xname); 808 } 809 810 /* Update the dirty transmit buffer pointer. */ 811 sc->sc_txdirty = i; 812 813 /* 814 * Cancel the watchdog timer if there are no pending 815 * transmissions. 816 */ 817 if (sc->sc_txpending == 0) 818 ifp->if_timer = 0; 819 820 /* 821 * Kick the transmitter after a DMA underrun. 822 */ 823 if (intstat & INTSTAT_TXU) { 824 printf("%s: transmit underrun\n", sc->sc_dev.dv_xname); 825 bus_space_write_4(sc->sc_st, sc->sc_sh, 826 EPIC_COMMAND, COMMAND_TXUGO); 827 if (sc->sc_txpending) 828 bus_space_write_4(sc->sc_st, sc->sc_sh, 829 EPIC_COMMAND, COMMAND_TXQUEUED); 830 } 831 832 /* 833 * Try to get more packets going. 834 */ 835 epic_start(ifp); 836 } 837 838 /* 839 * Check for fatal interrupts. 840 */ 841 if (intstat & INTSTAT_FATAL_INT) { 842 if (intstat & INTSTAT_PTA) 843 printf("%s: PCI target abort error\n", 844 sc->sc_dev.dv_xname); 845 else if (intstat & INTSTAT_PMA) 846 printf("%s: PCI master abort error\n", 847 sc->sc_dev.dv_xname); 848 else if (intstat & INTSTAT_APE) 849 printf("%s: PCI address parity error\n", 850 sc->sc_dev.dv_xname); 851 else if (intstat & INTSTAT_DPE) 852 printf("%s: PCI data parity error\n", 853 sc->sc_dev.dv_xname); 854 else 855 printf("%s: unknown fatal error\n", 856 sc->sc_dev.dv_xname); 857 (void) epic_init(ifp); 858 } 859 860 /* 861 * Check for more interrupts. 862 */ 863 goto top; 864 } 865 866 /* 867 * One second timer, used to tick the MII. 868 */ 869 void 870 epic_tick(arg) 871 void *arg; 872 { 873 struct epic_softc *sc = arg; 874 int s; 875 876 s = splnet(); 877 mii_tick(&sc->sc_mii); 878 splx(s); 879 880 callout_reset(&sc->sc_mii_callout, hz, epic_tick, sc); 881 } 882 883 /* 884 * Fixup the clock source on the EPIC. 885 */ 886 void 887 epic_fixup_clock_source(sc) 888 struct epic_softc *sc; 889 { 890 int i; 891 892 /* 893 * According to SMC Application Note 7-15, the EPIC's clock 894 * source is incorrect following a reset. This manifests itself 895 * as failure to recognize when host software has written to 896 * a register on the EPIC. The appnote recommends issuing at 897 * least 16 consecutive writes to the CLOCK TEST bit to correctly 898 * configure the clock source. 899 */ 900 for (i = 0; i < 16; i++) 901 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TEST, 902 TEST_CLOCKTEST); 903 } 904 905 /* 906 * Perform a soft reset on the EPIC. 907 */ 908 void 909 epic_reset(sc) 910 struct epic_softc *sc; 911 { 912 913 epic_fixup_clock_source(sc); 914 915 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, 0); 916 delay(100); 917 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_GENCTL, GENCTL_SOFTRESET); 918 delay(100); 919 920 epic_fixup_clock_source(sc); 921 } 922 923 /* 924 * Initialize the interface. Must be called at splnet(). 925 */ 926 int 927 epic_init(ifp) 928 struct ifnet *ifp; 929 { 930 struct epic_softc *sc = ifp->if_softc; 931 bus_space_tag_t st = sc->sc_st; 932 bus_space_handle_t sh = sc->sc_sh; 933 u_int8_t *enaddr = LLADDR(ifp->if_sadl); 934 struct epic_txdesc *txd; 935 struct epic_descsoft *ds; 936 u_int32_t genctl, reg0; 937 int i, error = 0; 938 939 /* 940 * Cancel any pending I/O. 941 */ 942 epic_stop(ifp, 0); 943 944 /* 945 * Reset the EPIC to a known state. 946 */ 947 epic_reset(sc); 948 949 /* 950 * Magical mystery initialization. 951 */ 952 bus_space_write_4(st, sh, EPIC_TXTEST, 0); 953 954 /* 955 * Initialize the EPIC genctl register: 956 * 957 * - 64 byte receive FIFO threshold 958 * - automatic advance to next receive frame 959 */ 960 genctl = GENCTL_RX_FIFO_THRESH0 | GENCTL_ONECOPY; 961 #if BYTE_ORDER == BIG_ENDIAN 962 genctl |= GENCTL_BIG_ENDIAN; 963 #endif 964 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 965 966 /* 967 * Reset the MII bus and PHY. 968 */ 969 reg0 = bus_space_read_4(st, sh, EPIC_NVCTL); 970 bus_space_write_4(st, sh, EPIC_NVCTL, reg0 | NVCTL_GPIO1 | NVCTL_GPOE1); 971 bus_space_write_4(st, sh, EPIC_MIICFG, MIICFG_ENASER); 972 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_RESET_PHY); 973 delay(100); 974 bus_space_write_4(st, sh, EPIC_GENCTL, genctl); 975 delay(1000); 976 bus_space_write_4(st, sh, EPIC_NVCTL, reg0); 977 978 /* 979 * Initialize Ethernet address. 980 */ 981 reg0 = enaddr[1] << 8 | enaddr[0]; 982 bus_space_write_4(st, sh, EPIC_LAN0, reg0); 983 reg0 = enaddr[3] << 8 | enaddr[2]; 984 bus_space_write_4(st, sh, EPIC_LAN1, reg0); 985 reg0 = enaddr[5] << 8 | enaddr[4]; 986 bus_space_write_4(st, sh, EPIC_LAN2, reg0); 987 988 /* 989 * Initialize receive control. Remember the external buffer 990 * size setting. 991 */ 992 reg0 = bus_space_read_4(st, sh, EPIC_RXCON) & 993 (RXCON_EXTBUFSIZESEL1 | RXCON_EXTBUFSIZESEL0); 994 reg0 |= (RXCON_RXMULTICAST | RXCON_RXBROADCAST); 995 if (ifp->if_flags & IFF_PROMISC) 996 reg0 |= RXCON_PROMISCMODE; 997 bus_space_write_4(st, sh, EPIC_RXCON, reg0); 998 999 /* Set the current media. */ 1000 epic_mediachange(ifp); 1001 1002 /* Set up the multicast hash table. */ 1003 epic_set_mchash(sc); 1004 1005 /* 1006 * Initialize the transmit descriptor ring. txlast is initialized 1007 * to the end of the list so that it will wrap around to the first 1008 * descriptor when the first packet is transmitted. 1009 */ 1010 for (i = 0; i < EPIC_NTXDESC; i++) { 1011 txd = EPIC_CDTX(sc, i); 1012 memset(txd, 0, sizeof(struct epic_txdesc)); 1013 txd->et_bufaddr = EPIC_CDFLADDR(sc, i); 1014 txd->et_nextdesc = EPIC_CDTXADDR(sc, EPIC_NEXTTX(i)); 1015 EPIC_CDTXSYNC(sc, i, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1016 } 1017 sc->sc_txpending = 0; 1018 sc->sc_txdirty = 0; 1019 sc->sc_txlast = EPIC_NTXDESC - 1; 1020 1021 /* 1022 * Initialize the receive descriptor ring. 1023 */ 1024 for (i = 0; i < EPIC_NRXDESC; i++) { 1025 ds = EPIC_DSRX(sc, i); 1026 if (ds->ds_mbuf == NULL) { 1027 if ((error = epic_add_rxbuf(sc, i)) != 0) { 1028 printf("%s: unable to allocate or map rx " 1029 "buffer %d error = %d\n", 1030 sc->sc_dev.dv_xname, i, error); 1031 /* 1032 * XXX Should attempt to run with fewer receive 1033 * XXX buffers instead of just failing. 1034 */ 1035 epic_rxdrain(sc); 1036 goto out; 1037 } 1038 } else 1039 EPIC_INIT_RXDESC(sc, i); 1040 } 1041 sc->sc_rxptr = 0; 1042 1043 /* 1044 * Initialize the interrupt mask and enable interrupts. 1045 */ 1046 bus_space_write_4(st, sh, EPIC_INTMASK, INTMASK); 1047 bus_space_write_4(st, sh, EPIC_GENCTL, genctl | GENCTL_INTENA); 1048 1049 /* 1050 * Give the transmit and receive rings to the EPIC. 1051 */ 1052 bus_space_write_4(st, sh, EPIC_PTCDAR, 1053 EPIC_CDTXADDR(sc, EPIC_NEXTTX(sc->sc_txlast))); 1054 bus_space_write_4(st, sh, EPIC_PRCDAR, 1055 EPIC_CDRXADDR(sc, sc->sc_rxptr)); 1056 1057 /* 1058 * Set the EPIC in motion. 1059 */ 1060 bus_space_write_4(st, sh, EPIC_COMMAND, 1061 COMMAND_RXQUEUED | COMMAND_START_RX); 1062 1063 /* 1064 * ...all done! 1065 */ 1066 ifp->if_flags |= IFF_RUNNING; 1067 ifp->if_flags &= ~IFF_OACTIVE; 1068 1069 /* 1070 * Start the one second clock. 1071 */ 1072 callout_reset(&sc->sc_mii_callout, hz, epic_tick, sc); 1073 1074 /* 1075 * Attempt to start output on the interface. 1076 */ 1077 epic_start(ifp); 1078 1079 out: 1080 if (error) 1081 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1082 return (error); 1083 } 1084 1085 /* 1086 * Drain the receive queue. 1087 */ 1088 void 1089 epic_rxdrain(sc) 1090 struct epic_softc *sc; 1091 { 1092 struct epic_descsoft *ds; 1093 int i; 1094 1095 for (i = 0; i < EPIC_NRXDESC; i++) { 1096 ds = EPIC_DSRX(sc, i); 1097 if (ds->ds_mbuf != NULL) { 1098 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1099 m_freem(ds->ds_mbuf); 1100 ds->ds_mbuf = NULL; 1101 } 1102 } 1103 } 1104 1105 /* 1106 * Stop transmission on the interface. 1107 */ 1108 void 1109 epic_stop(ifp, disable) 1110 struct ifnet *ifp; 1111 int disable; 1112 { 1113 struct epic_softc *sc = ifp->if_softc; 1114 bus_space_tag_t st = sc->sc_st; 1115 bus_space_handle_t sh = sc->sc_sh; 1116 struct epic_descsoft *ds; 1117 u_int32_t reg; 1118 int i; 1119 1120 /* 1121 * Stop the one second clock. 1122 */ 1123 callout_stop(&sc->sc_mii_callout); 1124 1125 /* Down the MII. */ 1126 mii_down(&sc->sc_mii); 1127 1128 /* Paranoia... */ 1129 epic_fixup_clock_source(sc); 1130 1131 /* 1132 * Disable interrupts. 1133 */ 1134 reg = bus_space_read_4(st, sh, EPIC_GENCTL); 1135 bus_space_write_4(st, sh, EPIC_GENCTL, reg & ~GENCTL_INTENA); 1136 bus_space_write_4(st, sh, EPIC_INTMASK, 0); 1137 1138 /* 1139 * Stop the DMA engine and take the receiver off-line. 1140 */ 1141 bus_space_write_4(st, sh, EPIC_COMMAND, COMMAND_STOP_RDMA | 1142 COMMAND_STOP_TDMA | COMMAND_STOP_RX); 1143 1144 /* 1145 * Release any queued transmit buffers. 1146 */ 1147 for (i = 0; i < EPIC_NTXDESC; i++) { 1148 ds = EPIC_DSTX(sc, i); 1149 if (ds->ds_mbuf != NULL) { 1150 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1151 m_freem(ds->ds_mbuf); 1152 ds->ds_mbuf = NULL; 1153 } 1154 } 1155 1156 if (disable) 1157 epic_rxdrain(sc); 1158 1159 /* 1160 * Mark the interface down and cancel the watchdog timer. 1161 */ 1162 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1163 ifp->if_timer = 0; 1164 } 1165 1166 /* 1167 * Read the EPIC Serial EEPROM. 1168 */ 1169 void 1170 epic_read_eeprom(sc, word, wordcnt, data) 1171 struct epic_softc *sc; 1172 int word, wordcnt; 1173 u_int16_t *data; 1174 { 1175 bus_space_tag_t st = sc->sc_st; 1176 bus_space_handle_t sh = sc->sc_sh; 1177 u_int16_t reg; 1178 int i, x; 1179 1180 #define EEPROM_WAIT_READY(st, sh) \ 1181 while ((bus_space_read_4((st), (sh), EPIC_EECTL) & EECTL_EERDY) == 0) \ 1182 /* nothing */ 1183 1184 /* 1185 * Enable the EEPROM. 1186 */ 1187 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1188 EEPROM_WAIT_READY(st, sh); 1189 1190 for (i = 0; i < wordcnt; i++) { 1191 /* Send CHIP SELECT for one clock tick. */ 1192 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE|EECTL_EECS); 1193 EEPROM_WAIT_READY(st, sh); 1194 1195 /* Shift in the READ opcode. */ 1196 for (x = 3; x > 0; x--) { 1197 reg = EECTL_ENABLE|EECTL_EECS; 1198 if (EPIC_EEPROM_OPC_READ & (1 << (x - 1))) 1199 reg |= EECTL_EEDI; 1200 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1201 EEPROM_WAIT_READY(st, sh); 1202 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1203 EEPROM_WAIT_READY(st, sh); 1204 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1205 EEPROM_WAIT_READY(st, sh); 1206 } 1207 1208 /* Shift in address. */ 1209 for (x = 6; x > 0; x--) { 1210 reg = EECTL_ENABLE|EECTL_EECS; 1211 if ((word + i) & (1 << (x - 1))) 1212 reg |= EECTL_EEDI; 1213 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1214 EEPROM_WAIT_READY(st, sh); 1215 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1216 EEPROM_WAIT_READY(st, sh); 1217 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1218 EEPROM_WAIT_READY(st, sh); 1219 } 1220 1221 /* Shift out data. */ 1222 reg = EECTL_ENABLE|EECTL_EECS; 1223 data[i] = 0; 1224 for (x = 16; x > 0; x--) { 1225 bus_space_write_4(st, sh, EPIC_EECTL, reg|EECTL_EESK); 1226 EEPROM_WAIT_READY(st, sh); 1227 if (bus_space_read_4(st, sh, EPIC_EECTL) & EECTL_EEDO) 1228 data[i] |= (1 << (x - 1)); 1229 bus_space_write_4(st, sh, EPIC_EECTL, reg); 1230 EEPROM_WAIT_READY(st, sh); 1231 } 1232 1233 /* Clear CHIP SELECT. */ 1234 bus_space_write_4(st, sh, EPIC_EECTL, EECTL_ENABLE); 1235 EEPROM_WAIT_READY(st, sh); 1236 } 1237 1238 /* 1239 * Disable the EEPROM. 1240 */ 1241 bus_space_write_4(st, sh, EPIC_EECTL, 0); 1242 1243 #undef EEPROM_WAIT_READY 1244 } 1245 1246 /* 1247 * Add a receive buffer to the indicated descriptor. 1248 */ 1249 int 1250 epic_add_rxbuf(sc, idx) 1251 struct epic_softc *sc; 1252 int idx; 1253 { 1254 struct epic_descsoft *ds = EPIC_DSRX(sc, idx); 1255 struct mbuf *m; 1256 int error; 1257 1258 MGETHDR(m, M_DONTWAIT, MT_DATA); 1259 if (m == NULL) 1260 return (ENOBUFS); 1261 1262 MCLGET(m, M_DONTWAIT); 1263 if ((m->m_flags & M_EXT) == 0) { 1264 m_freem(m); 1265 return (ENOBUFS); 1266 } 1267 1268 if (ds->ds_mbuf != NULL) 1269 bus_dmamap_unload(sc->sc_dmat, ds->ds_dmamap); 1270 1271 ds->ds_mbuf = m; 1272 1273 error = bus_dmamap_load(sc->sc_dmat, ds->ds_dmamap, 1274 m->m_ext.ext_buf, m->m_ext.ext_size, NULL, 1275 BUS_DMA_READ|BUS_DMA_NOWAIT); 1276 if (error) { 1277 printf("%s: can't load rx DMA map %d, error = %d\n", 1278 sc->sc_dev.dv_xname, idx, error); 1279 panic("epic_add_rxbuf"); /* XXX */ 1280 } 1281 1282 bus_dmamap_sync(sc->sc_dmat, ds->ds_dmamap, 0, 1283 ds->ds_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1284 1285 EPIC_INIT_RXDESC(sc, idx); 1286 1287 return (0); 1288 } 1289 1290 /* 1291 * Set the EPIC multicast hash table. 1292 * 1293 * NOTE: We rely on a recently-updated mii_media_active here! 1294 */ 1295 void 1296 epic_set_mchash(sc) 1297 struct epic_softc *sc; 1298 { 1299 struct ethercom *ec = &sc->sc_ethercom; 1300 struct ifnet *ifp = &sc->sc_ethercom.ec_if; 1301 struct ether_multi *enm; 1302 struct ether_multistep step; 1303 u_int32_t hash, mchash[4]; 1304 1305 /* 1306 * Set up the multicast address filter by passing all multicast 1307 * addresses through a CRC generator, and then using the low-order 1308 * 6 bits as an index into the 64 bit multicast hash table (only 1309 * the lower 16 bits of each 32 bit multicast hash register are 1310 * valid). The high order bits select the register, while the 1311 * rest of the bits select the bit within the register. 1312 */ 1313 1314 if (ifp->if_flags & IFF_PROMISC) 1315 goto allmulti; 1316 1317 if (IFM_SUBTYPE(sc->sc_mii.mii_media_active) == IFM_10_T) { 1318 /* XXX hardware bug in 10Mbps mode. */ 1319 goto allmulti; 1320 } 1321 1322 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0; 1323 1324 ETHER_FIRST_MULTI(step, ec, enm); 1325 while (enm != NULL) { 1326 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, ETHER_ADDR_LEN)) { 1327 /* 1328 * We must listen to a range of multicast addresses. 1329 * For now, just accept all multicasts, rather than 1330 * trying to set only those filter bits needed to match 1331 * the range. (At this time, the only use of address 1332 * ranges is for IP multicast routing, for which the 1333 * range is big enough to require all bits set.) 1334 */ 1335 goto allmulti; 1336 } 1337 1338 hash = ether_crc32_be(enm->enm_addrlo, ETHER_ADDR_LEN); 1339 hash >>= 26; 1340 1341 /* Set the corresponding bit in the hash table. */ 1342 mchash[hash >> 4] |= 1 << (hash & 0xf); 1343 1344 ETHER_NEXT_MULTI(step, enm); 1345 } 1346 1347 ifp->if_flags &= ~IFF_ALLMULTI; 1348 goto sethash; 1349 1350 allmulti: 1351 ifp->if_flags |= IFF_ALLMULTI; 1352 mchash[0] = mchash[1] = mchash[2] = mchash[3] = 0xffff; 1353 1354 sethash: 1355 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC0, mchash[0]); 1356 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC1, mchash[1]); 1357 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC2, mchash[2]); 1358 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MC3, mchash[3]); 1359 } 1360 1361 /* 1362 * Wait for the MII to become ready. 1363 */ 1364 int 1365 epic_mii_wait(sc, rw) 1366 struct epic_softc *sc; 1367 u_int32_t rw; 1368 { 1369 int i; 1370 1371 for (i = 0; i < 50; i++) { 1372 if ((bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL) & rw) 1373 == 0) 1374 break; 1375 delay(2); 1376 } 1377 if (i == 50) { 1378 printf("%s: MII timed out\n", sc->sc_dev.dv_xname); 1379 return (1); 1380 } 1381 1382 return (0); 1383 } 1384 1385 /* 1386 * Read from the MII. 1387 */ 1388 int 1389 epic_mii_read(self, phy, reg) 1390 struct device *self; 1391 int phy, reg; 1392 { 1393 struct epic_softc *sc = (struct epic_softc *)self; 1394 1395 if (epic_mii_wait(sc, MMCTL_WRITE)) 1396 return (0); 1397 1398 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1399 MMCTL_ARG(phy, reg, MMCTL_READ)); 1400 1401 if (epic_mii_wait(sc, MMCTL_READ)) 1402 return (0); 1403 1404 return (bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA) & 1405 MMDATA_MASK); 1406 } 1407 1408 /* 1409 * Write to the MII. 1410 */ 1411 void 1412 epic_mii_write(self, phy, reg, val) 1413 struct device *self; 1414 int phy, reg, val; 1415 { 1416 struct epic_softc *sc = (struct epic_softc *)self; 1417 1418 if (epic_mii_wait(sc, MMCTL_WRITE)) 1419 return; 1420 1421 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMDATA, val); 1422 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MMCTL, 1423 MMCTL_ARG(phy, reg, MMCTL_WRITE)); 1424 } 1425 1426 /* 1427 * Callback from PHY when media changes. 1428 */ 1429 void 1430 epic_statchg(self) 1431 struct device *self; 1432 { 1433 struct epic_softc *sc = (struct epic_softc *)self; 1434 u_int32_t txcon, miicfg; 1435 1436 /* 1437 * Update loopback bits in TXCON to reflect duplex mode. 1438 */ 1439 txcon = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_TXCON); 1440 if (sc->sc_mii.mii_media_active & IFM_FDX) 1441 txcon |= (TXCON_LOOPBACK_D1|TXCON_LOOPBACK_D2); 1442 else 1443 txcon &= ~(TXCON_LOOPBACK_D1|TXCON_LOOPBACK_D2); 1444 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_TXCON, txcon); 1445 1446 /* On some cards we need manualy set fullduplex led */ 1447 if (sc->sc_hwflags & EPIC_DUPLEXLED_ON_694) { 1448 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1449 if (IFM_OPTIONS(sc->sc_mii.mii_media_active) & IFM_FDX) 1450 miicfg |= MIICFG_ENABLE; 1451 else 1452 miicfg &= ~MIICFG_ENABLE; 1453 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1454 } 1455 1456 /* 1457 * There is a multicast filter bug in 10Mbps mode. Kick the 1458 * multicast filter in case the speed changed. 1459 */ 1460 epic_set_mchash(sc); 1461 } 1462 1463 /* 1464 * Callback from ifmedia to request current media status. 1465 */ 1466 void 1467 epic_mediastatus(ifp, ifmr) 1468 struct ifnet *ifp; 1469 struct ifmediareq *ifmr; 1470 { 1471 struct epic_softc *sc = ifp->if_softc; 1472 1473 mii_pollstat(&sc->sc_mii); 1474 ifmr->ifm_status = sc->sc_mii.mii_media_status; 1475 ifmr->ifm_active = sc->sc_mii.mii_media_active; 1476 } 1477 1478 /* 1479 * Callback from ifmedia to request new media setting. 1480 */ 1481 int 1482 epic_mediachange(ifp) 1483 struct ifnet *ifp; 1484 { 1485 struct epic_softc *sc = ifp->if_softc; 1486 struct mii_data *mii = &sc->sc_mii; 1487 struct ifmedia *ifm = &mii->mii_media; 1488 int media = ifm->ifm_cur->ifm_media; 1489 u_int32_t miicfg; 1490 struct mii_softc *miisc; 1491 int cfg; 1492 1493 if (!(ifp->if_flags & IFF_UP)) 1494 return (0); 1495 1496 if (IFM_INST(media) != sc->sc_serinst) { 1497 /* If we're not selecting serial interface, select MII mode */ 1498 #ifdef EPICMEDIADEBUG 1499 printf("%s: parallel mode\n", ifp->if_xname); 1500 #endif 1501 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1502 miicfg &= ~MIICFG_SERMODEENA; 1503 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1504 } 1505 1506 mii_mediachg(mii); 1507 1508 if (IFM_INST(media) == sc->sc_serinst) { 1509 /* select serial interface */ 1510 #ifdef EPICMEDIADEBUG 1511 printf("%s: serial mode\n", ifp->if_xname); 1512 #endif 1513 miicfg = bus_space_read_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG); 1514 miicfg |= (MIICFG_SERMODEENA | MIICFG_ENABLE); 1515 bus_space_write_4(sc->sc_st, sc->sc_sh, EPIC_MIICFG, miicfg); 1516 1517 /* There is no driver to fill this */ 1518 mii->mii_media_active = media; 1519 mii->mii_media_status = 0; 1520 1521 epic_statchg(&sc->sc_dev); 1522 return (0); 1523 } 1524 1525 /* Lookup selected PHY */ 1526 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1527 miisc = LIST_NEXT(miisc, mii_list)) { 1528 if (IFM_INST(media) == miisc->mii_inst) 1529 break; 1530 } 1531 if (!miisc) { 1532 printf("epic_mediachange: can't happen\n"); /* ??? panic */ 1533 return (0); 1534 } 1535 #ifdef EPICMEDIADEBUG 1536 printf("%s: using phy %s\n", ifp->if_xname, 1537 miisc->mii_dev.dv_xname); 1538 #endif 1539 1540 if (miisc->mii_flags & MIIF_HAVEFIBER) { 1541 /* XXX XXX assume it's a Level1 - should check */ 1542 1543 /* We have to powerup fiber transceivers */ 1544 cfg = PHY_READ(miisc, MII_LXTPHY_CONFIG); 1545 if (IFM_SUBTYPE(media) == IFM_100_FX) { 1546 #ifdef EPICMEDIADEBUG 1547 printf("%s: power up fiber\n", ifp->if_xname); 1548 #endif 1549 cfg |= (CONFIG_LEDC1 | CONFIG_LEDC0); 1550 } else { 1551 #ifdef EPICMEDIADEBUG 1552 printf("%s: power down fiber\n", ifp->if_xname); 1553 #endif 1554 cfg &= ~(CONFIG_LEDC1 | CONFIG_LEDC0); 1555 } 1556 PHY_WRITE(miisc, MII_LXTPHY_CONFIG, cfg); 1557 } 1558 1559 return (0); 1560 } 1561