1 /* $NetBSD: siopvar.h,v 1.15 2001/03/15 17:38:59 bouyer Exp $ */ 2 3 /* 4 * Copyright (c) 2000 Manuel Bouyer. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Manuel Bouyer 17 * 4. The name of the author may not be used to endorse or promote products 18 * derived from this software without specific prior written permission. 19 * 20 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 21 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 22 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 23 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 24 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 25 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 26 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 27 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 28 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 29 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 30 * 31 */ 32 33 /* structure and definitions for the siop driver */ 34 35 TAILQ_HEAD(cmd_list, siop_cmd); 36 TAILQ_HEAD(cbd_list, siop_cbd); 37 TAILQ_HEAD(lunsw_list, siop_lunsw); 38 39 /* Driver internal state */ 40 struct siop_softc { 41 struct device sc_dev; 42 struct scsipi_link sc_link; /* link to upper level */ 43 int features; /* chip's features */ 44 int ram_size; 45 int maxburst; 46 int maxoff; 47 int clock_div; /* async. clock divider (scntl3) */ 48 int clock_period; /* clock period (ns * 10) */ 49 int minsync; /* min and max sync period, */ 50 int maxsync; /* as sent in SDTR message */ 51 bus_space_tag_t sc_rt; /* bus_space registers tag */ 52 bus_space_handle_t sc_rh; /* bus_space registers handle */ 53 bus_addr_t sc_raddr; /* register adresses */ 54 bus_space_tag_t sc_ramt; /* bus_space ram tag */ 55 bus_space_handle_t sc_ramh; /* bus_space ram handle */ 56 bus_dma_tag_t sc_dmat; /* bus DMA tag */ 57 void (*sc_reset) __P((struct siop_softc*)); /* reset callback */ 58 bus_dmamap_t sc_scriptdma; /* DMA map for script */ 59 bus_addr_t sc_scriptaddr; /* on-board ram or physical adress */ 60 u_int32_t *sc_script; /* script location in memory */ 61 int sc_currschedslot; /* current scheduler slot */ 62 struct cbd_list cmds; /* list of command block descriptors */ 63 struct cmd_list free_list; /* cmd descr free list */ 64 struct cmd_list urgent_list; /* hitgh priority cmd descr list */ 65 struct cmd_list ready_list; /* cmd descr ready list */ 66 struct lunsw_list lunsw_list; /* lunsw free list */ 67 u_int32_t script_free_lo; /* free ram offset from sc_scriptaddr */ 68 u_int32_t script_free_hi; /* free ram offset from sc_scriptaddr */ 69 struct siop_target *targets[16]; /* per-target states */ 70 int sc_ntargets; /* number of known targets */ 71 u_int32_t sc_flags; 72 }; 73 /* defs for sc_flags */ 74 /* none for now */ 75 76 /* features */ 77 #define SF_BUS_WIDE 0x00000001 /* wide bus */ 78 #define SF_BUS_ULTRA 0x00000002 /* Ultra (20Mhz) bus */ 79 #define SF_BUS_ULTRA2 0x00000004 /* Ultra2 (40Mhz) bus */ 80 #define SF_BUS_DIFF 0x00000008 /* differential bus */ 81 82 #define SF_CHIP_LED0 0x00000100 /* led on GPIO0 */ 83 #define SF_CHIP_DBLR 0x00000200 /* clock doubler or quadrupler */ 84 #define SF_CHIP_QUAD 0x00000400 /* clock quadrupler, with PPL */ 85 #define SF_CHIP_FIFO 0x00000800 /* large fifo */ 86 #define SF_CHIP_PF 0x00001000 /* Intructions prefetch */ 87 #define SF_CHIP_RAM 0x00002000 /* on-board RAM */ 88 #define SF_CHIP_LS 0x00004000 /* load/store instruction */ 89 #define SF_CHIP_10REGS 0x00008000 /* 10 scratch registers */ 90 #define SF_CHIP_DFBC 0x00010000 /* Use DFBC register */ 91 92 #define SF_PCI_RL 0x01000000 /* PCI read line */ 93 #define SF_PCI_RM 0x02000000 /* PCI read multiple */ 94 #define SF_PCI_BOF 0x04000000 /* PCI burst opcode fetch */ 95 #define SF_PCI_CLS 0x08000000 /* PCI cache line size */ 96 #define SF_PCI_WRI 0x10000000 /* PCI write and invalidate */ 97 98 void siop_attach __P((struct siop_softc *)); 99 int siop_intr __P((void *)); 100