1*654326faSjdolecek /* $NetBSD: siisatavar.h,v 1.9 2018/10/24 19:38:00 jdolecek Exp $ */ 23f1ee498Sjnemeth 33f1ee498Sjnemeth /* from ahcisatavar.h */ 43f1ee498Sjnemeth 53f1ee498Sjnemeth /* 63f1ee498Sjnemeth * Copyright (c) 2006 Manuel Bouyer. 73f1ee498Sjnemeth * 83f1ee498Sjnemeth * Redistribution and use in source and binary forms, with or without 93f1ee498Sjnemeth * modification, are permitted provided that the following conditions 103f1ee498Sjnemeth * are met: 113f1ee498Sjnemeth * 1. Redistributions of source code must retain the above copyright 123f1ee498Sjnemeth * notice, this list of conditions and the following disclaimer. 133f1ee498Sjnemeth * 2. Redistributions in binary form must reproduce the above copyright 143f1ee498Sjnemeth * notice, this list of conditions and the following disclaimer in the 153f1ee498Sjnemeth * documentation and/or other materials provided with the distribution. 163f1ee498Sjnemeth * 173f1ee498Sjnemeth * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 183f1ee498Sjnemeth * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 193f1ee498Sjnemeth * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 203f1ee498Sjnemeth * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 213f1ee498Sjnemeth * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 223f1ee498Sjnemeth * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 233f1ee498Sjnemeth * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 243f1ee498Sjnemeth * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 253f1ee498Sjnemeth * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 263f1ee498Sjnemeth * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 273f1ee498Sjnemeth * 283f1ee498Sjnemeth */ 293f1ee498Sjnemeth 303f1ee498Sjnemeth /*- 31464a6f95Sjakllsch * Copyright (c) 2007, 2008, 2009 Jonathan A. Kollasch. 323f1ee498Sjnemeth * All rights reserved. 333f1ee498Sjnemeth * 343f1ee498Sjnemeth * Redistribution and use in source and binary forms, with or without 353f1ee498Sjnemeth * modification, are permitted provided that the following conditions 363f1ee498Sjnemeth * are met: 373f1ee498Sjnemeth * 1. Redistributions of source code must retain the above copyright 383f1ee498Sjnemeth * notice, this list of conditions and the following disclaimer. 393f1ee498Sjnemeth * 2. Redistributions in binary form must reproduce the above copyright 403f1ee498Sjnemeth * notice, this list of conditions and the following disclaimer in the 413f1ee498Sjnemeth * documentation and/or other materials provided with the distribution. 423f1ee498Sjnemeth * 433f1ee498Sjnemeth * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 443f1ee498Sjnemeth * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 453f1ee498Sjnemeth * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 463f1ee498Sjnemeth * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 473f1ee498Sjnemeth * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 483f1ee498Sjnemeth * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 493f1ee498Sjnemeth * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 503f1ee498Sjnemeth * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 513f1ee498Sjnemeth * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 523f1ee498Sjnemeth * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 533f1ee498Sjnemeth * 543f1ee498Sjnemeth */ 553f1ee498Sjnemeth 563f1ee498Sjnemeth #ifndef _IC_SIISATAVAR_H_ 573f1ee498Sjnemeth #define _IC_SIISATAVAR_H_ 583f1ee498Sjnemeth 593f1ee498Sjnemeth #include <dev/ic/siisatareg.h> 603f1ee498Sjnemeth #include <dev/ata/atavar.h> 613f1ee498Sjnemeth 623f1ee498Sjnemeth #define DEBUG_INTR 0x01 633f1ee498Sjnemeth #define DEBUG_XFERS 0x02 643f1ee498Sjnemeth #define DEBUG_FUNCS 0x08 653f1ee498Sjnemeth #define DEBUG_PROBE 0x10 663f1ee498Sjnemeth #define DEBUG_DETACH 0x20 673f1ee498Sjnemeth #define DEBUG_DEBUG 0x80000000 683f1ee498Sjnemeth #ifdef SIISATA_DEBUG 693f1ee498Sjnemeth extern int siisata_debug_mask; 703f1ee498Sjnemeth #define SIISATA_DEBUG_PRINT(args, level) \ 713f1ee498Sjnemeth if (siisata_debug_mask & (level)) \ 723f1ee498Sjnemeth printf args 733f1ee498Sjnemeth #else 743f1ee498Sjnemeth #define SIISATA_DEBUG_PRINT(args, level) 753f1ee498Sjnemeth #endif 763f1ee498Sjnemeth 773f1ee498Sjnemeth struct siisata_softc { 783f1ee498Sjnemeth struct atac_softc sc_atac; 793f1ee498Sjnemeth bus_space_tag_t sc_grt; 803f1ee498Sjnemeth bus_space_handle_t sc_grh; 81f38e8286Sjakllsch bus_size_t sc_grs; 823f1ee498Sjnemeth bus_space_tag_t sc_prt; 833f1ee498Sjnemeth bus_space_handle_t sc_prh; 84f38e8286Sjakllsch bus_size_t sc_prs; 853f1ee498Sjnemeth bus_dma_tag_t sc_dmat; 863f1ee498Sjnemeth 873f1ee498Sjnemeth struct ata_channel *sc_chanarray[SIISATA_MAX_PORTS]; 883f1ee498Sjnemeth struct siisata_channel { 893f1ee498Sjnemeth struct ata_channel ata_channel; 903f1ee498Sjnemeth bus_space_handle_t sch_scontrol; 913f1ee498Sjnemeth bus_space_handle_t sch_sstatus; 923f1ee498Sjnemeth bus_space_handle_t sch_serror; 933f1ee498Sjnemeth 94a08c2fefSjakllsch bus_dma_segment_t sch_prb_seg; 95a08c2fefSjakllsch int sch_prb_nseg; 963f1ee498Sjnemeth bus_dmamap_t sch_prbd; 97a08c2fefSjakllsch /* command activation PRBs */ 983f1ee498Sjnemeth struct siisata_prb *sch_prb[SIISATA_MAX_SLOTS]; 993f1ee498Sjnemeth bus_addr_t sch_bus_prb[SIISATA_MAX_SLOTS]; 1003f1ee498Sjnemeth 1013f1ee498Sjnemeth bus_dmamap_t sch_datad[SIISATA_MAX_SLOTS]; 1023f1ee498Sjnemeth } sc_channels[SIISATA_MAX_PORTS]; 1033f1ee498Sjnemeth }; 1043f1ee498Sjnemeth 1053f1ee498Sjnemeth #define SIISATANAME(sc) (device_xname((sc)->sc_atac.atac_dev)) 1063f1ee498Sjnemeth 1073f1ee498Sjnemeth #define GRREAD(sc, reg) bus_space_read_4((sc)->sc_grt, (sc)->sc_grh, (reg)) 1083f1ee498Sjnemeth #define GRWRITE(sc, reg, val) bus_space_write_4((sc)->sc_grt, (sc)->sc_grh, (reg), (val)) 1093f1ee498Sjnemeth #define PRREAD(sc, reg) bus_space_read_4((sc)->sc_prt, (sc)->sc_prh, (reg)) 1103f1ee498Sjnemeth #define PRWRITE(sc, reg, val) bus_space_write_4((sc)->sc_prt, (sc)->sc_prh, (reg), (val)) 1113f1ee498Sjnemeth 1123f1ee498Sjnemeth #define SIISATA_PRB_SYNC(sc, schp, slot, op) bus_dmamap_sync((sc)->sc_dmat, \ 1133f1ee498Sjnemeth (schp)->sch_prbd, slot * SIISATA_CMD_SIZE, SIISATA_CMD_SIZE, (op)) 1143f1ee498Sjnemeth 1153f1ee498Sjnemeth void siisata_attach(struct siisata_softc *); 116f38e8286Sjakllsch int siisata_detach(struct siisata_softc *, int); 117*654326faSjdolecek void siisata_childdetached(struct siisata_softc *, device_t); 1183f1ee498Sjnemeth void siisata_resume(struct siisata_softc *); 119f38e8286Sjakllsch int siisata_intr(void *); 1203f1ee498Sjnemeth 1213f1ee498Sjnemeth #endif /* !_IC_SIISATAVAR_H_ */ 122