1 /* $NetBSD: rtl81x9.c,v 1.49 2005/02/04 02:10:37 perry Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_rl.c,v 1.17 1999/06/19 20:17:37 wpaul Exp 35 */ 36 37 /* 38 * RealTek 8129/8139 PCI NIC driver 39 * 40 * Supports several extremely cheap PCI 10/100 adapters based on 41 * the RealTek chipset. Datasheets can be obtained from 42 * www.realtek.com.tw. 43 * 44 * Written by Bill Paul <wpaul@ctr.columbia.edu> 45 * Electrical Engineering Department 46 * Columbia University, New York City 47 */ 48 49 /* 50 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 51 * probably the worst PCI ethernet controller ever made, with the possible 52 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 53 * DMA, but it has a terrible interface that nullifies any performance 54 * gains that bus-master DMA usually offers. 55 * 56 * For transmission, the chip offers a series of four TX descriptor 57 * registers. Each transmit frame must be in a contiguous buffer, aligned 58 * on a longword (32-bit) boundary. This means we almost always have to 59 * do mbuf copies in order to transmit a frame, except in the unlikely 60 * case where a) the packet fits into a single mbuf, and b) the packet 61 * is 32-bit aligned within the mbuf's data area. The presence of only 62 * four descriptor registers means that we can never have more than four 63 * packets queued for transmission at any one time. 64 * 65 * Reception is not much better. The driver has to allocate a single large 66 * buffer area (up to 64K in size) into which the chip will DMA received 67 * frames. Because we don't know where within this region received packets 68 * will begin or end, we have no choice but to copy data from the buffer 69 * area into mbufs in order to pass the packets up to the higher protocol 70 * levels. 71 * 72 * It's impossible given this rotten design to really achieve decent 73 * performance at 100Mbps, unless you happen to have a 400MHz PII or 74 * some equally overmuscled CPU to drive it. 75 * 76 * On the bright side, the 8139 does have a built-in PHY, although 77 * rather than using an MDIO serial interface like most other NICs, the 78 * PHY registers are directly accessible through the 8139's register 79 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 80 * filter. 81 * 82 * The 8129 chip is an older version of the 8139 that uses an external PHY 83 * chip. The 8129 has a serial MDIO interface for accessing the MII where 84 * the 8139 lets you directly access the on-board PHY registers. We need 85 * to select which interface to use depending on the chip type. 86 */ 87 88 #include <sys/cdefs.h> 89 __KERNEL_RCSID(0, "$NetBSD: rtl81x9.c,v 1.49 2005/02/04 02:10:37 perry Exp $"); 90 91 #include "bpfilter.h" 92 #include "rnd.h" 93 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/callout.h> 97 #include <sys/device.h> 98 #include <sys/sockio.h> 99 #include <sys/mbuf.h> 100 #include <sys/malloc.h> 101 #include <sys/kernel.h> 102 #include <sys/socket.h> 103 104 #include <uvm/uvm_extern.h> 105 106 #include <net/if.h> 107 #include <net/if_arp.h> 108 #include <net/if_ether.h> 109 #include <net/if_dl.h> 110 #include <net/if_media.h> 111 112 #if NBPFILTER > 0 113 #include <net/bpf.h> 114 #endif 115 #if NRND > 0 116 #include <sys/rnd.h> 117 #endif 118 119 #include <machine/bus.h> 120 #include <machine/endian.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 125 #include <dev/ic/rtl81x9reg.h> 126 #include <dev/ic/rtl81x9var.h> 127 128 #if defined(DEBUG) 129 #define STATIC 130 #else 131 #define STATIC static 132 #endif 133 134 STATIC void rtk_reset (struct rtk_softc *); 135 STATIC void rtk_rxeof (struct rtk_softc *); 136 STATIC void rtk_txeof (struct rtk_softc *); 137 STATIC void rtk_start (struct ifnet *); 138 STATIC int rtk_ioctl (struct ifnet *, u_long, caddr_t); 139 STATIC int rtk_init (struct ifnet *); 140 STATIC void rtk_stop (struct ifnet *, int); 141 142 STATIC void rtk_watchdog(struct ifnet *); 143 STATIC void rtk_shutdown(void *); 144 STATIC int rtk_ifmedia_upd(struct ifnet *); 145 STATIC void rtk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 146 147 STATIC void rtk_eeprom_putbyte(struct rtk_softc *, int, int); 148 STATIC void rtk_mii_sync(struct rtk_softc *); 149 STATIC void rtk_mii_send(struct rtk_softc *, u_int32_t, int); 150 STATIC int rtk_mii_readreg(struct rtk_softc *, struct rtk_mii_frame *); 151 STATIC int rtk_mii_writereg(struct rtk_softc *, struct rtk_mii_frame *); 152 153 STATIC int rtk_phy_readreg(struct device *, int, int); 154 STATIC void rtk_phy_writereg(struct device *, int, int, int); 155 STATIC void rtk_phy_statchg(struct device *); 156 STATIC void rtk_tick (void *); 157 158 STATIC int rtk_enable (struct rtk_softc *); 159 STATIC void rtk_disable (struct rtk_softc *); 160 STATIC void rtk_power (int, void *); 161 162 STATIC int rtk_list_tx_init(struct rtk_softc *); 163 164 #define EE_SET(x) \ 165 CSR_WRITE_1(sc, RTK_EECMD, \ 166 CSR_READ_1(sc, RTK_EECMD) | (x)) 167 168 #define EE_CLR(x) \ 169 CSR_WRITE_1(sc, RTK_EECMD, \ 170 CSR_READ_1(sc, RTK_EECMD) & ~(x)) 171 172 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 173 174 /* 175 * Send a read command and address to the EEPROM, check for ACK. 176 */ 177 STATIC void rtk_eeprom_putbyte(sc, addr, addr_len) 178 struct rtk_softc *sc; 179 int addr, addr_len; 180 { 181 int d, i; 182 183 d = (RTK_EECMD_READ << addr_len) | addr; 184 185 /* 186 * Feed in each bit and stobe the clock. 187 */ 188 for (i = RTK_EECMD_LEN + addr_len; i > 0; i--) { 189 if (d & (1 << (i - 1))) { 190 EE_SET(RTK_EE_DATAIN); 191 } else { 192 EE_CLR(RTK_EE_DATAIN); 193 } 194 DELAY(4); 195 EE_SET(RTK_EE_CLK); 196 DELAY(4); 197 EE_CLR(RTK_EE_CLK); 198 DELAY(4); 199 } 200 } 201 202 /* 203 * Read a word of data stored in the EEPROM at address 'addr.' 204 */ 205 u_int16_t rtk_read_eeprom(sc, addr, addr_len) 206 struct rtk_softc *sc; 207 int addr, addr_len; 208 { 209 u_int16_t word = 0; 210 int i; 211 212 /* Enter EEPROM access mode. */ 213 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_PROGRAM|RTK_EE_SEL); 214 215 /* 216 * Send address of word we want to read. 217 */ 218 rtk_eeprom_putbyte(sc, addr, addr_len); 219 220 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_PROGRAM|RTK_EE_SEL); 221 222 /* 223 * Start reading bits from EEPROM. 224 */ 225 for (i = 16; i > 0; i--) { 226 EE_SET(RTK_EE_CLK); 227 DELAY(4); 228 if (CSR_READ_1(sc, RTK_EECMD) & RTK_EE_DATAOUT) 229 word |= 1 << (i - 1); 230 EE_CLR(RTK_EE_CLK); 231 DELAY(4); 232 } 233 234 /* Turn off EEPROM access mode. */ 235 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 236 237 return (word); 238 } 239 240 /* 241 * MII access routines are provided for the 8129, which 242 * doesn't have a built-in PHY. For the 8139, we fake things 243 * up by diverting rtk_phy_readreg()/rtk_phy_writereg() to the 244 * direct access PHY registers. 245 */ 246 #define MII_SET(x) \ 247 CSR_WRITE_1(sc, RTK_MII, \ 248 CSR_READ_1(sc, RTK_MII) | (x)) 249 250 #define MII_CLR(x) \ 251 CSR_WRITE_1(sc, RTK_MII, \ 252 CSR_READ_1(sc, RTK_MII) & ~(x)) 253 254 /* 255 * Sync the PHYs by setting data bit and strobing the clock 32 times. 256 */ 257 STATIC void rtk_mii_sync(sc) 258 struct rtk_softc *sc; 259 { 260 int i; 261 262 MII_SET(RTK_MII_DIR|RTK_MII_DATAOUT); 263 264 for (i = 0; i < 32; i++) { 265 MII_SET(RTK_MII_CLK); 266 DELAY(1); 267 MII_CLR(RTK_MII_CLK); 268 DELAY(1); 269 } 270 } 271 272 /* 273 * Clock a series of bits through the MII. 274 */ 275 STATIC void rtk_mii_send(sc, bits, cnt) 276 struct rtk_softc *sc; 277 u_int32_t bits; 278 int cnt; 279 { 280 int i; 281 282 MII_CLR(RTK_MII_CLK); 283 284 for (i = cnt; i > 0; i--) { 285 if (bits & (1 << (i - 1))) { 286 MII_SET(RTK_MII_DATAOUT); 287 } else { 288 MII_CLR(RTK_MII_DATAOUT); 289 } 290 DELAY(1); 291 MII_CLR(RTK_MII_CLK); 292 DELAY(1); 293 MII_SET(RTK_MII_CLK); 294 } 295 } 296 297 /* 298 * Read an PHY register through the MII. 299 */ 300 STATIC int rtk_mii_readreg(sc, frame) 301 struct rtk_softc *sc; 302 struct rtk_mii_frame *frame; 303 { 304 int i, ack, s; 305 306 s = splnet(); 307 308 /* 309 * Set up frame for RX. 310 */ 311 frame->mii_stdelim = RTK_MII_STARTDELIM; 312 frame->mii_opcode = RTK_MII_READOP; 313 frame->mii_turnaround = 0; 314 frame->mii_data = 0; 315 316 CSR_WRITE_2(sc, RTK_MII, 0); 317 318 /* 319 * Turn on data xmit. 320 */ 321 MII_SET(RTK_MII_DIR); 322 323 rtk_mii_sync(sc); 324 325 /* 326 * Send command/address info. 327 */ 328 rtk_mii_send(sc, frame->mii_stdelim, 2); 329 rtk_mii_send(sc, frame->mii_opcode, 2); 330 rtk_mii_send(sc, frame->mii_phyaddr, 5); 331 rtk_mii_send(sc, frame->mii_regaddr, 5); 332 333 /* Idle bit */ 334 MII_CLR((RTK_MII_CLK|RTK_MII_DATAOUT)); 335 DELAY(1); 336 MII_SET(RTK_MII_CLK); 337 DELAY(1); 338 339 /* Turn off xmit. */ 340 MII_CLR(RTK_MII_DIR); 341 342 /* Check for ack */ 343 MII_CLR(RTK_MII_CLK); 344 DELAY(1); 345 MII_SET(RTK_MII_CLK); 346 DELAY(1); 347 ack = CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN; 348 349 /* 350 * Now try reading data bits. If the ack failed, we still 351 * need to clock through 16 cycles to keep the PHY(s) in sync. 352 */ 353 if (ack) { 354 for (i = 0; i < 16; i++) { 355 MII_CLR(RTK_MII_CLK); 356 DELAY(1); 357 MII_SET(RTK_MII_CLK); 358 DELAY(1); 359 } 360 goto fail; 361 } 362 363 for (i = 16; i > 0; i--) { 364 MII_CLR(RTK_MII_CLK); 365 DELAY(1); 366 if (!ack) { 367 if (CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN) 368 frame->mii_data |= 1 << (i - 1); 369 DELAY(1); 370 } 371 MII_SET(RTK_MII_CLK); 372 DELAY(1); 373 } 374 375 fail: 376 MII_CLR(RTK_MII_CLK); 377 DELAY(1); 378 MII_SET(RTK_MII_CLK); 379 DELAY(1); 380 381 splx(s); 382 383 if (ack) 384 return (1); 385 return (0); 386 } 387 388 /* 389 * Write to a PHY register through the MII. 390 */ 391 STATIC int rtk_mii_writereg(sc, frame) 392 struct rtk_softc *sc; 393 struct rtk_mii_frame *frame; 394 { 395 int s; 396 397 s = splnet(); 398 /* 399 * Set up frame for TX. 400 */ 401 frame->mii_stdelim = RTK_MII_STARTDELIM; 402 frame->mii_opcode = RTK_MII_WRITEOP; 403 frame->mii_turnaround = RTK_MII_TURNAROUND; 404 405 /* 406 * Turn on data output. 407 */ 408 MII_SET(RTK_MII_DIR); 409 410 rtk_mii_sync(sc); 411 412 rtk_mii_send(sc, frame->mii_stdelim, 2); 413 rtk_mii_send(sc, frame->mii_opcode, 2); 414 rtk_mii_send(sc, frame->mii_phyaddr, 5); 415 rtk_mii_send(sc, frame->mii_regaddr, 5); 416 rtk_mii_send(sc, frame->mii_turnaround, 2); 417 rtk_mii_send(sc, frame->mii_data, 16); 418 419 /* Idle bit. */ 420 MII_SET(RTK_MII_CLK); 421 DELAY(1); 422 MII_CLR(RTK_MII_CLK); 423 DELAY(1); 424 425 /* 426 * Turn off xmit. 427 */ 428 MII_CLR(RTK_MII_DIR); 429 430 splx(s); 431 432 return (0); 433 } 434 435 STATIC int rtk_phy_readreg(self, phy, reg) 436 struct device *self; 437 int phy, reg; 438 { 439 struct rtk_softc *sc = (void *)self; 440 struct rtk_mii_frame frame; 441 int rval = 0; 442 int rtk8139_reg = 0; 443 444 if (sc->rtk_type == RTK_8139) { 445 if (phy != 7) 446 return (0); 447 448 switch(reg) { 449 case MII_BMCR: 450 rtk8139_reg = RTK_BMCR; 451 break; 452 case MII_BMSR: 453 rtk8139_reg = RTK_BMSR; 454 break; 455 case MII_ANAR: 456 rtk8139_reg = RTK_ANAR; 457 break; 458 case MII_ANER: 459 rtk8139_reg = RTK_ANER; 460 break; 461 case MII_ANLPAR: 462 rtk8139_reg = RTK_LPAR; 463 break; 464 default: 465 #if 0 466 printf("%s: bad phy register\n", sc->sc_dev.dv_xname); 467 #endif 468 return (0); 469 } 470 rval = CSR_READ_2(sc, rtk8139_reg); 471 return (rval); 472 } 473 474 memset((char *)&frame, 0, sizeof(frame)); 475 476 frame.mii_phyaddr = phy; 477 frame.mii_regaddr = reg; 478 rtk_mii_readreg(sc, &frame); 479 480 return (frame.mii_data); 481 } 482 483 STATIC void rtk_phy_writereg(self, phy, reg, data) 484 struct device *self; 485 int phy, reg; 486 int data; 487 { 488 struct rtk_softc *sc = (void *)self; 489 struct rtk_mii_frame frame; 490 int rtk8139_reg = 0; 491 492 if (sc->rtk_type == RTK_8139) { 493 if (phy != 7) 494 return; 495 496 switch(reg) { 497 case MII_BMCR: 498 rtk8139_reg = RTK_BMCR; 499 break; 500 case MII_BMSR: 501 rtk8139_reg = RTK_BMSR; 502 break; 503 case MII_ANAR: 504 rtk8139_reg = RTK_ANAR; 505 break; 506 case MII_ANER: 507 rtk8139_reg = RTK_ANER; 508 break; 509 case MII_ANLPAR: 510 rtk8139_reg = RTK_LPAR; 511 break; 512 default: 513 #if 0 514 printf("%s: bad phy register\n", sc->sc_dev.dv_xname); 515 #endif 516 return; 517 } 518 CSR_WRITE_2(sc, rtk8139_reg, data); 519 return; 520 } 521 522 memset((char *)&frame, 0, sizeof(frame)); 523 524 frame.mii_phyaddr = phy; 525 frame.mii_regaddr = reg; 526 frame.mii_data = data; 527 528 rtk_mii_writereg(sc, &frame); 529 } 530 531 STATIC void 532 rtk_phy_statchg(v) 533 struct device *v; 534 { 535 536 /* Nothing to do. */ 537 } 538 539 #define rtk_calchash(addr) \ 540 (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 541 542 /* 543 * Program the 64-bit multicast hash filter. 544 */ 545 void rtk_setmulti(sc) 546 struct rtk_softc *sc; 547 { 548 struct ifnet *ifp; 549 int h = 0; 550 u_int32_t hashes[2] = { 0, 0 }; 551 u_int32_t rxfilt; 552 int mcnt = 0; 553 struct ether_multi *enm; 554 struct ether_multistep step; 555 556 ifp = &sc->ethercom.ec_if; 557 558 rxfilt = CSR_READ_4(sc, RTK_RXCFG); 559 560 if (ifp->if_flags & IFF_PROMISC) { 561 allmulti: 562 ifp->if_flags |= IFF_ALLMULTI; 563 rxfilt |= RTK_RXCFG_RX_MULTI; 564 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt); 565 CSR_WRITE_4(sc, RTK_MAR0, 0xFFFFFFFF); 566 CSR_WRITE_4(sc, RTK_MAR4, 0xFFFFFFFF); 567 return; 568 } 569 570 /* first, zot all the existing hash bits */ 571 CSR_WRITE_4(sc, RTK_MAR0, 0); 572 CSR_WRITE_4(sc, RTK_MAR4, 0); 573 574 /* now program new ones */ 575 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 576 while (enm != NULL) { 577 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 578 ETHER_ADDR_LEN) != 0) 579 goto allmulti; 580 581 h = rtk_calchash(enm->enm_addrlo); 582 if (h < 32) 583 hashes[0] |= (1 << h); 584 else 585 hashes[1] |= (1 << (h - 32)); 586 mcnt++; 587 ETHER_NEXT_MULTI(step, enm); 588 } 589 590 ifp->if_flags &= ~IFF_ALLMULTI; 591 592 if (mcnt) 593 rxfilt |= RTK_RXCFG_RX_MULTI; 594 else 595 rxfilt &= ~RTK_RXCFG_RX_MULTI; 596 597 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt); 598 CSR_WRITE_4(sc, RTK_MAR0, hashes[0]); 599 CSR_WRITE_4(sc, RTK_MAR4, hashes[1]); 600 } 601 602 void rtk_reset(sc) 603 struct rtk_softc *sc; 604 { 605 int i; 606 607 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 608 609 for (i = 0; i < RTK_TIMEOUT; i++) { 610 DELAY(10); 611 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0) 612 break; 613 } 614 if (i == RTK_TIMEOUT) 615 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname); 616 } 617 618 /* 619 * Attach the interface. Allocate softc structures, do ifmedia 620 * setup and ethernet/BPF attach. 621 */ 622 void 623 rtk_attach(sc) 624 struct rtk_softc *sc; 625 { 626 struct ifnet *ifp; 627 struct rtk_tx_desc *txd; 628 u_int16_t val; 629 u_int8_t eaddr[ETHER_ADDR_LEN]; 630 int error; 631 int i, addr_len; 632 633 callout_init(&sc->rtk_tick_ch); 634 635 /* 636 * Check EEPROM type 9346 or 9356. 637 */ 638 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 639 addr_len = RTK_EEADDR_LEN1; 640 else 641 addr_len = RTK_EEADDR_LEN0; 642 643 /* 644 * Get station address. 645 */ 646 val = rtk_read_eeprom(sc, RTK_EE_EADDR0, addr_len); 647 eaddr[0] = val & 0xff; 648 eaddr[1] = val >> 8; 649 val = rtk_read_eeprom(sc, RTK_EE_EADDR1, addr_len); 650 eaddr[2] = val & 0xff; 651 eaddr[3] = val >> 8; 652 val = rtk_read_eeprom(sc, RTK_EE_EADDR2, addr_len); 653 eaddr[4] = val & 0xff; 654 eaddr[5] = val >> 8; 655 656 if ((error = bus_dmamem_alloc(sc->sc_dmat, 657 RTK_RXBUFLEN + 16, PAGE_SIZE, 0, &sc->sc_dmaseg, 1, &sc->sc_dmanseg, 658 BUS_DMA_NOWAIT)) != 0) { 659 printf("%s: can't allocate recv buffer, error = %d\n", 660 sc->sc_dev.dv_xname, error); 661 goto fail_0; 662 } 663 664 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg, 665 RTK_RXBUFLEN + 16, (caddr_t *)&sc->rtk_rx_buf, 666 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 667 printf("%s: can't map recv buffer, error = %d\n", 668 sc->sc_dev.dv_xname, error); 669 goto fail_1; 670 } 671 672 if ((error = bus_dmamap_create(sc->sc_dmat, 673 RTK_RXBUFLEN + 16, 1, RTK_RXBUFLEN + 16, 0, BUS_DMA_NOWAIT, 674 &sc->recv_dmamap)) != 0) { 675 printf("%s: can't create recv buffer DMA map, error = %d\n", 676 sc->sc_dev.dv_xname, error); 677 goto fail_2; 678 } 679 680 if ((error = bus_dmamap_load(sc->sc_dmat, sc->recv_dmamap, 681 sc->rtk_rx_buf, RTK_RXBUFLEN + 16, 682 NULL, BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 683 printf("%s: can't load recv buffer DMA map, error = %d\n", 684 sc->sc_dev.dv_xname, error); 685 goto fail_3; 686 } 687 688 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 689 txd = &sc->rtk_tx_descs[i]; 690 if ((error = bus_dmamap_create(sc->sc_dmat, 691 MCLBYTES, 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 692 &txd->txd_dmamap)) != 0) { 693 printf("%s: can't create snd buffer DMA map," 694 " error = %d\n", sc->sc_dev.dv_xname, error); 695 goto fail_4; 696 } 697 txd->txd_txaddr = RTK_TXADDR0 + (i * 4); 698 txd->txd_txstat = RTK_TXSTAT0 + (i * 4); 699 } 700 SIMPLEQ_INIT(&sc->rtk_tx_free); 701 SIMPLEQ_INIT(&sc->rtk_tx_dirty); 702 703 /* 704 * From this point forward, the attachment cannot fail. A failure 705 * before this releases all resources thar may have been 706 * allocated. 707 */ 708 sc->sc_flags |= RTK_ATTACHED; 709 710 /* Init Early TX threshold. */ 711 sc->sc_txthresh = TXTH_256; 712 713 /* Reset the adapter. */ 714 rtk_reset(sc); 715 716 printf("%s: Ethernet address %s\n", 717 sc->sc_dev.dv_xname, ether_sprintf(eaddr)); 718 719 ifp = &sc->ethercom.ec_if; 720 ifp->if_softc = sc; 721 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 722 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 723 ifp->if_ioctl = rtk_ioctl; 724 ifp->if_start = rtk_start; 725 ifp->if_watchdog = rtk_watchdog; 726 ifp->if_init = rtk_init; 727 ifp->if_stop = rtk_stop; 728 IFQ_SET_READY(&ifp->if_snd); 729 730 /* 731 * Do ifmedia setup. 732 */ 733 sc->mii.mii_ifp = ifp; 734 sc->mii.mii_readreg = rtk_phy_readreg; 735 sc->mii.mii_writereg = rtk_phy_writereg; 736 sc->mii.mii_statchg = rtk_phy_statchg; 737 ifmedia_init(&sc->mii.mii_media, IFM_IMASK, rtk_ifmedia_upd, rtk_ifmedia_sts); 738 mii_attach(&sc->sc_dev, &sc->mii, 0xffffffff, 739 MII_PHY_ANY, MII_OFFSET_ANY, 0); 740 741 /* Choose a default media. */ 742 if (LIST_FIRST(&sc->mii.mii_phys) == NULL) { 743 ifmedia_add(&sc->mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 744 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_NONE); 745 } else { 746 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_AUTO); 747 } 748 749 /* 750 * Call MI attach routines. 751 */ 752 if_attach(ifp); 753 ether_ifattach(ifp, eaddr); 754 755 /* 756 * Make sure the interface is shutdown during reboot. 757 */ 758 sc->sc_sdhook = shutdownhook_establish(rtk_shutdown, sc); 759 if (sc->sc_sdhook == NULL) 760 printf("%s: WARNING: unable to establish shutdown hook\n", 761 sc->sc_dev.dv_xname); 762 /* 763 * Add a suspend hook to make sure we come back up after a 764 * resume. 765 */ 766 sc->sc_powerhook = powerhook_establish(rtk_power, sc); 767 if (sc->sc_powerhook == NULL) 768 printf("%s: WARNING: unable to establish power hook\n", 769 sc->sc_dev.dv_xname); 770 771 772 #if NRND > 0 773 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 774 RND_TYPE_NET, 0); 775 #endif 776 777 return; 778 fail_4: 779 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 780 txd = &sc->rtk_tx_descs[i]; 781 if (txd->txd_dmamap != NULL) 782 bus_dmamap_destroy(sc->sc_dmat, txd->txd_dmamap); 783 } 784 fail_3: 785 bus_dmamap_destroy(sc->sc_dmat, sc->recv_dmamap); 786 fail_2: 787 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rtk_rx_buf, 788 RTK_RXBUFLEN + 16); 789 fail_1: 790 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg); 791 fail_0: 792 return; 793 } 794 795 /* 796 * Initialize the transmit descriptors. 797 */ 798 STATIC int rtk_list_tx_init(sc) 799 struct rtk_softc *sc; 800 { 801 struct rtk_tx_desc *txd; 802 int i; 803 804 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) 805 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q); 806 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_free)) != NULL) 807 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_free, txd_q); 808 809 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 810 txd = &sc->rtk_tx_descs[i]; 811 CSR_WRITE_4(sc, txd->txd_txaddr, 0); 812 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_free, txd, txd_q); 813 } 814 815 return (0); 816 } 817 818 /* 819 * rtk_activate: 820 * Handle device activation/deactivation requests. 821 */ 822 int 823 rtk_activate(self, act) 824 struct device *self; 825 enum devact act; 826 { 827 struct rtk_softc *sc = (void *) self; 828 int s, error = 0; 829 830 s = splnet(); 831 switch (act) { 832 case DVACT_ACTIVATE: 833 error = EOPNOTSUPP; 834 break; 835 case DVACT_DEACTIVATE: 836 mii_activate(&sc->mii, act, MII_PHY_ANY, MII_OFFSET_ANY); 837 if_deactivate(&sc->ethercom.ec_if); 838 break; 839 } 840 splx(s); 841 842 return (error); 843 } 844 845 /* 846 * rtk_detach: 847 * Detach a rtk interface. 848 */ 849 int 850 rtk_detach(sc) 851 struct rtk_softc *sc; 852 { 853 struct ifnet *ifp = &sc->ethercom.ec_if; 854 struct rtk_tx_desc *txd; 855 int i; 856 857 /* 858 * Succeed now if there isn't any work to do. 859 */ 860 if ((sc->sc_flags & RTK_ATTACHED) == 0) 861 return (0); 862 863 /* Unhook our tick handler. */ 864 callout_stop(&sc->rtk_tick_ch); 865 866 /* Detach all PHYs. */ 867 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 868 869 /* Delete all remaining media. */ 870 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY); 871 872 #if NRND > 0 873 rnd_detach_source(&sc->rnd_source); 874 #endif 875 876 ether_ifdetach(ifp); 877 if_detach(ifp); 878 879 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 880 txd = &sc->rtk_tx_descs[i]; 881 if (txd->txd_dmamap != NULL) 882 bus_dmamap_destroy(sc->sc_dmat, txd->txd_dmamap); 883 } 884 bus_dmamap_destroy(sc->sc_dmat, sc->recv_dmamap); 885 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rtk_rx_buf, 886 RTK_RXBUFLEN + 16); 887 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg); 888 889 shutdownhook_disestablish(sc->sc_sdhook); 890 powerhook_disestablish(sc->sc_powerhook); 891 892 return (0); 893 } 894 895 /* 896 * rtk_enable: 897 * Enable the RTL81X9 chip. 898 */ 899 int 900 rtk_enable(sc) 901 struct rtk_softc *sc; 902 { 903 904 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 905 if ((*sc->sc_enable)(sc) != 0) { 906 printf("%s: device enable failed\n", 907 sc->sc_dev.dv_xname); 908 return (EIO); 909 } 910 sc->sc_flags |= RTK_ENABLED; 911 } 912 return (0); 913 } 914 915 /* 916 * rtk_disable: 917 * Disable the RTL81X9 chip. 918 */ 919 void 920 rtk_disable(sc) 921 struct rtk_softc *sc; 922 { 923 924 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 925 (*sc->sc_disable)(sc); 926 sc->sc_flags &= ~RTK_ENABLED; 927 } 928 } 929 930 /* 931 * rtk_power: 932 * Power management (suspend/resume) hook. 933 */ 934 void 935 rtk_power(why, arg) 936 int why; 937 void *arg; 938 { 939 struct rtk_softc *sc = (void *) arg; 940 struct ifnet *ifp = &sc->ethercom.ec_if; 941 int s; 942 943 s = splnet(); 944 switch (why) { 945 case PWR_SUSPEND: 946 case PWR_STANDBY: 947 rtk_stop(ifp, 0); 948 if (sc->sc_power != NULL) 949 (*sc->sc_power)(sc, why); 950 break; 951 case PWR_RESUME: 952 if (ifp->if_flags & IFF_UP) { 953 if (sc->sc_power != NULL) 954 (*sc->sc_power)(sc, why); 955 rtk_init(ifp); 956 } 957 break; 958 case PWR_SOFTSUSPEND: 959 case PWR_SOFTSTANDBY: 960 case PWR_SOFTRESUME: 961 break; 962 } 963 splx(s); 964 } 965 966 /* 967 * A frame has been uploaded: pass the resulting mbuf chain up to 968 * the higher level protocols. 969 * 970 * You know there's something wrong with a PCI bus-master chip design. 971 * 972 * The receive operation is badly documented in the datasheet, so I'll 973 * attempt to document it here. The driver provides a buffer area and 974 * places its base address in the RX buffer start address register. 975 * The chip then begins copying frames into the RX buffer. Each frame 976 * is preceded by a 32-bit RX status word which specifies the length 977 * of the frame and certain other status bits. Each frame (starting with 978 * the status word) is also 32-bit aligned. The frame length is in the 979 * first 16 bits of the status word; the lower 15 bits correspond with 980 * the 'rx status register' mentioned in the datasheet. 981 * 982 * Note: to make the Alpha happy, the frame payload needs to be aligned 983 * on a 32-bit boundary. To achieve this, we copy the data to mbuf 984 * shifted forward 2 bytes. 985 */ 986 STATIC void rtk_rxeof(sc) 987 struct rtk_softc *sc; 988 { 989 struct mbuf *m; 990 struct ifnet *ifp; 991 caddr_t rxbufpos, dst; 992 u_int total_len, wrap = 0; 993 u_int32_t rxstat; 994 u_int16_t cur_rx, new_rx; 995 u_int16_t limit; 996 u_int16_t rx_bytes = 0, max_bytes; 997 998 ifp = &sc->ethercom.ec_if; 999 1000 cur_rx = (CSR_READ_2(sc, RTK_CURRXADDR) + 16) % RTK_RXBUFLEN; 1001 1002 /* Do not try to read past this point. */ 1003 limit = CSR_READ_2(sc, RTK_CURRXBUF) % RTK_RXBUFLEN; 1004 1005 if (limit < cur_rx) 1006 max_bytes = (RTK_RXBUFLEN - cur_rx) + limit; 1007 else 1008 max_bytes = limit - cur_rx; 1009 1010 while((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_EMPTY_RXBUF) == 0) { 1011 rxbufpos = sc->rtk_rx_buf + cur_rx; 1012 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 1013 RTK_RXSTAT_LEN, BUS_DMASYNC_POSTREAD); 1014 rxstat = le32toh(*(u_int32_t *)rxbufpos); 1015 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 1016 RTK_RXSTAT_LEN, BUS_DMASYNC_PREREAD); 1017 1018 /* 1019 * Here's a totally undocumented fact for you. When the 1020 * RealTek chip is in the process of copying a packet into 1021 * RAM for you, the length will be 0xfff0. If you spot a 1022 * packet header with this value, you need to stop. The 1023 * datasheet makes absolutely no mention of this and 1024 * RealTek should be shot for this. 1025 */ 1026 total_len = rxstat >> 16; 1027 if (total_len == RTK_RXSTAT_UNFINISHED) 1028 break; 1029 1030 if ((rxstat & RTK_RXSTAT_RXOK) == 0 || 1031 total_len > ETHER_MAX_LEN) { 1032 ifp->if_ierrors++; 1033 1034 /* 1035 * submitted by:[netbsd-pcmcia:00484] 1036 * Takahiro Kambe <taca@sky.yamashina.kyoto.jp> 1037 * obtain from: 1038 * FreeBSD if_rl.c rev 1.24->1.25 1039 * 1040 */ 1041 #if 0 1042 if (rxstat & (RTK_RXSTAT_BADSYM|RTK_RXSTAT_RUNT| 1043 RTK_RXSTAT_GIANT|RTK_RXSTAT_CRCERR| 1044 RTK_RXSTAT_ALIGNERR)) { 1045 CSR_WRITE_2(sc, RTK_COMMAND, RTK_CMD_TX_ENB); 1046 CSR_WRITE_2(sc, RTK_COMMAND, 1047 RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1048 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG); 1049 CSR_WRITE_4(sc, RTK_RXADDR, 1050 sc->recv_dmamap->dm_segs[0].ds_addr); 1051 cur_rx = 0; 1052 } 1053 break; 1054 #else 1055 rtk_init(ifp); 1056 return; 1057 #endif 1058 } 1059 1060 /* No errors; receive the packet. */ 1061 rx_bytes += total_len + RTK_RXSTAT_LEN; 1062 1063 /* 1064 * Avoid trying to read more bytes than we know 1065 * the chip has prepared for us. 1066 */ 1067 if (rx_bytes > max_bytes) 1068 break; 1069 1070 /* 1071 * Skip the status word, wrapping around to the beginning 1072 * of the Rx area, if necessary. 1073 */ 1074 cur_rx = (cur_rx + RTK_RXSTAT_LEN) % RTK_RXBUFLEN; 1075 rxbufpos = sc->rtk_rx_buf + cur_rx; 1076 1077 /* 1078 * Compute the number of bytes at which the packet 1079 * will wrap to the beginning of the ring buffer. 1080 */ 1081 wrap = RTK_RXBUFLEN - cur_rx; 1082 1083 /* 1084 * Compute where the next pending packet is. 1085 */ 1086 if (total_len > wrap) 1087 new_rx = total_len - wrap; 1088 else 1089 new_rx = cur_rx + total_len; 1090 /* Round up to 32-bit boundary. */ 1091 new_rx = (new_rx + 3) & ~3; 1092 1093 /* 1094 * Now allocate an mbuf (and possibly a cluster) to hold 1095 * the packet. Note we offset the packet 2 bytes so that 1096 * data after the Ethernet header will be 4-byte aligned. 1097 */ 1098 MGETHDR(m, M_DONTWAIT, MT_DATA); 1099 if (m == NULL) { 1100 printf("%s: unable to allocate Rx mbuf\n", 1101 sc->sc_dev.dv_xname); 1102 ifp->if_ierrors++; 1103 goto next_packet; 1104 } 1105 if (total_len > (MHLEN - RTK_ETHER_ALIGN)) { 1106 MCLGET(m, M_DONTWAIT); 1107 if ((m->m_flags & M_EXT) == 0) { 1108 printf("%s: unable to allocate Rx cluster\n", 1109 sc->sc_dev.dv_xname); 1110 ifp->if_ierrors++; 1111 m_freem(m); 1112 m = NULL; 1113 goto next_packet; 1114 } 1115 } 1116 m->m_data += RTK_ETHER_ALIGN; /* for alignment */ 1117 m->m_pkthdr.rcvif = ifp; 1118 m->m_pkthdr.len = m->m_len = total_len; 1119 dst = mtod(m, caddr_t); 1120 1121 /* 1122 * If the packet wraps, copy up to the wrapping point. 1123 */ 1124 if (total_len > wrap) { 1125 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1126 cur_rx, wrap, BUS_DMASYNC_POSTREAD); 1127 memcpy(dst, rxbufpos, wrap); 1128 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1129 cur_rx, wrap, BUS_DMASYNC_PREREAD); 1130 cur_rx = 0; 1131 rxbufpos = sc->rtk_rx_buf; 1132 total_len -= wrap; 1133 dst += wrap; 1134 } 1135 1136 /* 1137 * ...and now the rest. 1138 */ 1139 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1140 cur_rx, total_len, BUS_DMASYNC_POSTREAD); 1141 memcpy(dst, rxbufpos, total_len); 1142 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1143 cur_rx, total_len, BUS_DMASYNC_PREREAD); 1144 1145 next_packet: 1146 CSR_WRITE_2(sc, RTK_CURRXADDR, new_rx - 16); 1147 cur_rx = new_rx; 1148 1149 if (m == NULL) 1150 continue; 1151 1152 /* 1153 * The RealTek chip includes the CRC with every 1154 * incoming packet. 1155 */ 1156 m->m_flags |= M_HASFCS; 1157 1158 ifp->if_ipackets++; 1159 1160 #if NBPFILTER > 0 1161 if (ifp->if_bpf) 1162 bpf_mtap(ifp->if_bpf, m); 1163 #endif 1164 /* pass it on. */ 1165 (*ifp->if_input)(ifp, m); 1166 } 1167 } 1168 1169 /* 1170 * A frame was downloaded to the chip. It's safe for us to clean up 1171 * the list buffers. 1172 */ 1173 STATIC void rtk_txeof(sc) 1174 struct rtk_softc *sc; 1175 { 1176 struct ifnet *ifp; 1177 struct rtk_tx_desc *txd; 1178 u_int32_t txstat; 1179 1180 ifp = &sc->ethercom.ec_if; 1181 1182 /* Clear the timeout timer. */ 1183 ifp->if_timer = 0; 1184 1185 /* 1186 * Go through our tx list and free mbufs for those 1187 * frames that have been uploaded. 1188 */ 1189 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) { 1190 txstat = CSR_READ_4(sc, txd->txd_txstat); 1191 if ((txstat & (RTK_TXSTAT_TX_OK| 1192 RTK_TXSTAT_TX_UNDERRUN|RTK_TXSTAT_TXABRT)) == 0) 1193 break; 1194 1195 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q); 1196 1197 bus_dmamap_sync(sc->sc_dmat, txd->txd_dmamap, 0, 1198 txd->txd_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1199 bus_dmamap_unload(sc->sc_dmat, txd->txd_dmamap); 1200 m_freem(txd->txd_mbuf); 1201 txd->txd_mbuf = NULL; 1202 1203 ifp->if_collisions += (txstat & RTK_TXSTAT_COLLCNT) >> 24; 1204 1205 if (txstat & RTK_TXSTAT_TX_OK) 1206 ifp->if_opackets++; 1207 else { 1208 ifp->if_oerrors++; 1209 1210 /* 1211 * Increase Early TX threshold if underrun occurred. 1212 * Increase step 64 bytes. 1213 */ 1214 if (txstat & RTK_TXSTAT_TX_UNDERRUN) { 1215 printf("%s: transmit underrun;", 1216 sc->sc_dev.dv_xname); 1217 if (sc->sc_txthresh < TXTH_MAX) { 1218 sc->sc_txthresh += 2; 1219 printf(" new threshold: %d bytes", 1220 sc->sc_txthresh * 32); 1221 } 1222 printf("\n"); 1223 } 1224 if (txstat & (RTK_TXSTAT_TXABRT|RTK_TXSTAT_OUTOFWIN)) 1225 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG); 1226 } 1227 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_free, txd, txd_q); 1228 ifp->if_flags &= ~IFF_OACTIVE; 1229 } 1230 } 1231 1232 int rtk_intr(arg) 1233 void *arg; 1234 { 1235 struct rtk_softc *sc; 1236 struct ifnet *ifp; 1237 u_int16_t status; 1238 int handled = 0; 1239 1240 sc = arg; 1241 ifp = &sc->ethercom.ec_if; 1242 1243 /* Disable interrupts. */ 1244 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1245 1246 for (;;) { 1247 1248 status = CSR_READ_2(sc, RTK_ISR); 1249 if (status) 1250 CSR_WRITE_2(sc, RTK_ISR, status); 1251 1252 handled = 1; 1253 1254 if ((status & RTK_INTRS) == 0) 1255 break; 1256 1257 if (status & RTK_ISR_RX_OK) 1258 rtk_rxeof(sc); 1259 1260 if (status & RTK_ISR_RX_ERR) 1261 rtk_rxeof(sc); 1262 1263 if (status & (RTK_ISR_TX_OK|RTK_ISR_TX_ERR)) 1264 rtk_txeof(sc); 1265 1266 if (status & RTK_ISR_SYSTEM_ERR) { 1267 rtk_reset(sc); 1268 rtk_init(ifp); 1269 } 1270 } 1271 1272 /* Re-enable interrupts. */ 1273 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS); 1274 1275 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 1276 rtk_start(ifp); 1277 1278 #if NRND > 0 1279 if (RND_ENABLED(&sc->rnd_source)) 1280 rnd_add_uint32(&sc->rnd_source, status); 1281 #endif 1282 1283 return (handled); 1284 } 1285 1286 /* 1287 * Main transmit routine. 1288 */ 1289 1290 STATIC void rtk_start(ifp) 1291 struct ifnet *ifp; 1292 { 1293 struct rtk_softc *sc; 1294 struct rtk_tx_desc *txd; 1295 struct mbuf *m_head = NULL, *m_new; 1296 int error, len; 1297 1298 sc = ifp->if_softc; 1299 1300 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_free)) != NULL) { 1301 IFQ_POLL(&ifp->if_snd, m_head); 1302 if (m_head == NULL) 1303 break; 1304 m_new = NULL; 1305 1306 /* 1307 * Load the DMA map. If this fails, the packet didn't 1308 * fit in one DMA segment, and we need to copy. Note, 1309 * the packet must also be aligned. 1310 * if the packet is too small, copy it too, so we're sure 1311 * so have enouth room for the pad buffer. 1312 */ 1313 if ((mtod(m_head, uintptr_t) & 3) != 0 || 1314 m_head->m_pkthdr.len < ETHER_PAD_LEN || 1315 bus_dmamap_load_mbuf(sc->sc_dmat, txd->txd_dmamap, 1316 m_head, BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1317 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1318 if (m_new == NULL) { 1319 printf("%s: unable to allocate Tx mbuf\n", 1320 sc->sc_dev.dv_xname); 1321 break; 1322 } 1323 if (m_head->m_pkthdr.len > MHLEN) { 1324 MCLGET(m_new, M_DONTWAIT); 1325 if ((m_new->m_flags & M_EXT) == 0) { 1326 printf("%s: unable to allocate Tx " 1327 "cluster\n", sc->sc_dev.dv_xname); 1328 m_freem(m_new); 1329 break; 1330 } 1331 } 1332 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1333 mtod(m_new, caddr_t)); 1334 m_new->m_pkthdr.len = m_new->m_len = 1335 m_head->m_pkthdr.len; 1336 if (m_head->m_pkthdr.len < ETHER_PAD_LEN) { 1337 memset( 1338 mtod(m_new, caddr_t) + m_head->m_pkthdr.len, 1339 0, ETHER_PAD_LEN - m_head->m_pkthdr.len); 1340 m_new->m_pkthdr.len = m_new->m_len = 1341 ETHER_PAD_LEN; 1342 } 1343 error = bus_dmamap_load_mbuf(sc->sc_dmat, 1344 txd->txd_dmamap, m_new, 1345 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1346 if (error) { 1347 printf("%s: unable to load Tx buffer, " 1348 "error = %d\n", sc->sc_dev.dv_xname, error); 1349 break; 1350 } 1351 } 1352 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1353 #if NBPFILTER > 0 1354 /* 1355 * If there's a BPF listener, bounce a copy of this frame 1356 * to him. 1357 */ 1358 if (ifp->if_bpf) 1359 bpf_mtap(ifp->if_bpf, m_head); 1360 #endif 1361 if (m_new != NULL) { 1362 m_freem(m_head); 1363 m_head = m_new; 1364 } 1365 txd->txd_mbuf = m_head; 1366 1367 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_free, txd_q); 1368 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_dirty, txd, txd_q); 1369 1370 /* 1371 * Transmit the frame. 1372 */ 1373 bus_dmamap_sync(sc->sc_dmat, 1374 txd->txd_dmamap, 0, txd->txd_dmamap->dm_mapsize, 1375 BUS_DMASYNC_PREWRITE); 1376 1377 len = txd->txd_dmamap->dm_segs[0].ds_len; 1378 1379 CSR_WRITE_4(sc, txd->txd_txaddr, 1380 txd->txd_dmamap->dm_segs[0].ds_addr); 1381 CSR_WRITE_4(sc, txd->txd_txstat, RTK_TX_THRESH(sc) | len); 1382 } 1383 1384 /* 1385 * We broke out of the loop because all our TX slots are 1386 * full. Mark the NIC as busy until it drains some of the 1387 * packets from the queue. 1388 */ 1389 if (SIMPLEQ_EMPTY(&sc->rtk_tx_free)) 1390 ifp->if_flags |= IFF_OACTIVE; 1391 1392 /* 1393 * Set a timeout in case the chip goes out to lunch. 1394 */ 1395 ifp->if_timer = 5; 1396 } 1397 1398 STATIC int rtk_init(ifp) 1399 struct ifnet *ifp; 1400 { 1401 struct rtk_softc *sc = ifp->if_softc; 1402 int error = 0, i; 1403 u_int32_t rxcfg; 1404 1405 if ((error = rtk_enable(sc)) != 0) 1406 goto out; 1407 1408 /* 1409 * Cancel pending I/O. 1410 */ 1411 rtk_stop(ifp, 0); 1412 1413 /* Init our MAC address */ 1414 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1415 CSR_WRITE_1(sc, RTK_IDR0 + i, LLADDR(ifp->if_sadl)[i]); 1416 } 1417 1418 /* Init the RX buffer pointer register. */ 1419 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 0, 1420 sc->recv_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1421 CSR_WRITE_4(sc, RTK_RXADDR, sc->recv_dmamap->dm_segs[0].ds_addr); 1422 1423 /* Init TX descriptors. */ 1424 rtk_list_tx_init(sc); 1425 1426 /* Init Early TX threshold. */ 1427 sc->sc_txthresh = TXTH_256; 1428 /* 1429 * Enable transmit and receive. 1430 */ 1431 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1432 1433 /* 1434 * Set the initial TX and RX configuration. 1435 */ 1436 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG); 1437 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG); 1438 1439 /* Set the individual bit to receive frames for this host only. */ 1440 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 1441 rxcfg |= RTK_RXCFG_RX_INDIV; 1442 1443 /* If we want promiscuous mode, set the allframes bit. */ 1444 if (ifp->if_flags & IFF_PROMISC) { 1445 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 1446 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1447 } else { 1448 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 1449 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1450 } 1451 1452 /* 1453 * Set capture broadcast bit to capture broadcast frames. 1454 */ 1455 if (ifp->if_flags & IFF_BROADCAST) { 1456 rxcfg |= RTK_RXCFG_RX_BROAD; 1457 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1458 } else { 1459 rxcfg &= ~RTK_RXCFG_RX_BROAD; 1460 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1461 } 1462 1463 /* 1464 * Program the multicast filter, if necessary. 1465 */ 1466 rtk_setmulti(sc); 1467 1468 /* 1469 * Enable interrupts. 1470 */ 1471 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS); 1472 1473 /* Start RX/TX process. */ 1474 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 1475 1476 /* Enable receiver and transmitter. */ 1477 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1478 1479 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD|RTK_CFG1_FULLDUPLEX); 1480 1481 /* 1482 * Set current media. 1483 */ 1484 mii_mediachg(&sc->mii); 1485 1486 ifp->if_flags |= IFF_RUNNING; 1487 ifp->if_flags &= ~IFF_OACTIVE; 1488 1489 callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc); 1490 1491 out: 1492 if (error) { 1493 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1494 ifp->if_timer = 0; 1495 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1496 } 1497 return (error); 1498 } 1499 1500 /* 1501 * Set media options. 1502 */ 1503 STATIC int rtk_ifmedia_upd(ifp) 1504 struct ifnet *ifp; 1505 { 1506 struct rtk_softc *sc; 1507 1508 sc = ifp->if_softc; 1509 1510 return (mii_mediachg(&sc->mii)); 1511 } 1512 1513 /* 1514 * Report current media status. 1515 */ 1516 STATIC void rtk_ifmedia_sts(ifp, ifmr) 1517 struct ifnet *ifp; 1518 struct ifmediareq *ifmr; 1519 { 1520 struct rtk_softc *sc; 1521 1522 sc = ifp->if_softc; 1523 1524 mii_pollstat(&sc->mii); 1525 ifmr->ifm_status = sc->mii.mii_media_status; 1526 ifmr->ifm_active = sc->mii.mii_media_active; 1527 } 1528 1529 STATIC int rtk_ioctl(ifp, command, data) 1530 struct ifnet *ifp; 1531 u_long command; 1532 caddr_t data; 1533 { 1534 struct rtk_softc *sc = ifp->if_softc; 1535 struct ifreq *ifr = (struct ifreq *) data; 1536 int s, error = 0; 1537 1538 s = splnet(); 1539 1540 switch (command) { 1541 case SIOCGIFMEDIA: 1542 case SIOCSIFMEDIA: 1543 error = ifmedia_ioctl(ifp, ifr, &sc->mii.mii_media, command); 1544 break; 1545 1546 default: 1547 error = ether_ioctl(ifp, command, data); 1548 if (error == ENETRESET) { 1549 if (ifp->if_flags & IFF_RUNNING) { 1550 /* 1551 * Multicast list has changed. Set the 1552 * hardware filter accordingly. 1553 */ 1554 rtk_setmulti(sc); 1555 } 1556 error = 0; 1557 } 1558 break; 1559 } 1560 1561 splx(s); 1562 1563 return (error); 1564 } 1565 1566 STATIC void rtk_watchdog(ifp) 1567 struct ifnet *ifp; 1568 { 1569 struct rtk_softc *sc; 1570 1571 sc = ifp->if_softc; 1572 1573 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1574 ifp->if_oerrors++; 1575 rtk_txeof(sc); 1576 rtk_rxeof(sc); 1577 rtk_init(ifp); 1578 } 1579 1580 /* 1581 * Stop the adapter and free any mbufs allocated to the 1582 * RX and TX lists. 1583 */ 1584 STATIC void rtk_stop(ifp, disable) 1585 struct ifnet *ifp; 1586 int disable; 1587 { 1588 struct rtk_softc *sc = ifp->if_softc; 1589 struct rtk_tx_desc *txd; 1590 1591 callout_stop(&sc->rtk_tick_ch); 1592 1593 mii_down(&sc->mii); 1594 1595 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 1596 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1597 1598 /* 1599 * Free the TX list buffers. 1600 */ 1601 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) { 1602 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q); 1603 bus_dmamap_unload(sc->sc_dmat, txd->txd_dmamap); 1604 m_freem(txd->txd_mbuf); 1605 txd->txd_mbuf = NULL; 1606 CSR_WRITE_4(sc, txd->txd_txaddr, 0); 1607 } 1608 1609 if (disable) 1610 rtk_disable(sc); 1611 1612 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1613 ifp->if_timer = 0; 1614 } 1615 1616 /* 1617 * Stop all chip I/O so that the kernel's probe routines don't 1618 * get confused by errant DMAs when rebooting. 1619 */ 1620 STATIC void rtk_shutdown(vsc) 1621 void *vsc; 1622 { 1623 struct rtk_softc *sc = (struct rtk_softc *)vsc; 1624 1625 rtk_stop(&sc->ethercom.ec_if, 0); 1626 } 1627 1628 STATIC void 1629 rtk_tick(arg) 1630 void *arg; 1631 { 1632 struct rtk_softc *sc = arg; 1633 int s = splnet(); 1634 1635 mii_tick(&sc->mii); 1636 splx(s); 1637 1638 callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc); 1639 } 1640