1 /* $NetBSD: rtl81x9.c,v 1.45 2003/02/21 17:14:07 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_rl.c,v 1.17 1999/06/19 20:17:37 wpaul Exp 35 */ 36 37 /* 38 * RealTek 8129/8139 PCI NIC driver 39 * 40 * Supports several extremely cheap PCI 10/100 adapters based on 41 * the RealTek chipset. Datasheets can be obtained from 42 * www.realtek.com.tw. 43 * 44 * Written by Bill Paul <wpaul@ctr.columbia.edu> 45 * Electrical Engineering Department 46 * Columbia University, New York City 47 */ 48 49 /* 50 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 51 * probably the worst PCI ethernet controller ever made, with the possible 52 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 53 * DMA, but it has a terrible interface that nullifies any performance 54 * gains that bus-master DMA usually offers. 55 * 56 * For transmission, the chip offers a series of four TX descriptor 57 * registers. Each transmit frame must be in a contiguous buffer, aligned 58 * on a longword (32-bit) boundary. This means we almost always have to 59 * do mbuf copies in order to transmit a frame, except in the unlikely 60 * case where a) the packet fits into a single mbuf, and b) the packet 61 * is 32-bit aligned within the mbuf's data area. The presence of only 62 * four descriptor registers means that we can never have more than four 63 * packets queued for transmission at any one time. 64 * 65 * Reception is not much better. The driver has to allocate a single large 66 * buffer area (up to 64K in size) into which the chip will DMA received 67 * frames. Because we don't know where within this region received packets 68 * will begin or end, we have no choice but to copy data from the buffer 69 * area into mbufs in order to pass the packets up to the higher protocol 70 * levels. 71 * 72 * It's impossible given this rotten design to really achieve decent 73 * performance at 100Mbps, unless you happen to have a 400MHz PII or 74 * some equally overmuscled CPU to drive it. 75 * 76 * On the bright side, the 8139 does have a built-in PHY, although 77 * rather than using an MDIO serial interface like most other NICs, the 78 * PHY registers are directly accessible through the 8139's register 79 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 80 * filter. 81 * 82 * The 8129 chip is an older version of the 8139 that uses an external PHY 83 * chip. The 8129 has a serial MDIO interface for accessing the MII where 84 * the 8139 lets you directly access the on-board PHY registers. We need 85 * to select which interface to use depending on the chip type. 86 */ 87 88 #include <sys/cdefs.h> 89 __KERNEL_RCSID(0, "$NetBSD: rtl81x9.c,v 1.45 2003/02/21 17:14:07 tsutsui Exp $"); 90 91 #include "bpfilter.h" 92 #include "rnd.h" 93 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/callout.h> 97 #include <sys/device.h> 98 #include <sys/sockio.h> 99 #include <sys/mbuf.h> 100 #include <sys/malloc.h> 101 #include <sys/kernel.h> 102 #include <sys/socket.h> 103 104 #include <uvm/uvm_extern.h> 105 106 #include <net/if.h> 107 #include <net/if_arp.h> 108 #include <net/if_ether.h> 109 #include <net/if_dl.h> 110 #include <net/if_media.h> 111 112 #if NBPFILTER > 0 113 #include <net/bpf.h> 114 #endif 115 #if NRND > 0 116 #include <sys/rnd.h> 117 #endif 118 119 #include <machine/bus.h> 120 #include <machine/endian.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 125 #include <dev/ic/rtl81x9reg.h> 126 #include <dev/ic/rtl81x9var.h> 127 128 #if defined(DEBUG) 129 #define STATIC 130 #else 131 #define STATIC static 132 #endif 133 134 STATIC void rtk_reset __P((struct rtk_softc *)); 135 STATIC void rtk_rxeof __P((struct rtk_softc *)); 136 STATIC void rtk_txeof __P((struct rtk_softc *)); 137 STATIC void rtk_start __P((struct ifnet *)); 138 STATIC int rtk_ioctl __P((struct ifnet *, u_long, caddr_t)); 139 STATIC int rtk_init __P((struct ifnet *)); 140 STATIC void rtk_stop __P((struct ifnet *, int)); 141 142 STATIC void rtk_watchdog __P((struct ifnet *)); 143 STATIC void rtk_shutdown __P((void *)); 144 STATIC int rtk_ifmedia_upd __P((struct ifnet *)); 145 STATIC void rtk_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 146 147 STATIC u_int16_t rtk_read_eeprom __P((struct rtk_softc *, int, int)); 148 STATIC void rtk_eeprom_putbyte __P((struct rtk_softc *, int, int)); 149 STATIC void rtk_mii_sync __P((struct rtk_softc *)); 150 STATIC void rtk_mii_send __P((struct rtk_softc *, u_int32_t, int)); 151 STATIC int rtk_mii_readreg __P((struct rtk_softc *, struct rtk_mii_frame *)); 152 STATIC int rtk_mii_writereg __P((struct rtk_softc *, struct rtk_mii_frame *)); 153 154 STATIC int rtk_phy_readreg __P((struct device *, int, int)); 155 STATIC void rtk_phy_writereg __P((struct device *, int, int, int)); 156 STATIC void rtk_phy_statchg __P((struct device *)); 157 STATIC void rtk_tick __P((void *)); 158 159 STATIC int rtk_enable __P((struct rtk_softc *)); 160 STATIC void rtk_disable __P((struct rtk_softc *)); 161 STATIC void rtk_power __P((int, void *)); 162 163 STATIC void rtk_setmulti __P((struct rtk_softc *)); 164 STATIC int rtk_list_tx_init __P((struct rtk_softc *)); 165 166 #define EE_SET(x) \ 167 CSR_WRITE_1(sc, RTK_EECMD, \ 168 CSR_READ_1(sc, RTK_EECMD) | (x)) 169 170 #define EE_CLR(x) \ 171 CSR_WRITE_1(sc, RTK_EECMD, \ 172 CSR_READ_1(sc, RTK_EECMD) & ~(x)) 173 174 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 175 176 /* 177 * Send a read command and address to the EEPROM, check for ACK. 178 */ 179 STATIC void rtk_eeprom_putbyte(sc, addr, addr_len) 180 struct rtk_softc *sc; 181 int addr, addr_len; 182 { 183 int d, i; 184 185 d = (RTK_EECMD_READ << addr_len) | addr; 186 187 /* 188 * Feed in each bit and stobe the clock. 189 */ 190 for (i = RTK_EECMD_LEN + addr_len; i > 0; i--) { 191 if (d & (1 << (i - 1))) { 192 EE_SET(RTK_EE_DATAIN); 193 } else { 194 EE_CLR(RTK_EE_DATAIN); 195 } 196 DELAY(4); 197 EE_SET(RTK_EE_CLK); 198 DELAY(4); 199 EE_CLR(RTK_EE_CLK); 200 DELAY(4); 201 } 202 } 203 204 /* 205 * Read a word of data stored in the EEPROM at address 'addr.' 206 */ 207 u_int16_t rtk_read_eeprom(sc, addr, addr_len) 208 struct rtk_softc *sc; 209 int addr, addr_len; 210 { 211 u_int16_t word = 0; 212 int i; 213 214 /* Enter EEPROM access mode. */ 215 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_PROGRAM|RTK_EE_SEL); 216 217 /* 218 * Send address of word we want to read. 219 */ 220 rtk_eeprom_putbyte(sc, addr, addr_len); 221 222 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_PROGRAM|RTK_EE_SEL); 223 224 /* 225 * Start reading bits from EEPROM. 226 */ 227 for (i = 16; i > 0; i--) { 228 EE_SET(RTK_EE_CLK); 229 DELAY(4); 230 if (CSR_READ_1(sc, RTK_EECMD) & RTK_EE_DATAOUT) 231 word |= 1 << (i - 1); 232 EE_CLR(RTK_EE_CLK); 233 DELAY(4); 234 } 235 236 /* Turn off EEPROM access mode. */ 237 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 238 239 return (word); 240 } 241 242 /* 243 * MII access routines are provided for the 8129, which 244 * doesn't have a built-in PHY. For the 8139, we fake things 245 * up by diverting rtk_phy_readreg()/rtk_phy_writereg() to the 246 * direct access PHY registers. 247 */ 248 #define MII_SET(x) \ 249 CSR_WRITE_1(sc, RTK_MII, \ 250 CSR_READ_1(sc, RTK_MII) | (x)) 251 252 #define MII_CLR(x) \ 253 CSR_WRITE_1(sc, RTK_MII, \ 254 CSR_READ_1(sc, RTK_MII) & ~(x)) 255 256 /* 257 * Sync the PHYs by setting data bit and strobing the clock 32 times. 258 */ 259 STATIC void rtk_mii_sync(sc) 260 struct rtk_softc *sc; 261 { 262 int i; 263 264 MII_SET(RTK_MII_DIR|RTK_MII_DATAOUT); 265 266 for (i = 0; i < 32; i++) { 267 MII_SET(RTK_MII_CLK); 268 DELAY(1); 269 MII_CLR(RTK_MII_CLK); 270 DELAY(1); 271 } 272 } 273 274 /* 275 * Clock a series of bits through the MII. 276 */ 277 STATIC void rtk_mii_send(sc, bits, cnt) 278 struct rtk_softc *sc; 279 u_int32_t bits; 280 int cnt; 281 { 282 int i; 283 284 MII_CLR(RTK_MII_CLK); 285 286 for (i = cnt; i > 0; i--) { 287 if (bits & (1 << (i - 1))) { 288 MII_SET(RTK_MII_DATAOUT); 289 } else { 290 MII_CLR(RTK_MII_DATAOUT); 291 } 292 DELAY(1); 293 MII_CLR(RTK_MII_CLK); 294 DELAY(1); 295 MII_SET(RTK_MII_CLK); 296 } 297 } 298 299 /* 300 * Read an PHY register through the MII. 301 */ 302 STATIC int rtk_mii_readreg(sc, frame) 303 struct rtk_softc *sc; 304 struct rtk_mii_frame *frame; 305 { 306 int i, ack, s; 307 308 s = splnet(); 309 310 /* 311 * Set up frame for RX. 312 */ 313 frame->mii_stdelim = RTK_MII_STARTDELIM; 314 frame->mii_opcode = RTK_MII_READOP; 315 frame->mii_turnaround = 0; 316 frame->mii_data = 0; 317 318 CSR_WRITE_2(sc, RTK_MII, 0); 319 320 /* 321 * Turn on data xmit. 322 */ 323 MII_SET(RTK_MII_DIR); 324 325 rtk_mii_sync(sc); 326 327 /* 328 * Send command/address info. 329 */ 330 rtk_mii_send(sc, frame->mii_stdelim, 2); 331 rtk_mii_send(sc, frame->mii_opcode, 2); 332 rtk_mii_send(sc, frame->mii_phyaddr, 5); 333 rtk_mii_send(sc, frame->mii_regaddr, 5); 334 335 /* Idle bit */ 336 MII_CLR((RTK_MII_CLK|RTK_MII_DATAOUT)); 337 DELAY(1); 338 MII_SET(RTK_MII_CLK); 339 DELAY(1); 340 341 /* Turn off xmit. */ 342 MII_CLR(RTK_MII_DIR); 343 344 /* Check for ack */ 345 MII_CLR(RTK_MII_CLK); 346 DELAY(1); 347 MII_SET(RTK_MII_CLK); 348 DELAY(1); 349 ack = CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN; 350 351 /* 352 * Now try reading data bits. If the ack failed, we still 353 * need to clock through 16 cycles to keep the PHY(s) in sync. 354 */ 355 if (ack) { 356 for (i = 0; i < 16; i++) { 357 MII_CLR(RTK_MII_CLK); 358 DELAY(1); 359 MII_SET(RTK_MII_CLK); 360 DELAY(1); 361 } 362 goto fail; 363 } 364 365 for (i = 16; i > 0; i--) { 366 MII_CLR(RTK_MII_CLK); 367 DELAY(1); 368 if (!ack) { 369 if (CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN) 370 frame->mii_data |= 1 << (i - 1); 371 DELAY(1); 372 } 373 MII_SET(RTK_MII_CLK); 374 DELAY(1); 375 } 376 377 fail: 378 MII_CLR(RTK_MII_CLK); 379 DELAY(1); 380 MII_SET(RTK_MII_CLK); 381 DELAY(1); 382 383 splx(s); 384 385 if (ack) 386 return (1); 387 return (0); 388 } 389 390 /* 391 * Write to a PHY register through the MII. 392 */ 393 STATIC int rtk_mii_writereg(sc, frame) 394 struct rtk_softc *sc; 395 struct rtk_mii_frame *frame; 396 { 397 int s; 398 399 s = splnet(); 400 /* 401 * Set up frame for TX. 402 */ 403 frame->mii_stdelim = RTK_MII_STARTDELIM; 404 frame->mii_opcode = RTK_MII_WRITEOP; 405 frame->mii_turnaround = RTK_MII_TURNAROUND; 406 407 /* 408 * Turn on data output. 409 */ 410 MII_SET(RTK_MII_DIR); 411 412 rtk_mii_sync(sc); 413 414 rtk_mii_send(sc, frame->mii_stdelim, 2); 415 rtk_mii_send(sc, frame->mii_opcode, 2); 416 rtk_mii_send(sc, frame->mii_phyaddr, 5); 417 rtk_mii_send(sc, frame->mii_regaddr, 5); 418 rtk_mii_send(sc, frame->mii_turnaround, 2); 419 rtk_mii_send(sc, frame->mii_data, 16); 420 421 /* Idle bit. */ 422 MII_SET(RTK_MII_CLK); 423 DELAY(1); 424 MII_CLR(RTK_MII_CLK); 425 DELAY(1); 426 427 /* 428 * Turn off xmit. 429 */ 430 MII_CLR(RTK_MII_DIR); 431 432 splx(s); 433 434 return (0); 435 } 436 437 STATIC int rtk_phy_readreg(self, phy, reg) 438 struct device *self; 439 int phy, reg; 440 { 441 struct rtk_softc *sc = (void *)self; 442 struct rtk_mii_frame frame; 443 int rval = 0; 444 int rtk8139_reg = 0; 445 446 if (sc->rtk_type == RTK_8139) { 447 if (phy != 7) 448 return (0); 449 450 switch(reg) { 451 case MII_BMCR: 452 rtk8139_reg = RTK_BMCR; 453 break; 454 case MII_BMSR: 455 rtk8139_reg = RTK_BMSR; 456 break; 457 case MII_ANAR: 458 rtk8139_reg = RTK_ANAR; 459 break; 460 case MII_ANER: 461 rtk8139_reg = RTK_ANER; 462 break; 463 case MII_ANLPAR: 464 rtk8139_reg = RTK_LPAR; 465 break; 466 default: 467 #if 0 468 printf("%s: bad phy register\n", sc->sc_dev.dv_xname); 469 #endif 470 return (0); 471 } 472 rval = CSR_READ_2(sc, rtk8139_reg); 473 return (rval); 474 } 475 476 memset((char *)&frame, 0, sizeof(frame)); 477 478 frame.mii_phyaddr = phy; 479 frame.mii_regaddr = reg; 480 rtk_mii_readreg(sc, &frame); 481 482 return (frame.mii_data); 483 } 484 485 STATIC void rtk_phy_writereg(self, phy, reg, data) 486 struct device *self; 487 int phy, reg; 488 int data; 489 { 490 struct rtk_softc *sc = (void *)self; 491 struct rtk_mii_frame frame; 492 int rtk8139_reg = 0; 493 494 if (sc->rtk_type == RTK_8139) { 495 if (phy != 7) 496 return; 497 498 switch(reg) { 499 case MII_BMCR: 500 rtk8139_reg = RTK_BMCR; 501 break; 502 case MII_BMSR: 503 rtk8139_reg = RTK_BMSR; 504 break; 505 case MII_ANAR: 506 rtk8139_reg = RTK_ANAR; 507 break; 508 case MII_ANER: 509 rtk8139_reg = RTK_ANER; 510 break; 511 case MII_ANLPAR: 512 rtk8139_reg = RTK_LPAR; 513 break; 514 default: 515 #if 0 516 printf("%s: bad phy register\n", sc->sc_dev.dv_xname); 517 #endif 518 return; 519 } 520 CSR_WRITE_2(sc, rtk8139_reg, data); 521 return; 522 } 523 524 memset((char *)&frame, 0, sizeof(frame)); 525 526 frame.mii_phyaddr = phy; 527 frame.mii_regaddr = reg; 528 frame.mii_data = data; 529 530 rtk_mii_writereg(sc, &frame); 531 } 532 533 STATIC void 534 rtk_phy_statchg(v) 535 struct device *v; 536 { 537 538 /* Nothing to do. */ 539 } 540 541 #define rtk_calchash(addr) \ 542 (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 543 544 /* 545 * Program the 64-bit multicast hash filter. 546 */ 547 STATIC void rtk_setmulti(sc) 548 struct rtk_softc *sc; 549 { 550 struct ifnet *ifp; 551 int h = 0; 552 u_int32_t hashes[2] = { 0, 0 }; 553 u_int32_t rxfilt; 554 int mcnt = 0; 555 struct ether_multi *enm; 556 struct ether_multistep step; 557 558 ifp = &sc->ethercom.ec_if; 559 560 rxfilt = CSR_READ_4(sc, RTK_RXCFG); 561 562 if (ifp->if_flags & IFF_PROMISC) { 563 allmulti: 564 ifp->if_flags |= IFF_ALLMULTI; 565 rxfilt |= RTK_RXCFG_RX_MULTI; 566 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt); 567 CSR_WRITE_4(sc, RTK_MAR0, 0xFFFFFFFF); 568 CSR_WRITE_4(sc, RTK_MAR4, 0xFFFFFFFF); 569 return; 570 } 571 572 /* first, zot all the existing hash bits */ 573 CSR_WRITE_4(sc, RTK_MAR0, 0); 574 CSR_WRITE_4(sc, RTK_MAR4, 0); 575 576 /* now program new ones */ 577 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 578 while (enm != NULL) { 579 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 580 ETHER_ADDR_LEN) != 0) 581 goto allmulti; 582 583 h = rtk_calchash(enm->enm_addrlo); 584 if (h < 32) 585 hashes[0] |= (1 << h); 586 else 587 hashes[1] |= (1 << (h - 32)); 588 mcnt++; 589 ETHER_NEXT_MULTI(step, enm); 590 } 591 592 ifp->if_flags &= ~IFF_ALLMULTI; 593 594 if (mcnt) 595 rxfilt |= RTK_RXCFG_RX_MULTI; 596 else 597 rxfilt &= ~RTK_RXCFG_RX_MULTI; 598 599 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt); 600 CSR_WRITE_4(sc, RTK_MAR0, hashes[0]); 601 CSR_WRITE_4(sc, RTK_MAR4, hashes[1]); 602 } 603 604 void rtk_reset(sc) 605 struct rtk_softc *sc; 606 { 607 int i; 608 609 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 610 611 for (i = 0; i < RTK_TIMEOUT; i++) { 612 DELAY(10); 613 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0) 614 break; 615 } 616 if (i == RTK_TIMEOUT) 617 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname); 618 } 619 620 /* 621 * Attach the interface. Allocate softc structures, do ifmedia 622 * setup and ethernet/BPF attach. 623 */ 624 void 625 rtk_attach(sc) 626 struct rtk_softc *sc; 627 { 628 struct ifnet *ifp; 629 struct rtk_tx_desc *txd; 630 u_int16_t val; 631 u_int8_t eaddr[ETHER_ADDR_LEN]; 632 int error; 633 int i, addr_len; 634 635 callout_init(&sc->rtk_tick_ch); 636 637 /* 638 * Check EEPROM type 9346 or 9356. 639 */ 640 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 641 addr_len = RTK_EEADDR_LEN1; 642 else 643 addr_len = RTK_EEADDR_LEN0; 644 645 /* 646 * Get station address. 647 */ 648 val = rtk_read_eeprom(sc, RTK_EE_EADDR0, addr_len); 649 eaddr[0] = val & 0xff; 650 eaddr[1] = val >> 8; 651 val = rtk_read_eeprom(sc, RTK_EE_EADDR1, addr_len); 652 eaddr[2] = val & 0xff; 653 eaddr[3] = val >> 8; 654 val = rtk_read_eeprom(sc, RTK_EE_EADDR2, addr_len); 655 eaddr[4] = val & 0xff; 656 eaddr[5] = val >> 8; 657 658 if ((error = bus_dmamem_alloc(sc->sc_dmat, 659 RTK_RXBUFLEN + 16, PAGE_SIZE, 0, &sc->sc_dmaseg, 1, &sc->sc_dmanseg, 660 BUS_DMA_NOWAIT)) != 0) { 661 printf("%s: can't allocate recv buffer, error = %d\n", 662 sc->sc_dev.dv_xname, error); 663 goto fail_0; 664 } 665 666 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg, 667 RTK_RXBUFLEN + 16, (caddr_t *)&sc->rtk_rx_buf, 668 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 669 printf("%s: can't map recv buffer, error = %d\n", 670 sc->sc_dev.dv_xname, error); 671 goto fail_1; 672 } 673 674 if ((error = bus_dmamap_create(sc->sc_dmat, 675 RTK_RXBUFLEN + 16, 1, RTK_RXBUFLEN + 16, 0, BUS_DMA_NOWAIT, 676 &sc->recv_dmamap)) != 0) { 677 printf("%s: can't create recv buffer DMA map, error = %d\n", 678 sc->sc_dev.dv_xname, error); 679 goto fail_2; 680 } 681 682 if ((error = bus_dmamap_load(sc->sc_dmat, sc->recv_dmamap, 683 sc->rtk_rx_buf, RTK_RXBUFLEN + 16, 684 NULL, BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 685 printf("%s: can't load recv buffer DMA map, error = %d\n", 686 sc->sc_dev.dv_xname, error); 687 goto fail_3; 688 } 689 690 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 691 txd = &sc->rtk_tx_descs[i]; 692 if ((error = bus_dmamap_create(sc->sc_dmat, 693 MCLBYTES, 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 694 &txd->txd_dmamap)) != 0) { 695 printf("%s: can't create snd buffer DMA map," 696 " error = %d\n", sc->sc_dev.dv_xname, error); 697 goto fail_4; 698 } 699 txd->txd_txaddr = RTK_TXADDR0 + (i * 4); 700 txd->txd_txstat = RTK_TXSTAT0 + (i * 4); 701 } 702 SIMPLEQ_INIT(&sc->rtk_tx_free); 703 SIMPLEQ_INIT(&sc->rtk_tx_dirty); 704 705 /* 706 * From this point forward, the attachment cannot fail. A failure 707 * before this releases all resources thar may have been 708 * allocated. 709 */ 710 sc->sc_flags |= RTK_ATTACHED; 711 712 /* Init Early TX threshold. */ 713 sc->sc_txthresh = TXTH_256; 714 715 /* Reset the adapter. */ 716 rtk_reset(sc); 717 718 printf("%s: Ethernet address %s\n", 719 sc->sc_dev.dv_xname, ether_sprintf(eaddr)); 720 721 ifp = &sc->ethercom.ec_if; 722 ifp->if_softc = sc; 723 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 724 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 725 ifp->if_ioctl = rtk_ioctl; 726 ifp->if_start = rtk_start; 727 ifp->if_watchdog = rtk_watchdog; 728 ifp->if_init = rtk_init; 729 ifp->if_stop = rtk_stop; 730 IFQ_SET_READY(&ifp->if_snd); 731 732 /* 733 * Do ifmedia setup. 734 */ 735 sc->mii.mii_ifp = ifp; 736 sc->mii.mii_readreg = rtk_phy_readreg; 737 sc->mii.mii_writereg = rtk_phy_writereg; 738 sc->mii.mii_statchg = rtk_phy_statchg; 739 ifmedia_init(&sc->mii.mii_media, IFM_IMASK, rtk_ifmedia_upd, rtk_ifmedia_sts); 740 mii_attach(&sc->sc_dev, &sc->mii, 0xffffffff, 741 MII_PHY_ANY, MII_OFFSET_ANY, 0); 742 743 /* Choose a default media. */ 744 if (LIST_FIRST(&sc->mii.mii_phys) == NULL) { 745 ifmedia_add(&sc->mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 746 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_NONE); 747 } else { 748 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_AUTO); 749 } 750 751 /* 752 * Call MI attach routines. 753 */ 754 if_attach(ifp); 755 ether_ifattach(ifp, eaddr); 756 757 /* 758 * Make sure the interface is shutdown during reboot. 759 */ 760 sc->sc_sdhook = shutdownhook_establish(rtk_shutdown, sc); 761 if (sc->sc_sdhook == NULL) 762 printf("%s: WARNING: unable to establish shutdown hook\n", 763 sc->sc_dev.dv_xname); 764 /* 765 * Add a suspend hook to make sure we come back up after a 766 * resume. 767 */ 768 sc->sc_powerhook = powerhook_establish(rtk_power, sc); 769 if (sc->sc_powerhook == NULL) 770 printf("%s: WARNING: unable to establish power hook\n", 771 sc->sc_dev.dv_xname); 772 773 return; 774 fail_4: 775 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 776 txd = &sc->rtk_tx_descs[i]; 777 if (txd->txd_dmamap != NULL) 778 bus_dmamap_destroy(sc->sc_dmat, txd->txd_dmamap); 779 } 780 fail_3: 781 bus_dmamap_destroy(sc->sc_dmat, sc->recv_dmamap); 782 fail_2: 783 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rtk_rx_buf, 784 RTK_RXBUFLEN + 16); 785 fail_1: 786 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg); 787 fail_0: 788 return; 789 } 790 791 /* 792 * Initialize the transmit descriptors. 793 */ 794 STATIC int rtk_list_tx_init(sc) 795 struct rtk_softc *sc; 796 { 797 struct rtk_tx_desc *txd; 798 int i; 799 800 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) 801 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q); 802 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_free)) != NULL) 803 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_free, txd_q); 804 805 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 806 txd = &sc->rtk_tx_descs[i]; 807 CSR_WRITE_4(sc, txd->txd_txaddr, 0); 808 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_free, txd, txd_q); 809 } 810 811 return (0); 812 } 813 814 /* 815 * rtk_activate: 816 * Handle device activation/deactivation requests. 817 */ 818 int 819 rtk_activate(self, act) 820 struct device *self; 821 enum devact act; 822 { 823 struct rtk_softc *sc = (void *) self; 824 int s, error = 0; 825 826 s = splnet(); 827 switch (act) { 828 case DVACT_ACTIVATE: 829 error = EOPNOTSUPP; 830 break; 831 case DVACT_DEACTIVATE: 832 mii_activate(&sc->mii, act, MII_PHY_ANY, MII_OFFSET_ANY); 833 if_deactivate(&sc->ethercom.ec_if); 834 break; 835 } 836 splx(s); 837 838 return (error); 839 } 840 841 /* 842 * rtk_detach: 843 * Detach a rtk interface. 844 */ 845 int 846 rtk_detach(sc) 847 struct rtk_softc *sc; 848 { 849 struct ifnet *ifp = &sc->ethercom.ec_if; 850 struct rtk_tx_desc *txd; 851 int i; 852 853 /* 854 * Succeed now if there isn't any work to do. 855 */ 856 if ((sc->sc_flags & RTK_ATTACHED) == 0) 857 return (0); 858 859 /* Unhook our tick handler. */ 860 callout_stop(&sc->rtk_tick_ch); 861 862 /* Detach all PHYs. */ 863 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 864 865 /* Delete all remaining media. */ 866 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY); 867 868 ether_ifdetach(ifp); 869 if_detach(ifp); 870 871 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 872 txd = &sc->rtk_tx_descs[i]; 873 if (txd->txd_dmamap != NULL) 874 bus_dmamap_destroy(sc->sc_dmat, txd->txd_dmamap); 875 } 876 bus_dmamap_destroy(sc->sc_dmat, sc->recv_dmamap); 877 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rtk_rx_buf, 878 RTK_RXBUFLEN + 16); 879 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg); 880 881 shutdownhook_disestablish(sc->sc_sdhook); 882 powerhook_disestablish(sc->sc_powerhook); 883 884 return (0); 885 } 886 887 /* 888 * rtk_enable: 889 * Enable the RTL81X9 chip. 890 */ 891 int 892 rtk_enable(sc) 893 struct rtk_softc *sc; 894 { 895 896 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 897 if ((*sc->sc_enable)(sc) != 0) { 898 printf("%s: device enable failed\n", 899 sc->sc_dev.dv_xname); 900 return (EIO); 901 } 902 sc->sc_flags |= RTK_ENABLED; 903 } 904 return (0); 905 } 906 907 /* 908 * rtk_disable: 909 * Disable the RTL81X9 chip. 910 */ 911 void 912 rtk_disable(sc) 913 struct rtk_softc *sc; 914 { 915 916 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 917 (*sc->sc_disable)(sc); 918 sc->sc_flags &= ~RTK_ENABLED; 919 } 920 } 921 922 /* 923 * rtk_power: 924 * Power management (suspend/resume) hook. 925 */ 926 void 927 rtk_power(why, arg) 928 int why; 929 void *arg; 930 { 931 struct rtk_softc *sc = (void *) arg; 932 struct ifnet *ifp = &sc->ethercom.ec_if; 933 int s; 934 935 s = splnet(); 936 switch (why) { 937 case PWR_SUSPEND: 938 case PWR_STANDBY: 939 rtk_stop(ifp, 0); 940 if (sc->sc_power != NULL) 941 (*sc->sc_power)(sc, why); 942 break; 943 case PWR_RESUME: 944 if (ifp->if_flags & IFF_UP) { 945 if (sc->sc_power != NULL) 946 (*sc->sc_power)(sc, why); 947 rtk_init(ifp); 948 } 949 break; 950 case PWR_SOFTSUSPEND: 951 case PWR_SOFTSTANDBY: 952 case PWR_SOFTRESUME: 953 break; 954 } 955 splx(s); 956 } 957 958 /* 959 * A frame has been uploaded: pass the resulting mbuf chain up to 960 * the higher level protocols. 961 * 962 * You know there's something wrong with a PCI bus-master chip design. 963 * 964 * The receive operation is badly documented in the datasheet, so I'll 965 * attempt to document it here. The driver provides a buffer area and 966 * places its base address in the RX buffer start address register. 967 * The chip then begins copying frames into the RX buffer. Each frame 968 * is preceded by a 32-bit RX status word which specifies the length 969 * of the frame and certain other status bits. Each frame (starting with 970 * the status word) is also 32-bit aligned. The frame length is in the 971 * first 16 bits of the status word; the lower 15 bits correspond with 972 * the 'rx status register' mentioned in the datasheet. 973 * 974 * Note: to make the Alpha happy, the frame payload needs to be aligned 975 * on a 32-bit boundary. To achieve this, we copy the data to mbuf 976 * shifted forward 2 bytes. 977 */ 978 STATIC void rtk_rxeof(sc) 979 struct rtk_softc *sc; 980 { 981 struct mbuf *m; 982 struct ifnet *ifp; 983 caddr_t rxbufpos, dst; 984 u_int total_len, wrap = 0; 985 u_int32_t rxstat; 986 u_int16_t cur_rx, new_rx; 987 u_int16_t limit; 988 u_int16_t rx_bytes = 0, max_bytes; 989 990 ifp = &sc->ethercom.ec_if; 991 992 cur_rx = (CSR_READ_2(sc, RTK_CURRXADDR) + 16) % RTK_RXBUFLEN; 993 994 /* Do not try to read past this point. */ 995 limit = CSR_READ_2(sc, RTK_CURRXBUF) % RTK_RXBUFLEN; 996 997 if (limit < cur_rx) 998 max_bytes = (RTK_RXBUFLEN - cur_rx) + limit; 999 else 1000 max_bytes = limit - cur_rx; 1001 1002 while((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_EMPTY_RXBUF) == 0) { 1003 rxbufpos = sc->rtk_rx_buf + cur_rx; 1004 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 1005 RTK_RXSTAT_LEN, BUS_DMASYNC_POSTREAD); 1006 rxstat = le32toh(*(u_int32_t *)rxbufpos); 1007 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 1008 RTK_RXSTAT_LEN, BUS_DMASYNC_PREREAD); 1009 1010 /* 1011 * Here's a totally undocumented fact for you. When the 1012 * RealTek chip is in the process of copying a packet into 1013 * RAM for you, the length will be 0xfff0. If you spot a 1014 * packet header with this value, you need to stop. The 1015 * datasheet makes absolutely no mention of this and 1016 * RealTek should be shot for this. 1017 */ 1018 total_len = rxstat >> 16; 1019 if (total_len == RTK_RXSTAT_UNFINISHED) 1020 break; 1021 1022 if ((rxstat & RTK_RXSTAT_RXOK) == 0 || 1023 total_len > ETHER_MAX_LEN) { 1024 ifp->if_ierrors++; 1025 1026 /* 1027 * submitted by:[netbsd-pcmcia:00484] 1028 * Takahiro Kambe <taca@sky.yamashina.kyoto.jp> 1029 * obtain from: 1030 * FreeBSD if_rl.c rev 1.24->1.25 1031 * 1032 */ 1033 #if 0 1034 if (rxstat & (RTK_RXSTAT_BADSYM|RTK_RXSTAT_RUNT| 1035 RTK_RXSTAT_GIANT|RTK_RXSTAT_CRCERR| 1036 RTK_RXSTAT_ALIGNERR)) { 1037 CSR_WRITE_2(sc, RTK_COMMAND, RTK_CMD_TX_ENB); 1038 CSR_WRITE_2(sc, RTK_COMMAND, 1039 RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1040 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG); 1041 CSR_WRITE_4(sc, RTK_RXADDR, 1042 sc->recv_dmamap->dm_segs[0].ds_addr); 1043 cur_rx = 0; 1044 } 1045 break; 1046 #else 1047 rtk_init(ifp); 1048 return; 1049 #endif 1050 } 1051 1052 /* No errors; receive the packet. */ 1053 rx_bytes += total_len + RTK_RXSTAT_LEN; 1054 1055 /* 1056 * Avoid trying to read more bytes than we know 1057 * the chip has prepared for us. 1058 */ 1059 if (rx_bytes > max_bytes) 1060 break; 1061 1062 /* 1063 * Skip the status word, wrapping around to the beginning 1064 * of the Rx area, if necessary. 1065 */ 1066 cur_rx = (cur_rx + RTK_RXSTAT_LEN) % RTK_RXBUFLEN; 1067 rxbufpos = sc->rtk_rx_buf + cur_rx; 1068 1069 /* 1070 * Compute the number of bytes at which the packet 1071 * will wrap to the beginning of the ring buffer. 1072 */ 1073 wrap = RTK_RXBUFLEN - cur_rx; 1074 1075 /* 1076 * Compute where the next pending packet is. 1077 */ 1078 if (total_len > wrap) 1079 new_rx = total_len - wrap; 1080 else 1081 new_rx = cur_rx + total_len; 1082 /* Round up to 32-bit boundary. */ 1083 new_rx = (new_rx + 3) & ~3; 1084 1085 /* 1086 * Now allocate an mbuf (and possibly a cluster) to hold 1087 * the packet. Note we offset the packet 2 bytes so that 1088 * data after the Ethernet header will be 4-byte aligned. 1089 */ 1090 MGETHDR(m, M_DONTWAIT, MT_DATA); 1091 if (m == NULL) { 1092 printf("%s: unable to allocate Rx mbuf\n", 1093 sc->sc_dev.dv_xname); 1094 ifp->if_ierrors++; 1095 goto next_packet; 1096 } 1097 if (total_len > (MHLEN - RTK_ETHER_ALIGN)) { 1098 MCLGET(m, M_DONTWAIT); 1099 if ((m->m_flags & M_EXT) == 0) { 1100 printf("%s: unable to allocate Rx cluster\n", 1101 sc->sc_dev.dv_xname); 1102 ifp->if_ierrors++; 1103 m_freem(m); 1104 m = NULL; 1105 goto next_packet; 1106 } 1107 } 1108 m->m_data += RTK_ETHER_ALIGN; /* for alignment */ 1109 m->m_pkthdr.rcvif = ifp; 1110 m->m_pkthdr.len = m->m_len = total_len; 1111 dst = mtod(m, caddr_t); 1112 1113 /* 1114 * If the packet wraps, copy up to the wrapping point. 1115 */ 1116 if (total_len > wrap) { 1117 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1118 cur_rx, wrap, BUS_DMASYNC_POSTREAD); 1119 memcpy(dst, rxbufpos, wrap); 1120 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1121 cur_rx, wrap, BUS_DMASYNC_PREREAD); 1122 cur_rx = 0; 1123 rxbufpos = sc->rtk_rx_buf; 1124 total_len -= wrap; 1125 dst += wrap; 1126 } 1127 1128 /* 1129 * ...and now the rest. 1130 */ 1131 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1132 cur_rx, total_len, BUS_DMASYNC_POSTREAD); 1133 memcpy(dst, rxbufpos, total_len); 1134 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1135 cur_rx, total_len, BUS_DMASYNC_PREREAD); 1136 1137 next_packet: 1138 CSR_WRITE_2(sc, RTK_CURRXADDR, new_rx - 16); 1139 cur_rx = new_rx; 1140 1141 if (m == NULL) 1142 continue; 1143 1144 /* 1145 * The RealTek chip includes the CRC with every 1146 * incoming packet. 1147 */ 1148 m->m_flags |= M_HASFCS; 1149 1150 ifp->if_ipackets++; 1151 1152 #if NBPFILTER > 0 1153 if (ifp->if_bpf) 1154 bpf_mtap(ifp->if_bpf, m); 1155 #endif 1156 /* pass it on. */ 1157 (*ifp->if_input)(ifp, m); 1158 } 1159 } 1160 1161 /* 1162 * A frame was downloaded to the chip. It's safe for us to clean up 1163 * the list buffers. 1164 */ 1165 STATIC void rtk_txeof(sc) 1166 struct rtk_softc *sc; 1167 { 1168 struct ifnet *ifp; 1169 struct rtk_tx_desc *txd; 1170 u_int32_t txstat; 1171 1172 ifp = &sc->ethercom.ec_if; 1173 1174 /* Clear the timeout timer. */ 1175 ifp->if_timer = 0; 1176 1177 /* 1178 * Go through our tx list and free mbufs for those 1179 * frames that have been uploaded. 1180 */ 1181 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) { 1182 txstat = CSR_READ_4(sc, txd->txd_txstat); 1183 if ((txstat & (RTK_TXSTAT_TX_OK| 1184 RTK_TXSTAT_TX_UNDERRUN|RTK_TXSTAT_TXABRT)) == 0) 1185 break; 1186 1187 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q); 1188 1189 bus_dmamap_sync(sc->sc_dmat, txd->txd_dmamap, 0, 1190 txd->txd_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1191 bus_dmamap_unload(sc->sc_dmat, txd->txd_dmamap); 1192 m_freem(txd->txd_mbuf); 1193 txd->txd_mbuf = NULL; 1194 1195 ifp->if_collisions += (txstat & RTK_TXSTAT_COLLCNT) >> 24; 1196 1197 if (txstat & RTK_TXSTAT_TX_OK) 1198 ifp->if_opackets++; 1199 else { 1200 ifp->if_oerrors++; 1201 1202 /* 1203 * Increase Early TX threshold if underrun occurred. 1204 * Increase step 64 bytes. 1205 */ 1206 if (txstat & RTK_TXSTAT_TX_UNDERRUN) { 1207 printf("%s: transmit underrun;", 1208 sc->sc_dev.dv_xname); 1209 if (sc->sc_txthresh < TXTH_MAX) { 1210 sc->sc_txthresh += 2; 1211 printf(" new threshold: %d bytes", 1212 sc->sc_txthresh * 32); 1213 } 1214 printf("\n"); 1215 } 1216 if (txstat & (RTK_TXSTAT_TXABRT|RTK_TXSTAT_OUTOFWIN)) 1217 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG); 1218 } 1219 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_free, txd, txd_q); 1220 ifp->if_flags &= ~IFF_OACTIVE; 1221 } 1222 } 1223 1224 int rtk_intr(arg) 1225 void *arg; 1226 { 1227 struct rtk_softc *sc; 1228 struct ifnet *ifp; 1229 u_int16_t status; 1230 int handled = 0; 1231 1232 sc = arg; 1233 ifp = &sc->ethercom.ec_if; 1234 1235 /* Disable interrupts. */ 1236 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1237 1238 for (;;) { 1239 1240 status = CSR_READ_2(sc, RTK_ISR); 1241 if (status) 1242 CSR_WRITE_2(sc, RTK_ISR, status); 1243 1244 handled = 1; 1245 1246 if ((status & RTK_INTRS) == 0) 1247 break; 1248 1249 if (status & RTK_ISR_RX_OK) 1250 rtk_rxeof(sc); 1251 1252 if (status & RTK_ISR_RX_ERR) 1253 rtk_rxeof(sc); 1254 1255 if (status & (RTK_ISR_TX_OK|RTK_ISR_TX_ERR)) 1256 rtk_txeof(sc); 1257 1258 if (status & RTK_ISR_SYSTEM_ERR) { 1259 rtk_reset(sc); 1260 rtk_init(ifp); 1261 } 1262 } 1263 1264 /* Re-enable interrupts. */ 1265 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS); 1266 1267 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 1268 rtk_start(ifp); 1269 1270 return (handled); 1271 } 1272 1273 /* 1274 * Main transmit routine. 1275 */ 1276 1277 STATIC void rtk_start(ifp) 1278 struct ifnet *ifp; 1279 { 1280 struct rtk_softc *sc; 1281 struct rtk_tx_desc *txd; 1282 struct mbuf *m_head = NULL, *m_new; 1283 int error, len; 1284 1285 sc = ifp->if_softc; 1286 1287 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_free)) != NULL) { 1288 IFQ_POLL(&ifp->if_snd, m_head); 1289 if (m_head == NULL) 1290 break; 1291 m_new = NULL; 1292 1293 /* 1294 * Load the DMA map. If this fails, the packet didn't 1295 * fit in one DMA segment, and we need to copy. Note, 1296 * the packet must also be aligned. 1297 * if the packet is too small, copy it too, so we're sure 1298 * so have enouth room for the pad buffer. 1299 */ 1300 if ((mtod(m_head, uintptr_t) & 3) != 0 || 1301 m_head->m_pkthdr.len < ETHER_PAD_LEN || 1302 bus_dmamap_load_mbuf(sc->sc_dmat, txd->txd_dmamap, 1303 m_head, BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1304 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1305 if (m_new == NULL) { 1306 printf("%s: unable to allocate Tx mbuf\n", 1307 sc->sc_dev.dv_xname); 1308 break; 1309 } 1310 if (m_head->m_pkthdr.len > MHLEN) { 1311 MCLGET(m_new, M_DONTWAIT); 1312 if ((m_new->m_flags & M_EXT) == 0) { 1313 printf("%s: unable to allocate Tx " 1314 "cluster\n", sc->sc_dev.dv_xname); 1315 m_freem(m_new); 1316 break; 1317 } 1318 } 1319 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1320 mtod(m_new, caddr_t)); 1321 m_new->m_pkthdr.len = m_new->m_len = 1322 m_head->m_pkthdr.len; 1323 if (m_head->m_pkthdr.len < ETHER_PAD_LEN) { 1324 memset( 1325 mtod(m_new, caddr_t) + m_head->m_pkthdr.len, 1326 0, ETHER_PAD_LEN - m_head->m_pkthdr.len); 1327 m_new->m_pkthdr.len = m_new->m_len = 1328 ETHER_PAD_LEN; 1329 } 1330 error = bus_dmamap_load_mbuf(sc->sc_dmat, 1331 txd->txd_dmamap, m_new, 1332 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1333 if (error) { 1334 printf("%s: unable to load Tx buffer, " 1335 "error = %d\n", sc->sc_dev.dv_xname, error); 1336 break; 1337 } 1338 } 1339 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1340 #if NBPFILTER > 0 1341 /* 1342 * If there's a BPF listener, bounce a copy of this frame 1343 * to him. 1344 */ 1345 if (ifp->if_bpf) 1346 bpf_mtap(ifp->if_bpf, m_head); 1347 #endif 1348 if (m_new != NULL) { 1349 m_freem(m_head); 1350 m_head = m_new; 1351 } 1352 txd->txd_mbuf = m_head; 1353 1354 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_free, txd_q); 1355 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_dirty, txd, txd_q); 1356 1357 /* 1358 * Transmit the frame. 1359 */ 1360 bus_dmamap_sync(sc->sc_dmat, 1361 txd->txd_dmamap, 0, txd->txd_dmamap->dm_mapsize, 1362 BUS_DMASYNC_PREWRITE); 1363 1364 len = txd->txd_dmamap->dm_segs[0].ds_len; 1365 1366 CSR_WRITE_4(sc, txd->txd_txaddr, 1367 txd->txd_dmamap->dm_segs[0].ds_addr); 1368 CSR_WRITE_4(sc, txd->txd_txstat, RTK_TX_THRESH(sc) | len); 1369 } 1370 1371 /* 1372 * We broke out of the loop because all our TX slots are 1373 * full. Mark the NIC as busy until it drains some of the 1374 * packets from the queue. 1375 */ 1376 if (SIMPLEQ_EMPTY(&sc->rtk_tx_free)) 1377 ifp->if_flags |= IFF_OACTIVE; 1378 1379 /* 1380 * Set a timeout in case the chip goes out to lunch. 1381 */ 1382 ifp->if_timer = 5; 1383 } 1384 1385 STATIC int rtk_init(ifp) 1386 struct ifnet *ifp; 1387 { 1388 struct rtk_softc *sc = ifp->if_softc; 1389 int error = 0, i; 1390 u_int32_t rxcfg; 1391 1392 if ((error = rtk_enable(sc)) != 0) 1393 goto out; 1394 1395 /* 1396 * Cancel pending I/O. 1397 */ 1398 rtk_stop(ifp, 0); 1399 1400 /* Init our MAC address */ 1401 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1402 CSR_WRITE_1(sc, RTK_IDR0 + i, LLADDR(ifp->if_sadl)[i]); 1403 } 1404 1405 /* Init the RX buffer pointer register. */ 1406 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 0, 1407 sc->recv_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1408 CSR_WRITE_4(sc, RTK_RXADDR, sc->recv_dmamap->dm_segs[0].ds_addr); 1409 1410 /* Init TX descriptors. */ 1411 rtk_list_tx_init(sc); 1412 1413 /* Init Early TX threshold. */ 1414 sc->sc_txthresh = TXTH_256; 1415 /* 1416 * Enable transmit and receive. 1417 */ 1418 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1419 1420 /* 1421 * Set the initial TX and RX configuration. 1422 */ 1423 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG); 1424 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG); 1425 1426 /* Set the individual bit to receive frames for this host only. */ 1427 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 1428 rxcfg |= RTK_RXCFG_RX_INDIV; 1429 1430 /* If we want promiscuous mode, set the allframes bit. */ 1431 if (ifp->if_flags & IFF_PROMISC) { 1432 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 1433 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1434 } else { 1435 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 1436 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1437 } 1438 1439 /* 1440 * Set capture broadcast bit to capture broadcast frames. 1441 */ 1442 if (ifp->if_flags & IFF_BROADCAST) { 1443 rxcfg |= RTK_RXCFG_RX_BROAD; 1444 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1445 } else { 1446 rxcfg &= ~RTK_RXCFG_RX_BROAD; 1447 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1448 } 1449 1450 /* 1451 * Program the multicast filter, if necessary. 1452 */ 1453 rtk_setmulti(sc); 1454 1455 /* 1456 * Enable interrupts. 1457 */ 1458 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS); 1459 1460 /* Start RX/TX process. */ 1461 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 1462 1463 /* Enable receiver and transmitter. */ 1464 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1465 1466 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD|RTK_CFG1_FULLDUPLEX); 1467 1468 /* 1469 * Set current media. 1470 */ 1471 mii_mediachg(&sc->mii); 1472 1473 ifp->if_flags |= IFF_RUNNING; 1474 ifp->if_flags &= ~IFF_OACTIVE; 1475 1476 callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc); 1477 1478 out: 1479 if (error) { 1480 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1481 ifp->if_timer = 0; 1482 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1483 } 1484 return (error); 1485 } 1486 1487 /* 1488 * Set media options. 1489 */ 1490 STATIC int rtk_ifmedia_upd(ifp) 1491 struct ifnet *ifp; 1492 { 1493 struct rtk_softc *sc; 1494 1495 sc = ifp->if_softc; 1496 1497 return (mii_mediachg(&sc->mii)); 1498 } 1499 1500 /* 1501 * Report current media status. 1502 */ 1503 STATIC void rtk_ifmedia_sts(ifp, ifmr) 1504 struct ifnet *ifp; 1505 struct ifmediareq *ifmr; 1506 { 1507 struct rtk_softc *sc; 1508 1509 sc = ifp->if_softc; 1510 1511 mii_pollstat(&sc->mii); 1512 ifmr->ifm_status = sc->mii.mii_media_status; 1513 ifmr->ifm_active = sc->mii.mii_media_active; 1514 } 1515 1516 STATIC int rtk_ioctl(ifp, command, data) 1517 struct ifnet *ifp; 1518 u_long command; 1519 caddr_t data; 1520 { 1521 struct rtk_softc *sc = ifp->if_softc; 1522 struct ifreq *ifr = (struct ifreq *) data; 1523 int s, error = 0; 1524 1525 s = splnet(); 1526 1527 switch (command) { 1528 case SIOCGIFMEDIA: 1529 case SIOCSIFMEDIA: 1530 error = ifmedia_ioctl(ifp, ifr, &sc->mii.mii_media, command); 1531 break; 1532 1533 default: 1534 error = ether_ioctl(ifp, command, data); 1535 if (error == ENETRESET) { 1536 if (RTK_IS_ENABLED(sc)) { 1537 /* 1538 * Multicast list has changed. Set the 1539 * hardware filter accordingly. 1540 */ 1541 rtk_setmulti(sc); 1542 } 1543 error = 0; 1544 } 1545 break; 1546 } 1547 1548 splx(s); 1549 1550 return (error); 1551 } 1552 1553 STATIC void rtk_watchdog(ifp) 1554 struct ifnet *ifp; 1555 { 1556 struct rtk_softc *sc; 1557 1558 sc = ifp->if_softc; 1559 1560 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1561 ifp->if_oerrors++; 1562 rtk_txeof(sc); 1563 rtk_rxeof(sc); 1564 rtk_init(ifp); 1565 } 1566 1567 /* 1568 * Stop the adapter and free any mbufs allocated to the 1569 * RX and TX lists. 1570 */ 1571 STATIC void rtk_stop(ifp, disable) 1572 struct ifnet *ifp; 1573 int disable; 1574 { 1575 struct rtk_softc *sc = ifp->if_softc; 1576 struct rtk_tx_desc *txd; 1577 1578 callout_stop(&sc->rtk_tick_ch); 1579 1580 mii_down(&sc->mii); 1581 1582 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 1583 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1584 1585 /* 1586 * Free the TX list buffers. 1587 */ 1588 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) { 1589 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q); 1590 bus_dmamap_unload(sc->sc_dmat, txd->txd_dmamap); 1591 m_freem(txd->txd_mbuf); 1592 txd->txd_mbuf = NULL; 1593 CSR_WRITE_4(sc, txd->txd_txaddr, 0); 1594 } 1595 1596 if (disable) 1597 rtk_disable(sc); 1598 1599 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1600 ifp->if_timer = 0; 1601 } 1602 1603 /* 1604 * Stop all chip I/O so that the kernel's probe routines don't 1605 * get confused by errant DMAs when rebooting. 1606 */ 1607 STATIC void rtk_shutdown(vsc) 1608 void *vsc; 1609 { 1610 struct rtk_softc *sc = (struct rtk_softc *)vsc; 1611 1612 rtk_stop(&sc->ethercom.ec_if, 0); 1613 } 1614 1615 STATIC void 1616 rtk_tick(arg) 1617 void *arg; 1618 { 1619 struct rtk_softc *sc = arg; 1620 int s = splnet(); 1621 1622 mii_tick(&sc->mii); 1623 splx(s); 1624 1625 callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc); 1626 } 1627