1 /* $NetBSD: rtl81x9.c,v 1.64 2006/10/12 01:31:01 christos Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_rl.c,v 1.17 1999/06/19 20:17:37 wpaul Exp 35 */ 36 37 /* 38 * RealTek 8129/8139 PCI NIC driver 39 * 40 * Supports several extremely cheap PCI 10/100 adapters based on 41 * the RealTek chipset. Datasheets can be obtained from 42 * www.realtek.com.tw. 43 * 44 * Written by Bill Paul <wpaul@ctr.columbia.edu> 45 * Electrical Engineering Department 46 * Columbia University, New York City 47 */ 48 49 /* 50 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 51 * probably the worst PCI ethernet controller ever made, with the possible 52 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 53 * DMA, but it has a terrible interface that nullifies any performance 54 * gains that bus-master DMA usually offers. 55 * 56 * For transmission, the chip offers a series of four TX descriptor 57 * registers. Each transmit frame must be in a contiguous buffer, aligned 58 * on a longword (32-bit) boundary. This means we almost always have to 59 * do mbuf copies in order to transmit a frame, except in the unlikely 60 * case where a) the packet fits into a single mbuf, and b) the packet 61 * is 32-bit aligned within the mbuf's data area. The presence of only 62 * four descriptor registers means that we can never have more than four 63 * packets queued for transmission at any one time. 64 * 65 * Reception is not much better. The driver has to allocate a single large 66 * buffer area (up to 64K in size) into which the chip will DMA received 67 * frames. Because we don't know where within this region received packets 68 * will begin or end, we have no choice but to copy data from the buffer 69 * area into mbufs in order to pass the packets up to the higher protocol 70 * levels. 71 * 72 * It's impossible given this rotten design to really achieve decent 73 * performance at 100Mbps, unless you happen to have a 400MHz PII or 74 * some equally overmuscled CPU to drive it. 75 * 76 * On the bright side, the 8139 does have a built-in PHY, although 77 * rather than using an MDIO serial interface like most other NICs, the 78 * PHY registers are directly accessible through the 8139's register 79 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 80 * filter. 81 * 82 * The 8129 chip is an older version of the 8139 that uses an external PHY 83 * chip. The 8129 has a serial MDIO interface for accessing the MII where 84 * the 8139 lets you directly access the on-board PHY registers. We need 85 * to select which interface to use depending on the chip type. 86 */ 87 88 #include <sys/cdefs.h> 89 __KERNEL_RCSID(0, "$NetBSD: rtl81x9.c,v 1.64 2006/10/12 01:31:01 christos Exp $"); 90 91 #include "bpfilter.h" 92 #include "rnd.h" 93 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/callout.h> 97 #include <sys/device.h> 98 #include <sys/sockio.h> 99 #include <sys/mbuf.h> 100 #include <sys/malloc.h> 101 #include <sys/kernel.h> 102 #include <sys/socket.h> 103 104 #include <uvm/uvm_extern.h> 105 106 #include <net/if.h> 107 #include <net/if_arp.h> 108 #include <net/if_ether.h> 109 #include <net/if_dl.h> 110 #include <net/if_media.h> 111 112 #if NBPFILTER > 0 113 #include <net/bpf.h> 114 #endif 115 #if NRND > 0 116 #include <sys/rnd.h> 117 #endif 118 119 #include <machine/bus.h> 120 #include <machine/endian.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 125 #include <dev/ic/rtl81x9reg.h> 126 #include <dev/ic/rtl81x9var.h> 127 128 #if defined(DEBUG) 129 #define STATIC 130 #else 131 #define STATIC static 132 #endif 133 134 STATIC void rtk_reset(struct rtk_softc *); 135 STATIC void rtk_rxeof(struct rtk_softc *); 136 STATIC void rtk_txeof(struct rtk_softc *); 137 STATIC void rtk_start(struct ifnet *); 138 STATIC int rtk_ioctl(struct ifnet *, u_long, caddr_t); 139 STATIC int rtk_init(struct ifnet *); 140 STATIC void rtk_stop(struct ifnet *, int); 141 142 STATIC void rtk_watchdog(struct ifnet *); 143 STATIC void rtk_shutdown(void *); 144 STATIC int rtk_ifmedia_upd(struct ifnet *); 145 STATIC void rtk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 146 147 STATIC void rtk_eeprom_putbyte(struct rtk_softc *, int, int); 148 STATIC void rtk_mii_sync(struct rtk_softc *); 149 STATIC void rtk_mii_send(struct rtk_softc *, uint32_t, int); 150 STATIC int rtk_mii_readreg(struct rtk_softc *, struct rtk_mii_frame *); 151 STATIC int rtk_mii_writereg(struct rtk_softc *, struct rtk_mii_frame *); 152 153 STATIC int rtk_phy_readreg(struct device *, int, int); 154 STATIC void rtk_phy_writereg(struct device *, int, int, int); 155 STATIC void rtk_phy_statchg(struct device *); 156 STATIC void rtk_tick(void *); 157 158 STATIC int rtk_enable(struct rtk_softc *); 159 STATIC void rtk_disable(struct rtk_softc *); 160 STATIC void rtk_power(int, void *); 161 162 STATIC int rtk_list_tx_init(struct rtk_softc *); 163 164 #define EE_SET(x) \ 165 CSR_WRITE_1(sc, RTK_EECMD, \ 166 CSR_READ_1(sc, RTK_EECMD) | (x)) 167 168 #define EE_CLR(x) \ 169 CSR_WRITE_1(sc, RTK_EECMD, \ 170 CSR_READ_1(sc, RTK_EECMD) & ~(x)) 171 172 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 173 174 /* 175 * Send a read command and address to the EEPROM, check for ACK. 176 */ 177 STATIC void 178 rtk_eeprom_putbyte(struct rtk_softc *sc, int addr, int addr_len) 179 { 180 int d, i; 181 182 d = (RTK_EECMD_READ << addr_len) | addr; 183 184 /* 185 * Feed in each bit and stobe the clock. 186 */ 187 for (i = RTK_EECMD_LEN + addr_len; i > 0; i--) { 188 if (d & (1 << (i - 1))) { 189 EE_SET(RTK_EE_DATAIN); 190 } else { 191 EE_CLR(RTK_EE_DATAIN); 192 } 193 DELAY(4); 194 EE_SET(RTK_EE_CLK); 195 DELAY(4); 196 EE_CLR(RTK_EE_CLK); 197 DELAY(4); 198 } 199 } 200 201 /* 202 * Read a word of data stored in the EEPROM at address 'addr.' 203 */ 204 uint16_t 205 rtk_read_eeprom(struct rtk_softc *sc, int addr, int addr_len) 206 { 207 uint16_t word; 208 int i; 209 210 /* Enter EEPROM access mode. */ 211 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_PROGRAM|RTK_EE_SEL); 212 213 /* 214 * Send address of word we want to read. 215 */ 216 rtk_eeprom_putbyte(sc, addr, addr_len); 217 218 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_PROGRAM|RTK_EE_SEL); 219 220 /* 221 * Start reading bits from EEPROM. 222 */ 223 word = 0; 224 for (i = 16; i > 0; i--) { 225 EE_SET(RTK_EE_CLK); 226 DELAY(4); 227 if (CSR_READ_1(sc, RTK_EECMD) & RTK_EE_DATAOUT) 228 word |= 1 << (i - 1); 229 EE_CLR(RTK_EE_CLK); 230 DELAY(4); 231 } 232 233 /* Turn off EEPROM access mode. */ 234 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 235 236 return word; 237 } 238 239 /* 240 * MII access routines are provided for the 8129, which 241 * doesn't have a built-in PHY. For the 8139, we fake things 242 * up by diverting rtk_phy_readreg()/rtk_phy_writereg() to the 243 * direct access PHY registers. 244 */ 245 #define MII_SET(x) \ 246 CSR_WRITE_1(sc, RTK_MII, \ 247 CSR_READ_1(sc, RTK_MII) | (x)) 248 249 #define MII_CLR(x) \ 250 CSR_WRITE_1(sc, RTK_MII, \ 251 CSR_READ_1(sc, RTK_MII) & ~(x)) 252 253 /* 254 * Sync the PHYs by setting data bit and strobing the clock 32 times. 255 */ 256 STATIC void 257 rtk_mii_sync(struct rtk_softc *sc) 258 { 259 int i; 260 261 MII_SET(RTK_MII_DIR|RTK_MII_DATAOUT); 262 263 for (i = 0; i < 32; i++) { 264 MII_SET(RTK_MII_CLK); 265 DELAY(1); 266 MII_CLR(RTK_MII_CLK); 267 DELAY(1); 268 } 269 } 270 271 /* 272 * Clock a series of bits through the MII. 273 */ 274 STATIC void 275 rtk_mii_send(struct rtk_softc *sc, uint32_t bits, int cnt) 276 { 277 int i; 278 279 MII_CLR(RTK_MII_CLK); 280 281 for (i = cnt; i > 0; i--) { 282 if (bits & (1 << (i - 1))) { 283 MII_SET(RTK_MII_DATAOUT); 284 } else { 285 MII_CLR(RTK_MII_DATAOUT); 286 } 287 DELAY(1); 288 MII_CLR(RTK_MII_CLK); 289 DELAY(1); 290 MII_SET(RTK_MII_CLK); 291 } 292 } 293 294 /* 295 * Read an PHY register through the MII. 296 */ 297 STATIC int 298 rtk_mii_readreg(struct rtk_softc *sc, struct rtk_mii_frame *frame) 299 { 300 int i, ack, s; 301 302 s = splnet(); 303 304 /* 305 * Set up frame for RX. 306 */ 307 frame->mii_stdelim = RTK_MII_STARTDELIM; 308 frame->mii_opcode = RTK_MII_READOP; 309 frame->mii_turnaround = 0; 310 frame->mii_data = 0; 311 312 CSR_WRITE_2(sc, RTK_MII, 0); 313 314 /* 315 * Turn on data xmit. 316 */ 317 MII_SET(RTK_MII_DIR); 318 319 rtk_mii_sync(sc); 320 321 /* 322 * Send command/address info. 323 */ 324 rtk_mii_send(sc, frame->mii_stdelim, 2); 325 rtk_mii_send(sc, frame->mii_opcode, 2); 326 rtk_mii_send(sc, frame->mii_phyaddr, 5); 327 rtk_mii_send(sc, frame->mii_regaddr, 5); 328 329 /* Idle bit */ 330 MII_CLR((RTK_MII_CLK|RTK_MII_DATAOUT)); 331 DELAY(1); 332 MII_SET(RTK_MII_CLK); 333 DELAY(1); 334 335 /* Turn off xmit. */ 336 MII_CLR(RTK_MII_DIR); 337 338 /* Check for ack */ 339 MII_CLR(RTK_MII_CLK); 340 DELAY(1); 341 ack = CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN; 342 MII_SET(RTK_MII_CLK); 343 DELAY(1); 344 345 /* 346 * Now try reading data bits. If the ack failed, we still 347 * need to clock through 16 cycles to keep the PHY(s) in sync. 348 */ 349 if (ack) { 350 for (i = 0; i < 16; i++) { 351 MII_CLR(RTK_MII_CLK); 352 DELAY(1); 353 MII_SET(RTK_MII_CLK); 354 DELAY(1); 355 } 356 goto fail; 357 } 358 359 for (i = 16; i > 0; i--) { 360 MII_CLR(RTK_MII_CLK); 361 DELAY(1); 362 if (!ack) { 363 if (CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN) 364 frame->mii_data |= 1 << (i - 1); 365 DELAY(1); 366 } 367 MII_SET(RTK_MII_CLK); 368 DELAY(1); 369 } 370 371 fail: 372 MII_CLR(RTK_MII_CLK); 373 DELAY(1); 374 MII_SET(RTK_MII_CLK); 375 DELAY(1); 376 377 splx(s); 378 379 if (ack) 380 return 1; 381 return 0; 382 } 383 384 /* 385 * Write to a PHY register through the MII. 386 */ 387 STATIC int 388 rtk_mii_writereg(struct rtk_softc *sc, struct rtk_mii_frame *frame) 389 { 390 int s; 391 392 s = splnet(); 393 /* 394 * Set up frame for TX. 395 */ 396 frame->mii_stdelim = RTK_MII_STARTDELIM; 397 frame->mii_opcode = RTK_MII_WRITEOP; 398 frame->mii_turnaround = RTK_MII_TURNAROUND; 399 400 /* 401 * Turn on data output. 402 */ 403 MII_SET(RTK_MII_DIR); 404 405 rtk_mii_sync(sc); 406 407 rtk_mii_send(sc, frame->mii_stdelim, 2); 408 rtk_mii_send(sc, frame->mii_opcode, 2); 409 rtk_mii_send(sc, frame->mii_phyaddr, 5); 410 rtk_mii_send(sc, frame->mii_regaddr, 5); 411 rtk_mii_send(sc, frame->mii_turnaround, 2); 412 rtk_mii_send(sc, frame->mii_data, 16); 413 414 /* Idle bit. */ 415 MII_SET(RTK_MII_CLK); 416 DELAY(1); 417 MII_CLR(RTK_MII_CLK); 418 DELAY(1); 419 420 /* 421 * Turn off xmit. 422 */ 423 MII_CLR(RTK_MII_DIR); 424 425 splx(s); 426 427 return 0; 428 } 429 430 STATIC int 431 rtk_phy_readreg(struct device *self, int phy, int reg) 432 { 433 struct rtk_softc *sc = (void *)self; 434 struct rtk_mii_frame frame; 435 int rval; 436 int rtk8139_reg; 437 438 if (sc->rtk_type == RTK_8139) { 439 if (phy != 7) 440 return 0; 441 442 switch (reg) { 443 case MII_BMCR: 444 rtk8139_reg = RTK_BMCR; 445 break; 446 case MII_BMSR: 447 rtk8139_reg = RTK_BMSR; 448 break; 449 case MII_ANAR: 450 rtk8139_reg = RTK_ANAR; 451 break; 452 case MII_ANER: 453 rtk8139_reg = RTK_ANER; 454 break; 455 case MII_ANLPAR: 456 rtk8139_reg = RTK_LPAR; 457 break; 458 default: 459 #if 0 460 printf("%s: bad phy register\n", sc->sc_dev.dv_xname); 461 #endif 462 return 0; 463 } 464 rval = CSR_READ_2(sc, rtk8139_reg); 465 return rval; 466 } 467 468 memset((char *)&frame, 0, sizeof(frame)); 469 470 frame.mii_phyaddr = phy; 471 frame.mii_regaddr = reg; 472 rtk_mii_readreg(sc, &frame); 473 474 return frame.mii_data; 475 } 476 477 STATIC void rtk_phy_writereg(struct device *self, int phy, int reg, int data) 478 { 479 struct rtk_softc *sc = (void *)self; 480 struct rtk_mii_frame frame; 481 int rtk8139_reg; 482 483 if (sc->rtk_type == RTK_8139) { 484 if (phy != 7) 485 return; 486 487 switch (reg) { 488 case MII_BMCR: 489 rtk8139_reg = RTK_BMCR; 490 break; 491 case MII_BMSR: 492 rtk8139_reg = RTK_BMSR; 493 break; 494 case MII_ANAR: 495 rtk8139_reg = RTK_ANAR; 496 break; 497 case MII_ANER: 498 rtk8139_reg = RTK_ANER; 499 break; 500 case MII_ANLPAR: 501 rtk8139_reg = RTK_LPAR; 502 break; 503 default: 504 #if 0 505 printf("%s: bad phy register\n", sc->sc_dev.dv_xname); 506 #endif 507 return; 508 } 509 CSR_WRITE_2(sc, rtk8139_reg, data); 510 return; 511 } 512 513 memset((char *)&frame, 0, sizeof(frame)); 514 515 frame.mii_phyaddr = phy; 516 frame.mii_regaddr = reg; 517 frame.mii_data = data; 518 519 rtk_mii_writereg(sc, &frame); 520 } 521 522 STATIC void 523 rtk_phy_statchg(struct device *v __unused) 524 { 525 526 /* Nothing to do. */ 527 } 528 529 #define rtk_calchash(addr) \ 530 (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 531 532 /* 533 * Program the 64-bit multicast hash filter. 534 */ 535 void 536 rtk_setmulti(struct rtk_softc *sc) 537 { 538 struct ifnet *ifp; 539 uint32_t hashes[2] = { 0, 0 }; 540 uint32_t rxfilt; 541 struct ether_multi *enm; 542 struct ether_multistep step; 543 int h, mcnt; 544 545 ifp = &sc->ethercom.ec_if; 546 547 rxfilt = CSR_READ_4(sc, RTK_RXCFG); 548 549 if (ifp->if_flags & IFF_PROMISC) { 550 allmulti: 551 ifp->if_flags |= IFF_ALLMULTI; 552 rxfilt |= RTK_RXCFG_RX_MULTI; 553 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt); 554 CSR_WRITE_4(sc, RTK_MAR0, 0xFFFFFFFF); 555 CSR_WRITE_4(sc, RTK_MAR4, 0xFFFFFFFF); 556 return; 557 } 558 559 /* first, zot all the existing hash bits */ 560 CSR_WRITE_4(sc, RTK_MAR0, 0); 561 CSR_WRITE_4(sc, RTK_MAR4, 0); 562 563 /* now program new ones */ 564 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 565 mcnt = 0; 566 while (enm != NULL) { 567 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 568 ETHER_ADDR_LEN) != 0) 569 goto allmulti; 570 571 h = rtk_calchash(enm->enm_addrlo); 572 if (h < 32) 573 hashes[0] |= (1 << h); 574 else 575 hashes[1] |= (1 << (h - 32)); 576 mcnt++; 577 ETHER_NEXT_MULTI(step, enm); 578 } 579 580 ifp->if_flags &= ~IFF_ALLMULTI; 581 582 if (mcnt) 583 rxfilt |= RTK_RXCFG_RX_MULTI; 584 else 585 rxfilt &= ~RTK_RXCFG_RX_MULTI; 586 587 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt); 588 CSR_WRITE_4(sc, RTK_MAR0, hashes[0]); 589 CSR_WRITE_4(sc, RTK_MAR4, hashes[1]); 590 } 591 592 void 593 rtk_reset(struct rtk_softc *sc) 594 { 595 int i; 596 597 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 598 599 for (i = 0; i < RTK_TIMEOUT; i++) { 600 DELAY(10); 601 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0) 602 break; 603 } 604 if (i == RTK_TIMEOUT) 605 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname); 606 } 607 608 /* 609 * Attach the interface. Allocate softc structures, do ifmedia 610 * setup and ethernet/BPF attach. 611 */ 612 void 613 rtk_attach(struct rtk_softc *sc) 614 { 615 struct ifnet *ifp; 616 struct rtk_tx_desc *txd; 617 uint16_t val; 618 uint8_t eaddr[ETHER_ADDR_LEN]; 619 int error; 620 int i, addr_len; 621 622 callout_init(&sc->rtk_tick_ch); 623 624 /* 625 * Check EEPROM type 9346 or 9356. 626 */ 627 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 628 addr_len = RTK_EEADDR_LEN1; 629 else 630 addr_len = RTK_EEADDR_LEN0; 631 632 /* 633 * Get station address. 634 */ 635 val = rtk_read_eeprom(sc, RTK_EE_EADDR0, addr_len); 636 eaddr[0] = val & 0xff; 637 eaddr[1] = val >> 8; 638 val = rtk_read_eeprom(sc, RTK_EE_EADDR1, addr_len); 639 eaddr[2] = val & 0xff; 640 eaddr[3] = val >> 8; 641 val = rtk_read_eeprom(sc, RTK_EE_EADDR2, addr_len); 642 eaddr[4] = val & 0xff; 643 eaddr[5] = val >> 8; 644 645 if ((error = bus_dmamem_alloc(sc->sc_dmat, 646 RTK_RXBUFLEN + 16, PAGE_SIZE, 0, &sc->sc_dmaseg, 1, &sc->sc_dmanseg, 647 BUS_DMA_NOWAIT)) != 0) { 648 printf("%s: can't allocate recv buffer, error = %d\n", 649 sc->sc_dev.dv_xname, error); 650 goto fail_0; 651 } 652 653 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg, 654 RTK_RXBUFLEN + 16, (caddr_t *)&sc->rtk_rx_buf, 655 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 656 printf("%s: can't map recv buffer, error = %d\n", 657 sc->sc_dev.dv_xname, error); 658 goto fail_1; 659 } 660 661 if ((error = bus_dmamap_create(sc->sc_dmat, 662 RTK_RXBUFLEN + 16, 1, RTK_RXBUFLEN + 16, 0, BUS_DMA_NOWAIT, 663 &sc->recv_dmamap)) != 0) { 664 printf("%s: can't create recv buffer DMA map, error = %d\n", 665 sc->sc_dev.dv_xname, error); 666 goto fail_2; 667 } 668 669 if ((error = bus_dmamap_load(sc->sc_dmat, sc->recv_dmamap, 670 sc->rtk_rx_buf, RTK_RXBUFLEN + 16, 671 NULL, BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 672 printf("%s: can't load recv buffer DMA map, error = %d\n", 673 sc->sc_dev.dv_xname, error); 674 goto fail_3; 675 } 676 677 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 678 txd = &sc->rtk_tx_descs[i]; 679 if ((error = bus_dmamap_create(sc->sc_dmat, 680 MCLBYTES, 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 681 &txd->txd_dmamap)) != 0) { 682 printf("%s: can't create snd buffer DMA map," 683 " error = %d\n", sc->sc_dev.dv_xname, error); 684 goto fail_4; 685 } 686 txd->txd_txaddr = RTK_TXADDR0 + (i * 4); 687 txd->txd_txstat = RTK_TXSTAT0 + (i * 4); 688 } 689 SIMPLEQ_INIT(&sc->rtk_tx_free); 690 SIMPLEQ_INIT(&sc->rtk_tx_dirty); 691 692 /* 693 * From this point forward, the attachment cannot fail. A failure 694 * before this releases all resources thar may have been 695 * allocated. 696 */ 697 sc->sc_flags |= RTK_ATTACHED; 698 699 /* Init Early TX threshold. */ 700 sc->sc_txthresh = TXTH_256; 701 702 /* Reset the adapter. */ 703 rtk_reset(sc); 704 705 printf("%s: Ethernet address %s\n", 706 sc->sc_dev.dv_xname, ether_sprintf(eaddr)); 707 708 ifp = &sc->ethercom.ec_if; 709 ifp->if_softc = sc; 710 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 711 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 712 ifp->if_ioctl = rtk_ioctl; 713 ifp->if_start = rtk_start; 714 ifp->if_watchdog = rtk_watchdog; 715 ifp->if_init = rtk_init; 716 ifp->if_stop = rtk_stop; 717 IFQ_SET_READY(&ifp->if_snd); 718 719 /* 720 * Do ifmedia setup. 721 */ 722 sc->mii.mii_ifp = ifp; 723 sc->mii.mii_readreg = rtk_phy_readreg; 724 sc->mii.mii_writereg = rtk_phy_writereg; 725 sc->mii.mii_statchg = rtk_phy_statchg; 726 ifmedia_init(&sc->mii.mii_media, IFM_IMASK, rtk_ifmedia_upd, 727 rtk_ifmedia_sts); 728 mii_attach(&sc->sc_dev, &sc->mii, 0xffffffff, 729 MII_PHY_ANY, MII_OFFSET_ANY, 0); 730 731 /* Choose a default media. */ 732 if (LIST_FIRST(&sc->mii.mii_phys) == NULL) { 733 ifmedia_add(&sc->mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 734 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_NONE); 735 } else { 736 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_AUTO); 737 } 738 739 /* 740 * Call MI attach routines. 741 */ 742 if_attach(ifp); 743 ether_ifattach(ifp, eaddr); 744 745 /* 746 * Make sure the interface is shutdown during reboot. 747 */ 748 sc->sc_sdhook = shutdownhook_establish(rtk_shutdown, sc); 749 if (sc->sc_sdhook == NULL) 750 printf("%s: WARNING: unable to establish shutdown hook\n", 751 sc->sc_dev.dv_xname); 752 /* 753 * Add a suspend hook to make sure we come back up after a 754 * resume. 755 */ 756 sc->sc_powerhook = powerhook_establish(sc->sc_dev.dv_xname, 757 rtk_power, sc); 758 if (sc->sc_powerhook == NULL) 759 printf("%s: WARNING: unable to establish power hook\n", 760 sc->sc_dev.dv_xname); 761 762 763 #if NRND > 0 764 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 765 RND_TYPE_NET, 0); 766 #endif 767 768 return; 769 fail_4: 770 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 771 txd = &sc->rtk_tx_descs[i]; 772 if (txd->txd_dmamap != NULL) 773 bus_dmamap_destroy(sc->sc_dmat, txd->txd_dmamap); 774 } 775 fail_3: 776 bus_dmamap_destroy(sc->sc_dmat, sc->recv_dmamap); 777 fail_2: 778 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rtk_rx_buf, 779 RTK_RXBUFLEN + 16); 780 fail_1: 781 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg); 782 fail_0: 783 return; 784 } 785 786 /* 787 * Initialize the transmit descriptors. 788 */ 789 STATIC int 790 rtk_list_tx_init(struct rtk_softc *sc) 791 { 792 struct rtk_tx_desc *txd; 793 int i; 794 795 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) 796 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q); 797 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_free)) != NULL) 798 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_free, txd_q); 799 800 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 801 txd = &sc->rtk_tx_descs[i]; 802 CSR_WRITE_4(sc, txd->txd_txaddr, 0); 803 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_free, txd, txd_q); 804 } 805 806 return 0; 807 } 808 809 /* 810 * rtk_activate: 811 * Handle device activation/deactivation requests. 812 */ 813 int 814 rtk_activate(struct device *self, enum devact act) 815 { 816 struct rtk_softc *sc = (void *)self; 817 int s, error; 818 819 error = 0; 820 s = splnet(); 821 switch (act) { 822 case DVACT_ACTIVATE: 823 error = EOPNOTSUPP; 824 break; 825 case DVACT_DEACTIVATE: 826 mii_activate(&sc->mii, act, MII_PHY_ANY, MII_OFFSET_ANY); 827 if_deactivate(&sc->ethercom.ec_if); 828 break; 829 } 830 splx(s); 831 832 return error; 833 } 834 835 /* 836 * rtk_detach: 837 * Detach a rtk interface. 838 */ 839 int 840 rtk_detach(struct rtk_softc *sc) 841 { 842 struct ifnet *ifp = &sc->ethercom.ec_if; 843 struct rtk_tx_desc *txd; 844 int i; 845 846 /* 847 * Succeed now if there isn't any work to do. 848 */ 849 if ((sc->sc_flags & RTK_ATTACHED) == 0) 850 return 0; 851 852 /* Unhook our tick handler. */ 853 callout_stop(&sc->rtk_tick_ch); 854 855 /* Detach all PHYs. */ 856 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 857 858 /* Delete all remaining media. */ 859 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY); 860 861 #if NRND > 0 862 rnd_detach_source(&sc->rnd_source); 863 #endif 864 865 ether_ifdetach(ifp); 866 if_detach(ifp); 867 868 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 869 txd = &sc->rtk_tx_descs[i]; 870 if (txd->txd_dmamap != NULL) 871 bus_dmamap_destroy(sc->sc_dmat, txd->txd_dmamap); 872 } 873 bus_dmamap_destroy(sc->sc_dmat, sc->recv_dmamap); 874 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rtk_rx_buf, 875 RTK_RXBUFLEN + 16); 876 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg); 877 878 shutdownhook_disestablish(sc->sc_sdhook); 879 powerhook_disestablish(sc->sc_powerhook); 880 881 return 0; 882 } 883 884 /* 885 * rtk_enable: 886 * Enable the RTL81X9 chip. 887 */ 888 int 889 rtk_enable(struct rtk_softc *sc) 890 { 891 892 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 893 if ((*sc->sc_enable)(sc) != 0) { 894 printf("%s: device enable failed\n", 895 sc->sc_dev.dv_xname); 896 return EIO; 897 } 898 sc->sc_flags |= RTK_ENABLED; 899 } 900 return 0; 901 } 902 903 /* 904 * rtk_disable: 905 * Disable the RTL81X9 chip. 906 */ 907 void 908 rtk_disable(struct rtk_softc *sc) 909 { 910 911 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 912 (*sc->sc_disable)(sc); 913 sc->sc_flags &= ~RTK_ENABLED; 914 } 915 } 916 917 /* 918 * rtk_power: 919 * Power management (suspend/resume) hook. 920 */ 921 void 922 rtk_power(int why, void *arg) 923 { 924 struct rtk_softc *sc = (void *)arg; 925 struct ifnet *ifp = &sc->ethercom.ec_if; 926 int s; 927 928 s = splnet(); 929 switch (why) { 930 case PWR_SUSPEND: 931 case PWR_STANDBY: 932 rtk_stop(ifp, 0); 933 if (sc->sc_power != NULL) 934 (*sc->sc_power)(sc, why); 935 break; 936 case PWR_RESUME: 937 if (ifp->if_flags & IFF_UP) { 938 if (sc->sc_power != NULL) 939 (*sc->sc_power)(sc, why); 940 rtk_init(ifp); 941 } 942 break; 943 case PWR_SOFTSUSPEND: 944 case PWR_SOFTSTANDBY: 945 case PWR_SOFTRESUME: 946 break; 947 } 948 splx(s); 949 } 950 951 /* 952 * A frame has been uploaded: pass the resulting mbuf chain up to 953 * the higher level protocols. 954 * 955 * You know there's something wrong with a PCI bus-master chip design. 956 * 957 * The receive operation is badly documented in the datasheet, so I'll 958 * attempt to document it here. The driver provides a buffer area and 959 * places its base address in the RX buffer start address register. 960 * The chip then begins copying frames into the RX buffer. Each frame 961 * is preceded by a 32-bit RX status word which specifies the length 962 * of the frame and certain other status bits. Each frame (starting with 963 * the status word) is also 32-bit aligned. The frame length is in the 964 * first 16 bits of the status word; the lower 15 bits correspond with 965 * the 'rx status register' mentioned in the datasheet. 966 * 967 * Note: to make the Alpha happy, the frame payload needs to be aligned 968 * on a 32-bit boundary. To achieve this, we copy the data to mbuf 969 * shifted forward 2 bytes. 970 */ 971 STATIC void 972 rtk_rxeof(struct rtk_softc *sc) 973 { 974 struct mbuf *m; 975 struct ifnet *ifp; 976 caddr_t rxbufpos, dst; 977 u_int total_len, wrap; 978 uint32_t rxstat; 979 uint16_t cur_rx, new_rx; 980 uint16_t limit; 981 uint16_t rx_bytes, max_bytes; 982 983 ifp = &sc->ethercom.ec_if; 984 985 cur_rx = (CSR_READ_2(sc, RTK_CURRXADDR) + 16) % RTK_RXBUFLEN; 986 987 /* Do not try to read past this point. */ 988 limit = CSR_READ_2(sc, RTK_CURRXBUF) % RTK_RXBUFLEN; 989 990 if (limit < cur_rx) 991 max_bytes = (RTK_RXBUFLEN - cur_rx) + limit; 992 else 993 max_bytes = limit - cur_rx; 994 rx_bytes = 0; 995 996 while ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_EMPTY_RXBUF) == 0) { 997 rxbufpos = sc->rtk_rx_buf + cur_rx; 998 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 999 RTK_RXSTAT_LEN, BUS_DMASYNC_POSTREAD); 1000 rxstat = le32toh(*(uint32_t *)rxbufpos); 1001 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 1002 RTK_RXSTAT_LEN, BUS_DMASYNC_PREREAD); 1003 1004 /* 1005 * Here's a totally undocumented fact for you. When the 1006 * RealTek chip is in the process of copying a packet into 1007 * RAM for you, the length will be 0xfff0. If you spot a 1008 * packet header with this value, you need to stop. The 1009 * datasheet makes absolutely no mention of this and 1010 * RealTek should be shot for this. 1011 */ 1012 total_len = rxstat >> 16; 1013 if (total_len == RTK_RXSTAT_UNFINISHED) 1014 break; 1015 1016 if ((rxstat & RTK_RXSTAT_RXOK) == 0 || 1017 total_len < ETHER_MIN_LEN || 1018 total_len > ETHER_MAX_LEN) { 1019 ifp->if_ierrors++; 1020 1021 /* 1022 * submitted by:[netbsd-pcmcia:00484] 1023 * Takahiro Kambe <taca@sky.yamashina.kyoto.jp> 1024 * obtain from: 1025 * FreeBSD if_rl.c rev 1.24->1.25 1026 * 1027 */ 1028 #if 0 1029 if (rxstat & (RTK_RXSTAT_BADSYM|RTK_RXSTAT_RUNT| 1030 RTK_RXSTAT_GIANT|RTK_RXSTAT_CRCERR| 1031 RTK_RXSTAT_ALIGNERR)) { 1032 CSR_WRITE_2(sc, RTK_COMMAND, RTK_CMD_TX_ENB); 1033 CSR_WRITE_2(sc, RTK_COMMAND, 1034 RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1035 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG); 1036 CSR_WRITE_4(sc, RTK_RXADDR, 1037 sc->recv_dmamap->dm_segs[0].ds_addr); 1038 cur_rx = 0; 1039 } 1040 break; 1041 #else 1042 rtk_init(ifp); 1043 return; 1044 #endif 1045 } 1046 1047 /* No errors; receive the packet. */ 1048 rx_bytes += total_len + RTK_RXSTAT_LEN; 1049 1050 /* 1051 * Avoid trying to read more bytes than we know 1052 * the chip has prepared for us. 1053 */ 1054 if (rx_bytes > max_bytes) 1055 break; 1056 1057 /* 1058 * Skip the status word, wrapping around to the beginning 1059 * of the Rx area, if necessary. 1060 */ 1061 cur_rx = (cur_rx + RTK_RXSTAT_LEN) % RTK_RXBUFLEN; 1062 rxbufpos = sc->rtk_rx_buf + cur_rx; 1063 1064 /* 1065 * Compute the number of bytes at which the packet 1066 * will wrap to the beginning of the ring buffer. 1067 */ 1068 wrap = RTK_RXBUFLEN - cur_rx; 1069 1070 /* 1071 * Compute where the next pending packet is. 1072 */ 1073 if (total_len > wrap) 1074 new_rx = total_len - wrap; 1075 else 1076 new_rx = cur_rx + total_len; 1077 /* Round up to 32-bit boundary. */ 1078 new_rx = ((new_rx + 3) & ~3) % RTK_RXBUFLEN; 1079 1080 /* 1081 * The RealTek chip includes the CRC with every 1082 * incoming packet; trim it off here. 1083 */ 1084 total_len -= ETHER_CRC_LEN; 1085 1086 /* 1087 * Now allocate an mbuf (and possibly a cluster) to hold 1088 * the packet. Note we offset the packet 2 bytes so that 1089 * data after the Ethernet header will be 4-byte aligned. 1090 */ 1091 MGETHDR(m, M_DONTWAIT, MT_DATA); 1092 if (m == NULL) { 1093 printf("%s: unable to allocate Rx mbuf\n", 1094 sc->sc_dev.dv_xname); 1095 ifp->if_ierrors++; 1096 goto next_packet; 1097 } 1098 if (total_len > (MHLEN - RTK_ETHER_ALIGN)) { 1099 MCLGET(m, M_DONTWAIT); 1100 if ((m->m_flags & M_EXT) == 0) { 1101 printf("%s: unable to allocate Rx cluster\n", 1102 sc->sc_dev.dv_xname); 1103 ifp->if_ierrors++; 1104 m_freem(m); 1105 m = NULL; 1106 goto next_packet; 1107 } 1108 } 1109 m->m_data += RTK_ETHER_ALIGN; /* for alignment */ 1110 m->m_pkthdr.rcvif = ifp; 1111 m->m_pkthdr.len = m->m_len = total_len; 1112 dst = mtod(m, caddr_t); 1113 1114 /* 1115 * If the packet wraps, copy up to the wrapping point. 1116 */ 1117 if (total_len > wrap) { 1118 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1119 cur_rx, wrap, BUS_DMASYNC_POSTREAD); 1120 memcpy(dst, rxbufpos, wrap); 1121 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1122 cur_rx, wrap, BUS_DMASYNC_PREREAD); 1123 cur_rx = 0; 1124 rxbufpos = sc->rtk_rx_buf; 1125 total_len -= wrap; 1126 dst += wrap; 1127 } 1128 1129 /* 1130 * ...and now the rest. 1131 */ 1132 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1133 cur_rx, total_len, BUS_DMASYNC_POSTREAD); 1134 memcpy(dst, rxbufpos, total_len); 1135 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1136 cur_rx, total_len, BUS_DMASYNC_PREREAD); 1137 1138 next_packet: 1139 CSR_WRITE_2(sc, RTK_CURRXADDR, (new_rx - 16) % RTK_RXBUFLEN); 1140 cur_rx = new_rx; 1141 1142 if (m == NULL) 1143 continue; 1144 1145 ifp->if_ipackets++; 1146 1147 #if NBPFILTER > 0 1148 if (ifp->if_bpf) 1149 bpf_mtap(ifp->if_bpf, m); 1150 #endif 1151 /* pass it on. */ 1152 (*ifp->if_input)(ifp, m); 1153 } 1154 } 1155 1156 /* 1157 * A frame was downloaded to the chip. It's safe for us to clean up 1158 * the list buffers. 1159 */ 1160 STATIC void 1161 rtk_txeof(struct rtk_softc *sc) 1162 { 1163 struct ifnet *ifp; 1164 struct rtk_tx_desc *txd; 1165 uint32_t txstat; 1166 1167 ifp = &sc->ethercom.ec_if; 1168 1169 /* 1170 * Go through our tx list and free mbufs for those 1171 * frames that have been uploaded. 1172 */ 1173 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) { 1174 txstat = CSR_READ_4(sc, txd->txd_txstat); 1175 if ((txstat & (RTK_TXSTAT_TX_OK| 1176 RTK_TXSTAT_TX_UNDERRUN|RTK_TXSTAT_TXABRT)) == 0) 1177 break; 1178 1179 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q); 1180 1181 bus_dmamap_sync(sc->sc_dmat, txd->txd_dmamap, 0, 1182 txd->txd_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1183 bus_dmamap_unload(sc->sc_dmat, txd->txd_dmamap); 1184 m_freem(txd->txd_mbuf); 1185 txd->txd_mbuf = NULL; 1186 1187 ifp->if_collisions += (txstat & RTK_TXSTAT_COLLCNT) >> 24; 1188 1189 if (txstat & RTK_TXSTAT_TX_OK) 1190 ifp->if_opackets++; 1191 else { 1192 ifp->if_oerrors++; 1193 1194 /* 1195 * Increase Early TX threshold if underrun occurred. 1196 * Increase step 64 bytes. 1197 */ 1198 if (txstat & RTK_TXSTAT_TX_UNDERRUN) { 1199 #ifdef DEBUG 1200 printf("%s: transmit underrun;", 1201 sc->sc_dev.dv_xname); 1202 #endif 1203 if (sc->sc_txthresh < TXTH_MAX) { 1204 sc->sc_txthresh += 2; 1205 #ifdef DEBUG 1206 printf(" new threshold: %d bytes", 1207 sc->sc_txthresh * 32); 1208 #endif 1209 } 1210 printf("\n"); 1211 } 1212 if (txstat & (RTK_TXSTAT_TXABRT|RTK_TXSTAT_OUTOFWIN)) 1213 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG); 1214 } 1215 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_free, txd, txd_q); 1216 ifp->if_flags &= ~IFF_OACTIVE; 1217 } 1218 1219 /* Clear the timeout timer if there is no pending packet. */ 1220 if (SIMPLEQ_EMPTY(&sc->rtk_tx_dirty)) 1221 ifp->if_timer = 0; 1222 1223 } 1224 1225 int 1226 rtk_intr(void *arg) 1227 { 1228 struct rtk_softc *sc; 1229 struct ifnet *ifp; 1230 uint16_t status; 1231 int handled; 1232 1233 sc = arg; 1234 ifp = &sc->ethercom.ec_if; 1235 1236 /* Disable interrupts. */ 1237 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1238 1239 handled = 0; 1240 for (;;) { 1241 1242 status = CSR_READ_2(sc, RTK_ISR); 1243 if (status) 1244 CSR_WRITE_2(sc, RTK_ISR, status); 1245 1246 if ((status & RTK_INTRS) == 0) 1247 break; 1248 1249 handled = 1; 1250 1251 if (status & RTK_ISR_RX_OK) 1252 rtk_rxeof(sc); 1253 1254 if (status & RTK_ISR_RX_ERR) 1255 rtk_rxeof(sc); 1256 1257 if (status & (RTK_ISR_TX_OK|RTK_ISR_TX_ERR)) 1258 rtk_txeof(sc); 1259 1260 if (status & RTK_ISR_SYSTEM_ERR) { 1261 rtk_reset(sc); 1262 rtk_init(ifp); 1263 } 1264 } 1265 1266 /* Re-enable interrupts. */ 1267 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS); 1268 1269 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 1270 rtk_start(ifp); 1271 1272 #if NRND > 0 1273 if (RND_ENABLED(&sc->rnd_source)) 1274 rnd_add_uint32(&sc->rnd_source, status); 1275 #endif 1276 1277 return handled; 1278 } 1279 1280 /* 1281 * Main transmit routine. 1282 */ 1283 1284 STATIC void 1285 rtk_start(struct ifnet *ifp) 1286 { 1287 struct rtk_softc *sc; 1288 struct rtk_tx_desc *txd; 1289 struct mbuf *m_head, *m_new; 1290 int error, len; 1291 1292 sc = ifp->if_softc; 1293 1294 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_free)) != NULL) { 1295 IFQ_POLL(&ifp->if_snd, m_head); 1296 if (m_head == NULL) 1297 break; 1298 m_new = NULL; 1299 1300 /* 1301 * Load the DMA map. If this fails, the packet didn't 1302 * fit in one DMA segment, and we need to copy. Note, 1303 * the packet must also be aligned. 1304 * if the packet is too small, copy it too, so we're sure 1305 * so have enouth room for the pad buffer. 1306 */ 1307 if ((mtod(m_head, uintptr_t) & 3) != 0 || 1308 m_head->m_pkthdr.len < ETHER_PAD_LEN || 1309 bus_dmamap_load_mbuf(sc->sc_dmat, txd->txd_dmamap, 1310 m_head, BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1311 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1312 if (m_new == NULL) { 1313 printf("%s: unable to allocate Tx mbuf\n", 1314 sc->sc_dev.dv_xname); 1315 break; 1316 } 1317 if (m_head->m_pkthdr.len > MHLEN) { 1318 MCLGET(m_new, M_DONTWAIT); 1319 if ((m_new->m_flags & M_EXT) == 0) { 1320 printf("%s: unable to allocate Tx " 1321 "cluster\n", sc->sc_dev.dv_xname); 1322 m_freem(m_new); 1323 break; 1324 } 1325 } 1326 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1327 mtod(m_new, caddr_t)); 1328 m_new->m_pkthdr.len = m_new->m_len = 1329 m_head->m_pkthdr.len; 1330 if (m_head->m_pkthdr.len < ETHER_PAD_LEN) { 1331 memset( 1332 mtod(m_new, caddr_t) + m_head->m_pkthdr.len, 1333 0, ETHER_PAD_LEN - m_head->m_pkthdr.len); 1334 m_new->m_pkthdr.len = m_new->m_len = 1335 ETHER_PAD_LEN; 1336 } 1337 error = bus_dmamap_load_mbuf(sc->sc_dmat, 1338 txd->txd_dmamap, m_new, 1339 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1340 if (error) { 1341 printf("%s: unable to load Tx buffer, " 1342 "error = %d\n", sc->sc_dev.dv_xname, error); 1343 break; 1344 } 1345 } 1346 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1347 #if NBPFILTER > 0 1348 /* 1349 * If there's a BPF listener, bounce a copy of this frame 1350 * to him. 1351 */ 1352 if (ifp->if_bpf) 1353 bpf_mtap(ifp->if_bpf, m_head); 1354 #endif 1355 if (m_new != NULL) { 1356 m_freem(m_head); 1357 m_head = m_new; 1358 } 1359 txd->txd_mbuf = m_head; 1360 1361 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_free, txd_q); 1362 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_dirty, txd, txd_q); 1363 1364 /* 1365 * Transmit the frame. 1366 */ 1367 bus_dmamap_sync(sc->sc_dmat, 1368 txd->txd_dmamap, 0, txd->txd_dmamap->dm_mapsize, 1369 BUS_DMASYNC_PREWRITE); 1370 1371 len = txd->txd_dmamap->dm_segs[0].ds_len; 1372 1373 CSR_WRITE_4(sc, txd->txd_txaddr, 1374 txd->txd_dmamap->dm_segs[0].ds_addr); 1375 CSR_WRITE_4(sc, txd->txd_txstat, RTK_TX_THRESH(sc) | len); 1376 1377 /* 1378 * Set a timeout in case the chip goes out to lunch. 1379 */ 1380 ifp->if_timer = 5; 1381 } 1382 1383 /* 1384 * We broke out of the loop because all our TX slots are 1385 * full. Mark the NIC as busy until it drains some of the 1386 * packets from the queue. 1387 */ 1388 if (SIMPLEQ_EMPTY(&sc->rtk_tx_free)) 1389 ifp->if_flags |= IFF_OACTIVE; 1390 } 1391 1392 STATIC int 1393 rtk_init(struct ifnet *ifp) 1394 { 1395 struct rtk_softc *sc = ifp->if_softc; 1396 int error, i; 1397 uint32_t rxcfg; 1398 1399 if ((error = rtk_enable(sc)) != 0) 1400 goto out; 1401 1402 /* 1403 * Cancel pending I/O. 1404 */ 1405 rtk_stop(ifp, 0); 1406 1407 /* Init our MAC address */ 1408 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1409 CSR_WRITE_1(sc, RTK_IDR0 + i, LLADDR(ifp->if_sadl)[i]); 1410 } 1411 1412 /* Init the RX buffer pointer register. */ 1413 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 0, 1414 sc->recv_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1415 CSR_WRITE_4(sc, RTK_RXADDR, sc->recv_dmamap->dm_segs[0].ds_addr); 1416 1417 /* Init TX descriptors. */ 1418 rtk_list_tx_init(sc); 1419 1420 /* Init Early TX threshold. */ 1421 sc->sc_txthresh = TXTH_256; 1422 /* 1423 * Enable transmit and receive. 1424 */ 1425 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1426 1427 /* 1428 * Set the initial TX and RX configuration. 1429 */ 1430 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG); 1431 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG); 1432 1433 /* Set the individual bit to receive frames for this host only. */ 1434 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 1435 rxcfg |= RTK_RXCFG_RX_INDIV; 1436 1437 /* If we want promiscuous mode, set the allframes bit. */ 1438 if (ifp->if_flags & IFF_PROMISC) { 1439 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 1440 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1441 } else { 1442 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 1443 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1444 } 1445 1446 /* 1447 * Set capture broadcast bit to capture broadcast frames. 1448 */ 1449 if (ifp->if_flags & IFF_BROADCAST) { 1450 rxcfg |= RTK_RXCFG_RX_BROAD; 1451 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1452 } else { 1453 rxcfg &= ~RTK_RXCFG_RX_BROAD; 1454 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1455 } 1456 1457 /* 1458 * Program the multicast filter, if necessary. 1459 */ 1460 rtk_setmulti(sc); 1461 1462 /* 1463 * Enable interrupts. 1464 */ 1465 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS); 1466 1467 /* Start RX/TX process. */ 1468 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 1469 1470 /* Enable receiver and transmitter. */ 1471 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1472 1473 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD|RTK_CFG1_FULLDUPLEX); 1474 1475 /* 1476 * Set current media. 1477 */ 1478 mii_mediachg(&sc->mii); 1479 1480 ifp->if_flags |= IFF_RUNNING; 1481 ifp->if_flags &= ~IFF_OACTIVE; 1482 1483 callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc); 1484 1485 out: 1486 if (error) { 1487 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1488 ifp->if_timer = 0; 1489 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1490 } 1491 return error; 1492 } 1493 1494 /* 1495 * Set media options. 1496 */ 1497 STATIC int 1498 rtk_ifmedia_upd(struct ifnet *ifp) 1499 { 1500 struct rtk_softc *sc; 1501 1502 sc = ifp->if_softc; 1503 1504 return mii_mediachg(&sc->mii); 1505 } 1506 1507 /* 1508 * Report current media status. 1509 */ 1510 STATIC void 1511 rtk_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1512 { 1513 struct rtk_softc *sc; 1514 1515 sc = ifp->if_softc; 1516 1517 mii_pollstat(&sc->mii); 1518 ifmr->ifm_status = sc->mii.mii_media_status; 1519 ifmr->ifm_active = sc->mii.mii_media_active; 1520 } 1521 1522 STATIC int 1523 rtk_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1524 { 1525 struct rtk_softc *sc = ifp->if_softc; 1526 struct ifreq *ifr = (struct ifreq *)data; 1527 int s, error; 1528 1529 s = splnet(); 1530 1531 switch (command) { 1532 case SIOCGIFMEDIA: 1533 case SIOCSIFMEDIA: 1534 error = ifmedia_ioctl(ifp, ifr, &sc->mii.mii_media, command); 1535 break; 1536 1537 default: 1538 error = ether_ioctl(ifp, command, data); 1539 if (error == ENETRESET) { 1540 if (ifp->if_flags & IFF_RUNNING) { 1541 /* 1542 * Multicast list has changed. Set the 1543 * hardware filter accordingly. 1544 */ 1545 rtk_setmulti(sc); 1546 } 1547 error = 0; 1548 } 1549 break; 1550 } 1551 1552 splx(s); 1553 1554 return error; 1555 } 1556 1557 STATIC void 1558 rtk_watchdog(struct ifnet *ifp) 1559 { 1560 struct rtk_softc *sc; 1561 1562 sc = ifp->if_softc; 1563 1564 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1565 ifp->if_oerrors++; 1566 rtk_txeof(sc); 1567 rtk_rxeof(sc); 1568 rtk_init(ifp); 1569 } 1570 1571 /* 1572 * Stop the adapter and free any mbufs allocated to the 1573 * RX and TX lists. 1574 */ 1575 STATIC void 1576 rtk_stop(struct ifnet *ifp, int disable) 1577 { 1578 struct rtk_softc *sc = ifp->if_softc; 1579 struct rtk_tx_desc *txd; 1580 1581 callout_stop(&sc->rtk_tick_ch); 1582 1583 mii_down(&sc->mii); 1584 1585 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 1586 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1587 1588 /* 1589 * Free the TX list buffers. 1590 */ 1591 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) { 1592 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q); 1593 bus_dmamap_unload(sc->sc_dmat, txd->txd_dmamap); 1594 m_freem(txd->txd_mbuf); 1595 txd->txd_mbuf = NULL; 1596 CSR_WRITE_4(sc, txd->txd_txaddr, 0); 1597 } 1598 1599 if (disable) 1600 rtk_disable(sc); 1601 1602 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1603 ifp->if_timer = 0; 1604 } 1605 1606 /* 1607 * Stop all chip I/O so that the kernel's probe routines don't 1608 * get confused by errant DMAs when rebooting. 1609 */ 1610 STATIC void 1611 rtk_shutdown(void *arg) 1612 { 1613 struct rtk_softc *sc = (struct rtk_softc *)arg; 1614 1615 rtk_stop(&sc->ethercom.ec_if, 0); 1616 } 1617 1618 STATIC void 1619 rtk_tick(void *arg) 1620 { 1621 struct rtk_softc *sc = arg; 1622 int s; 1623 1624 s = splnet(); 1625 mii_tick(&sc->mii); 1626 splx(s); 1627 1628 callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc); 1629 } 1630