1 /* $NetBSD: rtl81x9.c,v 1.90 2010/04/05 07:19:36 joerg Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_rl.c,v 1.17 1999/06/19 20:17:37 wpaul Exp 35 */ 36 37 /* 38 * RealTek 8129/8139 PCI NIC driver 39 * 40 * Supports several extremely cheap PCI 10/100 adapters based on 41 * the RealTek chipset. Datasheets can be obtained from 42 * www.realtek.com.tw. 43 * 44 * Written by Bill Paul <wpaul@ctr.columbia.edu> 45 * Electrical Engineering Department 46 * Columbia University, New York City 47 */ 48 49 /* 50 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 51 * probably the worst PCI ethernet controller ever made, with the possible 52 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 53 * DMA, but it has a terrible interface that nullifies any performance 54 * gains that bus-master DMA usually offers. 55 * 56 * For transmission, the chip offers a series of four TX descriptor 57 * registers. Each transmit frame must be in a contiguous buffer, aligned 58 * on a longword (32-bit) boundary. This means we almost always have to 59 * do mbuf copies in order to transmit a frame, except in the unlikely 60 * case where a) the packet fits into a single mbuf, and b) the packet 61 * is 32-bit aligned within the mbuf's data area. The presence of only 62 * four descriptor registers means that we can never have more than four 63 * packets queued for transmission at any one time. 64 * 65 * Reception is not much better. The driver has to allocate a single large 66 * buffer area (up to 64K in size) into which the chip will DMA received 67 * frames. Because we don't know where within this region received packets 68 * will begin or end, we have no choice but to copy data from the buffer 69 * area into mbufs in order to pass the packets up to the higher protocol 70 * levels. 71 * 72 * It's impossible given this rotten design to really achieve decent 73 * performance at 100Mbps, unless you happen to have a 400MHz PII or 74 * some equally overmuscled CPU to drive it. 75 * 76 * On the bright side, the 8139 does have a built-in PHY, although 77 * rather than using an MDIO serial interface like most other NICs, the 78 * PHY registers are directly accessible through the 8139's register 79 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 80 * filter. 81 * 82 * The 8129 chip is an older version of the 8139 that uses an external PHY 83 * chip. The 8129 has a serial MDIO interface for accessing the MII where 84 * the 8139 lets you directly access the on-board PHY registers. We need 85 * to select which interface to use depending on the chip type. 86 */ 87 88 #include <sys/cdefs.h> 89 __KERNEL_RCSID(0, "$NetBSD: rtl81x9.c,v 1.90 2010/04/05 07:19:36 joerg Exp $"); 90 91 #include "rnd.h" 92 93 #include <sys/param.h> 94 #include <sys/systm.h> 95 #include <sys/callout.h> 96 #include <sys/device.h> 97 #include <sys/sockio.h> 98 #include <sys/mbuf.h> 99 #include <sys/malloc.h> 100 #include <sys/kernel.h> 101 #include <sys/socket.h> 102 103 #include <uvm/uvm_extern.h> 104 105 #include <net/if.h> 106 #include <net/if_arp.h> 107 #include <net/if_ether.h> 108 #include <net/if_dl.h> 109 #include <net/if_media.h> 110 111 #include <net/bpf.h> 112 #if NRND > 0 113 #include <sys/rnd.h> 114 #endif 115 116 #include <sys/bus.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 122 #include <dev/ic/rtl81x9reg.h> 123 #include <dev/ic/rtl81x9var.h> 124 125 static void rtk_reset(struct rtk_softc *); 126 static void rtk_rxeof(struct rtk_softc *); 127 static void rtk_txeof(struct rtk_softc *); 128 static void rtk_start(struct ifnet *); 129 static int rtk_ioctl(struct ifnet *, u_long, void *); 130 static int rtk_init(struct ifnet *); 131 static void rtk_stop(struct ifnet *, int); 132 133 static void rtk_watchdog(struct ifnet *); 134 135 static void rtk_eeprom_putbyte(struct rtk_softc *, int, int); 136 static void rtk_mii_sync(struct rtk_softc *); 137 static void rtk_mii_send(struct rtk_softc *, uint32_t, int); 138 static int rtk_mii_readreg(struct rtk_softc *, struct rtk_mii_frame *); 139 static int rtk_mii_writereg(struct rtk_softc *, struct rtk_mii_frame *); 140 141 static int rtk_phy_readreg(device_t, int, int); 142 static void rtk_phy_writereg(device_t, int, int, int); 143 static void rtk_phy_statchg(device_t); 144 static void rtk_tick(void *); 145 146 static int rtk_enable(struct rtk_softc *); 147 static void rtk_disable(struct rtk_softc *); 148 149 static void rtk_list_tx_init(struct rtk_softc *); 150 151 #define EE_SET(x) \ 152 CSR_WRITE_1(sc, RTK_EECMD, \ 153 CSR_READ_1(sc, RTK_EECMD) | (x)) 154 155 #define EE_CLR(x) \ 156 CSR_WRITE_1(sc, RTK_EECMD, \ 157 CSR_READ_1(sc, RTK_EECMD) & ~(x)) 158 159 #define EE_DELAY() DELAY(100) 160 161 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 162 163 /* 164 * Send a read command and address to the EEPROM, check for ACK. 165 */ 166 static void 167 rtk_eeprom_putbyte(struct rtk_softc *sc, int addr, int addr_len) 168 { 169 int d, i; 170 171 d = (RTK_EECMD_READ << addr_len) | addr; 172 173 /* 174 * Feed in each bit and stobe the clock. 175 */ 176 for (i = RTK_EECMD_LEN + addr_len; i > 0; i--) { 177 if (d & (1 << (i - 1))) { 178 EE_SET(RTK_EE_DATAIN); 179 } else { 180 EE_CLR(RTK_EE_DATAIN); 181 } 182 EE_DELAY(); 183 EE_SET(RTK_EE_CLK); 184 EE_DELAY(); 185 EE_CLR(RTK_EE_CLK); 186 EE_DELAY(); 187 } 188 } 189 190 /* 191 * Read a word of data stored in the EEPROM at address 'addr.' 192 */ 193 uint16_t 194 rtk_read_eeprom(struct rtk_softc *sc, int addr, int addr_len) 195 { 196 uint16_t word; 197 int i; 198 199 /* Enter EEPROM access mode. */ 200 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_PROGRAM); 201 EE_DELAY(); 202 EE_SET(RTK_EE_SEL); 203 204 /* 205 * Send address of word we want to read. 206 */ 207 rtk_eeprom_putbyte(sc, addr, addr_len); 208 209 /* 210 * Start reading bits from EEPROM. 211 */ 212 word = 0; 213 for (i = 16; i > 0; i--) { 214 EE_SET(RTK_EE_CLK); 215 EE_DELAY(); 216 if (CSR_READ_1(sc, RTK_EECMD) & RTK_EE_DATAOUT) 217 word |= 1 << (i - 1); 218 EE_CLR(RTK_EE_CLK); 219 EE_DELAY(); 220 } 221 222 /* Turn off EEPROM access mode. */ 223 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 224 225 return word; 226 } 227 228 /* 229 * MII access routines are provided for the 8129, which 230 * doesn't have a built-in PHY. For the 8139, we fake things 231 * up by diverting rtk_phy_readreg()/rtk_phy_writereg() to the 232 * direct access PHY registers. 233 */ 234 #define MII_SET(x) \ 235 CSR_WRITE_1(sc, RTK_MII, \ 236 CSR_READ_1(sc, RTK_MII) | (x)) 237 238 #define MII_CLR(x) \ 239 CSR_WRITE_1(sc, RTK_MII, \ 240 CSR_READ_1(sc, RTK_MII) & ~(x)) 241 242 /* 243 * Sync the PHYs by setting data bit and strobing the clock 32 times. 244 */ 245 static void 246 rtk_mii_sync(struct rtk_softc *sc) 247 { 248 int i; 249 250 MII_SET(RTK_MII_DIR|RTK_MII_DATAOUT); 251 252 for (i = 0; i < 32; i++) { 253 MII_SET(RTK_MII_CLK); 254 DELAY(1); 255 MII_CLR(RTK_MII_CLK); 256 DELAY(1); 257 } 258 } 259 260 /* 261 * Clock a series of bits through the MII. 262 */ 263 static void 264 rtk_mii_send(struct rtk_softc *sc, uint32_t bits, int cnt) 265 { 266 int i; 267 268 MII_CLR(RTK_MII_CLK); 269 270 for (i = cnt; i > 0; i--) { 271 if (bits & (1 << (i - 1))) { 272 MII_SET(RTK_MII_DATAOUT); 273 } else { 274 MII_CLR(RTK_MII_DATAOUT); 275 } 276 DELAY(1); 277 MII_CLR(RTK_MII_CLK); 278 DELAY(1); 279 MII_SET(RTK_MII_CLK); 280 } 281 } 282 283 /* 284 * Read an PHY register through the MII. 285 */ 286 static int 287 rtk_mii_readreg(struct rtk_softc *sc, struct rtk_mii_frame *frame) 288 { 289 int i, ack, s; 290 291 s = splnet(); 292 293 /* 294 * Set up frame for RX. 295 */ 296 frame->mii_stdelim = RTK_MII_STARTDELIM; 297 frame->mii_opcode = RTK_MII_READOP; 298 frame->mii_turnaround = 0; 299 frame->mii_data = 0; 300 301 CSR_WRITE_2(sc, RTK_MII, 0); 302 303 /* 304 * Turn on data xmit. 305 */ 306 MII_SET(RTK_MII_DIR); 307 308 rtk_mii_sync(sc); 309 310 /* 311 * Send command/address info. 312 */ 313 rtk_mii_send(sc, frame->mii_stdelim, 2); 314 rtk_mii_send(sc, frame->mii_opcode, 2); 315 rtk_mii_send(sc, frame->mii_phyaddr, 5); 316 rtk_mii_send(sc, frame->mii_regaddr, 5); 317 318 /* Idle bit */ 319 MII_CLR((RTK_MII_CLK|RTK_MII_DATAOUT)); 320 DELAY(1); 321 MII_SET(RTK_MII_CLK); 322 DELAY(1); 323 324 /* Turn off xmit. */ 325 MII_CLR(RTK_MII_DIR); 326 327 /* Check for ack */ 328 MII_CLR(RTK_MII_CLK); 329 DELAY(1); 330 ack = CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN; 331 MII_SET(RTK_MII_CLK); 332 DELAY(1); 333 334 /* 335 * Now try reading data bits. If the ack failed, we still 336 * need to clock through 16 cycles to keep the PHY(s) in sync. 337 */ 338 if (ack) { 339 for (i = 0; i < 16; i++) { 340 MII_CLR(RTK_MII_CLK); 341 DELAY(1); 342 MII_SET(RTK_MII_CLK); 343 DELAY(1); 344 } 345 goto fail; 346 } 347 348 for (i = 16; i > 0; i--) { 349 MII_CLR(RTK_MII_CLK); 350 DELAY(1); 351 if (!ack) { 352 if (CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN) 353 frame->mii_data |= 1 << (i - 1); 354 DELAY(1); 355 } 356 MII_SET(RTK_MII_CLK); 357 DELAY(1); 358 } 359 360 fail: 361 MII_CLR(RTK_MII_CLK); 362 DELAY(1); 363 MII_SET(RTK_MII_CLK); 364 DELAY(1); 365 366 splx(s); 367 368 if (ack) 369 return 1; 370 return 0; 371 } 372 373 /* 374 * Write to a PHY register through the MII. 375 */ 376 static int 377 rtk_mii_writereg(struct rtk_softc *sc, struct rtk_mii_frame *frame) 378 { 379 int s; 380 381 s = splnet(); 382 /* 383 * Set up frame for TX. 384 */ 385 frame->mii_stdelim = RTK_MII_STARTDELIM; 386 frame->mii_opcode = RTK_MII_WRITEOP; 387 frame->mii_turnaround = RTK_MII_TURNAROUND; 388 389 /* 390 * Turn on data output. 391 */ 392 MII_SET(RTK_MII_DIR); 393 394 rtk_mii_sync(sc); 395 396 rtk_mii_send(sc, frame->mii_stdelim, 2); 397 rtk_mii_send(sc, frame->mii_opcode, 2); 398 rtk_mii_send(sc, frame->mii_phyaddr, 5); 399 rtk_mii_send(sc, frame->mii_regaddr, 5); 400 rtk_mii_send(sc, frame->mii_turnaround, 2); 401 rtk_mii_send(sc, frame->mii_data, 16); 402 403 /* Idle bit. */ 404 MII_SET(RTK_MII_CLK); 405 DELAY(1); 406 MII_CLR(RTK_MII_CLK); 407 DELAY(1); 408 409 /* 410 * Turn off xmit. 411 */ 412 MII_CLR(RTK_MII_DIR); 413 414 splx(s); 415 416 return 0; 417 } 418 419 static int 420 rtk_phy_readreg(device_t self, int phy, int reg) 421 { 422 struct rtk_softc *sc = device_private(self); 423 struct rtk_mii_frame frame; 424 int rval; 425 int rtk8139_reg; 426 427 if ((sc->sc_quirk & RTKQ_8129) == 0) { 428 if (phy != 7) 429 return 0; 430 431 switch (reg) { 432 case MII_BMCR: 433 rtk8139_reg = RTK_BMCR; 434 break; 435 case MII_BMSR: 436 rtk8139_reg = RTK_BMSR; 437 break; 438 case MII_ANAR: 439 rtk8139_reg = RTK_ANAR; 440 break; 441 case MII_ANER: 442 rtk8139_reg = RTK_ANER; 443 break; 444 case MII_ANLPAR: 445 rtk8139_reg = RTK_LPAR; 446 break; 447 default: 448 #if 0 449 printf("%s: bad phy register\n", device_xname(self)); 450 #endif 451 return 0; 452 } 453 rval = CSR_READ_2(sc, rtk8139_reg); 454 return rval; 455 } 456 457 memset(&frame, 0, sizeof(frame)); 458 459 frame.mii_phyaddr = phy; 460 frame.mii_regaddr = reg; 461 rtk_mii_readreg(sc, &frame); 462 463 return frame.mii_data; 464 } 465 466 static void 467 rtk_phy_writereg(device_t self, int phy, int reg, int data) 468 { 469 struct rtk_softc *sc = device_private(self); 470 struct rtk_mii_frame frame; 471 int rtk8139_reg; 472 473 if ((sc->sc_quirk & RTKQ_8129) == 0) { 474 if (phy != 7) 475 return; 476 477 switch (reg) { 478 case MII_BMCR: 479 rtk8139_reg = RTK_BMCR; 480 break; 481 case MII_BMSR: 482 rtk8139_reg = RTK_BMSR; 483 break; 484 case MII_ANAR: 485 rtk8139_reg = RTK_ANAR; 486 break; 487 case MII_ANER: 488 rtk8139_reg = RTK_ANER; 489 break; 490 case MII_ANLPAR: 491 rtk8139_reg = RTK_LPAR; 492 break; 493 default: 494 #if 0 495 printf("%s: bad phy register\n", device_xname(self)); 496 #endif 497 return; 498 } 499 CSR_WRITE_2(sc, rtk8139_reg, data); 500 return; 501 } 502 503 memset(&frame, 0, sizeof(frame)); 504 505 frame.mii_phyaddr = phy; 506 frame.mii_regaddr = reg; 507 frame.mii_data = data; 508 509 rtk_mii_writereg(sc, &frame); 510 } 511 512 static void 513 rtk_phy_statchg(device_t v) 514 { 515 516 /* Nothing to do. */ 517 } 518 519 #define rtk_calchash(addr) \ 520 (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 521 522 /* 523 * Program the 64-bit multicast hash filter. 524 */ 525 void 526 rtk_setmulti(struct rtk_softc *sc) 527 { 528 struct ifnet *ifp; 529 uint32_t hashes[2] = { 0, 0 }; 530 uint32_t rxfilt; 531 struct ether_multi *enm; 532 struct ether_multistep step; 533 int h, mcnt; 534 535 ifp = &sc->ethercom.ec_if; 536 537 rxfilt = CSR_READ_4(sc, RTK_RXCFG); 538 539 if (ifp->if_flags & IFF_PROMISC) { 540 allmulti: 541 ifp->if_flags |= IFF_ALLMULTI; 542 rxfilt |= RTK_RXCFG_RX_MULTI; 543 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt); 544 CSR_WRITE_4(sc, RTK_MAR0, 0xFFFFFFFF); 545 CSR_WRITE_4(sc, RTK_MAR4, 0xFFFFFFFF); 546 return; 547 } 548 549 /* first, zot all the existing hash bits */ 550 CSR_WRITE_4(sc, RTK_MAR0, 0); 551 CSR_WRITE_4(sc, RTK_MAR4, 0); 552 553 /* now program new ones */ 554 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 555 mcnt = 0; 556 while (enm != NULL) { 557 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 558 ETHER_ADDR_LEN) != 0) 559 goto allmulti; 560 561 h = rtk_calchash(enm->enm_addrlo); 562 if (h < 32) 563 hashes[0] |= (1 << h); 564 else 565 hashes[1] |= (1 << (h - 32)); 566 mcnt++; 567 ETHER_NEXT_MULTI(step, enm); 568 } 569 570 ifp->if_flags &= ~IFF_ALLMULTI; 571 572 if (mcnt) 573 rxfilt |= RTK_RXCFG_RX_MULTI; 574 else 575 rxfilt &= ~RTK_RXCFG_RX_MULTI; 576 577 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt); 578 579 /* 580 * For some unfathomable reason, RealTek decided to reverse 581 * the order of the multicast hash registers in the PCI Express 582 * parts. This means we have to write the hash pattern in reverse 583 * order for those devices. 584 */ 585 if ((sc->sc_quirk & RTKQ_PCIE) != 0) { 586 CSR_WRITE_4(sc, RTK_MAR0, bswap32(hashes[1])); 587 CSR_WRITE_4(sc, RTK_MAR4, bswap32(hashes[0])); 588 } else { 589 CSR_WRITE_4(sc, RTK_MAR0, hashes[0]); 590 CSR_WRITE_4(sc, RTK_MAR4, hashes[1]); 591 } 592 } 593 594 void 595 rtk_reset(struct rtk_softc *sc) 596 { 597 int i; 598 599 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 600 601 for (i = 0; i < RTK_TIMEOUT; i++) { 602 DELAY(10); 603 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0) 604 break; 605 } 606 if (i == RTK_TIMEOUT) 607 printf("%s: reset never completed!\n", 608 device_xname(sc->sc_dev)); 609 } 610 611 /* 612 * Attach the interface. Allocate softc structures, do ifmedia 613 * setup and ethernet/BPF attach. 614 */ 615 void 616 rtk_attach(struct rtk_softc *sc) 617 { 618 device_t self = sc->sc_dev; 619 struct ifnet *ifp; 620 struct rtk_tx_desc *txd; 621 uint16_t val; 622 uint8_t eaddr[ETHER_ADDR_LEN]; 623 int error; 624 int i, addr_len; 625 626 callout_init(&sc->rtk_tick_ch, 0); 627 628 /* 629 * Check EEPROM type 9346 or 9356. 630 */ 631 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 632 addr_len = RTK_EEADDR_LEN1; 633 else 634 addr_len = RTK_EEADDR_LEN0; 635 636 /* 637 * Get station address. 638 */ 639 val = rtk_read_eeprom(sc, RTK_EE_EADDR0, addr_len); 640 eaddr[0] = val & 0xff; 641 eaddr[1] = val >> 8; 642 val = rtk_read_eeprom(sc, RTK_EE_EADDR1, addr_len); 643 eaddr[2] = val & 0xff; 644 eaddr[3] = val >> 8; 645 val = rtk_read_eeprom(sc, RTK_EE_EADDR2, addr_len); 646 eaddr[4] = val & 0xff; 647 eaddr[5] = val >> 8; 648 649 if ((error = bus_dmamem_alloc(sc->sc_dmat, 650 RTK_RXBUFLEN + 16, PAGE_SIZE, 0, &sc->sc_dmaseg, 1, &sc->sc_dmanseg, 651 BUS_DMA_NOWAIT)) != 0) { 652 aprint_error_dev(self, 653 "can't allocate recv buffer, error = %d\n", error); 654 goto fail_0; 655 } 656 657 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg, 658 RTK_RXBUFLEN + 16, (void **)&sc->rtk_rx_buf, 659 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 660 aprint_error_dev(self, 661 "can't map recv buffer, error = %d\n", error); 662 goto fail_1; 663 } 664 665 if ((error = bus_dmamap_create(sc->sc_dmat, 666 RTK_RXBUFLEN + 16, 1, RTK_RXBUFLEN + 16, 0, BUS_DMA_NOWAIT, 667 &sc->recv_dmamap)) != 0) { 668 aprint_error_dev(self, 669 "can't create recv buffer DMA map, error = %d\n", error); 670 goto fail_2; 671 } 672 673 if ((error = bus_dmamap_load(sc->sc_dmat, sc->recv_dmamap, 674 sc->rtk_rx_buf, RTK_RXBUFLEN + 16, 675 NULL, BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 676 aprint_error_dev(self, 677 "can't load recv buffer DMA map, error = %d\n", error); 678 goto fail_3; 679 } 680 681 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 682 txd = &sc->rtk_tx_descs[i]; 683 if ((error = bus_dmamap_create(sc->sc_dmat, 684 MCLBYTES, 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 685 &txd->txd_dmamap)) != 0) { 686 aprint_error_dev(self, 687 "can't create snd buffer DMA map, error = %d\n", 688 error); 689 goto fail_4; 690 } 691 txd->txd_txaddr = RTK_TXADDR0 + (i * 4); 692 txd->txd_txstat = RTK_TXSTAT0 + (i * 4); 693 } 694 SIMPLEQ_INIT(&sc->rtk_tx_free); 695 SIMPLEQ_INIT(&sc->rtk_tx_dirty); 696 697 /* 698 * From this point forward, the attachment cannot fail. A failure 699 * before this releases all resources thar may have been 700 * allocated. 701 */ 702 sc->sc_flags |= RTK_ATTACHED; 703 704 /* Reset the adapter. */ 705 rtk_reset(sc); 706 707 aprint_normal_dev(self, "Ethernet address %s\n", ether_sprintf(eaddr)); 708 709 ifp = &sc->ethercom.ec_if; 710 ifp->if_softc = sc; 711 strcpy(ifp->if_xname, device_xname(self)); 712 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 713 ifp->if_ioctl = rtk_ioctl; 714 ifp->if_start = rtk_start; 715 ifp->if_watchdog = rtk_watchdog; 716 ifp->if_init = rtk_init; 717 ifp->if_stop = rtk_stop; 718 IFQ_SET_READY(&ifp->if_snd); 719 720 /* 721 * Do ifmedia setup. 722 */ 723 sc->mii.mii_ifp = ifp; 724 sc->mii.mii_readreg = rtk_phy_readreg; 725 sc->mii.mii_writereg = rtk_phy_writereg; 726 sc->mii.mii_statchg = rtk_phy_statchg; 727 sc->ethercom.ec_mii = &sc->mii; 728 ifmedia_init(&sc->mii.mii_media, IFM_IMASK, ether_mediachange, 729 ether_mediastatus); 730 mii_attach(self, &sc->mii, 0xffffffff, 731 MII_PHY_ANY, MII_OFFSET_ANY, 0); 732 733 /* Choose a default media. */ 734 if (LIST_FIRST(&sc->mii.mii_phys) == NULL) { 735 ifmedia_add(&sc->mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 736 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_NONE); 737 } else { 738 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_AUTO); 739 } 740 741 /* 742 * Call MI attach routines. 743 */ 744 if_attach(ifp); 745 ether_ifattach(ifp, eaddr); 746 747 #if NRND > 0 748 rnd_attach_source(&sc->rnd_source, device_xname(self), 749 RND_TYPE_NET, 0); 750 #endif 751 752 return; 753 fail_4: 754 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 755 txd = &sc->rtk_tx_descs[i]; 756 if (txd->txd_dmamap != NULL) 757 bus_dmamap_destroy(sc->sc_dmat, txd->txd_dmamap); 758 } 759 fail_3: 760 bus_dmamap_destroy(sc->sc_dmat, sc->recv_dmamap); 761 fail_2: 762 bus_dmamem_unmap(sc->sc_dmat, sc->rtk_rx_buf, 763 RTK_RXBUFLEN + 16); 764 fail_1: 765 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg); 766 fail_0: 767 return; 768 } 769 770 /* 771 * Initialize the transmit descriptors. 772 */ 773 static void 774 rtk_list_tx_init(struct rtk_softc *sc) 775 { 776 struct rtk_tx_desc *txd; 777 int i; 778 779 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) 780 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q); 781 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_free)) != NULL) 782 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_free, txd_q); 783 784 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 785 txd = &sc->rtk_tx_descs[i]; 786 CSR_WRITE_4(sc, txd->txd_txaddr, 0); 787 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_free, txd, txd_q); 788 } 789 } 790 791 /* 792 * rtk_activate: 793 * Handle device activation/deactivation requests. 794 */ 795 int 796 rtk_activate(device_t self, enum devact act) 797 { 798 struct rtk_softc *sc = device_private(self); 799 800 switch (act) { 801 case DVACT_DEACTIVATE: 802 if_deactivate(&sc->ethercom.ec_if); 803 return 0; 804 default: 805 return EOPNOTSUPP; 806 } 807 } 808 809 /* 810 * rtk_detach: 811 * Detach a rtk interface. 812 */ 813 int 814 rtk_detach(struct rtk_softc *sc) 815 { 816 struct ifnet *ifp = &sc->ethercom.ec_if; 817 struct rtk_tx_desc *txd; 818 int i; 819 820 /* 821 * Succeed now if there isn't any work to do. 822 */ 823 if ((sc->sc_flags & RTK_ATTACHED) == 0) 824 return 0; 825 826 /* Unhook our tick handler. */ 827 callout_stop(&sc->rtk_tick_ch); 828 829 /* Detach all PHYs. */ 830 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 831 832 /* Delete all remaining media. */ 833 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY); 834 835 #if NRND > 0 836 rnd_detach_source(&sc->rnd_source); 837 #endif 838 839 ether_ifdetach(ifp); 840 if_detach(ifp); 841 842 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 843 txd = &sc->rtk_tx_descs[i]; 844 if (txd->txd_dmamap != NULL) 845 bus_dmamap_destroy(sc->sc_dmat, txd->txd_dmamap); 846 } 847 bus_dmamap_destroy(sc->sc_dmat, sc->recv_dmamap); 848 bus_dmamem_unmap(sc->sc_dmat, sc->rtk_rx_buf, 849 RTK_RXBUFLEN + 16); 850 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg); 851 852 return 0; 853 } 854 855 /* 856 * rtk_enable: 857 * Enable the RTL81X9 chip. 858 */ 859 int 860 rtk_enable(struct rtk_softc *sc) 861 { 862 863 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 864 if ((*sc->sc_enable)(sc) != 0) { 865 printf("%s: device enable failed\n", 866 device_xname(sc->sc_dev)); 867 return EIO; 868 } 869 sc->sc_flags |= RTK_ENABLED; 870 } 871 return 0; 872 } 873 874 /* 875 * rtk_disable: 876 * Disable the RTL81X9 chip. 877 */ 878 void 879 rtk_disable(struct rtk_softc *sc) 880 { 881 882 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 883 (*sc->sc_disable)(sc); 884 sc->sc_flags &= ~RTK_ENABLED; 885 } 886 } 887 888 /* 889 * A frame has been uploaded: pass the resulting mbuf chain up to 890 * the higher level protocols. 891 * 892 * You know there's something wrong with a PCI bus-master chip design. 893 * 894 * The receive operation is badly documented in the datasheet, so I'll 895 * attempt to document it here. The driver provides a buffer area and 896 * places its base address in the RX buffer start address register. 897 * The chip then begins copying frames into the RX buffer. Each frame 898 * is preceded by a 32-bit RX status word which specifies the length 899 * of the frame and certain other status bits. Each frame (starting with 900 * the status word) is also 32-bit aligned. The frame length is in the 901 * first 16 bits of the status word; the lower 15 bits correspond with 902 * the 'rx status register' mentioned in the datasheet. 903 * 904 * Note: to make the Alpha happy, the frame payload needs to be aligned 905 * on a 32-bit boundary. To achieve this, we copy the data to mbuf 906 * shifted forward 2 bytes. 907 */ 908 static void 909 rtk_rxeof(struct rtk_softc *sc) 910 { 911 struct mbuf *m; 912 struct ifnet *ifp; 913 uint8_t *rxbufpos, *dst; 914 u_int total_len, wrap; 915 uint32_t rxstat; 916 uint16_t cur_rx, new_rx; 917 uint16_t limit; 918 uint16_t rx_bytes, max_bytes; 919 920 ifp = &sc->ethercom.ec_if; 921 922 cur_rx = (CSR_READ_2(sc, RTK_CURRXADDR) + 16) % RTK_RXBUFLEN; 923 924 /* Do not try to read past this point. */ 925 limit = CSR_READ_2(sc, RTK_CURRXBUF) % RTK_RXBUFLEN; 926 927 if (limit < cur_rx) 928 max_bytes = (RTK_RXBUFLEN - cur_rx) + limit; 929 else 930 max_bytes = limit - cur_rx; 931 rx_bytes = 0; 932 933 while ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_EMPTY_RXBUF) == 0) { 934 rxbufpos = sc->rtk_rx_buf + cur_rx; 935 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 936 RTK_RXSTAT_LEN, BUS_DMASYNC_POSTREAD); 937 rxstat = le32toh(*(uint32_t *)rxbufpos); 938 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 939 RTK_RXSTAT_LEN, BUS_DMASYNC_PREREAD); 940 941 /* 942 * Here's a totally undocumented fact for you. When the 943 * RealTek chip is in the process of copying a packet into 944 * RAM for you, the length will be 0xfff0. If you spot a 945 * packet header with this value, you need to stop. The 946 * datasheet makes absolutely no mention of this and 947 * RealTek should be shot for this. 948 */ 949 total_len = rxstat >> 16; 950 if (total_len == RTK_RXSTAT_UNFINISHED) 951 break; 952 953 if ((rxstat & RTK_RXSTAT_RXOK) == 0 || 954 total_len < ETHER_MIN_LEN || 955 total_len > (MCLBYTES - RTK_ETHER_ALIGN)) { 956 ifp->if_ierrors++; 957 958 /* 959 * submitted by:[netbsd-pcmcia:00484] 960 * Takahiro Kambe <taca@sky.yamashina.kyoto.jp> 961 * obtain from: 962 * FreeBSD if_rl.c rev 1.24->1.25 963 * 964 */ 965 #if 0 966 if (rxstat & (RTK_RXSTAT_BADSYM|RTK_RXSTAT_RUNT| 967 RTK_RXSTAT_GIANT|RTK_RXSTAT_CRCERR| 968 RTK_RXSTAT_ALIGNERR)) { 969 CSR_WRITE_2(sc, RTK_COMMAND, RTK_CMD_TX_ENB); 970 CSR_WRITE_2(sc, RTK_COMMAND, 971 RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 972 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG); 973 CSR_WRITE_4(sc, RTK_RXADDR, 974 sc->recv_dmamap->dm_segs[0].ds_addr); 975 cur_rx = 0; 976 } 977 break; 978 #else 979 rtk_init(ifp); 980 return; 981 #endif 982 } 983 984 /* No errors; receive the packet. */ 985 rx_bytes += total_len + RTK_RXSTAT_LEN; 986 987 /* 988 * Avoid trying to read more bytes than we know 989 * the chip has prepared for us. 990 */ 991 if (rx_bytes > max_bytes) 992 break; 993 994 /* 995 * Skip the status word, wrapping around to the beginning 996 * of the Rx area, if necessary. 997 */ 998 cur_rx = (cur_rx + RTK_RXSTAT_LEN) % RTK_RXBUFLEN; 999 rxbufpos = sc->rtk_rx_buf + cur_rx; 1000 1001 /* 1002 * Compute the number of bytes at which the packet 1003 * will wrap to the beginning of the ring buffer. 1004 */ 1005 wrap = RTK_RXBUFLEN - cur_rx; 1006 1007 /* 1008 * Compute where the next pending packet is. 1009 */ 1010 if (total_len > wrap) 1011 new_rx = total_len - wrap; 1012 else 1013 new_rx = cur_rx + total_len; 1014 /* Round up to 32-bit boundary. */ 1015 new_rx = roundup2(new_rx, sizeof(uint32_t)) % RTK_RXBUFLEN; 1016 1017 /* 1018 * The RealTek chip includes the CRC with every 1019 * incoming packet; trim it off here. 1020 */ 1021 total_len -= ETHER_CRC_LEN; 1022 1023 /* 1024 * Now allocate an mbuf (and possibly a cluster) to hold 1025 * the packet. Note we offset the packet 2 bytes so that 1026 * data after the Ethernet header will be 4-byte aligned. 1027 */ 1028 MGETHDR(m, M_DONTWAIT, MT_DATA); 1029 if (m == NULL) { 1030 printf("%s: unable to allocate Rx mbuf\n", 1031 device_xname(sc->sc_dev)); 1032 ifp->if_ierrors++; 1033 goto next_packet; 1034 } 1035 if (total_len > (MHLEN - RTK_ETHER_ALIGN)) { 1036 MCLGET(m, M_DONTWAIT); 1037 if ((m->m_flags & M_EXT) == 0) { 1038 printf("%s: unable to allocate Rx cluster\n", 1039 device_xname(sc->sc_dev)); 1040 ifp->if_ierrors++; 1041 m_freem(m); 1042 m = NULL; 1043 goto next_packet; 1044 } 1045 } 1046 m->m_data += RTK_ETHER_ALIGN; /* for alignment */ 1047 m->m_pkthdr.rcvif = ifp; 1048 m->m_pkthdr.len = m->m_len = total_len; 1049 dst = mtod(m, void *); 1050 1051 /* 1052 * If the packet wraps, copy up to the wrapping point. 1053 */ 1054 if (total_len > wrap) { 1055 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1056 cur_rx, wrap, BUS_DMASYNC_POSTREAD); 1057 memcpy(dst, rxbufpos, wrap); 1058 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1059 cur_rx, wrap, BUS_DMASYNC_PREREAD); 1060 cur_rx = 0; 1061 rxbufpos = sc->rtk_rx_buf; 1062 total_len -= wrap; 1063 dst += wrap; 1064 } 1065 1066 /* 1067 * ...and now the rest. 1068 */ 1069 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1070 cur_rx, total_len, BUS_DMASYNC_POSTREAD); 1071 memcpy(dst, rxbufpos, total_len); 1072 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1073 cur_rx, total_len, BUS_DMASYNC_PREREAD); 1074 1075 next_packet: 1076 CSR_WRITE_2(sc, RTK_CURRXADDR, (new_rx - 16) % RTK_RXBUFLEN); 1077 cur_rx = new_rx; 1078 1079 if (m == NULL) 1080 continue; 1081 1082 ifp->if_ipackets++; 1083 1084 bpf_mtap(ifp, m); 1085 /* pass it on. */ 1086 (*ifp->if_input)(ifp, m); 1087 } 1088 } 1089 1090 /* 1091 * A frame was downloaded to the chip. It's safe for us to clean up 1092 * the list buffers. 1093 */ 1094 static void 1095 rtk_txeof(struct rtk_softc *sc) 1096 { 1097 struct ifnet *ifp; 1098 struct rtk_tx_desc *txd; 1099 uint32_t txstat; 1100 1101 ifp = &sc->ethercom.ec_if; 1102 1103 /* 1104 * Go through our tx list and free mbufs for those 1105 * frames that have been uploaded. 1106 */ 1107 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) { 1108 txstat = CSR_READ_4(sc, txd->txd_txstat); 1109 if ((txstat & (RTK_TXSTAT_TX_OK| 1110 RTK_TXSTAT_TX_UNDERRUN|RTK_TXSTAT_TXABRT)) == 0) 1111 break; 1112 1113 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q); 1114 1115 bus_dmamap_sync(sc->sc_dmat, txd->txd_dmamap, 0, 1116 txd->txd_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1117 bus_dmamap_unload(sc->sc_dmat, txd->txd_dmamap); 1118 m_freem(txd->txd_mbuf); 1119 txd->txd_mbuf = NULL; 1120 1121 ifp->if_collisions += (txstat & RTK_TXSTAT_COLLCNT) >> 24; 1122 1123 if (txstat & RTK_TXSTAT_TX_OK) 1124 ifp->if_opackets++; 1125 else { 1126 ifp->if_oerrors++; 1127 1128 /* 1129 * Increase Early TX threshold if underrun occurred. 1130 * Increase step 64 bytes. 1131 */ 1132 if (txstat & RTK_TXSTAT_TX_UNDERRUN) { 1133 #ifdef DEBUG 1134 printf("%s: transmit underrun;", 1135 device_xname(sc->sc_dev)); 1136 #endif 1137 if (sc->sc_txthresh < RTK_TXTH_MAX) { 1138 sc->sc_txthresh += 2; 1139 #ifdef DEBUG 1140 printf(" new threshold: %d bytes", 1141 sc->sc_txthresh * 32); 1142 #endif 1143 } 1144 #ifdef DEBUG 1145 printf("\n"); 1146 #endif 1147 } 1148 if (txstat & (RTK_TXSTAT_TXABRT|RTK_TXSTAT_OUTOFWIN)) 1149 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG); 1150 } 1151 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_free, txd, txd_q); 1152 ifp->if_flags &= ~IFF_OACTIVE; 1153 } 1154 1155 /* Clear the timeout timer if there is no pending packet. */ 1156 if (SIMPLEQ_EMPTY(&sc->rtk_tx_dirty)) 1157 ifp->if_timer = 0; 1158 1159 } 1160 1161 int 1162 rtk_intr(void *arg) 1163 { 1164 struct rtk_softc *sc; 1165 struct ifnet *ifp; 1166 uint16_t status; 1167 int handled; 1168 1169 sc = arg; 1170 ifp = &sc->ethercom.ec_if; 1171 1172 if (!device_has_power(sc->sc_dev)) 1173 return 0; 1174 1175 /* Disable interrupts. */ 1176 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1177 1178 handled = 0; 1179 for (;;) { 1180 1181 status = CSR_READ_2(sc, RTK_ISR); 1182 1183 if (status == 0xffff) 1184 break; /* Card is gone... */ 1185 1186 if (status) 1187 CSR_WRITE_2(sc, RTK_ISR, status); 1188 1189 if ((status & RTK_INTRS) == 0) 1190 break; 1191 1192 handled = 1; 1193 1194 if (status & RTK_ISR_RX_OK) 1195 rtk_rxeof(sc); 1196 1197 if (status & RTK_ISR_RX_ERR) 1198 rtk_rxeof(sc); 1199 1200 if (status & (RTK_ISR_TX_OK|RTK_ISR_TX_ERR)) 1201 rtk_txeof(sc); 1202 1203 if (status & RTK_ISR_SYSTEM_ERR) { 1204 rtk_reset(sc); 1205 rtk_init(ifp); 1206 } 1207 } 1208 1209 /* Re-enable interrupts. */ 1210 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS); 1211 1212 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 1213 rtk_start(ifp); 1214 1215 #if NRND > 0 1216 if (RND_ENABLED(&sc->rnd_source)) 1217 rnd_add_uint32(&sc->rnd_source, status); 1218 #endif 1219 1220 return handled; 1221 } 1222 1223 /* 1224 * Main transmit routine. 1225 */ 1226 1227 static void 1228 rtk_start(struct ifnet *ifp) 1229 { 1230 struct rtk_softc *sc; 1231 struct rtk_tx_desc *txd; 1232 struct mbuf *m_head, *m_new; 1233 int error, len; 1234 1235 sc = ifp->if_softc; 1236 1237 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_free)) != NULL) { 1238 IFQ_POLL(&ifp->if_snd, m_head); 1239 if (m_head == NULL) 1240 break; 1241 m_new = NULL; 1242 1243 /* 1244 * Load the DMA map. If this fails, the packet didn't 1245 * fit in one DMA segment, and we need to copy. Note, 1246 * the packet must also be aligned. 1247 * if the packet is too small, copy it too, so we're sure 1248 * so have enough room for the pad buffer. 1249 */ 1250 if ((mtod(m_head, uintptr_t) & 3) != 0 || 1251 m_head->m_pkthdr.len < ETHER_PAD_LEN || 1252 bus_dmamap_load_mbuf(sc->sc_dmat, txd->txd_dmamap, 1253 m_head, BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1254 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1255 if (m_new == NULL) { 1256 printf("%s: unable to allocate Tx mbuf\n", 1257 device_xname(sc->sc_dev)); 1258 break; 1259 } 1260 if (m_head->m_pkthdr.len > MHLEN) { 1261 MCLGET(m_new, M_DONTWAIT); 1262 if ((m_new->m_flags & M_EXT) == 0) { 1263 printf("%s: unable to allocate Tx " 1264 "cluster\n", 1265 device_xname(sc->sc_dev)); 1266 m_freem(m_new); 1267 break; 1268 } 1269 } 1270 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1271 mtod(m_new, void *)); 1272 m_new->m_pkthdr.len = m_new->m_len = 1273 m_head->m_pkthdr.len; 1274 if (m_head->m_pkthdr.len < ETHER_PAD_LEN) { 1275 memset( 1276 mtod(m_new, char *) + m_head->m_pkthdr.len, 1277 0, ETHER_PAD_LEN - m_head->m_pkthdr.len); 1278 m_new->m_pkthdr.len = m_new->m_len = 1279 ETHER_PAD_LEN; 1280 } 1281 error = bus_dmamap_load_mbuf(sc->sc_dmat, 1282 txd->txd_dmamap, m_new, 1283 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1284 if (error) { 1285 printf("%s: unable to load Tx buffer, " 1286 "error = %d\n", 1287 device_xname(sc->sc_dev), error); 1288 break; 1289 } 1290 } 1291 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1292 /* 1293 * If there's a BPF listener, bounce a copy of this frame 1294 * to him. 1295 */ 1296 bpf_mtap(ifp, m_head); 1297 if (m_new != NULL) { 1298 m_freem(m_head); 1299 m_head = m_new; 1300 } 1301 txd->txd_mbuf = m_head; 1302 1303 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_free, txd_q); 1304 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_dirty, txd, txd_q); 1305 1306 /* 1307 * Transmit the frame. 1308 */ 1309 bus_dmamap_sync(sc->sc_dmat, 1310 txd->txd_dmamap, 0, txd->txd_dmamap->dm_mapsize, 1311 BUS_DMASYNC_PREWRITE); 1312 1313 len = txd->txd_dmamap->dm_segs[0].ds_len; 1314 1315 CSR_WRITE_4(sc, txd->txd_txaddr, 1316 txd->txd_dmamap->dm_segs[0].ds_addr); 1317 CSR_WRITE_4(sc, txd->txd_txstat, 1318 RTK_TXSTAT_THRESH(sc->sc_txthresh) | len); 1319 1320 /* 1321 * Set a timeout in case the chip goes out to lunch. 1322 */ 1323 ifp->if_timer = 5; 1324 } 1325 1326 /* 1327 * We broke out of the loop because all our TX slots are 1328 * full. Mark the NIC as busy until it drains some of the 1329 * packets from the queue. 1330 */ 1331 if (SIMPLEQ_EMPTY(&sc->rtk_tx_free)) 1332 ifp->if_flags |= IFF_OACTIVE; 1333 } 1334 1335 static int 1336 rtk_init(struct ifnet *ifp) 1337 { 1338 struct rtk_softc *sc = ifp->if_softc; 1339 int error, i; 1340 uint32_t rxcfg; 1341 1342 if ((error = rtk_enable(sc)) != 0) 1343 goto out; 1344 1345 /* 1346 * Cancel pending I/O. 1347 */ 1348 rtk_stop(ifp, 0); 1349 1350 /* Init our MAC address */ 1351 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1352 CSR_WRITE_1(sc, RTK_IDR0 + i, CLLADDR(ifp->if_sadl)[i]); 1353 } 1354 1355 /* Init the RX buffer pointer register. */ 1356 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 0, 1357 sc->recv_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1358 CSR_WRITE_4(sc, RTK_RXADDR, sc->recv_dmamap->dm_segs[0].ds_addr); 1359 1360 /* Init TX descriptors. */ 1361 rtk_list_tx_init(sc); 1362 1363 /* Init Early TX threshold. */ 1364 sc->sc_txthresh = RTK_TXTH_256; 1365 /* 1366 * Enable transmit and receive. 1367 */ 1368 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1369 1370 /* 1371 * Set the initial TX and RX configuration. 1372 */ 1373 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG); 1374 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG); 1375 1376 /* Set the individual bit to receive frames for this host only. */ 1377 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 1378 rxcfg |= RTK_RXCFG_RX_INDIV; 1379 1380 /* If we want promiscuous mode, set the allframes bit. */ 1381 if (ifp->if_flags & IFF_PROMISC) { 1382 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 1383 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1384 } else { 1385 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 1386 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1387 } 1388 1389 /* 1390 * Set capture broadcast bit to capture broadcast frames. 1391 */ 1392 if (ifp->if_flags & IFF_BROADCAST) { 1393 rxcfg |= RTK_RXCFG_RX_BROAD; 1394 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1395 } else { 1396 rxcfg &= ~RTK_RXCFG_RX_BROAD; 1397 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1398 } 1399 1400 /* 1401 * Program the multicast filter, if necessary. 1402 */ 1403 rtk_setmulti(sc); 1404 1405 /* 1406 * Enable interrupts. 1407 */ 1408 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS); 1409 1410 /* Start RX/TX process. */ 1411 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 1412 1413 /* Enable receiver and transmitter. */ 1414 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1415 1416 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD|RTK_CFG1_FULLDUPLEX); 1417 1418 /* 1419 * Set current media. 1420 */ 1421 if ((error = ether_mediachange(ifp)) != 0) 1422 goto out; 1423 1424 ifp->if_flags |= IFF_RUNNING; 1425 ifp->if_flags &= ~IFF_OACTIVE; 1426 1427 callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc); 1428 1429 out: 1430 if (error) { 1431 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1432 ifp->if_timer = 0; 1433 printf("%s: interface not running\n", device_xname(sc->sc_dev)); 1434 } 1435 return error; 1436 } 1437 1438 static int 1439 rtk_ioctl(struct ifnet *ifp, u_long command, void *data) 1440 { 1441 struct rtk_softc *sc = ifp->if_softc; 1442 int s, error; 1443 1444 s = splnet(); 1445 error = ether_ioctl(ifp, command, data); 1446 if (error == ENETRESET) { 1447 if (ifp->if_flags & IFF_RUNNING) { 1448 /* 1449 * Multicast list has changed. Set the 1450 * hardware filter accordingly. 1451 */ 1452 rtk_setmulti(sc); 1453 } 1454 error = 0; 1455 } 1456 splx(s); 1457 1458 return error; 1459 } 1460 1461 static void 1462 rtk_watchdog(struct ifnet *ifp) 1463 { 1464 struct rtk_softc *sc; 1465 1466 sc = ifp->if_softc; 1467 1468 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1469 ifp->if_oerrors++; 1470 rtk_txeof(sc); 1471 rtk_rxeof(sc); 1472 rtk_init(ifp); 1473 } 1474 1475 /* 1476 * Stop the adapter and free any mbufs allocated to the 1477 * RX and TX lists. 1478 */ 1479 static void 1480 rtk_stop(struct ifnet *ifp, int disable) 1481 { 1482 struct rtk_softc *sc = ifp->if_softc; 1483 struct rtk_tx_desc *txd; 1484 1485 callout_stop(&sc->rtk_tick_ch); 1486 1487 mii_down(&sc->mii); 1488 1489 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 1490 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1491 1492 /* 1493 * Free the TX list buffers. 1494 */ 1495 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) { 1496 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q); 1497 bus_dmamap_unload(sc->sc_dmat, txd->txd_dmamap); 1498 m_freem(txd->txd_mbuf); 1499 txd->txd_mbuf = NULL; 1500 CSR_WRITE_4(sc, txd->txd_txaddr, 0); 1501 } 1502 1503 if (disable) 1504 rtk_disable(sc); 1505 1506 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1507 ifp->if_timer = 0; 1508 } 1509 1510 static void 1511 rtk_tick(void *arg) 1512 { 1513 struct rtk_softc *sc = arg; 1514 int s; 1515 1516 s = splnet(); 1517 mii_tick(&sc->mii); 1518 splx(s); 1519 1520 callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc); 1521 } 1522