1 /* $NetBSD: rtl81x9.c,v 1.52 2005/12/08 18:06:42 xtraeme Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_rl.c,v 1.17 1999/06/19 20:17:37 wpaul Exp 35 */ 36 37 /* 38 * RealTek 8129/8139 PCI NIC driver 39 * 40 * Supports several extremely cheap PCI 10/100 adapters based on 41 * the RealTek chipset. Datasheets can be obtained from 42 * www.realtek.com.tw. 43 * 44 * Written by Bill Paul <wpaul@ctr.columbia.edu> 45 * Electrical Engineering Department 46 * Columbia University, New York City 47 */ 48 49 /* 50 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 51 * probably the worst PCI ethernet controller ever made, with the possible 52 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 53 * DMA, but it has a terrible interface that nullifies any performance 54 * gains that bus-master DMA usually offers. 55 * 56 * For transmission, the chip offers a series of four TX descriptor 57 * registers. Each transmit frame must be in a contiguous buffer, aligned 58 * on a longword (32-bit) boundary. This means we almost always have to 59 * do mbuf copies in order to transmit a frame, except in the unlikely 60 * case where a) the packet fits into a single mbuf, and b) the packet 61 * is 32-bit aligned within the mbuf's data area. The presence of only 62 * four descriptor registers means that we can never have more than four 63 * packets queued for transmission at any one time. 64 * 65 * Reception is not much better. The driver has to allocate a single large 66 * buffer area (up to 64K in size) into which the chip will DMA received 67 * frames. Because we don't know where within this region received packets 68 * will begin or end, we have no choice but to copy data from the buffer 69 * area into mbufs in order to pass the packets up to the higher protocol 70 * levels. 71 * 72 * It's impossible given this rotten design to really achieve decent 73 * performance at 100Mbps, unless you happen to have a 400MHz PII or 74 * some equally overmuscled CPU to drive it. 75 * 76 * On the bright side, the 8139 does have a built-in PHY, although 77 * rather than using an MDIO serial interface like most other NICs, the 78 * PHY registers are directly accessible through the 8139's register 79 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 80 * filter. 81 * 82 * The 8129 chip is an older version of the 8139 that uses an external PHY 83 * chip. The 8129 has a serial MDIO interface for accessing the MII where 84 * the 8139 lets you directly access the on-board PHY registers. We need 85 * to select which interface to use depending on the chip type. 86 */ 87 88 #include <sys/cdefs.h> 89 __KERNEL_RCSID(0, "$NetBSD: rtl81x9.c,v 1.52 2005/12/08 18:06:42 xtraeme Exp $"); 90 91 #include "bpfilter.h" 92 #include "rnd.h" 93 94 #include <sys/param.h> 95 #include <sys/systm.h> 96 #include <sys/callout.h> 97 #include <sys/device.h> 98 #include <sys/sockio.h> 99 #include <sys/mbuf.h> 100 #include <sys/malloc.h> 101 #include <sys/kernel.h> 102 #include <sys/socket.h> 103 104 #include <uvm/uvm_extern.h> 105 106 #include <net/if.h> 107 #include <net/if_arp.h> 108 #include <net/if_ether.h> 109 #include <net/if_dl.h> 110 #include <net/if_media.h> 111 112 #if NBPFILTER > 0 113 #include <net/bpf.h> 114 #endif 115 #if NRND > 0 116 #include <sys/rnd.h> 117 #endif 118 119 #include <machine/bus.h> 120 #include <machine/endian.h> 121 122 #include <dev/mii/mii.h> 123 #include <dev/mii/miivar.h> 124 125 #include <dev/ic/rtl81x9reg.h> 126 #include <dev/ic/rtl81x9var.h> 127 128 #if defined(DEBUG) 129 #define STATIC 130 #else 131 #define STATIC static 132 #endif 133 134 STATIC void rtk_reset (struct rtk_softc *); 135 STATIC void rtk_rxeof (struct rtk_softc *); 136 STATIC void rtk_txeof (struct rtk_softc *); 137 STATIC void rtk_start (struct ifnet *); 138 STATIC int rtk_ioctl (struct ifnet *, u_long, caddr_t); 139 STATIC int rtk_init (struct ifnet *); 140 STATIC void rtk_stop (struct ifnet *, int); 141 142 STATIC void rtk_watchdog(struct ifnet *); 143 STATIC void rtk_shutdown(void *); 144 STATIC int rtk_ifmedia_upd(struct ifnet *); 145 STATIC void rtk_ifmedia_sts(struct ifnet *, struct ifmediareq *); 146 147 STATIC void rtk_eeprom_putbyte(struct rtk_softc *, int, int); 148 STATIC void rtk_mii_sync(struct rtk_softc *); 149 STATIC void rtk_mii_send(struct rtk_softc *, u_int32_t, int); 150 STATIC int rtk_mii_readreg(struct rtk_softc *, struct rtk_mii_frame *); 151 STATIC int rtk_mii_writereg(struct rtk_softc *, struct rtk_mii_frame *); 152 153 STATIC int rtk_phy_readreg(struct device *, int, int); 154 STATIC void rtk_phy_writereg(struct device *, int, int, int); 155 STATIC void rtk_phy_statchg(struct device *); 156 STATIC void rtk_tick (void *); 157 158 STATIC int rtk_enable (struct rtk_softc *); 159 STATIC void rtk_disable (struct rtk_softc *); 160 STATIC void rtk_power (int, void *); 161 162 STATIC int rtk_list_tx_init(struct rtk_softc *); 163 164 #define EE_SET(x) \ 165 CSR_WRITE_1(sc, RTK_EECMD, \ 166 CSR_READ_1(sc, RTK_EECMD) | (x)) 167 168 #define EE_CLR(x) \ 169 CSR_WRITE_1(sc, RTK_EECMD, \ 170 CSR_READ_1(sc, RTK_EECMD) & ~(x)) 171 172 #define ETHER_PAD_LEN (ETHER_MIN_LEN - ETHER_CRC_LEN) 173 174 /* 175 * Send a read command and address to the EEPROM, check for ACK. 176 */ 177 STATIC void 178 rtk_eeprom_putbyte(sc, addr, addr_len) 179 struct rtk_softc *sc; 180 int addr, addr_len; 181 { 182 int d, i; 183 184 d = (RTK_EECMD_READ << addr_len) | addr; 185 186 /* 187 * Feed in each bit and stobe the clock. 188 */ 189 for (i = RTK_EECMD_LEN + addr_len; i > 0; i--) { 190 if (d & (1 << (i - 1))) { 191 EE_SET(RTK_EE_DATAIN); 192 } else { 193 EE_CLR(RTK_EE_DATAIN); 194 } 195 DELAY(4); 196 EE_SET(RTK_EE_CLK); 197 DELAY(4); 198 EE_CLR(RTK_EE_CLK); 199 DELAY(4); 200 } 201 } 202 203 /* 204 * Read a word of data stored in the EEPROM at address 'addr.' 205 */ 206 u_int16_t 207 rtk_read_eeprom(sc, addr, addr_len) 208 struct rtk_softc *sc; 209 int addr, addr_len; 210 { 211 u_int16_t word = 0; 212 int i; 213 214 /* Enter EEPROM access mode. */ 215 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_PROGRAM|RTK_EE_SEL); 216 217 /* 218 * Send address of word we want to read. 219 */ 220 rtk_eeprom_putbyte(sc, addr, addr_len); 221 222 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_PROGRAM|RTK_EE_SEL); 223 224 /* 225 * Start reading bits from EEPROM. 226 */ 227 for (i = 16; i > 0; i--) { 228 EE_SET(RTK_EE_CLK); 229 DELAY(4); 230 if (CSR_READ_1(sc, RTK_EECMD) & RTK_EE_DATAOUT) 231 word |= 1 << (i - 1); 232 EE_CLR(RTK_EE_CLK); 233 DELAY(4); 234 } 235 236 /* Turn off EEPROM access mode. */ 237 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 238 239 return (word); 240 } 241 242 /* 243 * MII access routines are provided for the 8129, which 244 * doesn't have a built-in PHY. For the 8139, we fake things 245 * up by diverting rtk_phy_readreg()/rtk_phy_writereg() to the 246 * direct access PHY registers. 247 */ 248 #define MII_SET(x) \ 249 CSR_WRITE_1(sc, RTK_MII, \ 250 CSR_READ_1(sc, RTK_MII) | (x)) 251 252 #define MII_CLR(x) \ 253 CSR_WRITE_1(sc, RTK_MII, \ 254 CSR_READ_1(sc, RTK_MII) & ~(x)) 255 256 /* 257 * Sync the PHYs by setting data bit and strobing the clock 32 times. 258 */ 259 STATIC void 260 rtk_mii_sync(sc) 261 struct rtk_softc *sc; 262 { 263 int i; 264 265 MII_SET(RTK_MII_DIR|RTK_MII_DATAOUT); 266 267 for (i = 0; i < 32; i++) { 268 MII_SET(RTK_MII_CLK); 269 DELAY(1); 270 MII_CLR(RTK_MII_CLK); 271 DELAY(1); 272 } 273 } 274 275 /* 276 * Clock a series of bits through the MII. 277 */ 278 STATIC void 279 rtk_mii_send(sc, bits, cnt) 280 struct rtk_softc *sc; 281 u_int32_t bits; 282 int cnt; 283 { 284 int i; 285 286 MII_CLR(RTK_MII_CLK); 287 288 for (i = cnt; i > 0; i--) { 289 if (bits & (1 << (i - 1))) { 290 MII_SET(RTK_MII_DATAOUT); 291 } else { 292 MII_CLR(RTK_MII_DATAOUT); 293 } 294 DELAY(1); 295 MII_CLR(RTK_MII_CLK); 296 DELAY(1); 297 MII_SET(RTK_MII_CLK); 298 } 299 } 300 301 /* 302 * Read an PHY register through the MII. 303 */ 304 STATIC int 305 rtk_mii_readreg(sc, frame) 306 struct rtk_softc *sc; 307 struct rtk_mii_frame *frame; 308 { 309 int i, ack, s; 310 311 s = splnet(); 312 313 /* 314 * Set up frame for RX. 315 */ 316 frame->mii_stdelim = RTK_MII_STARTDELIM; 317 frame->mii_opcode = RTK_MII_READOP; 318 frame->mii_turnaround = 0; 319 frame->mii_data = 0; 320 321 CSR_WRITE_2(sc, RTK_MII, 0); 322 323 /* 324 * Turn on data xmit. 325 */ 326 MII_SET(RTK_MII_DIR); 327 328 rtk_mii_sync(sc); 329 330 /* 331 * Send command/address info. 332 */ 333 rtk_mii_send(sc, frame->mii_stdelim, 2); 334 rtk_mii_send(sc, frame->mii_opcode, 2); 335 rtk_mii_send(sc, frame->mii_phyaddr, 5); 336 rtk_mii_send(sc, frame->mii_regaddr, 5); 337 338 /* Idle bit */ 339 MII_CLR((RTK_MII_CLK|RTK_MII_DATAOUT)); 340 DELAY(1); 341 MII_SET(RTK_MII_CLK); 342 DELAY(1); 343 344 /* Turn off xmit. */ 345 MII_CLR(RTK_MII_DIR); 346 347 /* Check for ack */ 348 MII_CLR(RTK_MII_CLK); 349 DELAY(1); 350 MII_SET(RTK_MII_CLK); 351 DELAY(1); 352 ack = CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN; 353 354 /* 355 * Now try reading data bits. If the ack failed, we still 356 * need to clock through 16 cycles to keep the PHY(s) in sync. 357 */ 358 if (ack) { 359 for (i = 0; i < 16; i++) { 360 MII_CLR(RTK_MII_CLK); 361 DELAY(1); 362 MII_SET(RTK_MII_CLK); 363 DELAY(1); 364 } 365 goto fail; 366 } 367 368 for (i = 16; i > 0; i--) { 369 MII_CLR(RTK_MII_CLK); 370 DELAY(1); 371 if (!ack) { 372 if (CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN) 373 frame->mii_data |= 1 << (i - 1); 374 DELAY(1); 375 } 376 MII_SET(RTK_MII_CLK); 377 DELAY(1); 378 } 379 380 fail: 381 MII_CLR(RTK_MII_CLK); 382 DELAY(1); 383 MII_SET(RTK_MII_CLK); 384 DELAY(1); 385 386 splx(s); 387 388 if (ack) 389 return (1); 390 return (0); 391 } 392 393 /* 394 * Write to a PHY register through the MII. 395 */ 396 STATIC int 397 rtk_mii_writereg(sc, frame) 398 struct rtk_softc *sc; 399 struct rtk_mii_frame *frame; 400 { 401 int s; 402 403 s = splnet(); 404 /* 405 * Set up frame for TX. 406 */ 407 frame->mii_stdelim = RTK_MII_STARTDELIM; 408 frame->mii_opcode = RTK_MII_WRITEOP; 409 frame->mii_turnaround = RTK_MII_TURNAROUND; 410 411 /* 412 * Turn on data output. 413 */ 414 MII_SET(RTK_MII_DIR); 415 416 rtk_mii_sync(sc); 417 418 rtk_mii_send(sc, frame->mii_stdelim, 2); 419 rtk_mii_send(sc, frame->mii_opcode, 2); 420 rtk_mii_send(sc, frame->mii_phyaddr, 5); 421 rtk_mii_send(sc, frame->mii_regaddr, 5); 422 rtk_mii_send(sc, frame->mii_turnaround, 2); 423 rtk_mii_send(sc, frame->mii_data, 16); 424 425 /* Idle bit. */ 426 MII_SET(RTK_MII_CLK); 427 DELAY(1); 428 MII_CLR(RTK_MII_CLK); 429 DELAY(1); 430 431 /* 432 * Turn off xmit. 433 */ 434 MII_CLR(RTK_MII_DIR); 435 436 splx(s); 437 438 return (0); 439 } 440 441 STATIC int 442 rtk_phy_readreg(self, phy, reg) 443 struct device *self; 444 int phy, reg; 445 { 446 struct rtk_softc *sc = (void *)self; 447 struct rtk_mii_frame frame; 448 int rval = 0; 449 int rtk8139_reg = 0; 450 451 if (sc->rtk_type == RTK_8139) { 452 if (phy != 7) 453 return (0); 454 455 switch(reg) { 456 case MII_BMCR: 457 rtk8139_reg = RTK_BMCR; 458 break; 459 case MII_BMSR: 460 rtk8139_reg = RTK_BMSR; 461 break; 462 case MII_ANAR: 463 rtk8139_reg = RTK_ANAR; 464 break; 465 case MII_ANER: 466 rtk8139_reg = RTK_ANER; 467 break; 468 case MII_ANLPAR: 469 rtk8139_reg = RTK_LPAR; 470 break; 471 default: 472 #if 0 473 printf("%s: bad phy register\n", sc->sc_dev.dv_xname); 474 #endif 475 return (0); 476 } 477 rval = CSR_READ_2(sc, rtk8139_reg); 478 return (rval); 479 } 480 481 memset((char *)&frame, 0, sizeof(frame)); 482 483 frame.mii_phyaddr = phy; 484 frame.mii_regaddr = reg; 485 rtk_mii_readreg(sc, &frame); 486 487 return (frame.mii_data); 488 } 489 490 STATIC void rtk_phy_writereg(self, phy, reg, data) 491 struct device *self; 492 int phy, reg; 493 int data; 494 { 495 struct rtk_softc *sc = (void *)self; 496 struct rtk_mii_frame frame; 497 int rtk8139_reg = 0; 498 499 if (sc->rtk_type == RTK_8139) { 500 if (phy != 7) 501 return; 502 503 switch(reg) { 504 case MII_BMCR: 505 rtk8139_reg = RTK_BMCR; 506 break; 507 case MII_BMSR: 508 rtk8139_reg = RTK_BMSR; 509 break; 510 case MII_ANAR: 511 rtk8139_reg = RTK_ANAR; 512 break; 513 case MII_ANER: 514 rtk8139_reg = RTK_ANER; 515 break; 516 case MII_ANLPAR: 517 rtk8139_reg = RTK_LPAR; 518 break; 519 default: 520 #if 0 521 printf("%s: bad phy register\n", sc->sc_dev.dv_xname); 522 #endif 523 return; 524 } 525 CSR_WRITE_2(sc, rtk8139_reg, data); 526 return; 527 } 528 529 memset((char *)&frame, 0, sizeof(frame)); 530 531 frame.mii_phyaddr = phy; 532 frame.mii_regaddr = reg; 533 frame.mii_data = data; 534 535 rtk_mii_writereg(sc, &frame); 536 } 537 538 STATIC void 539 rtk_phy_statchg(v) 540 struct device *v; 541 { 542 543 /* Nothing to do. */ 544 } 545 546 #define rtk_calchash(addr) \ 547 (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 548 549 /* 550 * Program the 64-bit multicast hash filter. 551 */ 552 void 553 rtk_setmulti(sc) 554 struct rtk_softc *sc; 555 { 556 struct ifnet *ifp; 557 int h = 0; 558 u_int32_t hashes[2] = { 0, 0 }; 559 u_int32_t rxfilt; 560 int mcnt = 0; 561 struct ether_multi *enm; 562 struct ether_multistep step; 563 564 ifp = &sc->ethercom.ec_if; 565 566 rxfilt = CSR_READ_4(sc, RTK_RXCFG); 567 568 if (ifp->if_flags & IFF_PROMISC) { 569 allmulti: 570 ifp->if_flags |= IFF_ALLMULTI; 571 rxfilt |= RTK_RXCFG_RX_MULTI; 572 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt); 573 CSR_WRITE_4(sc, RTK_MAR0, 0xFFFFFFFF); 574 CSR_WRITE_4(sc, RTK_MAR4, 0xFFFFFFFF); 575 return; 576 } 577 578 /* first, zot all the existing hash bits */ 579 CSR_WRITE_4(sc, RTK_MAR0, 0); 580 CSR_WRITE_4(sc, RTK_MAR4, 0); 581 582 /* now program new ones */ 583 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 584 while (enm != NULL) { 585 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 586 ETHER_ADDR_LEN) != 0) 587 goto allmulti; 588 589 h = rtk_calchash(enm->enm_addrlo); 590 if (h < 32) 591 hashes[0] |= (1 << h); 592 else 593 hashes[1] |= (1 << (h - 32)); 594 mcnt++; 595 ETHER_NEXT_MULTI(step, enm); 596 } 597 598 ifp->if_flags &= ~IFF_ALLMULTI; 599 600 if (mcnt) 601 rxfilt |= RTK_RXCFG_RX_MULTI; 602 else 603 rxfilt &= ~RTK_RXCFG_RX_MULTI; 604 605 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt); 606 CSR_WRITE_4(sc, RTK_MAR0, hashes[0]); 607 CSR_WRITE_4(sc, RTK_MAR4, hashes[1]); 608 } 609 610 void 611 rtk_reset(sc) 612 struct rtk_softc *sc; 613 { 614 int i; 615 616 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 617 618 for (i = 0; i < RTK_TIMEOUT; i++) { 619 DELAY(10); 620 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0) 621 break; 622 } 623 if (i == RTK_TIMEOUT) 624 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname); 625 } 626 627 /* 628 * Attach the interface. Allocate softc structures, do ifmedia 629 * setup and ethernet/BPF attach. 630 */ 631 void 632 rtk_attach(sc) 633 struct rtk_softc *sc; 634 { 635 struct ifnet *ifp; 636 struct rtk_tx_desc *txd; 637 u_int16_t val; 638 u_int8_t eaddr[ETHER_ADDR_LEN]; 639 int error; 640 int i, addr_len; 641 642 callout_init(&sc->rtk_tick_ch); 643 644 /* 645 * Check EEPROM type 9346 or 9356. 646 */ 647 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 648 addr_len = RTK_EEADDR_LEN1; 649 else 650 addr_len = RTK_EEADDR_LEN0; 651 652 /* 653 * Get station address. 654 */ 655 val = rtk_read_eeprom(sc, RTK_EE_EADDR0, addr_len); 656 eaddr[0] = val & 0xff; 657 eaddr[1] = val >> 8; 658 val = rtk_read_eeprom(sc, RTK_EE_EADDR1, addr_len); 659 eaddr[2] = val & 0xff; 660 eaddr[3] = val >> 8; 661 val = rtk_read_eeprom(sc, RTK_EE_EADDR2, addr_len); 662 eaddr[4] = val & 0xff; 663 eaddr[5] = val >> 8; 664 665 if ((error = bus_dmamem_alloc(sc->sc_dmat, 666 RTK_RXBUFLEN + 16, PAGE_SIZE, 0, &sc->sc_dmaseg, 1, &sc->sc_dmanseg, 667 BUS_DMA_NOWAIT)) != 0) { 668 printf("%s: can't allocate recv buffer, error = %d\n", 669 sc->sc_dev.dv_xname, error); 670 goto fail_0; 671 } 672 673 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg, 674 RTK_RXBUFLEN + 16, (caddr_t *)&sc->rtk_rx_buf, 675 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 676 printf("%s: can't map recv buffer, error = %d\n", 677 sc->sc_dev.dv_xname, error); 678 goto fail_1; 679 } 680 681 if ((error = bus_dmamap_create(sc->sc_dmat, 682 RTK_RXBUFLEN + 16, 1, RTK_RXBUFLEN + 16, 0, BUS_DMA_NOWAIT, 683 &sc->recv_dmamap)) != 0) { 684 printf("%s: can't create recv buffer DMA map, error = %d\n", 685 sc->sc_dev.dv_xname, error); 686 goto fail_2; 687 } 688 689 if ((error = bus_dmamap_load(sc->sc_dmat, sc->recv_dmamap, 690 sc->rtk_rx_buf, RTK_RXBUFLEN + 16, 691 NULL, BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 692 printf("%s: can't load recv buffer DMA map, error = %d\n", 693 sc->sc_dev.dv_xname, error); 694 goto fail_3; 695 } 696 697 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 698 txd = &sc->rtk_tx_descs[i]; 699 if ((error = bus_dmamap_create(sc->sc_dmat, 700 MCLBYTES, 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 701 &txd->txd_dmamap)) != 0) { 702 printf("%s: can't create snd buffer DMA map," 703 " error = %d\n", sc->sc_dev.dv_xname, error); 704 goto fail_4; 705 } 706 txd->txd_txaddr = RTK_TXADDR0 + (i * 4); 707 txd->txd_txstat = RTK_TXSTAT0 + (i * 4); 708 } 709 SIMPLEQ_INIT(&sc->rtk_tx_free); 710 SIMPLEQ_INIT(&sc->rtk_tx_dirty); 711 712 /* 713 * From this point forward, the attachment cannot fail. A failure 714 * before this releases all resources thar may have been 715 * allocated. 716 */ 717 sc->sc_flags |= RTK_ATTACHED; 718 719 /* Init Early TX threshold. */ 720 sc->sc_txthresh = TXTH_256; 721 722 /* Reset the adapter. */ 723 rtk_reset(sc); 724 725 printf("%s: Ethernet address %s\n", 726 sc->sc_dev.dv_xname, ether_sprintf(eaddr)); 727 728 ifp = &sc->ethercom.ec_if; 729 ifp->if_softc = sc; 730 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 731 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 732 ifp->if_ioctl = rtk_ioctl; 733 ifp->if_start = rtk_start; 734 ifp->if_watchdog = rtk_watchdog; 735 ifp->if_init = rtk_init; 736 ifp->if_stop = rtk_stop; 737 IFQ_SET_READY(&ifp->if_snd); 738 739 /* 740 * Do ifmedia setup. 741 */ 742 sc->mii.mii_ifp = ifp; 743 sc->mii.mii_readreg = rtk_phy_readreg; 744 sc->mii.mii_writereg = rtk_phy_writereg; 745 sc->mii.mii_statchg = rtk_phy_statchg; 746 ifmedia_init(&sc->mii.mii_media, IFM_IMASK, rtk_ifmedia_upd, rtk_ifmedia_sts); 747 mii_attach(&sc->sc_dev, &sc->mii, 0xffffffff, 748 MII_PHY_ANY, MII_OFFSET_ANY, 0); 749 750 /* Choose a default media. */ 751 if (LIST_FIRST(&sc->mii.mii_phys) == NULL) { 752 ifmedia_add(&sc->mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 753 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_NONE); 754 } else { 755 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_AUTO); 756 } 757 758 /* 759 * Call MI attach routines. 760 */ 761 if_attach(ifp); 762 ether_ifattach(ifp, eaddr); 763 764 /* 765 * Make sure the interface is shutdown during reboot. 766 */ 767 sc->sc_sdhook = shutdownhook_establish(rtk_shutdown, sc); 768 if (sc->sc_sdhook == NULL) 769 printf("%s: WARNING: unable to establish shutdown hook\n", 770 sc->sc_dev.dv_xname); 771 /* 772 * Add a suspend hook to make sure we come back up after a 773 * resume. 774 */ 775 sc->sc_powerhook = powerhook_establish(rtk_power, sc); 776 if (sc->sc_powerhook == NULL) 777 printf("%s: WARNING: unable to establish power hook\n", 778 sc->sc_dev.dv_xname); 779 780 781 #if NRND > 0 782 rnd_attach_source(&sc->rnd_source, sc->sc_dev.dv_xname, 783 RND_TYPE_NET, 0); 784 #endif 785 786 return; 787 fail_4: 788 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 789 txd = &sc->rtk_tx_descs[i]; 790 if (txd->txd_dmamap != NULL) 791 bus_dmamap_destroy(sc->sc_dmat, txd->txd_dmamap); 792 } 793 fail_3: 794 bus_dmamap_destroy(sc->sc_dmat, sc->recv_dmamap); 795 fail_2: 796 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rtk_rx_buf, 797 RTK_RXBUFLEN + 16); 798 fail_1: 799 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg); 800 fail_0: 801 return; 802 } 803 804 /* 805 * Initialize the transmit descriptors. 806 */ 807 STATIC int 808 rtk_list_tx_init(sc) 809 struct rtk_softc *sc; 810 { 811 struct rtk_tx_desc *txd; 812 int i; 813 814 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) 815 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q); 816 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_free)) != NULL) 817 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_free, txd_q); 818 819 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 820 txd = &sc->rtk_tx_descs[i]; 821 CSR_WRITE_4(sc, txd->txd_txaddr, 0); 822 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_free, txd, txd_q); 823 } 824 825 return (0); 826 } 827 828 /* 829 * rtk_activate: 830 * Handle device activation/deactivation requests. 831 */ 832 int 833 rtk_activate(self, act) 834 struct device *self; 835 enum devact act; 836 { 837 struct rtk_softc *sc = (void *) self; 838 int s, error = 0; 839 840 s = splnet(); 841 switch (act) { 842 case DVACT_ACTIVATE: 843 error = EOPNOTSUPP; 844 break; 845 case DVACT_DEACTIVATE: 846 mii_activate(&sc->mii, act, MII_PHY_ANY, MII_OFFSET_ANY); 847 if_deactivate(&sc->ethercom.ec_if); 848 break; 849 } 850 splx(s); 851 852 return (error); 853 } 854 855 /* 856 * rtk_detach: 857 * Detach a rtk interface. 858 */ 859 int 860 rtk_detach(sc) 861 struct rtk_softc *sc; 862 { 863 struct ifnet *ifp = &sc->ethercom.ec_if; 864 struct rtk_tx_desc *txd; 865 int i; 866 867 /* 868 * Succeed now if there isn't any work to do. 869 */ 870 if ((sc->sc_flags & RTK_ATTACHED) == 0) 871 return (0); 872 873 /* Unhook our tick handler. */ 874 callout_stop(&sc->rtk_tick_ch); 875 876 /* Detach all PHYs. */ 877 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 878 879 /* Delete all remaining media. */ 880 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY); 881 882 #if NRND > 0 883 rnd_detach_source(&sc->rnd_source); 884 #endif 885 886 ether_ifdetach(ifp); 887 if_detach(ifp); 888 889 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 890 txd = &sc->rtk_tx_descs[i]; 891 if (txd->txd_dmamap != NULL) 892 bus_dmamap_destroy(sc->sc_dmat, txd->txd_dmamap); 893 } 894 bus_dmamap_destroy(sc->sc_dmat, sc->recv_dmamap); 895 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rtk_rx_buf, 896 RTK_RXBUFLEN + 16); 897 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg); 898 899 shutdownhook_disestablish(sc->sc_sdhook); 900 powerhook_disestablish(sc->sc_powerhook); 901 902 return (0); 903 } 904 905 /* 906 * rtk_enable: 907 * Enable the RTL81X9 chip. 908 */ 909 int 910 rtk_enable(sc) 911 struct rtk_softc *sc; 912 { 913 914 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 915 if ((*sc->sc_enable)(sc) != 0) { 916 printf("%s: device enable failed\n", 917 sc->sc_dev.dv_xname); 918 return (EIO); 919 } 920 sc->sc_flags |= RTK_ENABLED; 921 } 922 return (0); 923 } 924 925 /* 926 * rtk_disable: 927 * Disable the RTL81X9 chip. 928 */ 929 void 930 rtk_disable(sc) 931 struct rtk_softc *sc; 932 { 933 934 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 935 (*sc->sc_disable)(sc); 936 sc->sc_flags &= ~RTK_ENABLED; 937 } 938 } 939 940 /* 941 * rtk_power: 942 * Power management (suspend/resume) hook. 943 */ 944 void 945 rtk_power(why, arg) 946 int why; 947 void *arg; 948 { 949 struct rtk_softc *sc = (void *) arg; 950 struct ifnet *ifp = &sc->ethercom.ec_if; 951 int s; 952 953 s = splnet(); 954 switch (why) { 955 case PWR_SUSPEND: 956 case PWR_STANDBY: 957 rtk_stop(ifp, 0); 958 if (sc->sc_power != NULL) 959 (*sc->sc_power)(sc, why); 960 break; 961 case PWR_RESUME: 962 if (ifp->if_flags & IFF_UP) { 963 if (sc->sc_power != NULL) 964 (*sc->sc_power)(sc, why); 965 rtk_init(ifp); 966 } 967 break; 968 case PWR_SOFTSUSPEND: 969 case PWR_SOFTSTANDBY: 970 case PWR_SOFTRESUME: 971 break; 972 } 973 splx(s); 974 } 975 976 /* 977 * A frame has been uploaded: pass the resulting mbuf chain up to 978 * the higher level protocols. 979 * 980 * You know there's something wrong with a PCI bus-master chip design. 981 * 982 * The receive operation is badly documented in the datasheet, so I'll 983 * attempt to document it here. The driver provides a buffer area and 984 * places its base address in the RX buffer start address register. 985 * The chip then begins copying frames into the RX buffer. Each frame 986 * is preceded by a 32-bit RX status word which specifies the length 987 * of the frame and certain other status bits. Each frame (starting with 988 * the status word) is also 32-bit aligned. The frame length is in the 989 * first 16 bits of the status word; the lower 15 bits correspond with 990 * the 'rx status register' mentioned in the datasheet. 991 * 992 * Note: to make the Alpha happy, the frame payload needs to be aligned 993 * on a 32-bit boundary. To achieve this, we copy the data to mbuf 994 * shifted forward 2 bytes. 995 */ 996 STATIC void 997 rtk_rxeof(sc) 998 struct rtk_softc *sc; 999 { 1000 struct mbuf *m; 1001 struct ifnet *ifp; 1002 caddr_t rxbufpos, dst; 1003 u_int total_len, wrap = 0; 1004 u_int32_t rxstat; 1005 u_int16_t cur_rx, new_rx; 1006 u_int16_t limit; 1007 u_int16_t rx_bytes = 0, max_bytes; 1008 1009 ifp = &sc->ethercom.ec_if; 1010 1011 cur_rx = (CSR_READ_2(sc, RTK_CURRXADDR) + 16) % RTK_RXBUFLEN; 1012 1013 /* Do not try to read past this point. */ 1014 limit = CSR_READ_2(sc, RTK_CURRXBUF) % RTK_RXBUFLEN; 1015 1016 if (limit < cur_rx) 1017 max_bytes = (RTK_RXBUFLEN - cur_rx) + limit; 1018 else 1019 max_bytes = limit - cur_rx; 1020 1021 while((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_EMPTY_RXBUF) == 0) { 1022 rxbufpos = sc->rtk_rx_buf + cur_rx; 1023 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 1024 RTK_RXSTAT_LEN, BUS_DMASYNC_POSTREAD); 1025 rxstat = le32toh(*(u_int32_t *)rxbufpos); 1026 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 1027 RTK_RXSTAT_LEN, BUS_DMASYNC_PREREAD); 1028 1029 /* 1030 * Here's a totally undocumented fact for you. When the 1031 * RealTek chip is in the process of copying a packet into 1032 * RAM for you, the length will be 0xfff0. If you spot a 1033 * packet header with this value, you need to stop. The 1034 * datasheet makes absolutely no mention of this and 1035 * RealTek should be shot for this. 1036 */ 1037 total_len = rxstat >> 16; 1038 if (total_len == RTK_RXSTAT_UNFINISHED) 1039 break; 1040 1041 if ((rxstat & RTK_RXSTAT_RXOK) == 0 || 1042 total_len > ETHER_MAX_LEN) { 1043 ifp->if_ierrors++; 1044 1045 /* 1046 * submitted by:[netbsd-pcmcia:00484] 1047 * Takahiro Kambe <taca@sky.yamashina.kyoto.jp> 1048 * obtain from: 1049 * FreeBSD if_rl.c rev 1.24->1.25 1050 * 1051 */ 1052 #if 0 1053 if (rxstat & (RTK_RXSTAT_BADSYM|RTK_RXSTAT_RUNT| 1054 RTK_RXSTAT_GIANT|RTK_RXSTAT_CRCERR| 1055 RTK_RXSTAT_ALIGNERR)) { 1056 CSR_WRITE_2(sc, RTK_COMMAND, RTK_CMD_TX_ENB); 1057 CSR_WRITE_2(sc, RTK_COMMAND, 1058 RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1059 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG); 1060 CSR_WRITE_4(sc, RTK_RXADDR, 1061 sc->recv_dmamap->dm_segs[0].ds_addr); 1062 cur_rx = 0; 1063 } 1064 break; 1065 #else 1066 rtk_init(ifp); 1067 return; 1068 #endif 1069 } 1070 1071 /* No errors; receive the packet. */ 1072 rx_bytes += total_len + RTK_RXSTAT_LEN; 1073 1074 /* 1075 * Avoid trying to read more bytes than we know 1076 * the chip has prepared for us. 1077 */ 1078 if (rx_bytes > max_bytes) 1079 break; 1080 1081 /* 1082 * Skip the status word, wrapping around to the beginning 1083 * of the Rx area, if necessary. 1084 */ 1085 cur_rx = (cur_rx + RTK_RXSTAT_LEN) % RTK_RXBUFLEN; 1086 rxbufpos = sc->rtk_rx_buf + cur_rx; 1087 1088 /* 1089 * Compute the number of bytes at which the packet 1090 * will wrap to the beginning of the ring buffer. 1091 */ 1092 wrap = RTK_RXBUFLEN - cur_rx; 1093 1094 /* 1095 * Compute where the next pending packet is. 1096 */ 1097 if (total_len > wrap) 1098 new_rx = total_len - wrap; 1099 else 1100 new_rx = cur_rx + total_len; 1101 /* Round up to 32-bit boundary. */ 1102 new_rx = (new_rx + 3) & ~3; 1103 1104 /* 1105 * Now allocate an mbuf (and possibly a cluster) to hold 1106 * the packet. Note we offset the packet 2 bytes so that 1107 * data after the Ethernet header will be 4-byte aligned. 1108 */ 1109 MGETHDR(m, M_DONTWAIT, MT_DATA); 1110 if (m == NULL) { 1111 printf("%s: unable to allocate Rx mbuf\n", 1112 sc->sc_dev.dv_xname); 1113 ifp->if_ierrors++; 1114 goto next_packet; 1115 } 1116 if (total_len > (MHLEN - RTK_ETHER_ALIGN)) { 1117 MCLGET(m, M_DONTWAIT); 1118 if ((m->m_flags & M_EXT) == 0) { 1119 printf("%s: unable to allocate Rx cluster\n", 1120 sc->sc_dev.dv_xname); 1121 ifp->if_ierrors++; 1122 m_freem(m); 1123 m = NULL; 1124 goto next_packet; 1125 } 1126 } 1127 m->m_data += RTK_ETHER_ALIGN; /* for alignment */ 1128 m->m_pkthdr.rcvif = ifp; 1129 m->m_pkthdr.len = m->m_len = total_len; 1130 dst = mtod(m, caddr_t); 1131 1132 /* 1133 * If the packet wraps, copy up to the wrapping point. 1134 */ 1135 if (total_len > wrap) { 1136 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1137 cur_rx, wrap, BUS_DMASYNC_POSTREAD); 1138 memcpy(dst, rxbufpos, wrap); 1139 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1140 cur_rx, wrap, BUS_DMASYNC_PREREAD); 1141 cur_rx = 0; 1142 rxbufpos = sc->rtk_rx_buf; 1143 total_len -= wrap; 1144 dst += wrap; 1145 } 1146 1147 /* 1148 * ...and now the rest. 1149 */ 1150 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1151 cur_rx, total_len, BUS_DMASYNC_POSTREAD); 1152 memcpy(dst, rxbufpos, total_len); 1153 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1154 cur_rx, total_len, BUS_DMASYNC_PREREAD); 1155 1156 next_packet: 1157 CSR_WRITE_2(sc, RTK_CURRXADDR, new_rx - 16); 1158 cur_rx = new_rx; 1159 1160 if (m == NULL) 1161 continue; 1162 1163 /* 1164 * The RealTek chip includes the CRC with every 1165 * incoming packet. 1166 */ 1167 m->m_flags |= M_HASFCS; 1168 1169 ifp->if_ipackets++; 1170 1171 #if NBPFILTER > 0 1172 if (ifp->if_bpf) 1173 bpf_mtap(ifp->if_bpf, m); 1174 #endif 1175 /* pass it on. */ 1176 (*ifp->if_input)(ifp, m); 1177 } 1178 } 1179 1180 /* 1181 * A frame was downloaded to the chip. It's safe for us to clean up 1182 * the list buffers. 1183 */ 1184 STATIC void 1185 rtk_txeof(sc) 1186 struct rtk_softc *sc; 1187 { 1188 struct ifnet *ifp; 1189 struct rtk_tx_desc *txd; 1190 u_int32_t txstat; 1191 1192 ifp = &sc->ethercom.ec_if; 1193 1194 /* Clear the timeout timer. */ 1195 ifp->if_timer = 0; 1196 1197 /* 1198 * Go through our tx list and free mbufs for those 1199 * frames that have been uploaded. 1200 */ 1201 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) { 1202 txstat = CSR_READ_4(sc, txd->txd_txstat); 1203 if ((txstat & (RTK_TXSTAT_TX_OK| 1204 RTK_TXSTAT_TX_UNDERRUN|RTK_TXSTAT_TXABRT)) == 0) 1205 break; 1206 1207 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q); 1208 1209 bus_dmamap_sync(sc->sc_dmat, txd->txd_dmamap, 0, 1210 txd->txd_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1211 bus_dmamap_unload(sc->sc_dmat, txd->txd_dmamap); 1212 m_freem(txd->txd_mbuf); 1213 txd->txd_mbuf = NULL; 1214 1215 ifp->if_collisions += (txstat & RTK_TXSTAT_COLLCNT) >> 24; 1216 1217 if (txstat & RTK_TXSTAT_TX_OK) 1218 ifp->if_opackets++; 1219 else { 1220 ifp->if_oerrors++; 1221 1222 /* 1223 * Increase Early TX threshold if underrun occurred. 1224 * Increase step 64 bytes. 1225 */ 1226 if (txstat & RTK_TXSTAT_TX_UNDERRUN) { 1227 #ifdef DEBUG 1228 printf("%s: transmit underrun;", 1229 sc->sc_dev.dv_xname); 1230 #endif 1231 if (sc->sc_txthresh < TXTH_MAX) { 1232 sc->sc_txthresh += 2; 1233 #ifdef DEBUG 1234 printf(" new threshold: %d bytes", 1235 sc->sc_txthresh * 32); 1236 #endif 1237 } 1238 printf("\n"); 1239 } 1240 if (txstat & (RTK_TXSTAT_TXABRT|RTK_TXSTAT_OUTOFWIN)) 1241 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG); 1242 } 1243 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_free, txd, txd_q); 1244 ifp->if_flags &= ~IFF_OACTIVE; 1245 } 1246 } 1247 1248 int 1249 rtk_intr(arg) 1250 void *arg; 1251 { 1252 struct rtk_softc *sc; 1253 struct ifnet *ifp; 1254 u_int16_t status; 1255 int handled = 0; 1256 1257 sc = arg; 1258 ifp = &sc->ethercom.ec_if; 1259 1260 /* Disable interrupts. */ 1261 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1262 1263 for (;;) { 1264 1265 status = CSR_READ_2(sc, RTK_ISR); 1266 if (status) 1267 CSR_WRITE_2(sc, RTK_ISR, status); 1268 1269 handled = 1; 1270 1271 if ((status & RTK_INTRS) == 0) 1272 break; 1273 1274 if (status & RTK_ISR_RX_OK) 1275 rtk_rxeof(sc); 1276 1277 if (status & RTK_ISR_RX_ERR) 1278 rtk_rxeof(sc); 1279 1280 if (status & (RTK_ISR_TX_OK|RTK_ISR_TX_ERR)) 1281 rtk_txeof(sc); 1282 1283 if (status & RTK_ISR_SYSTEM_ERR) { 1284 rtk_reset(sc); 1285 rtk_init(ifp); 1286 } 1287 } 1288 1289 /* Re-enable interrupts. */ 1290 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS); 1291 1292 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 1293 rtk_start(ifp); 1294 1295 #if NRND > 0 1296 if (RND_ENABLED(&sc->rnd_source)) 1297 rnd_add_uint32(&sc->rnd_source, status); 1298 #endif 1299 1300 return (handled); 1301 } 1302 1303 /* 1304 * Main transmit routine. 1305 */ 1306 1307 STATIC void 1308 rtk_start(ifp) 1309 struct ifnet *ifp; 1310 { 1311 struct rtk_softc *sc; 1312 struct rtk_tx_desc *txd; 1313 struct mbuf *m_head = NULL, *m_new; 1314 int error, len; 1315 1316 sc = ifp->if_softc; 1317 1318 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_free)) != NULL) { 1319 IFQ_POLL(&ifp->if_snd, m_head); 1320 if (m_head == NULL) 1321 break; 1322 m_new = NULL; 1323 1324 /* 1325 * Load the DMA map. If this fails, the packet didn't 1326 * fit in one DMA segment, and we need to copy. Note, 1327 * the packet must also be aligned. 1328 * if the packet is too small, copy it too, so we're sure 1329 * so have enouth room for the pad buffer. 1330 */ 1331 if ((mtod(m_head, uintptr_t) & 3) != 0 || 1332 m_head->m_pkthdr.len < ETHER_PAD_LEN || 1333 bus_dmamap_load_mbuf(sc->sc_dmat, txd->txd_dmamap, 1334 m_head, BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1335 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1336 if (m_new == NULL) { 1337 printf("%s: unable to allocate Tx mbuf\n", 1338 sc->sc_dev.dv_xname); 1339 break; 1340 } 1341 if (m_head->m_pkthdr.len > MHLEN) { 1342 MCLGET(m_new, M_DONTWAIT); 1343 if ((m_new->m_flags & M_EXT) == 0) { 1344 printf("%s: unable to allocate Tx " 1345 "cluster\n", sc->sc_dev.dv_xname); 1346 m_freem(m_new); 1347 break; 1348 } 1349 } 1350 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1351 mtod(m_new, caddr_t)); 1352 m_new->m_pkthdr.len = m_new->m_len = 1353 m_head->m_pkthdr.len; 1354 if (m_head->m_pkthdr.len < ETHER_PAD_LEN) { 1355 memset( 1356 mtod(m_new, caddr_t) + m_head->m_pkthdr.len, 1357 0, ETHER_PAD_LEN - m_head->m_pkthdr.len); 1358 m_new->m_pkthdr.len = m_new->m_len = 1359 ETHER_PAD_LEN; 1360 } 1361 error = bus_dmamap_load_mbuf(sc->sc_dmat, 1362 txd->txd_dmamap, m_new, 1363 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1364 if (error) { 1365 printf("%s: unable to load Tx buffer, " 1366 "error = %d\n", sc->sc_dev.dv_xname, error); 1367 break; 1368 } 1369 } 1370 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1371 #if NBPFILTER > 0 1372 /* 1373 * If there's a BPF listener, bounce a copy of this frame 1374 * to him. 1375 */ 1376 if (ifp->if_bpf) 1377 bpf_mtap(ifp->if_bpf, m_head); 1378 #endif 1379 if (m_new != NULL) { 1380 m_freem(m_head); 1381 m_head = m_new; 1382 } 1383 txd->txd_mbuf = m_head; 1384 1385 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_free, txd_q); 1386 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_dirty, txd, txd_q); 1387 1388 /* 1389 * Transmit the frame. 1390 */ 1391 bus_dmamap_sync(sc->sc_dmat, 1392 txd->txd_dmamap, 0, txd->txd_dmamap->dm_mapsize, 1393 BUS_DMASYNC_PREWRITE); 1394 1395 len = txd->txd_dmamap->dm_segs[0].ds_len; 1396 1397 CSR_WRITE_4(sc, txd->txd_txaddr, 1398 txd->txd_dmamap->dm_segs[0].ds_addr); 1399 CSR_WRITE_4(sc, txd->txd_txstat, RTK_TX_THRESH(sc) | len); 1400 } 1401 1402 /* 1403 * We broke out of the loop because all our TX slots are 1404 * full. Mark the NIC as busy until it drains some of the 1405 * packets from the queue. 1406 */ 1407 if (SIMPLEQ_EMPTY(&sc->rtk_tx_free)) 1408 ifp->if_flags |= IFF_OACTIVE; 1409 1410 /* 1411 * Set a timeout in case the chip goes out to lunch. 1412 */ 1413 ifp->if_timer = 5; 1414 } 1415 1416 STATIC int 1417 rtk_init(ifp) 1418 struct ifnet *ifp; 1419 { 1420 struct rtk_softc *sc = ifp->if_softc; 1421 int error = 0, i; 1422 u_int32_t rxcfg; 1423 1424 if ((error = rtk_enable(sc)) != 0) 1425 goto out; 1426 1427 /* 1428 * Cancel pending I/O. 1429 */ 1430 rtk_stop(ifp, 0); 1431 1432 /* Init our MAC address */ 1433 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1434 CSR_WRITE_1(sc, RTK_IDR0 + i, LLADDR(ifp->if_sadl)[i]); 1435 } 1436 1437 /* Init the RX buffer pointer register. */ 1438 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 0, 1439 sc->recv_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1440 CSR_WRITE_4(sc, RTK_RXADDR, sc->recv_dmamap->dm_segs[0].ds_addr); 1441 1442 /* Init TX descriptors. */ 1443 rtk_list_tx_init(sc); 1444 1445 /* Init Early TX threshold. */ 1446 sc->sc_txthresh = TXTH_256; 1447 /* 1448 * Enable transmit and receive. 1449 */ 1450 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1451 1452 /* 1453 * Set the initial TX and RX configuration. 1454 */ 1455 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG); 1456 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG); 1457 1458 /* Set the individual bit to receive frames for this host only. */ 1459 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 1460 rxcfg |= RTK_RXCFG_RX_INDIV; 1461 1462 /* If we want promiscuous mode, set the allframes bit. */ 1463 if (ifp->if_flags & IFF_PROMISC) { 1464 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 1465 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1466 } else { 1467 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 1468 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1469 } 1470 1471 /* 1472 * Set capture broadcast bit to capture broadcast frames. 1473 */ 1474 if (ifp->if_flags & IFF_BROADCAST) { 1475 rxcfg |= RTK_RXCFG_RX_BROAD; 1476 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1477 } else { 1478 rxcfg &= ~RTK_RXCFG_RX_BROAD; 1479 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1480 } 1481 1482 /* 1483 * Program the multicast filter, if necessary. 1484 */ 1485 rtk_setmulti(sc); 1486 1487 /* 1488 * Enable interrupts. 1489 */ 1490 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS); 1491 1492 /* Start RX/TX process. */ 1493 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 1494 1495 /* Enable receiver and transmitter. */ 1496 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1497 1498 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD|RTK_CFG1_FULLDUPLEX); 1499 1500 /* 1501 * Set current media. 1502 */ 1503 mii_mediachg(&sc->mii); 1504 1505 ifp->if_flags |= IFF_RUNNING; 1506 ifp->if_flags &= ~IFF_OACTIVE; 1507 1508 callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc); 1509 1510 out: 1511 if (error) { 1512 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1513 ifp->if_timer = 0; 1514 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1515 } 1516 return (error); 1517 } 1518 1519 /* 1520 * Set media options. 1521 */ 1522 STATIC int 1523 rtk_ifmedia_upd(ifp) 1524 struct ifnet *ifp; 1525 { 1526 struct rtk_softc *sc; 1527 1528 sc = ifp->if_softc; 1529 1530 return (mii_mediachg(&sc->mii)); 1531 } 1532 1533 /* 1534 * Report current media status. 1535 */ 1536 STATIC void 1537 rtk_ifmedia_sts(ifp, ifmr) 1538 struct ifnet *ifp; 1539 struct ifmediareq *ifmr; 1540 { 1541 struct rtk_softc *sc; 1542 1543 sc = ifp->if_softc; 1544 1545 mii_pollstat(&sc->mii); 1546 ifmr->ifm_status = sc->mii.mii_media_status; 1547 ifmr->ifm_active = sc->mii.mii_media_active; 1548 } 1549 1550 STATIC int 1551 rtk_ioctl(ifp, command, data) 1552 struct ifnet *ifp; 1553 u_long command; 1554 caddr_t data; 1555 { 1556 struct rtk_softc *sc = ifp->if_softc; 1557 struct ifreq *ifr = (struct ifreq *) data; 1558 int s, error = 0; 1559 1560 s = splnet(); 1561 1562 switch (command) { 1563 case SIOCGIFMEDIA: 1564 case SIOCSIFMEDIA: 1565 error = ifmedia_ioctl(ifp, ifr, &sc->mii.mii_media, command); 1566 break; 1567 1568 default: 1569 error = ether_ioctl(ifp, command, data); 1570 if (error == ENETRESET) { 1571 if (ifp->if_flags & IFF_RUNNING) { 1572 /* 1573 * Multicast list has changed. Set the 1574 * hardware filter accordingly. 1575 */ 1576 rtk_setmulti(sc); 1577 } 1578 error = 0; 1579 } 1580 break; 1581 } 1582 1583 splx(s); 1584 1585 return (error); 1586 } 1587 1588 STATIC void 1589 rtk_watchdog(ifp) 1590 struct ifnet *ifp; 1591 { 1592 struct rtk_softc *sc; 1593 1594 sc = ifp->if_softc; 1595 1596 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1597 ifp->if_oerrors++; 1598 rtk_txeof(sc); 1599 rtk_rxeof(sc); 1600 rtk_init(ifp); 1601 } 1602 1603 /* 1604 * Stop the adapter and free any mbufs allocated to the 1605 * RX and TX lists. 1606 */ 1607 STATIC void 1608 rtk_stop(ifp, disable) 1609 struct ifnet *ifp; 1610 int disable; 1611 { 1612 struct rtk_softc *sc = ifp->if_softc; 1613 struct rtk_tx_desc *txd; 1614 1615 callout_stop(&sc->rtk_tick_ch); 1616 1617 mii_down(&sc->mii); 1618 1619 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 1620 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1621 1622 /* 1623 * Free the TX list buffers. 1624 */ 1625 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) { 1626 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd_q); 1627 bus_dmamap_unload(sc->sc_dmat, txd->txd_dmamap); 1628 m_freem(txd->txd_mbuf); 1629 txd->txd_mbuf = NULL; 1630 CSR_WRITE_4(sc, txd->txd_txaddr, 0); 1631 } 1632 1633 if (disable) 1634 rtk_disable(sc); 1635 1636 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1637 ifp->if_timer = 0; 1638 } 1639 1640 /* 1641 * Stop all chip I/O so that the kernel's probe routines don't 1642 * get confused by errant DMAs when rebooting. 1643 */ 1644 STATIC void 1645 rtk_shutdown(vsc) 1646 void *vsc; 1647 { 1648 struct rtk_softc *sc = (struct rtk_softc *)vsc; 1649 1650 rtk_stop(&sc->ethercom.ec_if, 0); 1651 } 1652 1653 STATIC void 1654 rtk_tick(arg) 1655 void *arg; 1656 { 1657 struct rtk_softc *sc = arg; 1658 int s = splnet(); 1659 1660 mii_tick(&sc->mii); 1661 splx(s); 1662 1663 callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc); 1664 } 1665