1 /* $NetBSD: rtl81x9.c,v 1.11 2000/05/21 13:00:46 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_rl.c,v 1.17 1999/06/19 20:17:37 wpaul Exp 35 */ 36 37 /* 38 * RealTek 8129/8139 PCI NIC driver 39 * 40 * Supports several extremely cheap PCI 10/100 adapters based on 41 * the RealTek chipset. Datasheets can be obtained from 42 * www.realtek.com.tw. 43 * 44 * Written by Bill Paul <wpaul@ctr.columbia.edu> 45 * Electrical Engineering Department 46 * Columbia University, New York City 47 */ 48 49 /* 50 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 51 * probably the worst PCI ethernet controller ever made, with the possible 52 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 53 * DMA, but it has a terrible interface that nullifies any performance 54 * gains that bus-master DMA usually offers. 55 * 56 * For transmission, the chip offers a series of four TX descriptor 57 * registers. Each transmit frame must be in a contiguous buffer, aligned 58 * on a longword (32-bit) boundary. This means we almost always have to 59 * do mbuf copies in order to transmit a frame, except in the unlikely 60 * case where a) the packet fits into a single mbuf, and b) the packet 61 * is 32-bit aligned within the mbuf's data area. The presence of only 62 * four descriptor registers means that we can never have more than four 63 * packets queued for transmission at any one time. 64 * 65 * Reception is not much better. The driver has to allocate a single large 66 * buffer area (up to 64K in size) into which the chip will DMA received 67 * frames. Because we don't know where within this region received packets 68 * will begin or end, we have no choice but to copy data from the buffer 69 * area into mbufs in order to pass the packets up to the higher protocol 70 * levels. 71 * 72 * It's impossible given this rotten design to really achieve decent 73 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 74 * some equally overmuscled CPU to drive it. 75 * 76 * On the bright side, the 8139 does have a built-in PHY, although 77 * rather than using an MDIO serial interface like most other NICs, the 78 * PHY registers are directly accessible through the 8139's register 79 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 80 * filter. 81 * 82 * The 8129 chip is an older version of the 8139 that uses an external PHY 83 * chip. The 8129 has a serial MDIO interface for accessing the MII where 84 * the 8139 lets you directly access the on-board PHY registers. We need 85 * to select which interface to use depending on the chip type. 86 */ 87 88 #include "opt_inet.h" 89 #include "opt_ns.h" 90 #include "bpfilter.h" 91 #include "rnd.h" 92 93 #include <sys/param.h> 94 #include <sys/systm.h> 95 #include <sys/callout.h> 96 #include <sys/device.h> 97 #include <sys/sockio.h> 98 #include <sys/mbuf.h> 99 #include <sys/malloc.h> 100 #include <sys/kernel.h> 101 #include <sys/socket.h> 102 103 #include <net/if.h> 104 #include <net/if_arp.h> 105 #include <net/if_ether.h> 106 #include <net/if_dl.h> 107 #include <net/if_media.h> 108 #ifdef INET 109 #include <netinet/in.h> 110 #include <netinet/if_inarp.h> 111 #endif 112 #ifdef NS 113 #include <netns/ns.h> 114 #include <netns/ns_if.h> 115 #endif 116 117 #if NBPFILTER > 0 118 #include <net/bpf.h> 119 #endif 120 #if NRND > 0 121 #include <sys/rnd.h> 122 #endif 123 124 #include <machine/bus.h> 125 #include <machine/endian.h> 126 127 #include <dev/mii/mii.h> 128 #include <dev/mii/miivar.h> 129 130 #include <dev/ic/rtl81x9reg.h> 131 #include <dev/ic/rtl81x9var.h> 132 133 #if defined DEBUG 134 #define STATIC 135 #else 136 #define STATIC static 137 #endif 138 139 STATIC void rtk_reset __P((struct rtk_softc *)); 140 STATIC void rtk_rxeof __P((struct rtk_softc *)); 141 STATIC void rtk_txeof __P((struct rtk_softc *)); 142 STATIC void rtk_start __P((struct ifnet *)); 143 STATIC int rtk_ioctl __P((struct ifnet *, u_long, caddr_t)); 144 STATIC void rtk_init __P((void *)); 145 STATIC void rtk_stop __P((struct rtk_softc *)); 146 STATIC void rtk_watchdog __P((struct ifnet *)); 147 STATIC void rtk_shutdown __P((void *)); 148 STATIC int rtk_ifmedia_upd __P((struct ifnet *)); 149 STATIC void rtk_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 150 151 STATIC u_int16_t rtk_read_eeprom __P((struct rtk_softc *, int, int)); 152 STATIC void rtk_eeprom_putbyte __P((struct rtk_softc *, int, int)); 153 STATIC void rtk_mii_sync __P((struct rtk_softc *)); 154 STATIC void rtk_mii_send __P((struct rtk_softc *, u_int32_t, int)); 155 STATIC int rtk_mii_readreg __P((struct rtk_softc *, struct rtk_mii_frame *)); 156 STATIC int rtk_mii_writereg __P((struct rtk_softc *, struct rtk_mii_frame *)); 157 158 STATIC int rtk_phy_readreg __P((struct device *, int, int)); 159 STATIC void rtk_phy_writereg __P((struct device *, int, int, int)); 160 STATIC void rtk_phy_statchg __P((struct device *)); 161 STATIC void rtk_tick __P((void *)); 162 163 STATIC int rtk_enable __P((struct rtk_softc *)); 164 STATIC void rtk_disable __P((struct rtk_softc *)); 165 STATIC void rtk_power __P((int, void *)); 166 167 STATIC void rtk_setmulti __P((struct rtk_softc *)); 168 STATIC int rtk_list_tx_init __P((struct rtk_softc *)); 169 170 STATIC int rtk_ether_ioctl __P((struct ifnet *, u_long, caddr_t)); 171 172 173 #define EE_SET(x) \ 174 CSR_WRITE_1(sc, RTK_EECMD, \ 175 CSR_READ_1(sc, RTK_EECMD) | (x)) 176 177 #define EE_CLR(x) \ 178 CSR_WRITE_1(sc, RTK_EECMD, \ 179 CSR_READ_1(sc, RTK_EECMD) & ~(x)) 180 181 /* 182 * Send a read command and address to the EEPROM, check for ACK. 183 */ 184 STATIC void rtk_eeprom_putbyte(sc, addr, addr_len) 185 struct rtk_softc *sc; 186 int addr, addr_len; 187 { 188 int d, i; 189 190 d = (RTK_EECMD_READ << addr_len) | addr; 191 192 /* 193 * Feed in each bit and stobe the clock. 194 */ 195 for (i = RTK_EECMD_LEN + addr_len - 1; i >= 0; i--) { 196 if (d & (1 << i)) { 197 EE_SET(RTK_EE_DATAIN); 198 } else { 199 EE_CLR(RTK_EE_DATAIN); 200 } 201 DELAY(100); 202 EE_SET(RTK_EE_CLK); 203 DELAY(150); 204 EE_CLR(RTK_EE_CLK); 205 DELAY(100); 206 } 207 } 208 209 /* 210 * Read a word of data stored in the EEPROM at address 'addr.' 211 */ 212 u_int16_t rtk_read_eeprom(sc, addr, addr_len) 213 struct rtk_softc *sc; 214 int addr, addr_len; 215 { 216 u_int16_t word = 0; 217 int i; 218 219 /* Enter EEPROM access mode. */ 220 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_PROGRAM|RTK_EE_SEL); 221 222 /* 223 * Send address of word we want to read. 224 */ 225 rtk_eeprom_putbyte(sc, addr, addr_len); 226 227 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_PROGRAM|RTK_EE_SEL); 228 229 /* 230 * Start reading bits from EEPROM. 231 */ 232 for (i = 15; i >= 0; i--) { 233 EE_SET(RTK_EE_CLK); 234 DELAY(100); 235 if (CSR_READ_1(sc, RTK_EECMD) & RTK_EE_DATAOUT) 236 word |= (1 << i); 237 EE_CLR(RTK_EE_CLK); 238 DELAY(100); 239 } 240 241 /* Turn off EEPROM access mode. */ 242 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 243 244 return (word); 245 } 246 247 /* 248 * MII access routines are provided for the 8129, which 249 * doesn't have a built-in PHY. For the 8139, we fake things 250 * up by diverting rtk_phy_readreg()/rtk_phy_writereg() to the 251 * direct access PHY registers. 252 */ 253 #define MII_SET(x) \ 254 CSR_WRITE_1(sc, RTK_MII, \ 255 CSR_READ_1(sc, RTK_MII) | (x)) 256 257 #define MII_CLR(x) \ 258 CSR_WRITE_1(sc, RTK_MII, \ 259 CSR_READ_1(sc, RTK_MII) & ~(x)) 260 261 /* 262 * Sync the PHYs by setting data bit and strobing the clock 32 times. 263 */ 264 STATIC void rtk_mii_sync(sc) 265 struct rtk_softc *sc; 266 { 267 int i; 268 269 MII_SET(RTK_MII_DIR|RTK_MII_DATAOUT); 270 271 for (i = 0; i < 32; i++) { 272 MII_SET(RTK_MII_CLK); 273 DELAY(1); 274 MII_CLR(RTK_MII_CLK); 275 DELAY(1); 276 } 277 278 return; 279 } 280 281 /* 282 * Clock a series of bits through the MII. 283 */ 284 STATIC void rtk_mii_send(sc, bits, cnt) 285 struct rtk_softc *sc; 286 u_int32_t bits; 287 int cnt; 288 { 289 int i; 290 291 MII_CLR(RTK_MII_CLK); 292 293 for (i = (0x1 << (cnt - 1)); i; i >>= 1) { 294 if (bits & i) { 295 MII_SET(RTK_MII_DATAOUT); 296 } else { 297 MII_CLR(RTK_MII_DATAOUT); 298 } 299 DELAY(1); 300 MII_CLR(RTK_MII_CLK); 301 DELAY(1); 302 MII_SET(RTK_MII_CLK); 303 } 304 } 305 306 /* 307 * Read an PHY register through the MII. 308 */ 309 STATIC int rtk_mii_readreg(sc, frame) 310 struct rtk_softc *sc; 311 struct rtk_mii_frame *frame; 312 313 { 314 int i, ack, s; 315 316 s = splnet(); 317 318 /* 319 * Set up frame for RX. 320 */ 321 frame->mii_stdelim = RTK_MII_STARTDELIM; 322 frame->mii_opcode = RTK_MII_READOP; 323 frame->mii_turnaround = 0; 324 frame->mii_data = 0; 325 326 CSR_WRITE_2(sc, RTK_MII, 0); 327 328 /* 329 * Turn on data xmit. 330 */ 331 MII_SET(RTK_MII_DIR); 332 333 rtk_mii_sync(sc); 334 335 /* 336 * Send command/address info. 337 */ 338 rtk_mii_send(sc, frame->mii_stdelim, 2); 339 rtk_mii_send(sc, frame->mii_opcode, 2); 340 rtk_mii_send(sc, frame->mii_phyaddr, 5); 341 rtk_mii_send(sc, frame->mii_regaddr, 5); 342 343 /* Idle bit */ 344 MII_CLR((RTK_MII_CLK|RTK_MII_DATAOUT)); 345 DELAY(1); 346 MII_SET(RTK_MII_CLK); 347 DELAY(1); 348 349 /* Turn off xmit. */ 350 MII_CLR(RTK_MII_DIR); 351 352 /* Check for ack */ 353 MII_CLR(RTK_MII_CLK); 354 DELAY(1); 355 MII_SET(RTK_MII_CLK); 356 DELAY(1); 357 ack = CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN; 358 359 /* 360 * Now try reading data bits. If the ack failed, we still 361 * need to clock through 16 cycles to keep the PHY(s) in sync. 362 */ 363 if (ack) { 364 for(i = 0; i < 16; i++) { 365 MII_CLR(RTK_MII_CLK); 366 DELAY(1); 367 MII_SET(RTK_MII_CLK); 368 DELAY(1); 369 } 370 goto fail; 371 } 372 373 for (i = 0x8000; i; i >>= 1) { 374 MII_CLR(RTK_MII_CLK); 375 DELAY(1); 376 if (!ack) { 377 if (CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN) 378 frame->mii_data |= i; 379 DELAY(1); 380 } 381 MII_SET(RTK_MII_CLK); 382 DELAY(1); 383 } 384 385 fail: 386 387 MII_CLR(RTK_MII_CLK); 388 DELAY(1); 389 MII_SET(RTK_MII_CLK); 390 DELAY(1); 391 392 splx(s); 393 394 if (ack) 395 return(1); 396 return(0); 397 } 398 399 /* 400 * Write to a PHY register through the MII. 401 */ 402 STATIC int rtk_mii_writereg(sc, frame) 403 struct rtk_softc *sc; 404 struct rtk_mii_frame *frame; 405 406 { 407 int s; 408 409 s = splnet(); 410 /* 411 * Set up frame for TX. 412 */ 413 414 frame->mii_stdelim = RTK_MII_STARTDELIM; 415 frame->mii_opcode = RTK_MII_WRITEOP; 416 frame->mii_turnaround = RTK_MII_TURNAROUND; 417 418 /* 419 * Turn on data output. 420 */ 421 MII_SET(RTK_MII_DIR); 422 423 rtk_mii_sync(sc); 424 425 rtk_mii_send(sc, frame->mii_stdelim, 2); 426 rtk_mii_send(sc, frame->mii_opcode, 2); 427 rtk_mii_send(sc, frame->mii_phyaddr, 5); 428 rtk_mii_send(sc, frame->mii_regaddr, 5); 429 rtk_mii_send(sc, frame->mii_turnaround, 2); 430 rtk_mii_send(sc, frame->mii_data, 16); 431 432 /* Idle bit. */ 433 MII_SET(RTK_MII_CLK); 434 DELAY(1); 435 MII_CLR(RTK_MII_CLK); 436 DELAY(1); 437 438 /* 439 * Turn off xmit. 440 */ 441 MII_CLR(RTK_MII_DIR); 442 443 splx(s); 444 445 return(0); 446 } 447 448 STATIC int rtk_phy_readreg(self, phy, reg) 449 struct device *self; 450 int phy, reg; 451 { 452 struct rtk_softc *sc = (void *)self; 453 struct rtk_mii_frame frame; 454 u_int16_t rval = 0; 455 u_int16_t rtk8139_reg = 0; 456 457 if (sc->rtk_type == RTK_8139) { 458 if (phy != 7) 459 return (0); 460 461 switch(reg) { 462 case MII_BMCR: 463 rtk8139_reg = RTK_BMCR; 464 break; 465 case MII_BMSR: 466 rtk8139_reg = RTK_BMSR; 467 break; 468 case MII_ANAR: 469 rtk8139_reg = RTK_ANAR; 470 break; 471 case MII_ANLPAR: 472 rtk8139_reg = RTK_LPAR; 473 break; 474 default: 475 #if 0 476 printf("%s: bad phy register\n", sc->sc_dev.dv_xname); 477 #endif 478 return(0); 479 } 480 rval = CSR_READ_2(sc, rtk8139_reg); 481 return(rval); 482 } 483 484 bzero((char *)&frame, sizeof(frame)); 485 486 frame.mii_phyaddr = phy; 487 frame.mii_regaddr = reg; 488 rtk_mii_readreg(sc, &frame); 489 490 return(frame.mii_data); 491 } 492 493 STATIC void rtk_phy_writereg(self, phy, reg, data) 494 struct device *self; 495 int phy, reg; 496 int data; 497 { 498 struct rtk_softc *sc = (void *)self; 499 struct rtk_mii_frame frame; 500 u_int16_t rtk8139_reg = 0; 501 502 if (sc->rtk_type == RTK_8139) { 503 if (phy != 7) 504 return; 505 506 switch(reg) { 507 case MII_BMCR: 508 rtk8139_reg = RTK_BMCR; 509 break; 510 case MII_BMSR: 511 rtk8139_reg = RTK_BMSR; 512 break; 513 case MII_ANAR: 514 rtk8139_reg = RTK_ANAR; 515 break; 516 case MII_ANLPAR: 517 rtk8139_reg = RTK_LPAR; 518 break; 519 default: 520 #if 0 521 printf("%s: bad phy register\n", sc->sc_dev.dv_xname); 522 #endif 523 return; 524 } 525 CSR_WRITE_2(sc, rtk8139_reg, data); 526 return; 527 } 528 529 bzero((char *)&frame, sizeof(frame)); 530 531 frame.mii_phyaddr = phy; 532 frame.mii_regaddr = reg; 533 frame.mii_data = data; 534 535 rtk_mii_writereg(sc, &frame); 536 537 return; 538 } 539 540 STATIC void 541 rtk_phy_statchg(v) 542 struct device *v; 543 { 544 545 /* Nothing to do. */ 546 } 547 548 #define rtk_calchash(addr) \ 549 (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 550 551 /* 552 * Program the 64-bit multicast hash filter. 553 */ 554 STATIC void rtk_setmulti(sc) 555 struct rtk_softc *sc; 556 { 557 struct ifnet *ifp; 558 int h = 0; 559 u_int32_t hashes[2] = { 0, 0 }; 560 u_int32_t rxfilt; 561 int mcnt = 0; 562 struct ether_multi *enm; 563 struct ether_multistep step; 564 565 ifp = &sc->ethercom.ec_if; 566 567 rxfilt = CSR_READ_4(sc, RTK_RXCFG); 568 569 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 570 rxfilt |= RTK_RXCFG_RX_MULTI; 571 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt); 572 CSR_WRITE_4(sc, RTK_MAR0, 0xFFFFFFFF); 573 CSR_WRITE_4(sc, RTK_MAR4, 0xFFFFFFFF); 574 return; 575 } 576 577 /* first, zot all the existing hash bits */ 578 CSR_WRITE_4(sc, RTK_MAR0, 0); 579 CSR_WRITE_4(sc, RTK_MAR4, 0); 580 581 /* now program new ones */ 582 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 583 while (enm != NULL) { 584 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 585 ETHER_ADDR_LEN) != 0) 586 continue; 587 588 h = rtk_calchash(enm->enm_addrlo); 589 if (h < 32) 590 hashes[0] |= (1 << h); 591 else 592 hashes[1] |= (1 << (h - 32)); 593 mcnt++; 594 ETHER_NEXT_MULTI(step, enm); 595 } 596 597 if (mcnt) 598 rxfilt |= RTK_RXCFG_RX_MULTI; 599 else 600 rxfilt &= ~RTK_RXCFG_RX_MULTI; 601 602 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt); 603 CSR_WRITE_4(sc, RTK_MAR0, hashes[0]); 604 CSR_WRITE_4(sc, RTK_MAR4, hashes[1]); 605 606 return; 607 } 608 609 void rtk_reset(sc) 610 struct rtk_softc *sc; 611 { 612 int i; 613 614 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 615 616 for (i = 0; i < RTK_TIMEOUT; i++) { 617 DELAY(10); 618 if (!(CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET)) 619 break; 620 } 621 if (i == RTK_TIMEOUT) 622 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname); 623 624 return; 625 } 626 627 /* 628 * Attach the interface. Allocate softc structures, do ifmedia 629 * setup and ethernet/BPF attach. 630 */ 631 void 632 rtk_attach(sc) 633 struct rtk_softc *sc; 634 { 635 636 struct ifnet *ifp; 637 u_int16_t val; 638 u_int8_t eaddr[ETHER_ADDR_LEN]; 639 int error; 640 int i,addr_len; 641 642 callout_init(&sc->rtk_tick_ch); 643 644 /* 645 * Check EEPROM type 9346 or 9356. 646 */ 647 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 648 addr_len = RTK_EEADDR_LEN1; 649 else 650 addr_len = RTK_EEADDR_LEN0; 651 652 /* 653 * Get station address. 654 */ 655 val = rtk_read_eeprom(sc, RTK_EE_EADDR0, addr_len); 656 eaddr[0] = val & 0xff; 657 eaddr[1] = val >> 8; 658 val = rtk_read_eeprom(sc, RTK_EE_EADDR1, addr_len); 659 eaddr[2] = val & 0xff; 660 eaddr[3] = val >> 8; 661 val = rtk_read_eeprom(sc, RTK_EE_EADDR2, addr_len); 662 eaddr[4] = val & 0xff; 663 eaddr[5] = val >> 8; 664 665 if ((error = bus_dmamem_alloc(sc->sc_dmat, 666 RTK_RXBUFLEN + 32, NBPG, 0, &sc->sc_dmaseg, 1, &sc->sc_dmanseg, 667 BUS_DMA_NOWAIT)) != 0) { 668 printf("%s: can't allocate recv buffer, error = %d\n", 669 sc->sc_dev.dv_xname, error); 670 goto fail_0; 671 } 672 673 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg, 674 RTK_RXBUFLEN + 32, (caddr_t *)&sc->rtk_cdata.rtk_rx_buf, 675 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 676 printf("%s: can't map recv buffer, error = %d\n", 677 sc->sc_dev.dv_xname, error); 678 goto fail_1; 679 } 680 681 /* Leave a few bytes before the start of the RX ring buffer. */ 682 sc->rtk_cdata.rtk_rx_buf_ptr = sc->rtk_cdata.rtk_rx_buf; 683 sc->rtk_cdata.rtk_rx_buf += sizeof(u_int64_t); 684 685 if ((error = bus_dmamap_create(sc->sc_dmat, 686 RTK_RXBUFLEN + 32 - sizeof(u_int64_t), 1, 687 RTK_RXBUFLEN + 32 - sizeof(u_int64_t), 0, BUS_DMA_NOWAIT, 688 &sc->recv_dmamap)) != 0) { 689 printf("%s: can't create recv buffer DMA map, error = %d\n", 690 sc->sc_dev.dv_xname, error); 691 goto fail_2; 692 } 693 694 if ((error = bus_dmamap_load(sc->sc_dmat, sc->recv_dmamap, 695 sc->rtk_cdata.rtk_rx_buf, RTK_RXBUFLEN + 32 - sizeof(u_int64_t), 696 NULL, BUS_DMA_NOWAIT)) != 0) { 697 printf("%s: can't load recv buffer DMA map, error = %d\n", 698 sc->sc_dev.dv_xname, error); 699 goto fail_3; 700 } 701 702 for (i = 0; i < RTK_TX_LIST_CNT; i++) 703 if ((error = bus_dmamap_create(sc->sc_dmat, 704 MCLBYTES, 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 705 &sc->snd_dmamap[i])) != 0) { 706 printf("%s: can't create snd buffer DMA map," 707 " error = %d\n", sc->sc_dev.dv_xname, error); 708 goto fail_4; 709 } 710 /* 711 * From this point forward, the attachment cannot fail. A failure 712 * before this releases all resources thar may have been 713 * allocated. 714 */ 715 sc->sc_flags |= RTK_ATTACHED; 716 717 /* Reset the adapter. */ 718 rtk_reset(sc); 719 720 printf("%s: Ethernet address %s\n", sc->sc_dev.dv_xname, 721 ether_sprintf(eaddr)); 722 723 ifp = &sc->ethercom.ec_if; 724 ifp->if_softc = sc; 725 bcopy(sc->sc_dev.dv_xname, ifp->if_xname, IFNAMSIZ); 726 ifp->if_mtu = ETHERMTU; 727 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 728 ifp->if_ioctl = rtk_ioctl; 729 #if 0 730 ifp->if_output = ether_output; 731 #endif 732 ifp->if_start = rtk_start; 733 ifp->if_watchdog = rtk_watchdog; 734 ifp->if_snd.ifq_maxlen = IFQ_MAXLEN; 735 736 /* 737 * Do ifmedia setup. 738 */ 739 sc->mii.mii_ifp = ifp; 740 sc->mii.mii_readreg = rtk_phy_readreg; 741 sc->mii.mii_writereg = rtk_phy_writereg; 742 sc->mii.mii_statchg = rtk_phy_statchg; 743 ifmedia_init(&sc->mii.mii_media, 0, rtk_ifmedia_upd, rtk_ifmedia_sts); 744 mii_attach(&sc->sc_dev, &sc->mii, 0xffffffff, 745 MII_PHY_ANY, MII_OFFSET_ANY, 0); 746 747 /* Choose a default media. */ 748 if (LIST_FIRST(&sc->mii.mii_phys) == NULL) { 749 ifmedia_add(&sc->mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 750 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_NONE); 751 } else { 752 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_AUTO); 753 } 754 755 /* 756 * Call MI attach routines. 757 */ 758 if_attach(ifp); 759 ether_ifattach(ifp, eaddr); 760 761 #if NBPFILTER > 0 762 bpfattach(&sc->ethercom.ec_if.if_bpf, ifp, DLT_EN10MB, 763 sizeof(struct ether_header)); 764 #endif 765 /* 766 * Make sure the interface is shutdown during reboot. 767 */ 768 sc->sc_sdhook = shutdownhook_establish(rtk_shutdown, sc); 769 if (sc->sc_sdhook == NULL) 770 printf("%s: WARNING: unbale to establish shutdown hook\n", 771 sc->sc_dev.dv_xname); 772 /* 773 * Add a suspend hook to make sure we come back up after a 774 * resume. 775 */ 776 sc->sc_powerhook = powerhook_establish(rtk_power, sc); 777 if (sc->sc_powerhook == NULL) 778 printf("%s: WARNING: unable to establish power hook\n", 779 sc->sc_dev.dv_xname); 780 781 return; 782 fail_4: 783 for (i = 0; i < RTK_TX_LIST_CNT; i++) 784 if (sc->snd_dmamap[i] != NULL) 785 bus_dmamap_destroy(sc->sc_dmat, sc->snd_dmamap[i]); 786 fail_3: 787 bus_dmamap_destroy(sc->sc_dmat, sc->recv_dmamap); 788 fail_2: 789 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rtk_cdata.rtk_rx_buf_ptr, 790 RTK_RXBUFLEN + 32 - sizeof(u_int64_t)); 791 fail_1: 792 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg); 793 fail_0: 794 return; 795 } 796 797 /* 798 * Initialize the transmit descriptors. 799 */ 800 STATIC int rtk_list_tx_init(sc) 801 struct rtk_softc *sc; 802 { 803 struct rtk_chain_data *cd; 804 int i; 805 806 cd = &sc->rtk_cdata; 807 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 808 cd->rtk_tx_chain[i] = NULL; 809 CSR_WRITE_4(sc, 810 RTK_TXADDR0 + (i * sizeof(u_int32_t)), 0x0000000); 811 } 812 813 sc->rtk_cdata.cur_tx = 0; 814 sc->rtk_cdata.last_tx = 0; 815 816 return(0); 817 } 818 819 /* 820 * rtk_activate: 821 * Handle device activation/deactivation requests. 822 */ 823 int 824 rtk_activate(self, act) 825 struct device *self; 826 enum devact act; 827 { 828 struct rtk_softc *sc = (void *) self; 829 int s, error = 0; 830 831 s = splnet(); 832 switch (act) { 833 case DVACT_ACTIVATE: 834 error = EOPNOTSUPP; 835 break; 836 case DVACT_DEACTIVATE: 837 mii_activate(&sc->mii, act, MII_PHY_ANY, MII_OFFSET_ANY); 838 if_deactivate(&sc->ethercom.ec_if); 839 break; 840 } 841 splx(s); 842 843 return (error); 844 } 845 846 /* 847 * rtk_detach: 848 * Detach a rtk interface. 849 */ 850 int 851 rtk_detach(sc) 852 struct rtk_softc *sc; 853 { 854 struct ifnet *ifp = &sc->ethercom.ec_if; 855 int i; 856 857 /* 858 * Succeed now if thereisn't any work to do. 859 */ 860 if ((sc->sc_flags & RTK_ATTACHED) == 0) 861 return (0); 862 863 /* Unhook our tick handler. */ 864 callout_stop(&sc->rtk_tick_ch); 865 866 /* Detach all PHYs. */ 867 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 868 869 /* Delete all remaining media. */ 870 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY); 871 872 #if NBPFILTER > 0 873 bpfdetach(ifp); 874 #endif 875 ether_ifdetach(ifp); 876 if_detach(ifp); 877 878 for (i = 0; i < RTK_TX_LIST_CNT; i++) 879 if (sc->snd_dmamap[i] != NULL) 880 bus_dmamap_destroy(sc->sc_dmat, sc->snd_dmamap[i]); 881 bus_dmamap_destroy(sc->sc_dmat, sc->recv_dmamap); 882 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rtk_cdata.rtk_rx_buf_ptr, 883 RTK_RXBUFLEN + 32 - sizeof(u_int64_t)); 884 885 shutdownhook_disestablish(sc->sc_sdhook); 886 powerhook_disestablish(sc->sc_powerhook); 887 888 return (0); 889 } 890 891 /* 892 * rtk_enable: 893 * Enable the RTL81X9 chip. 894 */ 895 int 896 rtk_enable(sc) 897 struct rtk_softc *sc; 898 { 899 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 900 if ((*sc->sc_enable)(sc) != 0) { 901 printf("%s: device enable failed\n", 902 sc->sc_dev.dv_xname); 903 return(EIO); 904 } 905 sc->sc_flags |= RTK_ENABLED; 906 } 907 return (0); 908 } 909 910 /* 911 * rtk_disable: 912 * Disable the RTL81X9 chip. 913 */ 914 void 915 rtk_disable(sc) 916 struct rtk_softc *sc; 917 { 918 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 919 (*sc->sc_disable)(sc); 920 sc->sc_flags &= ~RTK_ENABLED; 921 } 922 } 923 924 /* 925 * rtk_power: 926 * Power management (suspend/resume) hook. 927 */ 928 void 929 rtk_power(why, arg) 930 int why; 931 void *arg; 932 { 933 struct rtk_softc *sc = (void *) arg; 934 struct ifnet *ifp = &sc->ethercom.ec_if; 935 int s; 936 937 s = splnet(); 938 if (why != PWR_RESUME) { 939 rtk_stop(sc); 940 if (sc->sc_power != NULL) 941 (*sc->sc_power)(sc, why); 942 } else if (ifp->if_flags & IFF_UP) { 943 if (sc->sc_power != NULL) 944 (*sc->sc_power)(sc, why); 945 rtk_init(sc); 946 } 947 splx(s); 948 949 } 950 951 /* 952 * A frame has been uploaded: pass the resulting mbuf chain up to 953 * the higher level protocols. 954 * 955 * You know there's something wrong with a PCI bus-master chip design 956 * when you have to use m_devget(). 957 * 958 * The receive operation is badly documented in the datasheet, so I'll 959 * attempt to document it here. The driver provides a buffer area and 960 * places its base address in the RX buffer start address register. 961 * The chip then begins copying frames into the RX buffer. Each frame 962 * is preceeded by a 32-bit RX status word which specifies the length 963 * of the frame and certain other status bits. Each frame (starting with 964 * the status word) is also 32-bit aligned. The frame length is in the 965 * first 16 bits of the status word; the lower 15 bits correspond with 966 * the 'rx status register' mentioned in the datasheet. 967 * 968 * Note: to make the Alpha happy, the frame payload needs to be aligned 969 * on a 32-bit boundary. To achieve this, we cheat a bit by copying from 970 * the ring buffer starting at an address two bytes before the actual 971 * data location. We can then shave off the first two bytes using m_adj(). 972 * The reason we do this is because m_devget() doesn't let us specify an 973 * offset into the mbuf storage space, so we have to artificially create 974 * one. The ring is allocated in such a way that there are a few unused 975 * bytes of space preceecing it so that it will be safe for us to do the 976 * 2-byte backstep even if reading from the ring at offset 0. 977 */ 978 STATIC void rtk_rxeof(sc) 979 struct rtk_softc *sc; 980 { 981 struct ether_header *eh; 982 struct mbuf *m; 983 struct ifnet *ifp; 984 int total_len = 0; 985 u_int32_t rxstat; 986 caddr_t rxbufpos; 987 int wrap = 0; 988 u_int16_t cur_rx; 989 u_int16_t limit; 990 u_int16_t rx_bytes = 0, max_bytes; 991 992 ifp = &sc->ethercom.ec_if; 993 994 cur_rx = (CSR_READ_2(sc, RTK_CURRXADDR) + 16) % RTK_RXBUFLEN; 995 996 /* Do not try to read past this point. */ 997 limit = CSR_READ_2(sc, RTK_CURRXBUF) % RTK_RXBUFLEN; 998 999 if (limit < cur_rx) 1000 max_bytes = (RTK_RXBUFLEN - cur_rx) + limit; 1001 else 1002 max_bytes = limit - cur_rx; 1003 1004 while((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_EMPTY_RXBUF) == 0) { 1005 rxbufpos = sc->rtk_cdata.rtk_rx_buf + cur_rx; 1006 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 1007 sizeof(u_int32_t *), BUS_DMASYNC_POSTREAD); 1008 rxstat = le32toh(*(u_int32_t *)rxbufpos); 1009 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 1010 sizeof(u_int32_t *), BUS_DMASYNC_PREREAD); 1011 1012 /* 1013 * Here's a totally undocumented fact for you. When the 1014 * RealTek chip is in the process of copying a packet into 1015 * RAM for you, the length will be 0xfff0. If you spot a 1016 * packet header with this value, you need to stop. The 1017 * datasheet makes absolutely no mention of this and 1018 * RealTek should be shot for this. 1019 */ 1020 if ((u_int16_t)(rxstat >> 16) == RTK_RXSTAT_UNFINISHED) 1021 break; 1022 1023 if (!(rxstat & RTK_RXSTAT_RXOK)) { 1024 ifp->if_ierrors++; 1025 1026 /* 1027 * submitted by:[netbsd-pcmcia:00484] 1028 * Takahiro Kambe <taca@sky.yamashina.kyoto.jp> 1029 * obtain from: 1030 * FreeBSD if_rl.c rev 1.24->1.25 1031 * 1032 */ 1033 #if 0 1034 if (rxstat & (RTK_RXSTAT_BADSYM|RTK_RXSTAT_RUNT| 1035 RTK_RXSTAT_GIANT|RTK_RXSTAT_CRCERR| 1036 RTK_RXSTAT_ALIGNERR)) { 1037 if (rxstat & (RTK_RXSTAT_BADSYM|RTK_RXSTAT_RUNT| 1038 RTK_RXSTAT_GIANT|RTK_RXSTAT_CRCERR| 1039 RTK_RXSTAT_ALIGNERR)) { 1040 CSR_WRITE_2(sc, RTK_COMMAND, RTK_CMD_TX_ENB); 1041 CSR_WRITE_2(sc, RTK_COMMAND, RTK_CMD_TX_ENB| 1042 RTK_CMD_RX_ENB); 1043 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG); 1044 CSR_WRITE_4(sc, RTK_RXADDR, 1045 sc->recv_dmamap->dm_segs[0].ds_addr); 1046 CSR_WRITE_2(sc, RTK_CURRXADDR, cur_rx - 16); 1047 cur_rx = 0; 1048 } 1049 break; 1050 #else 1051 rtk_init(sc); 1052 return; 1053 #endif 1054 } 1055 1056 /* No errors; receive the packet. */ 1057 total_len = rxstat >> 16; 1058 rx_bytes += total_len + 4; 1059 1060 /* 1061 * XXX The RealTek chip includes the CRC with every 1062 * received frame, and there's no way to turn this 1063 * behavior off (at least, I can't find anything in 1064 * the manual that explains how to do it) so we have 1065 * to trim off the CRC manually. 1066 */ 1067 total_len -= ETHER_CRC_LEN; 1068 1069 /* 1070 * Avoid trying to read more bytes than we know 1071 * the chip has prepared for us. 1072 */ 1073 if (rx_bytes > max_bytes) 1074 break; 1075 1076 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1077 cur_rx + sizeof(u_int32_t), total_len, 1078 BUS_DMASYNC_POSTREAD); 1079 1080 rxbufpos = sc->rtk_cdata.rtk_rx_buf + 1081 ((cur_rx + sizeof(u_int32_t)) % RTK_RXBUFLEN); 1082 1083 if (rxbufpos == (sc->rtk_cdata.rtk_rx_buf + RTK_RXBUFLEN)) 1084 rxbufpos = sc->rtk_cdata.rtk_rx_buf; 1085 1086 wrap = (sc->rtk_cdata.rtk_rx_buf + RTK_RXBUFLEN) - rxbufpos; 1087 1088 if (total_len > wrap) { 1089 m = m_devget(rxbufpos - RTK_ETHER_ALIGN, 1090 wrap + RTK_ETHER_ALIGN, 0, ifp, NULL); 1091 if (m == NULL) { 1092 ifp->if_ierrors++; 1093 printf("%s: out of mbufs, tried to " 1094 "copy %d bytes\n", sc->sc_dev.dv_xname, 1095 wrap); 1096 } else { 1097 m_adj(m, RTK_ETHER_ALIGN); 1098 m_copyback(m, wrap, total_len - wrap, 1099 sc->rtk_cdata.rtk_rx_buf); 1100 } 1101 cur_rx = (total_len - wrap + ETHER_CRC_LEN); 1102 } else { 1103 m = m_devget(rxbufpos - RTK_ETHER_ALIGN, 1104 total_len + RTK_ETHER_ALIGN, 0, ifp, NULL); 1105 if (m == NULL) { 1106 ifp->if_ierrors++; 1107 printf("%s: out of mbufs, tried to " 1108 "copy %d bytes\n", sc->sc_dev.dv_xname, 1109 total_len); 1110 } else 1111 m_adj(m, RTK_ETHER_ALIGN); 1112 cur_rx += total_len + 4 + ETHER_CRC_LEN; 1113 } 1114 1115 /* 1116 * Round up to 32-bit boundary. 1117 */ 1118 cur_rx = (cur_rx + 3) & ~3; 1119 CSR_WRITE_2(sc, RTK_CURRXADDR, cur_rx - 16); 1120 1121 if (m == NULL) 1122 continue; 1123 1124 eh = mtod(m, struct ether_header *); 1125 ifp->if_ipackets++; 1126 1127 #if NBPFILTER > 0 1128 /* 1129 * Handle BPF listeners. Let the BPF user see the packet, but 1130 * don't pass it up to the ether_input() layer unless it's 1131 * a broadcast packet, multicast packet, matches our ethernet 1132 * address or the interface is in promiscuous mode. 1133 */ 1134 if (ifp->if_bpf) { 1135 bpf_mtap(ifp->if_bpf, m); 1136 if ((ifp->if_flags & IFF_PROMISC) != 0 && 1137 ETHER_IS_MULTICAST(eh->ether_dhost) == 0 && 1138 memcmp(eh->ether_dhost, LLADDR(ifp->if_sadl), 1139 ETHER_ADDR_LEN) != 0) { 1140 m_freem(m); 1141 continue; 1142 } 1143 } 1144 #endif 1145 /* pass it on. */ 1146 (*ifp->if_input)(ifp, m); 1147 1148 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1149 cur_rx + sizeof(u_int32_t), 1150 total_len, BUS_DMASYNC_PREREAD); 1151 } 1152 1153 return; 1154 } 1155 1156 /* 1157 * A frame was downloaded to the chip. It's safe for us to clean up 1158 * the list buffers. 1159 */ 1160 STATIC void rtk_txeof(sc) 1161 struct rtk_softc *sc; 1162 { 1163 struct ifnet *ifp; 1164 u_int32_t txstat; 1165 1166 ifp = &sc->ethercom.ec_if; 1167 1168 /* Clear the timeout timer. */ 1169 ifp->if_timer = 0; 1170 1171 /* 1172 * Go through our tx list and free mbufs for those 1173 * frames that have been uploaded. 1174 */ 1175 do { 1176 txstat = CSR_READ_4(sc, RTK_LAST_TXSTAT(sc)); 1177 if (!(txstat & (RTK_TXSTAT_TX_OK| 1178 RTK_TXSTAT_TX_UNDERRUN|RTK_TXSTAT_TXABRT))) 1179 break; 1180 1181 bus_dmamap_sync(sc->sc_dmat, 1182 sc->snd_dmamap[sc->rtk_cdata.last_tx], 0, 1183 sc->snd_dmamap[sc->rtk_cdata.last_tx]->dm_mapsize, 1184 BUS_DMASYNC_POSTWRITE); 1185 bus_dmamap_unload(sc->sc_dmat, 1186 sc->snd_dmamap[sc->rtk_cdata.last_tx]); 1187 m_freem(RTK_LAST_TXMBUF(sc)); 1188 RTK_LAST_TXMBUF(sc) = NULL; 1189 1190 ifp->if_collisions += (txstat & RTK_TXSTAT_COLLCNT) >> 24; 1191 1192 if (txstat & RTK_TXSTAT_TX_OK) 1193 ifp->if_opackets++; 1194 else { 1195 ifp->if_oerrors++; 1196 if ((txstat & RTK_TXSTAT_TXABRT) || 1197 (txstat & RTK_TXSTAT_OUTOFWIN)) 1198 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG); 1199 } 1200 RTK_INC(sc->rtk_cdata.last_tx); 1201 ifp->if_flags &= ~IFF_OACTIVE; 1202 } while (sc->rtk_cdata.last_tx != sc->rtk_cdata.cur_tx); 1203 1204 return; 1205 } 1206 1207 int rtk_intr(arg) 1208 void *arg; 1209 { 1210 struct rtk_softc *sc; 1211 struct ifnet *ifp; 1212 u_int16_t status; 1213 int handled = 0; 1214 1215 sc = arg; 1216 ifp = &sc->ethercom.ec_if; 1217 1218 /* Disable interrupts. */ 1219 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1220 1221 for (;;) { 1222 1223 status = CSR_READ_2(sc, RTK_ISR); 1224 if (status) 1225 CSR_WRITE_2(sc, RTK_ISR, status); 1226 1227 handled = 1; 1228 1229 if ((status & RTK_INTRS) == 0) 1230 break; 1231 1232 if (status & RTK_ISR_RX_OK) 1233 rtk_rxeof(sc); 1234 1235 if (status & RTK_ISR_RX_ERR) 1236 rtk_rxeof(sc); 1237 1238 if ((status & RTK_ISR_TX_OK) || (status & RTK_ISR_TX_ERR)) 1239 rtk_txeof(sc); 1240 1241 if (status & RTK_ISR_SYSTEM_ERR) { 1242 rtk_reset(sc); 1243 rtk_init(sc); 1244 } 1245 1246 } 1247 1248 /* Re-enable interrupts. */ 1249 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS); 1250 1251 if (ifp->if_snd.ifq_head != NULL) { 1252 rtk_start(ifp); 1253 } 1254 1255 return (handled); 1256 } 1257 1258 /* 1259 * Main transmit routine. 1260 */ 1261 1262 STATIC void rtk_start(ifp) 1263 struct ifnet *ifp; 1264 { 1265 struct rtk_softc *sc; 1266 struct mbuf *m_head = NULL, *m_new; 1267 int error, idx, len; 1268 1269 sc = ifp->if_softc; 1270 1271 while(RTK_CUR_TXMBUF(sc) == NULL) { 1272 IF_DEQUEUE(&ifp->if_snd, m_head); 1273 if (m_head == NULL) 1274 break; 1275 1276 idx = sc->rtk_cdata.cur_tx; 1277 1278 /* 1279 * Load the DMA map. If this fails, the packet didn't 1280 * fit in one DMA segment, and we need to copy. Note, 1281 * the packet must also be aligned. 1282 */ 1283 if ((mtod(m_head, bus_addr_t) & 3) != 0 || 1284 bus_dmamap_load_mbuf(sc->sc_dmat, sc->snd_dmamap[idx], 1285 m_head, BUS_DMA_NOWAIT) != 0) { 1286 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1287 if (m_new == NULL) { 1288 printf("%s: unable to allocate Tx mbuf\n", 1289 sc->sc_dev.dv_xname); 1290 IF_PREPEND(&ifp->if_snd, m_new); 1291 break; 1292 } 1293 if (m_head->m_pkthdr.len > MHLEN) { 1294 MCLGET(m_new, M_DONTWAIT); 1295 if ((m_new->m_flags & M_EXT) == 0) { 1296 printf("%s: unable to allocate Tx " 1297 "cluster\n", sc->sc_dev.dv_xname); 1298 m_freem(m_new); 1299 IF_PREPEND(&ifp->if_snd, m_head); 1300 break; 1301 } 1302 } 1303 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1304 mtod(m_new, caddr_t)); 1305 m_new->m_pkthdr.len = m_new->m_len = 1306 m_head->m_pkthdr.len; 1307 m_freem(m_head); 1308 m_head = m_new; 1309 error = bus_dmamap_load_mbuf(sc->sc_dmat, 1310 sc->snd_dmamap[idx], m_head, BUS_DMA_NOWAIT); 1311 if (error) { 1312 printf("%s: unable to load Tx buffer, " 1313 "error = %d\n", sc->sc_dev.dv_xname, error); 1314 IF_PREPEND(&ifp->if_snd, m_head); 1315 break; 1316 } 1317 } 1318 1319 RTK_CUR_TXMBUF(sc) = m_head; 1320 1321 #if NBPFILTER > 0 1322 /* 1323 * If there's a BPF listener, bounce a copy of this frame 1324 * to him. 1325 */ 1326 if (ifp->if_bpf) 1327 bpf_mtap(ifp->if_bpf, RTK_CUR_TXMBUF(sc)); 1328 #endif 1329 /* 1330 * Transmit the frame. 1331 */ 1332 bus_dmamap_sync(sc->sc_dmat, 1333 sc->snd_dmamap[idx], 0, sc->snd_dmamap[idx]->dm_mapsize, 1334 BUS_DMASYNC_PREWRITE); 1335 1336 len = sc->snd_dmamap[idx]->dm_segs[0].ds_len; 1337 if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 1338 len = (ETHER_MIN_LEN - ETHER_CRC_LEN); 1339 1340 CSR_WRITE_4(sc, RTK_CUR_TXADDR(sc), 1341 sc->snd_dmamap[idx]->dm_segs[0].ds_addr); 1342 CSR_WRITE_4(sc, RTK_CUR_TXSTAT(sc), RTK_TX_EARLYTHRESH | len); 1343 1344 RTK_INC(sc->rtk_cdata.cur_tx); 1345 } 1346 1347 /* 1348 * We broke out of the loop because all our TX slots are 1349 * full. Mark the NIC as busy until it drains some of the 1350 * packets from the queue. 1351 */ 1352 if (RTK_CUR_TXMBUF(sc) != NULL) 1353 ifp->if_flags |= IFF_OACTIVE; 1354 1355 /* 1356 * Set a timeout in case the chip goes out to lunch. 1357 */ 1358 ifp->if_timer = 5; 1359 1360 return; 1361 } 1362 1363 STATIC void rtk_init(xsc) 1364 void *xsc; 1365 { 1366 struct rtk_softc *sc = xsc; 1367 struct ifnet *ifp = &sc->ethercom.ec_if; 1368 int s, i; 1369 u_int32_t rxcfg; 1370 u_int16_t phy_bmcr = 0; 1371 1372 s = splnet(); 1373 1374 /* 1375 * XXX Hack for the 8139: the built-in autoneg logic's state 1376 * gets reset by rtk_init() when we don't want it to. Try 1377 * to preserve it. 1378 */ 1379 if (sc->rtk_type == RTK_8139) 1380 phy_bmcr = rtk_phy_readreg((struct device *)sc, 7, MII_BMCR); 1381 1382 /* 1383 * Cancel pending I/O and free all RX/TX buffers. 1384 */ 1385 rtk_stop(sc); 1386 1387 /* Init our MAC address */ 1388 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1389 CSR_WRITE_1(sc, RTK_IDR0 + i, LLADDR(ifp->if_sadl)[i]); 1390 } 1391 1392 /* Init the RX buffer pointer register. */ 1393 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 0, 1394 sc->recv_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1395 CSR_WRITE_4(sc, RTK_RXADDR, sc->recv_dmamap->dm_segs[0].ds_addr); 1396 1397 /* Init TX descriptors. */ 1398 rtk_list_tx_init(sc); 1399 1400 /* 1401 * Enable transmit and receive. 1402 */ 1403 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1404 1405 /* 1406 * Set the initial TX and RX configuration. 1407 */ 1408 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG); 1409 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG); 1410 1411 /* Set the individual bit to receive frames for this host only. */ 1412 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 1413 rxcfg |= RTK_RXCFG_RX_INDIV; 1414 1415 /* If we want promiscuous mode, set the allframes bit. */ 1416 if (ifp->if_flags & IFF_PROMISC) { 1417 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 1418 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1419 } else { 1420 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 1421 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1422 } 1423 1424 /* 1425 * Set capture broadcast bit to capture broadcast frames. 1426 */ 1427 if (ifp->if_flags & IFF_BROADCAST) { 1428 rxcfg |= RTK_RXCFG_RX_BROAD; 1429 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1430 } else { 1431 rxcfg &= ~RTK_RXCFG_RX_BROAD; 1432 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1433 } 1434 1435 /* 1436 * Program the multicast filter, if necessary. 1437 */ 1438 rtk_setmulti(sc); 1439 1440 /* 1441 * Enable interrupts. 1442 */ 1443 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS); 1444 1445 /* Start RX/TX process. */ 1446 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 1447 1448 /* Enable receiver and transmitter. */ 1449 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1450 1451 /* Restore state of BMCR */ 1452 if (sc->rtk_type == RTK_8139) 1453 rtk_phy_writereg((struct device *)sc, 7, MII_BMCR, phy_bmcr); 1454 1455 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD|RTK_CFG1_FULLDUPLEX); 1456 1457 /* 1458 * Set current media. 1459 */ 1460 mii_mediachg(&sc->mii); 1461 1462 ifp->if_flags |= IFF_RUNNING; 1463 ifp->if_flags &= ~IFF_OACTIVE; 1464 1465 (void)splx(s); 1466 1467 callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc); 1468 } 1469 1470 /* 1471 * Set media options. 1472 */ 1473 STATIC int rtk_ifmedia_upd(ifp) 1474 struct ifnet *ifp; 1475 { 1476 struct rtk_softc *sc; 1477 struct ifmedia *ifm; 1478 1479 sc = ifp->if_softc; 1480 ifm = &sc->mii.mii_media; 1481 1482 if (IFM_TYPE(ifm->ifm_media) != IFM_ETHER) 1483 return(EINVAL); 1484 1485 return (mii_mediachg(&sc->mii)); 1486 } 1487 1488 /* 1489 * Report current media status. 1490 */ 1491 STATIC void rtk_ifmedia_sts(ifp, ifmr) 1492 struct ifnet *ifp; 1493 struct ifmediareq *ifmr; 1494 { 1495 struct rtk_softc *sc; 1496 1497 sc = ifp->if_softc; 1498 1499 mii_pollstat(&sc->mii); 1500 ifmr->ifm_status = sc->mii.mii_media_status; 1501 ifmr->ifm_active = sc->mii.mii_media_active; 1502 } 1503 1504 STATIC int 1505 rtk_ether_ioctl(ifp, cmd, data) 1506 struct ifnet *ifp; 1507 u_long cmd; 1508 caddr_t data; 1509 { 1510 struct ifaddr *ifa = (struct ifaddr *) data; 1511 struct rtk_softc *sc = ifp->if_softc; 1512 int error = 0; 1513 1514 switch (cmd) { 1515 case SIOCSIFADDR: 1516 if ((error = rtk_enable(sc)) != 0) 1517 break; 1518 ifp->if_flags |= IFF_UP; 1519 1520 switch (ifa->ifa_addr->sa_family) { 1521 #ifdef INET 1522 case AF_INET: 1523 rtk_init(sc); 1524 arp_ifinit(ifp, ifa); 1525 break; 1526 #endif 1527 #ifdef NS 1528 case AF_NS: 1529 { 1530 struct ns_addr *ina = &IA_SNS(ifa)->sns_addr; 1531 1532 if (ns_nullhost(*ina)) 1533 ina->x_host = *(union ns_host *) 1534 LLADDR(ifp->if_sadl); 1535 else 1536 bcopy(ina->x_host.c_host, LLADDR(ifp->if_sadl), 1537 ifp->if_addrlen); 1538 /* Set new address. */ 1539 rtk_init(sc); 1540 break; 1541 } 1542 #endif 1543 default: 1544 rtk_init(sc); 1545 break; 1546 } 1547 break; 1548 1549 default: 1550 return (EINVAL); 1551 } 1552 1553 return (error); 1554 } 1555 1556 STATIC int rtk_ioctl(ifp, command, data) 1557 struct ifnet *ifp; 1558 u_long command; 1559 caddr_t data; 1560 { 1561 struct rtk_softc *sc = ifp->if_softc; 1562 struct ifreq *ifr = (struct ifreq *) data; 1563 int s, error = 0; 1564 1565 s = splnet(); 1566 1567 switch(command) { 1568 case SIOCSIFADDR: 1569 case SIOCGIFADDR: 1570 case SIOCSIFMTU: 1571 error = rtk_ether_ioctl(ifp, command, data); 1572 break; 1573 case SIOCSIFFLAGS: 1574 if (ifp->if_flags & IFF_UP) { 1575 if ((error = rtk_enable(sc)) != 0) 1576 break; 1577 rtk_init(sc); 1578 } else { 1579 if (ifp->if_flags & IFF_RUNNING) { 1580 rtk_stop(sc); 1581 rtk_disable(sc); 1582 } 1583 } 1584 error = 0; 1585 break; 1586 case SIOCADDMULTI: 1587 case SIOCDELMULTI: 1588 rtk_setmulti(sc); 1589 error = 0; 1590 break; 1591 case SIOCGIFMEDIA: 1592 case SIOCSIFMEDIA: 1593 error = ifmedia_ioctl(ifp, ifr, &sc->mii.mii_media, command); 1594 break; 1595 default: 1596 error = EINVAL; 1597 break; 1598 } 1599 1600 (void)splx(s); 1601 1602 return(error); 1603 } 1604 1605 STATIC void rtk_watchdog(ifp) 1606 struct ifnet *ifp; 1607 { 1608 struct rtk_softc *sc; 1609 1610 sc = ifp->if_softc; 1611 1612 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1613 ifp->if_oerrors++; 1614 rtk_txeof(sc); 1615 rtk_rxeof(sc); 1616 rtk_init(sc); 1617 1618 return; 1619 } 1620 1621 /* 1622 * Stop the adapter and free any mbufs allocated to the 1623 * RX and TX lists. 1624 */ 1625 STATIC void rtk_stop(sc) 1626 struct rtk_softc *sc; 1627 { 1628 int i; 1629 struct ifnet *ifp; 1630 1631 ifp = &sc->ethercom.ec_if; 1632 ifp->if_timer = 0; 1633 1634 callout_stop(&sc->rtk_tick_ch); 1635 1636 mii_down(&sc->mii); 1637 1638 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 1639 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1640 1641 /* 1642 * Free the TX list buffers. 1643 */ 1644 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 1645 if (sc->rtk_cdata.rtk_tx_chain[i] != NULL) { 1646 bus_dmamap_unload(sc->sc_dmat, sc->snd_dmamap[i]); 1647 m_freem(sc->rtk_cdata.rtk_tx_chain[i]); 1648 sc->rtk_cdata.rtk_tx_chain[i] = NULL; 1649 CSR_WRITE_4(sc, RTK_TXADDR0 + i, 0x0000000); 1650 } 1651 } 1652 1653 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1654 1655 return; 1656 } 1657 1658 /* 1659 * Stop all chip I/O so that the kernel's probe routines don't 1660 * get confused by errant DMAs when rebooting. 1661 */ 1662 STATIC void rtk_shutdown(vsc) 1663 void *vsc; 1664 { 1665 struct rtk_softc *sc = (struct rtk_softc *)vsc; 1666 1667 rtk_stop(sc); 1668 1669 return; 1670 } 1671 1672 STATIC void 1673 rtk_tick(arg) 1674 void *arg; 1675 { 1676 struct rtk_softc *sc = arg; 1677 int s = splnet(); 1678 1679 mii_tick(&sc->mii); 1680 splx(s); 1681 1682 callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc); 1683 } 1684