1 /* $NetBSD: rtl81x9.c,v 1.36 2001/07/25 09:57:31 kanaoka Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998 5 * Bill Paul <wpaul@ctr.columbia.edu>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 * 34 * FreeBSD Id: if_rl.c,v 1.17 1999/06/19 20:17:37 wpaul Exp 35 */ 36 37 /* 38 * RealTek 8129/8139 PCI NIC driver 39 * 40 * Supports several extremely cheap PCI 10/100 adapters based on 41 * the RealTek chipset. Datasheets can be obtained from 42 * www.realtek.com.tw. 43 * 44 * Written by Bill Paul <wpaul@ctr.columbia.edu> 45 * Electrical Engineering Department 46 * Columbia University, New York City 47 */ 48 49 /* 50 * The RealTek 8139 PCI NIC redefines the meaning of 'low end.' This is 51 * probably the worst PCI ethernet controller ever made, with the possible 52 * exception of the FEAST chip made by SMC. The 8139 supports bus-master 53 * DMA, but it has a terrible interface that nullifies any performance 54 * gains that bus-master DMA usually offers. 55 * 56 * For transmission, the chip offers a series of four TX descriptor 57 * registers. Each transmit frame must be in a contiguous buffer, aligned 58 * on a longword (32-bit) boundary. This means we almost always have to 59 * do mbuf copies in order to transmit a frame, except in the unlikely 60 * case where a) the packet fits into a single mbuf, and b) the packet 61 * is 32-bit aligned within the mbuf's data area. The presence of only 62 * four descriptor registers means that we can never have more than four 63 * packets queued for transmission at any one time. 64 * 65 * Reception is not much better. The driver has to allocate a single large 66 * buffer area (up to 64K in size) into which the chip will DMA received 67 * frames. Because we don't know where within this region received packets 68 * will begin or end, we have no choice but to copy data from the buffer 69 * area into mbufs in order to pass the packets up to the higher protocol 70 * levels. 71 * 72 * It's impossible given this rotten design to really achieve decent 73 * performance at 100Mbps, unless you happen to have a 400Mhz PII or 74 * some equally overmuscled CPU to drive it. 75 * 76 * On the bright side, the 8139 does have a built-in PHY, although 77 * rather than using an MDIO serial interface like most other NICs, the 78 * PHY registers are directly accessible through the 8139's register 79 * space. The 8139 supports autonegotiation, as well as a 64-bit multicast 80 * filter. 81 * 82 * The 8129 chip is an older version of the 8139 that uses an external PHY 83 * chip. The 8129 has a serial MDIO interface for accessing the MII where 84 * the 8139 lets you directly access the on-board PHY registers. We need 85 * to select which interface to use depending on the chip type. 86 */ 87 88 #include "bpfilter.h" 89 #include "rnd.h" 90 91 #include <sys/param.h> 92 #include <sys/systm.h> 93 #include <sys/callout.h> 94 #include <sys/device.h> 95 #include <sys/sockio.h> 96 #include <sys/mbuf.h> 97 #include <sys/malloc.h> 98 #include <sys/kernel.h> 99 #include <sys/socket.h> 100 101 #include <uvm/uvm_extern.h> 102 103 #include <net/if.h> 104 #include <net/if_arp.h> 105 #include <net/if_ether.h> 106 #include <net/if_dl.h> 107 #include <net/if_media.h> 108 109 #if NBPFILTER > 0 110 #include <net/bpf.h> 111 #endif 112 #if NRND > 0 113 #include <sys/rnd.h> 114 #endif 115 116 #include <machine/bus.h> 117 #include <machine/endian.h> 118 119 #include <dev/mii/mii.h> 120 #include <dev/mii/miivar.h> 121 122 #include <dev/ic/rtl81x9reg.h> 123 #include <dev/ic/rtl81x9var.h> 124 125 #if defined(DEBUG) 126 #define STATIC 127 #else 128 #define STATIC static 129 #endif 130 131 STATIC void rtk_reset __P((struct rtk_softc *)); 132 STATIC void rtk_rxeof __P((struct rtk_softc *)); 133 STATIC void rtk_txeof __P((struct rtk_softc *)); 134 STATIC void rtk_start __P((struct ifnet *)); 135 STATIC int rtk_ioctl __P((struct ifnet *, u_long, caddr_t)); 136 STATIC int rtk_init __P((struct ifnet *)); 137 STATIC void rtk_stop __P((struct ifnet *, int)); 138 139 STATIC void rtk_watchdog __P((struct ifnet *)); 140 STATIC void rtk_shutdown __P((void *)); 141 STATIC int rtk_ifmedia_upd __P((struct ifnet *)); 142 STATIC void rtk_ifmedia_sts __P((struct ifnet *, struct ifmediareq *)); 143 144 STATIC u_int16_t rtk_read_eeprom __P((struct rtk_softc *, int, int)); 145 STATIC void rtk_eeprom_putbyte __P((struct rtk_softc *, int, int)); 146 STATIC void rtk_mii_sync __P((struct rtk_softc *)); 147 STATIC void rtk_mii_send __P((struct rtk_softc *, u_int32_t, int)); 148 STATIC int rtk_mii_readreg __P((struct rtk_softc *, struct rtk_mii_frame *)); 149 STATIC int rtk_mii_writereg __P((struct rtk_softc *, struct rtk_mii_frame *)); 150 151 STATIC int rtk_phy_readreg __P((struct device *, int, int)); 152 STATIC void rtk_phy_writereg __P((struct device *, int, int, int)); 153 STATIC void rtk_phy_statchg __P((struct device *)); 154 STATIC void rtk_tick __P((void *)); 155 156 STATIC int rtk_enable __P((struct rtk_softc *)); 157 STATIC void rtk_disable __P((struct rtk_softc *)); 158 STATIC void rtk_power __P((int, void *)); 159 160 STATIC void rtk_setmulti __P((struct rtk_softc *)); 161 STATIC int rtk_list_tx_init __P((struct rtk_softc *)); 162 163 #define EE_SET(x) \ 164 CSR_WRITE_1(sc, RTK_EECMD, \ 165 CSR_READ_1(sc, RTK_EECMD) | (x)) 166 167 #define EE_CLR(x) \ 168 CSR_WRITE_1(sc, RTK_EECMD, \ 169 CSR_READ_1(sc, RTK_EECMD) & ~(x)) 170 171 /* 172 * Send a read command and address to the EEPROM, check for ACK. 173 */ 174 STATIC void rtk_eeprom_putbyte(sc, addr, addr_len) 175 struct rtk_softc *sc; 176 int addr, addr_len; 177 { 178 int d, i; 179 180 d = (RTK_EECMD_READ << addr_len) | addr; 181 182 /* 183 * Feed in each bit and stobe the clock. 184 */ 185 for (i = RTK_EECMD_LEN + addr_len; i > 0; i--) { 186 if (d & (1 << (i - 1))) { 187 EE_SET(RTK_EE_DATAIN); 188 } else { 189 EE_CLR(RTK_EE_DATAIN); 190 } 191 DELAY(4); 192 EE_SET(RTK_EE_CLK); 193 DELAY(4); 194 EE_CLR(RTK_EE_CLK); 195 DELAY(4); 196 } 197 } 198 199 /* 200 * Read a word of data stored in the EEPROM at address 'addr.' 201 */ 202 u_int16_t rtk_read_eeprom(sc, addr, addr_len) 203 struct rtk_softc *sc; 204 int addr, addr_len; 205 { 206 u_int16_t word = 0; 207 int i; 208 209 /* Enter EEPROM access mode. */ 210 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_PROGRAM|RTK_EE_SEL); 211 212 /* 213 * Send address of word we want to read. 214 */ 215 rtk_eeprom_putbyte(sc, addr, addr_len); 216 217 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_PROGRAM|RTK_EE_SEL); 218 219 /* 220 * Start reading bits from EEPROM. 221 */ 222 for (i = 16; i > 0; i--) { 223 EE_SET(RTK_EE_CLK); 224 DELAY(4); 225 if (CSR_READ_1(sc, RTK_EECMD) & RTK_EE_DATAOUT) 226 word |= 1 << (i - 1); 227 EE_CLR(RTK_EE_CLK); 228 DELAY(4); 229 } 230 231 /* Turn off EEPROM access mode. */ 232 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 233 234 return (word); 235 } 236 237 /* 238 * MII access routines are provided for the 8129, which 239 * doesn't have a built-in PHY. For the 8139, we fake things 240 * up by diverting rtk_phy_readreg()/rtk_phy_writereg() to the 241 * direct access PHY registers. 242 */ 243 #define MII_SET(x) \ 244 CSR_WRITE_1(sc, RTK_MII, \ 245 CSR_READ_1(sc, RTK_MII) | (x)) 246 247 #define MII_CLR(x) \ 248 CSR_WRITE_1(sc, RTK_MII, \ 249 CSR_READ_1(sc, RTK_MII) & ~(x)) 250 251 /* 252 * Sync the PHYs by setting data bit and strobing the clock 32 times. 253 */ 254 STATIC void rtk_mii_sync(sc) 255 struct rtk_softc *sc; 256 { 257 int i; 258 259 MII_SET(RTK_MII_DIR|RTK_MII_DATAOUT); 260 261 for (i = 0; i < 32; i++) { 262 MII_SET(RTK_MII_CLK); 263 DELAY(1); 264 MII_CLR(RTK_MII_CLK); 265 DELAY(1); 266 } 267 } 268 269 /* 270 * Clock a series of bits through the MII. 271 */ 272 STATIC void rtk_mii_send(sc, bits, cnt) 273 struct rtk_softc *sc; 274 u_int32_t bits; 275 int cnt; 276 { 277 int i; 278 279 MII_CLR(RTK_MII_CLK); 280 281 for (i = cnt; i > 0; i--) { 282 if (bits & (1 << (i - 1))) { 283 MII_SET(RTK_MII_DATAOUT); 284 } else { 285 MII_CLR(RTK_MII_DATAOUT); 286 } 287 DELAY(1); 288 MII_CLR(RTK_MII_CLK); 289 DELAY(1); 290 MII_SET(RTK_MII_CLK); 291 } 292 } 293 294 /* 295 * Read an PHY register through the MII. 296 */ 297 STATIC int rtk_mii_readreg(sc, frame) 298 struct rtk_softc *sc; 299 struct rtk_mii_frame *frame; 300 { 301 int i, ack, s; 302 303 s = splnet(); 304 305 /* 306 * Set up frame for RX. 307 */ 308 frame->mii_stdelim = RTK_MII_STARTDELIM; 309 frame->mii_opcode = RTK_MII_READOP; 310 frame->mii_turnaround = 0; 311 frame->mii_data = 0; 312 313 CSR_WRITE_2(sc, RTK_MII, 0); 314 315 /* 316 * Turn on data xmit. 317 */ 318 MII_SET(RTK_MII_DIR); 319 320 rtk_mii_sync(sc); 321 322 /* 323 * Send command/address info. 324 */ 325 rtk_mii_send(sc, frame->mii_stdelim, 2); 326 rtk_mii_send(sc, frame->mii_opcode, 2); 327 rtk_mii_send(sc, frame->mii_phyaddr, 5); 328 rtk_mii_send(sc, frame->mii_regaddr, 5); 329 330 /* Idle bit */ 331 MII_CLR((RTK_MII_CLK|RTK_MII_DATAOUT)); 332 DELAY(1); 333 MII_SET(RTK_MII_CLK); 334 DELAY(1); 335 336 /* Turn off xmit. */ 337 MII_CLR(RTK_MII_DIR); 338 339 /* Check for ack */ 340 MII_CLR(RTK_MII_CLK); 341 DELAY(1); 342 MII_SET(RTK_MII_CLK); 343 DELAY(1); 344 ack = CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN; 345 346 /* 347 * Now try reading data bits. If the ack failed, we still 348 * need to clock through 16 cycles to keep the PHY(s) in sync. 349 */ 350 if (ack) { 351 for (i = 0; i < 16; i++) { 352 MII_CLR(RTK_MII_CLK); 353 DELAY(1); 354 MII_SET(RTK_MII_CLK); 355 DELAY(1); 356 } 357 goto fail; 358 } 359 360 for (i = 16; i > 0; i--) { 361 MII_CLR(RTK_MII_CLK); 362 DELAY(1); 363 if (!ack) { 364 if (CSR_READ_2(sc, RTK_MII) & RTK_MII_DATAIN) 365 frame->mii_data |= 1 << (i - 1); 366 DELAY(1); 367 } 368 MII_SET(RTK_MII_CLK); 369 DELAY(1); 370 } 371 372 fail: 373 MII_CLR(RTK_MII_CLK); 374 DELAY(1); 375 MII_SET(RTK_MII_CLK); 376 DELAY(1); 377 378 splx(s); 379 380 if (ack) 381 return (1); 382 return (0); 383 } 384 385 /* 386 * Write to a PHY register through the MII. 387 */ 388 STATIC int rtk_mii_writereg(sc, frame) 389 struct rtk_softc *sc; 390 struct rtk_mii_frame *frame; 391 { 392 int s; 393 394 s = splnet(); 395 /* 396 * Set up frame for TX. 397 */ 398 frame->mii_stdelim = RTK_MII_STARTDELIM; 399 frame->mii_opcode = RTK_MII_WRITEOP; 400 frame->mii_turnaround = RTK_MII_TURNAROUND; 401 402 /* 403 * Turn on data output. 404 */ 405 MII_SET(RTK_MII_DIR); 406 407 rtk_mii_sync(sc); 408 409 rtk_mii_send(sc, frame->mii_stdelim, 2); 410 rtk_mii_send(sc, frame->mii_opcode, 2); 411 rtk_mii_send(sc, frame->mii_phyaddr, 5); 412 rtk_mii_send(sc, frame->mii_regaddr, 5); 413 rtk_mii_send(sc, frame->mii_turnaround, 2); 414 rtk_mii_send(sc, frame->mii_data, 16); 415 416 /* Idle bit. */ 417 MII_SET(RTK_MII_CLK); 418 DELAY(1); 419 MII_CLR(RTK_MII_CLK); 420 DELAY(1); 421 422 /* 423 * Turn off xmit. 424 */ 425 MII_CLR(RTK_MII_DIR); 426 427 splx(s); 428 429 return (0); 430 } 431 432 STATIC int rtk_phy_readreg(self, phy, reg) 433 struct device *self; 434 int phy, reg; 435 { 436 struct rtk_softc *sc = (void *)self; 437 struct rtk_mii_frame frame; 438 int rval = 0; 439 int rtk8139_reg = 0; 440 441 if (sc->rtk_type == RTK_8139) { 442 if (phy != 7) 443 return (0); 444 445 switch(reg) { 446 case MII_BMCR: 447 rtk8139_reg = RTK_BMCR; 448 break; 449 case MII_BMSR: 450 rtk8139_reg = RTK_BMSR; 451 break; 452 case MII_ANAR: 453 rtk8139_reg = RTK_ANAR; 454 break; 455 case MII_ANER: 456 rtk8139_reg = RTK_ANER; 457 break; 458 case MII_ANLPAR: 459 rtk8139_reg = RTK_LPAR; 460 break; 461 default: 462 #if 0 463 printf("%s: bad phy register\n", sc->sc_dev.dv_xname); 464 #endif 465 return (0); 466 } 467 rval = CSR_READ_2(sc, rtk8139_reg); 468 return (rval); 469 } 470 471 memset((char *)&frame, 0, sizeof(frame)); 472 473 frame.mii_phyaddr = phy; 474 frame.mii_regaddr = reg; 475 rtk_mii_readreg(sc, &frame); 476 477 return (frame.mii_data); 478 } 479 480 STATIC void rtk_phy_writereg(self, phy, reg, data) 481 struct device *self; 482 int phy, reg; 483 int data; 484 { 485 struct rtk_softc *sc = (void *)self; 486 struct rtk_mii_frame frame; 487 int rtk8139_reg = 0; 488 489 if (sc->rtk_type == RTK_8139) { 490 if (phy != 7) 491 return; 492 493 switch(reg) { 494 case MII_BMCR: 495 rtk8139_reg = RTK_BMCR; 496 break; 497 case MII_BMSR: 498 rtk8139_reg = RTK_BMSR; 499 break; 500 case MII_ANAR: 501 rtk8139_reg = RTK_ANAR; 502 break; 503 case MII_ANER: 504 rtk8139_reg = RTK_ANER; 505 break; 506 case MII_ANLPAR: 507 rtk8139_reg = RTK_LPAR; 508 break; 509 default: 510 #if 0 511 printf("%s: bad phy register\n", sc->sc_dev.dv_xname); 512 #endif 513 return; 514 } 515 CSR_WRITE_2(sc, rtk8139_reg, data); 516 return; 517 } 518 519 memset((char *)&frame, 0, sizeof(frame)); 520 521 frame.mii_phyaddr = phy; 522 frame.mii_regaddr = reg; 523 frame.mii_data = data; 524 525 rtk_mii_writereg(sc, &frame); 526 } 527 528 STATIC void 529 rtk_phy_statchg(v) 530 struct device *v; 531 { 532 533 /* Nothing to do. */ 534 } 535 536 #define rtk_calchash(addr) \ 537 (ether_crc32_be((addr), ETHER_ADDR_LEN) >> 26) 538 539 /* 540 * Program the 64-bit multicast hash filter. 541 */ 542 STATIC void rtk_setmulti(sc) 543 struct rtk_softc *sc; 544 { 545 struct ifnet *ifp; 546 int h = 0; 547 u_int32_t hashes[2] = { 0, 0 }; 548 u_int32_t rxfilt; 549 int mcnt = 0; 550 struct ether_multi *enm; 551 struct ether_multistep step; 552 553 ifp = &sc->ethercom.ec_if; 554 555 rxfilt = CSR_READ_4(sc, RTK_RXCFG); 556 557 if (ifp->if_flags & IFF_PROMISC) { 558 allmulti: 559 ifp->if_flags |= IFF_ALLMULTI; 560 rxfilt |= RTK_RXCFG_RX_MULTI; 561 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt); 562 CSR_WRITE_4(sc, RTK_MAR0, 0xFFFFFFFF); 563 CSR_WRITE_4(sc, RTK_MAR4, 0xFFFFFFFF); 564 return; 565 } 566 567 /* first, zot all the existing hash bits */ 568 CSR_WRITE_4(sc, RTK_MAR0, 0); 569 CSR_WRITE_4(sc, RTK_MAR4, 0); 570 571 /* now program new ones */ 572 ETHER_FIRST_MULTI(step, &sc->ethercom, enm); 573 while (enm != NULL) { 574 if (memcmp(enm->enm_addrlo, enm->enm_addrhi, 575 ETHER_ADDR_LEN) != 0) 576 goto allmulti; 577 578 h = rtk_calchash(enm->enm_addrlo); 579 if (h < 32) 580 hashes[0] |= (1 << h); 581 else 582 hashes[1] |= (1 << (h - 32)); 583 mcnt++; 584 ETHER_NEXT_MULTI(step, enm); 585 } 586 587 ifp->if_flags &= ~IFF_ALLMULTI; 588 589 if (mcnt) 590 rxfilt |= RTK_RXCFG_RX_MULTI; 591 else 592 rxfilt &= ~RTK_RXCFG_RX_MULTI; 593 594 CSR_WRITE_4(sc, RTK_RXCFG, rxfilt); 595 CSR_WRITE_4(sc, RTK_MAR0, hashes[0]); 596 CSR_WRITE_4(sc, RTK_MAR4, hashes[1]); 597 } 598 599 void rtk_reset(sc) 600 struct rtk_softc *sc; 601 { 602 int i; 603 604 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 605 606 for (i = 0; i < RTK_TIMEOUT; i++) { 607 DELAY(10); 608 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0) 609 break; 610 } 611 if (i == RTK_TIMEOUT) 612 printf("%s: reset never completed!\n", sc->sc_dev.dv_xname); 613 } 614 615 /* 616 * Attach the interface. Allocate softc structures, do ifmedia 617 * setup and ethernet/BPF attach. 618 */ 619 void 620 rtk_attach(sc) 621 struct rtk_softc *sc; 622 { 623 struct ifnet *ifp; 624 struct rtk_tx_desc *txd; 625 u_int16_t val; 626 u_int8_t eaddr[ETHER_ADDR_LEN]; 627 int error; 628 int i, addr_len; 629 630 callout_init(&sc->rtk_tick_ch); 631 632 /* 633 * Check EEPROM type 9346 or 9356. 634 */ 635 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 636 addr_len = RTK_EEADDR_LEN1; 637 else 638 addr_len = RTK_EEADDR_LEN0; 639 640 /* 641 * Get station address. 642 */ 643 val = rtk_read_eeprom(sc, RTK_EE_EADDR0, addr_len); 644 eaddr[0] = val & 0xff; 645 eaddr[1] = val >> 8; 646 val = rtk_read_eeprom(sc, RTK_EE_EADDR1, addr_len); 647 eaddr[2] = val & 0xff; 648 eaddr[3] = val >> 8; 649 val = rtk_read_eeprom(sc, RTK_EE_EADDR2, addr_len); 650 eaddr[4] = val & 0xff; 651 eaddr[5] = val >> 8; 652 653 if ((error = bus_dmamem_alloc(sc->sc_dmat, 654 RTK_RXBUFLEN + 16, PAGE_SIZE, 0, &sc->sc_dmaseg, 1, &sc->sc_dmanseg, 655 BUS_DMA_NOWAIT)) != 0) { 656 printf("%s: can't allocate recv buffer, error = %d\n", 657 sc->sc_dev.dv_xname, error); 658 goto fail_0; 659 } 660 661 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg, 662 RTK_RXBUFLEN + 16, (caddr_t *)&sc->rtk_rx_buf, 663 BUS_DMA_NOWAIT|BUS_DMA_COHERENT)) != 0) { 664 printf("%s: can't map recv buffer, error = %d\n", 665 sc->sc_dev.dv_xname, error); 666 goto fail_1; 667 } 668 669 if ((error = bus_dmamap_create(sc->sc_dmat, 670 RTK_RXBUFLEN + 16, 1, RTK_RXBUFLEN + 16, 0, BUS_DMA_NOWAIT, 671 &sc->recv_dmamap)) != 0) { 672 printf("%s: can't create recv buffer DMA map, error = %d\n", 673 sc->sc_dev.dv_xname, error); 674 goto fail_2; 675 } 676 677 if ((error = bus_dmamap_load(sc->sc_dmat, sc->recv_dmamap, 678 sc->rtk_rx_buf, RTK_RXBUFLEN + 16, 679 NULL, BUS_DMA_READ|BUS_DMA_NOWAIT)) != 0) { 680 printf("%s: can't load recv buffer DMA map, error = %d\n", 681 sc->sc_dev.dv_xname, error); 682 goto fail_3; 683 } 684 685 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 686 txd = &sc->rtk_tx_descs[i]; 687 if ((error = bus_dmamap_create(sc->sc_dmat, 688 MCLBYTES, 1, MCLBYTES, 0, BUS_DMA_NOWAIT, 689 &txd->txd_dmamap)) != 0) { 690 printf("%s: can't create snd buffer DMA map," 691 " error = %d\n", sc->sc_dev.dv_xname, error); 692 goto fail_4; 693 } 694 txd->txd_txaddr = RTK_TXADDR0 + (i * 4); 695 txd->txd_txstat = RTK_TXSTAT0 + (i * 4); 696 } 697 SIMPLEQ_INIT(&sc->rtk_tx_free); 698 SIMPLEQ_INIT(&sc->rtk_tx_dirty); 699 700 /* 701 * From this point forward, the attachment cannot fail. A failure 702 * before this releases all resources thar may have been 703 * allocated. 704 */ 705 sc->sc_flags |= RTK_ATTACHED; 706 707 /* Init Early TX threshold. */ 708 sc->sc_txthresh = TXTH_256; 709 710 /* Reset the adapter. */ 711 rtk_reset(sc); 712 713 printf("%s: Ethernet address %s\n", 714 sc->sc_dev.dv_xname, ether_sprintf(eaddr)); 715 716 ifp = &sc->ethercom.ec_if; 717 ifp->if_softc = sc; 718 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 719 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 720 ifp->if_ioctl = rtk_ioctl; 721 ifp->if_start = rtk_start; 722 ifp->if_watchdog = rtk_watchdog; 723 ifp->if_init = rtk_init; 724 ifp->if_stop = rtk_stop; 725 IFQ_SET_READY(&ifp->if_snd); 726 727 /* 728 * Do ifmedia setup. 729 */ 730 sc->mii.mii_ifp = ifp; 731 sc->mii.mii_readreg = rtk_phy_readreg; 732 sc->mii.mii_writereg = rtk_phy_writereg; 733 sc->mii.mii_statchg = rtk_phy_statchg; 734 ifmedia_init(&sc->mii.mii_media, 0, rtk_ifmedia_upd, rtk_ifmedia_sts); 735 mii_attach(&sc->sc_dev, &sc->mii, 0xffffffff, 736 MII_PHY_ANY, MII_OFFSET_ANY, 0); 737 738 /* Choose a default media. */ 739 if (LIST_FIRST(&sc->mii.mii_phys) == NULL) { 740 ifmedia_add(&sc->mii.mii_media, IFM_ETHER|IFM_NONE, 0, NULL); 741 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_NONE); 742 } else { 743 ifmedia_set(&sc->mii.mii_media, IFM_ETHER|IFM_AUTO); 744 } 745 746 /* 747 * Call MI attach routines. 748 */ 749 if_attach(ifp); 750 ether_ifattach(ifp, eaddr); 751 752 /* 753 * Make sure the interface is shutdown during reboot. 754 */ 755 sc->sc_sdhook = shutdownhook_establish(rtk_shutdown, sc); 756 if (sc->sc_sdhook == NULL) 757 printf("%s: WARNING: unbale to establish shutdown hook\n", 758 sc->sc_dev.dv_xname); 759 /* 760 * Add a suspend hook to make sure we come back up after a 761 * resume. 762 */ 763 sc->sc_powerhook = powerhook_establish(rtk_power, sc); 764 if (sc->sc_powerhook == NULL) 765 printf("%s: WARNING: unable to establish power hook\n", 766 sc->sc_dev.dv_xname); 767 768 return; 769 fail_4: 770 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 771 txd = &sc->rtk_tx_descs[i]; 772 if (txd->txd_dmamap != NULL) 773 bus_dmamap_destroy(sc->sc_dmat, txd->txd_dmamap); 774 } 775 fail_3: 776 bus_dmamap_destroy(sc->sc_dmat, sc->recv_dmamap); 777 fail_2: 778 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rtk_rx_buf, 779 RTK_RXBUFLEN + 16); 780 fail_1: 781 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg); 782 fail_0: 783 return; 784 } 785 786 /* 787 * Initialize the transmit descriptors. 788 */ 789 STATIC int rtk_list_tx_init(sc) 790 struct rtk_softc *sc; 791 { 792 struct rtk_tx_desc *txd; 793 int i; 794 795 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) 796 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd, txd_q); 797 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_free)) != NULL) 798 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_free, txd, txd_q); 799 800 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 801 txd = &sc->rtk_tx_descs[i]; 802 CSR_WRITE_4(sc, txd->txd_txaddr, 0); 803 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_free, txd, txd_q); 804 } 805 806 return (0); 807 } 808 809 /* 810 * rtk_activate: 811 * Handle device activation/deactivation requests. 812 */ 813 int 814 rtk_activate(self, act) 815 struct device *self; 816 enum devact act; 817 { 818 struct rtk_softc *sc = (void *) self; 819 int s, error = 0; 820 821 s = splnet(); 822 switch (act) { 823 case DVACT_ACTIVATE: 824 error = EOPNOTSUPP; 825 break; 826 case DVACT_DEACTIVATE: 827 mii_activate(&sc->mii, act, MII_PHY_ANY, MII_OFFSET_ANY); 828 if_deactivate(&sc->ethercom.ec_if); 829 break; 830 } 831 splx(s); 832 833 return (error); 834 } 835 836 /* 837 * rtk_detach: 838 * Detach a rtk interface. 839 */ 840 int 841 rtk_detach(sc) 842 struct rtk_softc *sc; 843 { 844 struct ifnet *ifp = &sc->ethercom.ec_if; 845 struct rtk_tx_desc *txd; 846 int i; 847 848 /* 849 * Succeed now if thereisn't any work to do. 850 */ 851 if ((sc->sc_flags & RTK_ATTACHED) == 0) 852 return (0); 853 854 /* Unhook our tick handler. */ 855 callout_stop(&sc->rtk_tick_ch); 856 857 /* Detach all PHYs. */ 858 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 859 860 /* Delete all remaining media. */ 861 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY); 862 863 ether_ifdetach(ifp); 864 if_detach(ifp); 865 866 for (i = 0; i < RTK_TX_LIST_CNT; i++) { 867 txd = &sc->rtk_tx_descs[i]; 868 if (txd->txd_dmamap != NULL) 869 bus_dmamap_destroy(sc->sc_dmat, txd->txd_dmamap); 870 } 871 bus_dmamap_destroy(sc->sc_dmat, sc->recv_dmamap); 872 bus_dmamem_unmap(sc->sc_dmat, (caddr_t)sc->rtk_rx_buf, 873 RTK_RXBUFLEN + 16); 874 bus_dmamem_free(sc->sc_dmat, &sc->sc_dmaseg, sc->sc_dmanseg); 875 876 shutdownhook_disestablish(sc->sc_sdhook); 877 powerhook_disestablish(sc->sc_powerhook); 878 879 return (0); 880 } 881 882 /* 883 * rtk_enable: 884 * Enable the RTL81X9 chip. 885 */ 886 int 887 rtk_enable(sc) 888 struct rtk_softc *sc; 889 { 890 891 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 892 if ((*sc->sc_enable)(sc) != 0) { 893 printf("%s: device enable failed\n", 894 sc->sc_dev.dv_xname); 895 return (EIO); 896 } 897 sc->sc_flags |= RTK_ENABLED; 898 } 899 return (0); 900 } 901 902 /* 903 * rtk_disable: 904 * Disable the RTL81X9 chip. 905 */ 906 void 907 rtk_disable(sc) 908 struct rtk_softc *sc; 909 { 910 911 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 912 (*sc->sc_disable)(sc); 913 sc->sc_flags &= ~RTK_ENABLED; 914 } 915 } 916 917 /* 918 * rtk_power: 919 * Power management (suspend/resume) hook. 920 */ 921 void 922 rtk_power(why, arg) 923 int why; 924 void *arg; 925 { 926 struct rtk_softc *sc = (void *) arg; 927 struct ifnet *ifp = &sc->ethercom.ec_if; 928 int s; 929 930 s = splnet(); 931 switch (why) { 932 case PWR_SUSPEND: 933 case PWR_STANDBY: 934 rtk_stop(ifp, 0); 935 if (sc->sc_power != NULL) 936 (*sc->sc_power)(sc, why); 937 break; 938 case PWR_RESUME: 939 if (ifp->if_flags & IFF_UP) { 940 if (sc->sc_power != NULL) 941 (*sc->sc_power)(sc, why); 942 rtk_init(ifp); 943 } 944 break; 945 case PWR_SOFTSUSPEND: 946 case PWR_SOFTSTANDBY: 947 case PWR_SOFTRESUME: 948 break; 949 } 950 splx(s); 951 } 952 953 /* 954 * A frame has been uploaded: pass the resulting mbuf chain up to 955 * the higher level protocols. 956 * 957 * You know there's something wrong with a PCI bus-master chip design. 958 * 959 * The receive operation is badly documented in the datasheet, so I'll 960 * attempt to document it here. The driver provides a buffer area and 961 * places its base address in the RX buffer start address register. 962 * The chip then begins copying frames into the RX buffer. Each frame 963 * is preceeded by a 32-bit RX status word which specifies the length 964 * of the frame and certain other status bits. Each frame (starting with 965 * the status word) is also 32-bit aligned. The frame length is in the 966 * first 16 bits of the status word; the lower 15 bits correspond with 967 * the 'rx status register' mentioned in the datasheet. 968 * 969 * Note: to make the Alpha happy, the frame payload needs to be aligned 970 * on a 32-bit boundary. To achieve this, we copy the data to mbuf 971 * shifted forward 2 bytes. 972 */ 973 STATIC void rtk_rxeof(sc) 974 struct rtk_softc *sc; 975 { 976 struct mbuf *m; 977 struct ifnet *ifp; 978 caddr_t rxbufpos, dst; 979 int total_len, wrap = 0; 980 u_int32_t rxstat; 981 u_int16_t cur_rx, new_rx; 982 u_int16_t limit; 983 u_int16_t rx_bytes = 0, max_bytes; 984 985 ifp = &sc->ethercom.ec_if; 986 987 cur_rx = (CSR_READ_2(sc, RTK_CURRXADDR) + 16) % RTK_RXBUFLEN; 988 989 /* Do not try to read past this point. */ 990 limit = CSR_READ_2(sc, RTK_CURRXBUF) % RTK_RXBUFLEN; 991 992 if (limit < cur_rx) 993 max_bytes = (RTK_RXBUFLEN - cur_rx) + limit; 994 else 995 max_bytes = limit - cur_rx; 996 997 while((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_EMPTY_RXBUF) == 0) { 998 rxbufpos = sc->rtk_rx_buf + cur_rx; 999 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 1000 RTK_RXSTAT_LEN, BUS_DMASYNC_POSTREAD); 1001 rxstat = le32toh(*(u_int32_t *)rxbufpos); 1002 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, cur_rx, 1003 RTK_RXSTAT_LEN, BUS_DMASYNC_PREREAD); 1004 1005 /* 1006 * Here's a totally undocumented fact for you. When the 1007 * RealTek chip is in the process of copying a packet into 1008 * RAM for you, the length will be 0xfff0. If you spot a 1009 * packet header with this value, you need to stop. The 1010 * datasheet makes absolutely no mention of this and 1011 * RealTek should be shot for this. 1012 */ 1013 total_len = rxstat >> 16; 1014 if (total_len == RTK_RXSTAT_UNFINISHED) 1015 break; 1016 1017 if ((rxstat & RTK_RXSTAT_RXOK) == 0 || 1018 total_len > ETHER_MAX_LEN) { 1019 ifp->if_ierrors++; 1020 1021 /* 1022 * submitted by:[netbsd-pcmcia:00484] 1023 * Takahiro Kambe <taca@sky.yamashina.kyoto.jp> 1024 * obtain from: 1025 * FreeBSD if_rl.c rev 1.24->1.25 1026 * 1027 */ 1028 #if 0 1029 if (rxstat & (RTK_RXSTAT_BADSYM|RTK_RXSTAT_RUNT| 1030 RTK_RXSTAT_GIANT|RTK_RXSTAT_CRCERR| 1031 RTK_RXSTAT_ALIGNERR)) { 1032 CSR_WRITE_2(sc, RTK_COMMAND, RTK_CMD_TX_ENB); 1033 CSR_WRITE_2(sc, RTK_COMMAND, 1034 RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1035 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG); 1036 CSR_WRITE_4(sc, RTK_RXADDR, 1037 sc->recv_dmamap->dm_segs[0].ds_addr); 1038 cur_rx = 0; 1039 } 1040 break; 1041 #else 1042 rtk_init(ifp); 1043 return; 1044 #endif 1045 } 1046 1047 /* No errors; receive the packet. */ 1048 rx_bytes += total_len + RTK_RXSTAT_LEN; 1049 1050 /* 1051 * Avoid trying to read more bytes than we know 1052 * the chip has prepared for us. 1053 */ 1054 if (rx_bytes > max_bytes) 1055 break; 1056 1057 /* 1058 * Skip the status word, wrapping around to the beginning 1059 * of the Rx area, if necessary. 1060 */ 1061 cur_rx = (cur_rx + RTK_RXSTAT_LEN) % RTK_RXBUFLEN; 1062 rxbufpos = sc->rtk_rx_buf + cur_rx; 1063 1064 /* 1065 * Compute the number of bytes at which the packet 1066 * will wrap to the beginning of the ring buffer. 1067 */ 1068 wrap = RTK_RXBUFLEN - cur_rx; 1069 1070 /* 1071 * Compute where the next pending packet is. 1072 */ 1073 if (total_len > wrap) 1074 new_rx = total_len - wrap; 1075 else 1076 new_rx = cur_rx + total_len; 1077 /* Round up to 32-bit boundary. */ 1078 new_rx = (new_rx + 3) & ~3; 1079 1080 /* 1081 * Now allocate an mbuf (and possibly a cluster) to hold 1082 * the packet. Note we offset the packet 2 bytes so that 1083 * data after the Ethernet header will be 4-byte aligned. 1084 */ 1085 MGETHDR(m, M_DONTWAIT, MT_DATA); 1086 if (m == NULL) { 1087 printf("%s: unable to allocate Rx mbuf\n", 1088 sc->sc_dev.dv_xname); 1089 ifp->if_ierrors++; 1090 goto next_packet; 1091 } 1092 if (total_len > (MHLEN - RTK_ETHER_ALIGN)) { 1093 MCLGET(m, M_DONTWAIT); 1094 if ((m->m_flags & M_EXT) == 0) { 1095 printf("%s: unable to allocate Rx cluster\n", 1096 sc->sc_dev.dv_xname); 1097 ifp->if_ierrors++; 1098 m_freem(m); 1099 m = NULL; 1100 goto next_packet; 1101 } 1102 } 1103 m->m_data += RTK_ETHER_ALIGN; /* for alignment */ 1104 m->m_pkthdr.rcvif = ifp; 1105 m->m_pkthdr.len = m->m_len = total_len; 1106 dst = mtod(m, caddr_t); 1107 1108 /* 1109 * If the packet wraps, copy up to the wrapping point. 1110 */ 1111 if (total_len > wrap) { 1112 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1113 cur_rx, wrap, BUS_DMASYNC_POSTREAD); 1114 memcpy(dst, rxbufpos, wrap); 1115 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1116 cur_rx, wrap, BUS_DMASYNC_PREREAD); 1117 cur_rx = 0; 1118 rxbufpos = sc->rtk_rx_buf; 1119 total_len -= wrap; 1120 dst += wrap; 1121 } 1122 1123 /* 1124 * ...and now the rest. 1125 */ 1126 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1127 cur_rx, total_len, BUS_DMASYNC_POSTREAD); 1128 memcpy(dst, rxbufpos, total_len); 1129 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 1130 cur_rx, total_len, BUS_DMASYNC_PREREAD); 1131 1132 next_packet: 1133 CSR_WRITE_2(sc, RTK_CURRXADDR, new_rx - 16); 1134 cur_rx = new_rx; 1135 1136 if (m == NULL) 1137 continue; 1138 1139 /* 1140 * The RealTek chip includes the CRC with every 1141 * incoming packet. 1142 */ 1143 m->m_flags |= M_HASFCS; 1144 1145 ifp->if_ipackets++; 1146 1147 #if NBPFILTER > 0 1148 if (ifp->if_bpf) 1149 bpf_mtap(ifp->if_bpf, m); 1150 #endif 1151 /* pass it on. */ 1152 (*ifp->if_input)(ifp, m); 1153 } 1154 } 1155 1156 /* 1157 * A frame was downloaded to the chip. It's safe for us to clean up 1158 * the list buffers. 1159 */ 1160 STATIC void rtk_txeof(sc) 1161 struct rtk_softc *sc; 1162 { 1163 struct ifnet *ifp; 1164 struct rtk_tx_desc *txd; 1165 u_int32_t txstat; 1166 1167 ifp = &sc->ethercom.ec_if; 1168 1169 /* Clear the timeout timer. */ 1170 ifp->if_timer = 0; 1171 1172 /* 1173 * Go through our tx list and free mbufs for those 1174 * frames that have been uploaded. 1175 */ 1176 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) { 1177 txstat = CSR_READ_4(sc, txd->txd_txstat); 1178 if ((txstat & (RTK_TXSTAT_TX_OK| 1179 RTK_TXSTAT_TX_UNDERRUN|RTK_TXSTAT_TXABRT)) == 0) 1180 break; 1181 1182 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd, txd_q); 1183 1184 bus_dmamap_sync(sc->sc_dmat, txd->txd_dmamap, 0, 1185 txd->txd_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1186 bus_dmamap_unload(sc->sc_dmat, txd->txd_dmamap); 1187 m_freem(txd->txd_mbuf); 1188 txd->txd_mbuf = NULL; 1189 1190 ifp->if_collisions += (txstat & RTK_TXSTAT_COLLCNT) >> 24; 1191 1192 if (txstat & RTK_TXSTAT_TX_OK) 1193 ifp->if_opackets++; 1194 else { 1195 ifp->if_oerrors++; 1196 1197 /* 1198 * Increase Early TX threshold if underrun occurred. 1199 * Increase step 64 bytes. 1200 */ 1201 if (txstat & RTK_TXSTAT_TX_UNDERRUN) { 1202 printf("%s: transmit underrun;", 1203 sc->sc_dev.dv_xname); 1204 if (sc->sc_txthresh < TXTH_MAX) { 1205 sc->sc_txthresh += 2; 1206 printf(" new threshold: %d bytes", 1207 sc->sc_txthresh * 32); 1208 } 1209 printf("\n"); 1210 } 1211 if (txstat & (RTK_TXSTAT_TXABRT|RTK_TXSTAT_OUTOFWIN)) 1212 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG); 1213 } 1214 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_free, txd, txd_q); 1215 ifp->if_flags &= ~IFF_OACTIVE; 1216 } 1217 } 1218 1219 int rtk_intr(arg) 1220 void *arg; 1221 { 1222 struct rtk_softc *sc; 1223 struct ifnet *ifp; 1224 u_int16_t status; 1225 int handled = 0; 1226 1227 sc = arg; 1228 ifp = &sc->ethercom.ec_if; 1229 1230 /* Disable interrupts. */ 1231 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1232 1233 for (;;) { 1234 1235 status = CSR_READ_2(sc, RTK_ISR); 1236 if (status) 1237 CSR_WRITE_2(sc, RTK_ISR, status); 1238 1239 handled = 1; 1240 1241 if ((status & RTK_INTRS) == 0) 1242 break; 1243 1244 if (status & RTK_ISR_RX_OK) 1245 rtk_rxeof(sc); 1246 1247 if (status & RTK_ISR_RX_ERR) 1248 rtk_rxeof(sc); 1249 1250 if (status & (RTK_ISR_TX_OK|RTK_ISR_TX_ERR)) 1251 rtk_txeof(sc); 1252 1253 if (status & RTK_ISR_SYSTEM_ERR) { 1254 rtk_reset(sc); 1255 rtk_init(ifp); 1256 } 1257 } 1258 1259 /* Re-enable interrupts. */ 1260 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS); 1261 1262 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 1263 rtk_start(ifp); 1264 1265 return (handled); 1266 } 1267 1268 /* 1269 * Main transmit routine. 1270 */ 1271 1272 STATIC void rtk_start(ifp) 1273 struct ifnet *ifp; 1274 { 1275 struct rtk_softc *sc; 1276 struct rtk_tx_desc *txd; 1277 struct mbuf *m_head = NULL, *m_new; 1278 int error, len; 1279 1280 sc = ifp->if_softc; 1281 1282 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_free)) != NULL) { 1283 IFQ_POLL(&ifp->if_snd, m_head); 1284 if (m_head == NULL) 1285 break; 1286 m_new = NULL; 1287 1288 /* 1289 * Load the DMA map. If this fails, the packet didn't 1290 * fit in one DMA segment, and we need to copy. Note, 1291 * the packet must also be aligned. 1292 */ 1293 if ((mtod(m_head, bus_addr_t) & 3) != 0 || 1294 bus_dmamap_load_mbuf(sc->sc_dmat, txd->txd_dmamap, 1295 m_head, BUS_DMA_WRITE|BUS_DMA_NOWAIT) != 0) { 1296 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 1297 if (m_new == NULL) { 1298 printf("%s: unable to allocate Tx mbuf\n", 1299 sc->sc_dev.dv_xname); 1300 break; 1301 } 1302 if (m_head->m_pkthdr.len > MHLEN) { 1303 MCLGET(m_new, M_DONTWAIT); 1304 if ((m_new->m_flags & M_EXT) == 0) { 1305 printf("%s: unable to allocate Tx " 1306 "cluster\n", sc->sc_dev.dv_xname); 1307 m_freem(m_new); 1308 break; 1309 } 1310 } 1311 m_copydata(m_head, 0, m_head->m_pkthdr.len, 1312 mtod(m_new, caddr_t)); 1313 m_new->m_pkthdr.len = m_new->m_len = 1314 m_head->m_pkthdr.len; 1315 error = bus_dmamap_load_mbuf(sc->sc_dmat, 1316 txd->txd_dmamap, m_new, 1317 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1318 if (error) { 1319 printf("%s: unable to load Tx buffer, " 1320 "error = %d\n", sc->sc_dev.dv_xname, error); 1321 break; 1322 } 1323 } 1324 IFQ_DEQUEUE(&ifp->if_snd, m_head); 1325 if (m_new != NULL) { 1326 m_freem(m_head); 1327 m_head = m_new; 1328 } 1329 txd->txd_mbuf = m_head; 1330 1331 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_free, txd, txd_q); 1332 SIMPLEQ_INSERT_TAIL(&sc->rtk_tx_dirty, txd, txd_q); 1333 1334 #if NBPFILTER > 0 1335 /* 1336 * If there's a BPF listener, bounce a copy of this frame 1337 * to him. 1338 */ 1339 if (ifp->if_bpf) 1340 bpf_mtap(ifp->if_bpf, m_head); 1341 #endif 1342 /* 1343 * Transmit the frame. 1344 */ 1345 bus_dmamap_sync(sc->sc_dmat, 1346 txd->txd_dmamap, 0, txd->txd_dmamap->dm_mapsize, 1347 BUS_DMASYNC_PREWRITE); 1348 1349 len = txd->txd_dmamap->dm_segs[0].ds_len; 1350 if (len < (ETHER_MIN_LEN - ETHER_CRC_LEN)) 1351 len = (ETHER_MIN_LEN - ETHER_CRC_LEN); 1352 1353 CSR_WRITE_4(sc, txd->txd_txaddr, 1354 txd->txd_dmamap->dm_segs[0].ds_addr); 1355 CSR_WRITE_4(sc, txd->txd_txstat, RTK_TX_THRESH(sc) | len); 1356 } 1357 1358 /* 1359 * We broke out of the loop because all our TX slots are 1360 * full. Mark the NIC as busy until it drains some of the 1361 * packets from the queue. 1362 */ 1363 if (SIMPLEQ_FIRST(&sc->rtk_tx_free) == NULL) 1364 ifp->if_flags |= IFF_OACTIVE; 1365 1366 /* 1367 * Set a timeout in case the chip goes out to lunch. 1368 */ 1369 ifp->if_timer = 5; 1370 } 1371 1372 STATIC int rtk_init(ifp) 1373 struct ifnet *ifp; 1374 { 1375 struct rtk_softc *sc = ifp->if_softc; 1376 int error = 0, i; 1377 u_int32_t rxcfg; 1378 1379 if ((error = rtk_enable(sc)) != 0) 1380 goto out; 1381 1382 /* 1383 * Cancel pending I/O. 1384 */ 1385 rtk_stop(ifp, 0); 1386 1387 /* Init our MAC address */ 1388 for (i = 0; i < ETHER_ADDR_LEN; i++) { 1389 CSR_WRITE_1(sc, RTK_IDR0 + i, LLADDR(ifp->if_sadl)[i]); 1390 } 1391 1392 /* Init the RX buffer pointer register. */ 1393 bus_dmamap_sync(sc->sc_dmat, sc->recv_dmamap, 0, 1394 sc->recv_dmamap->dm_mapsize, BUS_DMASYNC_PREREAD); 1395 CSR_WRITE_4(sc, RTK_RXADDR, sc->recv_dmamap->dm_segs[0].ds_addr); 1396 1397 /* Init TX descriptors. */ 1398 rtk_list_tx_init(sc); 1399 1400 /* Init Early TX threshold. */ 1401 sc->sc_txthresh = TXTH_256; 1402 /* 1403 * Enable transmit and receive. 1404 */ 1405 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1406 1407 /* 1408 * Set the initial TX and RX configuration. 1409 */ 1410 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG); 1411 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG); 1412 1413 /* Set the individual bit to receive frames for this host only. */ 1414 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 1415 rxcfg |= RTK_RXCFG_RX_INDIV; 1416 1417 /* If we want promiscuous mode, set the allframes bit. */ 1418 if (ifp->if_flags & IFF_PROMISC) { 1419 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 1420 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1421 } else { 1422 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 1423 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1424 } 1425 1426 /* 1427 * Set capture broadcast bit to capture broadcast frames. 1428 */ 1429 if (ifp->if_flags & IFF_BROADCAST) { 1430 rxcfg |= RTK_RXCFG_RX_BROAD; 1431 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1432 } else { 1433 rxcfg &= ~RTK_RXCFG_RX_BROAD; 1434 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1435 } 1436 1437 /* 1438 * Program the multicast filter, if necessary. 1439 */ 1440 rtk_setmulti(sc); 1441 1442 /* 1443 * Enable interrupts. 1444 */ 1445 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS); 1446 1447 /* Start RX/TX process. */ 1448 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 1449 1450 /* Enable receiver and transmitter. */ 1451 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB|RTK_CMD_RX_ENB); 1452 1453 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD|RTK_CFG1_FULLDUPLEX); 1454 1455 /* 1456 * Set current media. 1457 */ 1458 mii_mediachg(&sc->mii); 1459 1460 ifp->if_flags |= IFF_RUNNING; 1461 ifp->if_flags &= ~IFF_OACTIVE; 1462 1463 callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc); 1464 1465 out: 1466 if (error) { 1467 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1468 ifp->if_timer = 0; 1469 printf("%s: interface not running\n", sc->sc_dev.dv_xname); 1470 } 1471 return (error); 1472 } 1473 1474 /* 1475 * Set media options. 1476 */ 1477 STATIC int rtk_ifmedia_upd(ifp) 1478 struct ifnet *ifp; 1479 { 1480 struct rtk_softc *sc; 1481 1482 sc = ifp->if_softc; 1483 1484 return (mii_mediachg(&sc->mii)); 1485 } 1486 1487 /* 1488 * Report current media status. 1489 */ 1490 STATIC void rtk_ifmedia_sts(ifp, ifmr) 1491 struct ifnet *ifp; 1492 struct ifmediareq *ifmr; 1493 { 1494 struct rtk_softc *sc; 1495 1496 sc = ifp->if_softc; 1497 1498 mii_pollstat(&sc->mii); 1499 ifmr->ifm_status = sc->mii.mii_media_status; 1500 ifmr->ifm_active = sc->mii.mii_media_active; 1501 } 1502 1503 STATIC int rtk_ioctl(ifp, command, data) 1504 struct ifnet *ifp; 1505 u_long command; 1506 caddr_t data; 1507 { 1508 struct rtk_softc *sc = ifp->if_softc; 1509 struct ifreq *ifr = (struct ifreq *) data; 1510 int s, error = 0; 1511 1512 s = splnet(); 1513 1514 switch (command) { 1515 case SIOCGIFMEDIA: 1516 case SIOCSIFMEDIA: 1517 error = ifmedia_ioctl(ifp, ifr, &sc->mii.mii_media, command); 1518 break; 1519 1520 default: 1521 error = ether_ioctl(ifp, command, data); 1522 if (error == ENETRESET) { 1523 if (RTK_IS_ENABLED(sc)) { 1524 /* 1525 * Multicast list has changed. Set the 1526 * hardware filter accordingly. 1527 */ 1528 rtk_setmulti(sc); 1529 } 1530 error = 0; 1531 } 1532 break; 1533 } 1534 1535 splx(s); 1536 1537 return (error); 1538 } 1539 1540 STATIC void rtk_watchdog(ifp) 1541 struct ifnet *ifp; 1542 { 1543 struct rtk_softc *sc; 1544 1545 sc = ifp->if_softc; 1546 1547 printf("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1548 ifp->if_oerrors++; 1549 rtk_txeof(sc); 1550 rtk_rxeof(sc); 1551 rtk_init(ifp); 1552 } 1553 1554 /* 1555 * Stop the adapter and free any mbufs allocated to the 1556 * RX and TX lists. 1557 */ 1558 STATIC void rtk_stop(ifp, disable) 1559 struct ifnet *ifp; 1560 int disable; 1561 { 1562 struct rtk_softc *sc = ifp->if_softc; 1563 struct rtk_tx_desc *txd; 1564 1565 callout_stop(&sc->rtk_tick_ch); 1566 1567 mii_down(&sc->mii); 1568 1569 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 1570 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1571 1572 /* 1573 * Free the TX list buffers. 1574 */ 1575 while ((txd = SIMPLEQ_FIRST(&sc->rtk_tx_dirty)) != NULL) { 1576 SIMPLEQ_REMOVE_HEAD(&sc->rtk_tx_dirty, txd, txd_q); 1577 bus_dmamap_unload(sc->sc_dmat, txd->txd_dmamap); 1578 m_freem(txd->txd_mbuf); 1579 txd->txd_mbuf = NULL; 1580 CSR_WRITE_4(sc, txd->txd_txaddr, 0); 1581 } 1582 1583 if (disable) 1584 rtk_disable(sc); 1585 1586 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1587 ifp->if_timer = 0; 1588 } 1589 1590 /* 1591 * Stop all chip I/O so that the kernel's probe routines don't 1592 * get confused by errant DMAs when rebooting. 1593 */ 1594 STATIC void rtk_shutdown(vsc) 1595 void *vsc; 1596 { 1597 struct rtk_softc *sc = (struct rtk_softc *)vsc; 1598 1599 rtk_stop(&sc->ethercom.ec_if, 0); 1600 } 1601 1602 STATIC void 1603 rtk_tick(arg) 1604 void *arg; 1605 { 1606 struct rtk_softc *sc = arg; 1607 int s = splnet(); 1608 1609 mii_tick(&sc->mii); 1610 splx(s); 1611 1612 callout_reset(&sc->rtk_tick_ch, hz, rtk_tick, sc); 1613 } 1614