1 /* $NetBSD: rtl8169.c,v 1.25 2006/06/18 16:14:10 rpaulo Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998-2003 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 /* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */ 37 38 /* 39 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 40 * 41 * Written by Bill Paul <wpaul@windriver.com> 42 * Senior Networking Software Engineer 43 * Wind River Systems 44 */ 45 46 /* 47 * This driver is designed to support RealTek's next generation of 48 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 49 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 50 * and the RTL8110S. 51 * 52 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 53 * with the older 8139 family, however it also supports a special 54 * C+ mode of operation that provides several new performance enhancing 55 * features. These include: 56 * 57 * o Descriptor based DMA mechanism. Each descriptor represents 58 * a single packet fragment. Data buffers may be aligned on 59 * any byte boundary. 60 * 61 * o 64-bit DMA 62 * 63 * o TCP/IP checksum offload for both RX and TX 64 * 65 * o High and normal priority transmit DMA rings 66 * 67 * o VLAN tag insertion and extraction 68 * 69 * o TCP large send (segmentation offload) 70 * 71 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 72 * programming API is fairly straightforward. The RX filtering, EEPROM 73 * access and PHY access is the same as it is on the older 8139 series 74 * chips. 75 * 76 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 77 * same programming API and feature set as the 8139C+ with the following 78 * differences and additions: 79 * 80 * o 1000Mbps mode 81 * 82 * o Jumbo frames 83 * 84 * o GMII and TBI ports/registers for interfacing with copper 85 * or fiber PHYs 86 * 87 * o RX and TX DMA rings can have up to 1024 descriptors 88 * (the 8139C+ allows a maximum of 64) 89 * 90 * o Slight differences in register layout from the 8139C+ 91 * 92 * The TX start and timer interrupt registers are at different locations 93 * on the 8169 than they are on the 8139C+. Also, the status word in the 94 * RX descriptor has a slightly different bit layout. The 8169 does not 95 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 96 * copper gigE PHY. 97 * 98 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 99 * (the 'S' stands for 'single-chip'). These devices have the same 100 * programming API as the older 8169, but also have some vendor-specific 101 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 102 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 103 * 104 * This driver takes advantage of the RX and TX checksum offload and 105 * VLAN tag insertion/extraction features. It also implements TX 106 * interrupt moderation using the timer interrupt registers, which 107 * significantly reduces TX interrupt load. There is also support 108 * for jumbo frames, however the 8169/8169S/8110S can not transmit 109 * jumbo frames larger than 7.5K, so the max MTU possible with this 110 * driver is 7500 bytes. 111 */ 112 113 #include "bpfilter.h" 114 #include "vlan.h" 115 116 #include <sys/param.h> 117 #include <sys/endian.h> 118 #include <sys/systm.h> 119 #include <sys/sockio.h> 120 #include <sys/mbuf.h> 121 #include <sys/malloc.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/device.h> 125 126 #include <net/if.h> 127 #include <net/if_arp.h> 128 #include <net/if_dl.h> 129 #include <net/if_ether.h> 130 #include <net/if_media.h> 131 #include <net/if_vlanvar.h> 132 133 #include <netinet/in_systm.h> /* XXX for IP_MAXPACKET */ 134 #include <netinet/in.h> /* XXX for IP_MAXPACKET */ 135 #include <netinet/ip.h> /* XXX for IP_MAXPACKET */ 136 137 #if NBPFILTER > 0 138 #include <net/bpf.h> 139 #endif 140 141 #include <machine/bus.h> 142 143 #include <dev/mii/mii.h> 144 #include <dev/mii/miivar.h> 145 146 #include <dev/pci/pcireg.h> 147 #include <dev/pci/pcivar.h> 148 #include <dev/pci/pcidevs.h> 149 150 #include <dev/ic/rtl81x9reg.h> 151 #include <dev/ic/rtl81x9var.h> 152 153 #include <dev/ic/rtl8169var.h> 154 155 156 static int re_encap(struct rtk_softc *, struct mbuf *, int *); 157 158 static int re_newbuf(struct rtk_softc *, int, struct mbuf *); 159 static int re_rx_list_init(struct rtk_softc *); 160 static int re_tx_list_init(struct rtk_softc *); 161 static void re_rxeof(struct rtk_softc *); 162 static void re_txeof(struct rtk_softc *); 163 static void re_tick(void *); 164 static void re_start(struct ifnet *); 165 static int re_ioctl(struct ifnet *, u_long, caddr_t); 166 static int re_init(struct ifnet *); 167 static void re_stop(struct ifnet *, int); 168 static void re_watchdog(struct ifnet *); 169 170 static void re_shutdown(void *); 171 static int re_enable(struct rtk_softc *); 172 static void re_disable(struct rtk_softc *); 173 static void re_power(int, void *); 174 175 static int re_ifmedia_upd(struct ifnet *); 176 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *); 177 178 static int re_gmii_readreg(struct device *, int, int); 179 static void re_gmii_writereg(struct device *, int, int, int); 180 181 static int re_miibus_readreg(struct device *, int, int); 182 static void re_miibus_writereg(struct device *, int, int, int); 183 static void re_miibus_statchg(struct device *); 184 185 static void re_reset(struct rtk_softc *); 186 187 static int 188 re_gmii_readreg(struct device *self, int phy, int reg) 189 { 190 struct rtk_softc *sc = (void *)self; 191 u_int32_t rval; 192 int i; 193 194 if (phy != 7) 195 return 0; 196 197 /* Let the rgephy driver read the GMEDIASTAT register */ 198 199 if (reg == RTK_GMEDIASTAT) { 200 rval = CSR_READ_1(sc, RTK_GMEDIASTAT); 201 return rval; 202 } 203 204 CSR_WRITE_4(sc, RTK_PHYAR, reg << 16); 205 DELAY(1000); 206 207 for (i = 0; i < RTK_TIMEOUT; i++) { 208 rval = CSR_READ_4(sc, RTK_PHYAR); 209 if (rval & RTK_PHYAR_BUSY) 210 break; 211 DELAY(100); 212 } 213 214 if (i == RTK_TIMEOUT) { 215 aprint_error("%s: PHY read failed\n", sc->sc_dev.dv_xname); 216 return 0; 217 } 218 219 return rval & RTK_PHYAR_PHYDATA; 220 } 221 222 static void 223 re_gmii_writereg(struct device *dev, int phy, int reg, int data) 224 { 225 struct rtk_softc *sc = (void *)dev; 226 u_int32_t rval; 227 int i; 228 229 CSR_WRITE_4(sc, RTK_PHYAR, (reg << 16) | 230 (data & RTK_PHYAR_PHYDATA) | RTK_PHYAR_BUSY); 231 DELAY(1000); 232 233 for (i = 0; i < RTK_TIMEOUT; i++) { 234 rval = CSR_READ_4(sc, RTK_PHYAR); 235 if (!(rval & RTK_PHYAR_BUSY)) 236 break; 237 DELAY(100); 238 } 239 240 if (i == RTK_TIMEOUT) { 241 aprint_error("%s: PHY write reg %x <- %x failed\n", 242 sc->sc_dev.dv_xname, reg, data); 243 return; 244 } 245 246 return; 247 } 248 249 static int 250 re_miibus_readreg(struct device *dev, int phy, int reg) 251 { 252 struct rtk_softc *sc = (void *)dev; 253 u_int16_t rval = 0; 254 u_int16_t re8139_reg = 0; 255 int s; 256 257 s = splnet(); 258 259 if (sc->rtk_type == RTK_8169) { 260 rval = re_gmii_readreg(dev, phy, reg); 261 splx(s); 262 return rval; 263 } 264 265 /* Pretend the internal PHY is only at address 0 */ 266 if (phy) { 267 splx(s); 268 return 0; 269 } 270 switch (reg) { 271 case MII_BMCR: 272 re8139_reg = RTK_BMCR; 273 break; 274 case MII_BMSR: 275 re8139_reg = RTK_BMSR; 276 break; 277 case MII_ANAR: 278 re8139_reg = RTK_ANAR; 279 break; 280 case MII_ANER: 281 re8139_reg = RTK_ANER; 282 break; 283 case MII_ANLPAR: 284 re8139_reg = RTK_LPAR; 285 break; 286 case MII_PHYIDR1: 287 case MII_PHYIDR2: 288 splx(s); 289 return 0; 290 /* 291 * Allow the rlphy driver to read the media status 292 * register. If we have a link partner which does not 293 * support NWAY, this is the register which will tell 294 * us the results of parallel detection. 295 */ 296 case RTK_MEDIASTAT: 297 rval = CSR_READ_1(sc, RTK_MEDIASTAT); 298 splx(s); 299 return rval; 300 default: 301 aprint_error("%s: bad phy register\n", sc->sc_dev.dv_xname); 302 splx(s); 303 return 0; 304 } 305 rval = CSR_READ_2(sc, re8139_reg); 306 splx(s); 307 return rval; 308 } 309 310 static void 311 re_miibus_writereg(struct device *dev, int phy, int reg, int data) 312 { 313 struct rtk_softc *sc = (void *)dev; 314 u_int16_t re8139_reg = 0; 315 int s; 316 317 s = splnet(); 318 319 if (sc->rtk_type == RTK_8169) { 320 re_gmii_writereg(dev, phy, reg, data); 321 splx(s); 322 return; 323 } 324 325 /* Pretend the internal PHY is only at address 0 */ 326 if (phy) { 327 splx(s); 328 return; 329 } 330 switch (reg) { 331 case MII_BMCR: 332 re8139_reg = RTK_BMCR; 333 break; 334 case MII_BMSR: 335 re8139_reg = RTK_BMSR; 336 break; 337 case MII_ANAR: 338 re8139_reg = RTK_ANAR; 339 break; 340 case MII_ANER: 341 re8139_reg = RTK_ANER; 342 break; 343 case MII_ANLPAR: 344 re8139_reg = RTK_LPAR; 345 break; 346 case MII_PHYIDR1: 347 case MII_PHYIDR2: 348 splx(s); 349 return; 350 break; 351 default: 352 aprint_error("%s: bad phy register\n", sc->sc_dev.dv_xname); 353 splx(s); 354 return; 355 } 356 CSR_WRITE_2(sc, re8139_reg, data); 357 splx(s); 358 return; 359 } 360 361 static void 362 re_miibus_statchg(struct device *dev) 363 { 364 365 return; 366 } 367 368 static void 369 re_reset(struct rtk_softc *sc) 370 { 371 register int i; 372 373 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 374 375 for (i = 0; i < RTK_TIMEOUT; i++) { 376 DELAY(10); 377 if (!(CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET)) 378 break; 379 } 380 if (i == RTK_TIMEOUT) 381 aprint_error("%s: reset never completed!\n", 382 sc->sc_dev.dv_xname); 383 384 /* 385 * NB: Realtek-supplied Linux driver does this only for 386 * MCFG_METHOD_2, which corresponds to sc->sc_rev == 2. 387 */ 388 if (1) /* XXX check softc flag for 8169s version */ 389 CSR_WRITE_1(sc, 0x82, 1); 390 391 return; 392 } 393 394 /* 395 * The following routine is designed to test for a defect on some 396 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 397 * lines connected to the bus, however for a 32-bit only card, they 398 * should be pulled high. The result of this defect is that the 399 * NIC will not work right if you plug it into a 64-bit slot: DMA 400 * operations will be done with 64-bit transfers, which will fail 401 * because the 64-bit data lines aren't connected. 402 * 403 * There's no way to work around this (short of talking a soldering 404 * iron to the board), however we can detect it. The method we use 405 * here is to put the NIC into digital loopback mode, set the receiver 406 * to promiscuous mode, and then try to send a frame. We then compare 407 * the frame data we sent to what was received. If the data matches, 408 * then the NIC is working correctly, otherwise we know the user has 409 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 410 * slot. In the latter case, there's no way the NIC can work correctly, 411 * so we print out a message on the console and abort the device attach. 412 */ 413 414 int 415 re_diag(struct rtk_softc *sc) 416 { 417 struct ifnet *ifp = &sc->ethercom.ec_if; 418 struct mbuf *m0; 419 struct ether_header *eh; 420 struct rtk_desc *cur_rx; 421 bus_dmamap_t dmamap; 422 u_int16_t status; 423 u_int32_t rxstat; 424 int total_len, i, s, error = 0; 425 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 426 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 427 428 /* Allocate a single mbuf */ 429 430 MGETHDR(m0, M_DONTWAIT, MT_DATA); 431 if (m0 == NULL) 432 return ENOBUFS; 433 434 /* 435 * Initialize the NIC in test mode. This sets the chip up 436 * so that it can send and receive frames, but performs the 437 * following special functions: 438 * - Puts receiver in promiscuous mode 439 * - Enables digital loopback mode 440 * - Leaves interrupts turned off 441 */ 442 443 ifp->if_flags |= IFF_PROMISC; 444 sc->rtk_testmode = 1; 445 re_init(ifp); 446 re_stop(ifp, 0); 447 DELAY(100000); 448 re_init(ifp); 449 450 /* Put some data in the mbuf */ 451 452 eh = mtod(m0, struct ether_header *); 453 bcopy((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 454 bcopy((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 455 eh->ether_type = htons(ETHERTYPE_IP); 456 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 457 458 /* 459 * Queue the packet, start transmission. 460 */ 461 462 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF); 463 s = splnet(); 464 IF_ENQUEUE(&ifp->if_snd, m0); 465 re_start(ifp); 466 splx(s); 467 m0 = NULL; 468 469 /* Wait for it to propagate through the chip */ 470 471 DELAY(100000); 472 for (i = 0; i < RTK_TIMEOUT; i++) { 473 status = CSR_READ_2(sc, RTK_ISR); 474 if ((status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) == 475 (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) 476 break; 477 DELAY(10); 478 } 479 if (i == RTK_TIMEOUT) { 480 aprint_error("%s: diagnostic failed, failed to receive packet " 481 "in loopback mode\n", sc->sc_dev.dv_xname); 482 error = EIO; 483 goto done; 484 } 485 486 /* 487 * The packet should have been dumped into the first 488 * entry in the RX DMA ring. Grab it from there. 489 */ 490 491 dmamap = sc->rtk_ldata.rtk_rx_list_map; 492 bus_dmamap_sync(sc->sc_dmat, 493 dmamap, 0, dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 494 dmamap = sc->rtk_ldata.rtk_rx_dmamap[0]; 495 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 496 BUS_DMASYNC_POSTREAD); 497 bus_dmamap_unload(sc->sc_dmat, 498 sc->rtk_ldata.rtk_rx_dmamap[0]); 499 500 m0 = sc->rtk_ldata.rtk_rx_mbuf[0]; 501 sc->rtk_ldata.rtk_rx_mbuf[0] = NULL; 502 eh = mtod(m0, struct ether_header *); 503 504 cur_rx = &sc->rtk_ldata.rtk_rx_list[0]; 505 total_len = RTK_RXBYTES(cur_rx); 506 rxstat = le32toh(cur_rx->rtk_cmdstat); 507 508 if (total_len != ETHER_MIN_LEN) { 509 aprint_error("%s: diagnostic failed, received short packet\n", 510 sc->sc_dev.dv_xname); 511 error = EIO; 512 goto done; 513 } 514 515 /* Test that the received packet data matches what we sent. */ 516 517 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 518 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 519 ntohs(eh->ether_type) != ETHERTYPE_IP) { 520 aprint_error("%s: WARNING, DMA FAILURE!\n", 521 sc->sc_dev.dv_xname); 522 aprint_error("%s: expected TX data: %s", 523 sc->sc_dev.dv_xname, ether_sprintf(dst)); 524 aprint_error("/%s/0x%x\n", ether_sprintf(src), ETHERTYPE_IP); 525 aprint_error("%s: received RX data: %s", 526 sc->sc_dev.dv_xname, 527 ether_sprintf(eh->ether_dhost)); 528 aprint_error("/%s/0x%x\n", ether_sprintf(eh->ether_shost), 529 ntohs(eh->ether_type)); 530 aprint_error("%s: You may have a defective 32-bit NIC plugged " 531 "into a 64-bit PCI slot.\n", sc->sc_dev.dv_xname); 532 aprint_error("%s: Please re-install the NIC in a 32-bit slot " 533 "for proper operation.\n", sc->sc_dev.dv_xname); 534 aprint_error("%s: Read the re(4) man page for more details.\n", 535 sc->sc_dev.dv_xname); 536 error = EIO; 537 } 538 539 done: 540 /* Turn interface off, release resources */ 541 542 sc->rtk_testmode = 0; 543 ifp->if_flags &= ~IFF_PROMISC; 544 re_stop(ifp, 0); 545 if (m0 != NULL) 546 m_freem(m0); 547 548 return error; 549 } 550 551 552 /* 553 * Attach the interface. Allocate softc structures, do ifmedia 554 * setup and ethernet/BPF attach. 555 */ 556 void 557 re_attach(struct rtk_softc *sc) 558 { 559 u_char eaddr[ETHER_ADDR_LEN]; 560 u_int16_t val; 561 struct ifnet *ifp; 562 int error = 0, i, addr_len; 563 564 565 /* XXX JRS: bus-attach-independent code begins approximately here */ 566 567 /* Reset the adapter. */ 568 re_reset(sc); 569 570 if (sc->rtk_type == RTK_8169) { 571 uint32_t hwrev; 572 573 /* Revision of 8169/8169S/8110s in bits 30..26, 23 */ 574 hwrev = CSR_READ_4(sc, RTK_TXCFG) & 0x7c800000; 575 if (hwrev == (0x1 << 28)) { 576 sc->sc_rev = 4; 577 } else if (hwrev == (0x1 << 26)) { 578 sc->sc_rev = 3; 579 } else if (hwrev == (0x1 << 23)) { 580 sc->sc_rev = 2; 581 } else 582 sc->sc_rev = 1; 583 584 /* Set RX length mask */ 585 586 sc->rtk_rxlenmask = RTK_RDESC_STAT_GFRAGLEN; 587 588 /* Force station address autoload from the EEPROM */ 589 590 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_AUTOLOAD); 591 for (i = 0; i < RTK_TIMEOUT; i++) { 592 if (!(CSR_READ_1(sc, RTK_EECMD) & RTK_EEMODE_AUTOLOAD)) 593 break; 594 DELAY(100); 595 } 596 if (i == RTK_TIMEOUT) 597 aprint_error("%s: eeprom autoload timed out\n", 598 sc->sc_dev.dv_xname); 599 600 for (i = 0; i < ETHER_ADDR_LEN; i++) 601 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i); 602 603 sc->rtk_ldata.rtk_tx_desc_cnt = RTK_TX_DESC_CNT_8169; 604 } else { 605 606 /* Set RX length mask */ 607 608 sc->rtk_rxlenmask = RTK_RDESC_STAT_FRAGLEN; 609 610 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 611 addr_len = RTK_EEADDR_LEN1; 612 else 613 addr_len = RTK_EEADDR_LEN0; 614 615 /* 616 * Get station address from the EEPROM. 617 */ 618 for (i = 0; i < 3; i++) { 619 val = rtk_read_eeprom(sc, RTK_EE_EADDR0 + i, addr_len); 620 eaddr[(i * 2) + 0] = val & 0xff; 621 eaddr[(i * 2) + 1] = val >> 8; 622 } 623 624 sc->rtk_ldata.rtk_tx_desc_cnt = RTK_TX_DESC_CNT_8139; 625 } 626 627 aprint_normal("%s: Ethernet address %s\n", 628 sc->sc_dev.dv_xname, ether_sprintf(eaddr)); 629 630 if (sc->rtk_ldata.rtk_tx_desc_cnt > 631 PAGE_SIZE / sizeof(struct rtk_desc)) { 632 sc->rtk_ldata.rtk_tx_desc_cnt = 633 PAGE_SIZE / sizeof(struct rtk_desc); 634 } 635 636 aprint_verbose("%s: using %d tx descriptors\n", 637 sc->sc_dev.dv_xname, sc->rtk_ldata.rtk_tx_desc_cnt); 638 639 /* Allocate DMA'able memory for the TX ring */ 640 if ((error = bus_dmamem_alloc(sc->sc_dmat, RTK_TX_LIST_SZ(sc), 641 RTK_ETHER_ALIGN, 0, &sc->rtk_ldata.rtk_tx_listseg, 642 1, &sc->rtk_ldata.rtk_tx_listnseg, BUS_DMA_NOWAIT)) != 0) { 643 aprint_error("%s: can't allocate tx listseg, error = %d\n", 644 sc->sc_dev.dv_xname, error); 645 goto fail_0; 646 } 647 648 /* Load the map for the TX ring. */ 649 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->rtk_ldata.rtk_tx_listseg, 650 sc->rtk_ldata.rtk_tx_listnseg, RTK_TX_LIST_SZ(sc), 651 (caddr_t *)&sc->rtk_ldata.rtk_tx_list, 652 BUS_DMA_NOWAIT)) != 0) { 653 aprint_error("%s: can't map tx list, error = %d\n", 654 sc->sc_dev.dv_xname, error); 655 goto fail_1; 656 } 657 memset(sc->rtk_ldata.rtk_tx_list, 0, RTK_TX_LIST_SZ(sc)); 658 659 if ((error = bus_dmamap_create(sc->sc_dmat, RTK_TX_LIST_SZ(sc), 1, 660 RTK_TX_LIST_SZ(sc), 0, BUS_DMA_ALLOCNOW, 661 &sc->rtk_ldata.rtk_tx_list_map)) != 0) { 662 aprint_error("%s: can't create tx list map, error = %d\n", 663 sc->sc_dev.dv_xname, error); 664 goto fail_2; 665 } 666 667 668 if ((error = bus_dmamap_load(sc->sc_dmat, 669 sc->rtk_ldata.rtk_tx_list_map, sc->rtk_ldata.rtk_tx_list, 670 RTK_TX_LIST_SZ(sc), NULL, BUS_DMA_NOWAIT)) != 0) { 671 aprint_error("%s: can't load tx list, error = %d\n", 672 sc->sc_dev.dv_xname, error); 673 goto fail_3; 674 } 675 676 /* Create DMA maps for TX buffers */ 677 for (i = 0; i < RTK_TX_QLEN; i++) { 678 error = bus_dmamap_create(sc->sc_dmat, 679 round_page(IP_MAXPACKET), 680 RTK_TX_DESC_CNT(sc) - 4, RTK_TDESC_CMD_FRAGLEN, 681 0, BUS_DMA_ALLOCNOW, 682 &sc->rtk_ldata.rtk_txq[i].txq_dmamap); 683 if (error) { 684 aprint_error("%s: can't create DMA map for TX\n", 685 sc->sc_dev.dv_xname); 686 goto fail_4; 687 } 688 } 689 690 /* Allocate DMA'able memory for the RX ring */ 691 if ((error = bus_dmamem_alloc(sc->sc_dmat, RTK_RX_LIST_SZ, 692 RTK_RING_ALIGN, 0, &sc->rtk_ldata.rtk_rx_listseg, 1, 693 &sc->rtk_ldata.rtk_rx_listnseg, BUS_DMA_NOWAIT)) != 0) { 694 aprint_error("%s: can't allocate rx listseg, error = %d\n", 695 sc->sc_dev.dv_xname, error); 696 goto fail_4; 697 } 698 699 /* Load the map for the RX ring. */ 700 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->rtk_ldata.rtk_rx_listseg, 701 sc->rtk_ldata.rtk_rx_listnseg, RTK_RX_LIST_SZ, 702 (caddr_t *)&sc->rtk_ldata.rtk_rx_list, 703 BUS_DMA_NOWAIT)) != 0) { 704 aprint_error("%s: can't map rx list, error = %d\n", 705 sc->sc_dev.dv_xname, error); 706 goto fail_5; 707 } 708 memset(sc->rtk_ldata.rtk_rx_list, 0, RTK_RX_LIST_SZ); 709 710 if ((error = bus_dmamap_create(sc->sc_dmat, RTK_RX_LIST_SZ, 1, 711 RTK_RX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 712 &sc->rtk_ldata.rtk_rx_list_map)) != 0) { 713 aprint_error("%s: can't create rx list map, error = %d\n", 714 sc->sc_dev.dv_xname, error); 715 goto fail_6; 716 } 717 718 if ((error = bus_dmamap_load(sc->sc_dmat, 719 sc->rtk_ldata.rtk_rx_list_map, sc->rtk_ldata.rtk_rx_list, 720 RTK_RX_LIST_SZ, NULL, BUS_DMA_NOWAIT)) != 0) { 721 aprint_error("%s: can't load rx list, error = %d\n", 722 sc->sc_dev.dv_xname, error); 723 goto fail_7; 724 } 725 726 /* Create DMA maps for RX buffers */ 727 for (i = 0; i < RTK_RX_DESC_CNT; i++) { 728 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 729 0, BUS_DMA_ALLOCNOW, &sc->rtk_ldata.rtk_rx_dmamap[i]); 730 if (error) { 731 aprint_error("%s: can't create DMA map for RX\n", 732 sc->sc_dev.dv_xname); 733 goto fail_8; 734 } 735 } 736 737 /* 738 * Record interface as attached. From here, we should not fail. 739 */ 740 sc->sc_flags |= RTK_ATTACHED; 741 742 ifp = &sc->ethercom.ec_if; 743 ifp->if_softc = sc; 744 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 745 ifp->if_mtu = ETHERMTU; 746 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 747 ifp->if_ioctl = re_ioctl; 748 sc->ethercom.ec_capabilities |= ETHERCAP_VLAN_MTU; 749 750 /* 751 * This is a way to disable hw VLAN tagging by default 752 * (RE_VLAN is undefined), as it is problematic. PR 32643 753 */ 754 755 #ifdef RE_VLAN 756 sc->ethercom.ec_capabilities |= ETHERCAP_VLAN_HWTAGGING; 757 #endif 758 ifp->if_start = re_start; 759 ifp->if_stop = re_stop; 760 761 /* 762 * IFCAP_CSUM_IPv4_Tx seems broken for small packets. 763 */ 764 765 ifp->if_capabilities |= 766 /* IFCAP_CSUM_IPv4_Tx | */ IFCAP_CSUM_IPv4_Rx | 767 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 768 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 769 IFCAP_TSOv4; 770 ifp->if_watchdog = re_watchdog; 771 ifp->if_init = re_init; 772 if (sc->rtk_type == RTK_8169) 773 ifp->if_baudrate = 1000000000; 774 else 775 ifp->if_baudrate = 100000000; 776 ifp->if_snd.ifq_maxlen = RTK_IFQ_MAXLEN; 777 ifp->if_capenable = ifp->if_capabilities; 778 IFQ_SET_READY(&ifp->if_snd); 779 780 callout_init(&sc->rtk_tick_ch); 781 782 /* Do MII setup */ 783 sc->mii.mii_ifp = ifp; 784 sc->mii.mii_readreg = re_miibus_readreg; 785 sc->mii.mii_writereg = re_miibus_writereg; 786 sc->mii.mii_statchg = re_miibus_statchg; 787 ifmedia_init(&sc->mii.mii_media, IFM_IMASK, re_ifmedia_upd, 788 re_ifmedia_sts); 789 mii_attach(&sc->sc_dev, &sc->mii, 0xffffffff, MII_PHY_ANY, 790 MII_OFFSET_ANY, 0); 791 ifmedia_set(&sc->mii.mii_media, IFM_ETHER | IFM_AUTO); 792 793 /* 794 * Call MI attach routine. 795 */ 796 if_attach(ifp); 797 ether_ifattach(ifp, eaddr); 798 799 800 /* 801 * Make sure the interface is shutdown during reboot. 802 */ 803 sc->sc_sdhook = shutdownhook_establish(re_shutdown, sc); 804 if (sc->sc_sdhook == NULL) 805 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 806 sc->sc_dev.dv_xname); 807 /* 808 * Add a suspend hook to make sure we come back up after a 809 * resume. 810 */ 811 sc->sc_powerhook = powerhook_establish(re_power, sc); 812 if (sc->sc_powerhook == NULL) 813 aprint_error("%s: WARNING: unable to establish power hook\n", 814 sc->sc_dev.dv_xname); 815 816 817 return; 818 819 fail_8: 820 /* Destroy DMA maps for RX buffers. */ 821 for (i = 0; i < RTK_RX_DESC_CNT; i++) 822 if (sc->rtk_ldata.rtk_rx_dmamap[i] != NULL) 823 bus_dmamap_destroy(sc->sc_dmat, 824 sc->rtk_ldata.rtk_rx_dmamap[i]); 825 826 /* Free DMA'able memory for the RX ring. */ 827 bus_dmamap_unload(sc->sc_dmat, sc->rtk_ldata.rtk_rx_list_map); 828 fail_7: 829 bus_dmamap_destroy(sc->sc_dmat, sc->rtk_ldata.rtk_rx_list_map); 830 fail_6: 831 bus_dmamem_unmap(sc->sc_dmat, 832 (caddr_t)sc->rtk_ldata.rtk_rx_list, RTK_RX_LIST_SZ); 833 fail_5: 834 bus_dmamem_free(sc->sc_dmat, 835 &sc->rtk_ldata.rtk_rx_listseg, sc->rtk_ldata.rtk_rx_listnseg); 836 837 fail_4: 838 /* Destroy DMA maps for TX buffers. */ 839 for (i = 0; i < RTK_TX_QLEN; i++) 840 if (sc->rtk_ldata.rtk_txq[i].txq_dmamap != NULL) 841 bus_dmamap_destroy(sc->sc_dmat, 842 sc->rtk_ldata.rtk_txq[i].txq_dmamap); 843 844 /* Free DMA'able memory for the TX ring. */ 845 bus_dmamap_unload(sc->sc_dmat, sc->rtk_ldata.rtk_tx_list_map); 846 fail_3: 847 bus_dmamap_destroy(sc->sc_dmat, sc->rtk_ldata.rtk_tx_list_map); 848 fail_2: 849 bus_dmamem_unmap(sc->sc_dmat, 850 (caddr_t)sc->rtk_ldata.rtk_tx_list, RTK_TX_LIST_SZ(sc)); 851 fail_1: 852 bus_dmamem_free(sc->sc_dmat, 853 &sc->rtk_ldata.rtk_tx_listseg, sc->rtk_ldata.rtk_tx_listnseg); 854 fail_0: 855 return; 856 } 857 858 859 /* 860 * re_activate: 861 * Handle device activation/deactivation requests. 862 */ 863 int 864 re_activate(struct device *self, enum devact act) 865 { 866 struct rtk_softc *sc = (void *) self; 867 int s, error = 0; 868 869 s = splnet(); 870 switch (act) { 871 case DVACT_ACTIVATE: 872 error = EOPNOTSUPP; 873 break; 874 case DVACT_DEACTIVATE: 875 mii_activate(&sc->mii, act, MII_PHY_ANY, MII_OFFSET_ANY); 876 if_deactivate(&sc->ethercom.ec_if); 877 break; 878 } 879 splx(s); 880 881 return error; 882 } 883 884 /* 885 * re_detach: 886 * Detach a rtk interface. 887 */ 888 int 889 re_detach(struct rtk_softc *sc) 890 { 891 struct ifnet *ifp = &sc->ethercom.ec_if; 892 int i; 893 894 /* 895 * Succeed now if there isn't any work to do. 896 */ 897 if ((sc->sc_flags & RTK_ATTACHED) == 0) 898 return 0; 899 900 /* Unhook our tick handler. */ 901 callout_stop(&sc->rtk_tick_ch); 902 903 /* Detach all PHYs. */ 904 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 905 906 /* Delete all remaining media. */ 907 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY); 908 909 ether_ifdetach(ifp); 910 if_detach(ifp); 911 912 /* XXX undo re_allocmem() */ 913 914 /* Destroy DMA maps for RX buffers. */ 915 for (i = 0; i < RTK_RX_DESC_CNT; i++) 916 if (sc->rtk_ldata.rtk_rx_dmamap[i] != NULL) 917 bus_dmamap_destroy(sc->sc_dmat, 918 sc->rtk_ldata.rtk_rx_dmamap[i]); 919 920 /* Free DMA'able memory for the RX ring. */ 921 bus_dmamap_unload(sc->sc_dmat, sc->rtk_ldata.rtk_rx_list_map); 922 bus_dmamap_destroy(sc->sc_dmat, sc->rtk_ldata.rtk_rx_list_map); 923 bus_dmamem_unmap(sc->sc_dmat, 924 (caddr_t)sc->rtk_ldata.rtk_rx_list, RTK_RX_LIST_SZ); 925 bus_dmamem_free(sc->sc_dmat, 926 &sc->rtk_ldata.rtk_rx_listseg, sc->rtk_ldata.rtk_rx_listnseg); 927 928 /* Destroy DMA maps for TX buffers. */ 929 for (i = 0; i < RTK_TX_QLEN; i++) 930 if (sc->rtk_ldata.rtk_txq[i].txq_dmamap != NULL) 931 bus_dmamap_destroy(sc->sc_dmat, 932 sc->rtk_ldata.rtk_txq[i].txq_dmamap); 933 934 /* Free DMA'able memory for the TX ring. */ 935 bus_dmamap_unload(sc->sc_dmat, sc->rtk_ldata.rtk_tx_list_map); 936 bus_dmamap_destroy(sc->sc_dmat, sc->rtk_ldata.rtk_tx_list_map); 937 bus_dmamem_unmap(sc->sc_dmat, 938 (caddr_t)sc->rtk_ldata.rtk_tx_list, RTK_TX_LIST_SZ(sc)); 939 bus_dmamem_free(sc->sc_dmat, 940 &sc->rtk_ldata.rtk_tx_listseg, sc->rtk_ldata.rtk_tx_listnseg); 941 942 943 shutdownhook_disestablish(sc->sc_sdhook); 944 powerhook_disestablish(sc->sc_powerhook); 945 946 return 0; 947 } 948 949 /* 950 * re_enable: 951 * Enable the RTL81X9 chip. 952 */ 953 static int 954 re_enable(struct rtk_softc *sc) 955 { 956 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 957 if ((*sc->sc_enable)(sc) != 0) { 958 aprint_error("%s: device enable failed\n", 959 sc->sc_dev.dv_xname); 960 return EIO; 961 } 962 sc->sc_flags |= RTK_ENABLED; 963 } 964 return 0; 965 } 966 967 /* 968 * re_disable: 969 * Disable the RTL81X9 chip. 970 */ 971 static void 972 re_disable(struct rtk_softc *sc) 973 { 974 975 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 976 (*sc->sc_disable)(sc); 977 sc->sc_flags &= ~RTK_ENABLED; 978 } 979 } 980 981 /* 982 * re_power: 983 * Power management (suspend/resume) hook. 984 */ 985 void 986 re_power(int why, void *arg) 987 { 988 struct rtk_softc *sc = (void *) arg; 989 struct ifnet *ifp = &sc->ethercom.ec_if; 990 int s; 991 992 s = splnet(); 993 switch (why) { 994 case PWR_SUSPEND: 995 case PWR_STANDBY: 996 re_stop(ifp, 0); 997 if (sc->sc_power != NULL) 998 (*sc->sc_power)(sc, why); 999 break; 1000 case PWR_RESUME: 1001 if (ifp->if_flags & IFF_UP) { 1002 if (sc->sc_power != NULL) 1003 (*sc->sc_power)(sc, why); 1004 re_init(ifp); 1005 } 1006 break; 1007 case PWR_SOFTSUSPEND: 1008 case PWR_SOFTSTANDBY: 1009 case PWR_SOFTRESUME: 1010 break; 1011 } 1012 splx(s); 1013 } 1014 1015 1016 static int 1017 re_newbuf(struct rtk_softc *sc, int idx, struct mbuf *m) 1018 { 1019 struct mbuf *n = NULL; 1020 bus_dmamap_t map; 1021 struct rtk_desc *d; 1022 u_int32_t cmdstat; 1023 int error; 1024 1025 if (m == NULL) { 1026 MGETHDR(n, M_DONTWAIT, MT_DATA); 1027 if (n == NULL) 1028 return ENOBUFS; 1029 m = n; 1030 1031 MCLGET(m, M_DONTWAIT); 1032 if (!(m->m_flags & M_EXT)) { 1033 m_freem(m); 1034 return ENOBUFS; 1035 } 1036 } else 1037 m->m_data = m->m_ext.ext_buf; 1038 1039 /* 1040 * Initialize mbuf length fields and fixup 1041 * alignment so that the frame payload is 1042 * longword aligned. 1043 */ 1044 m->m_len = m->m_pkthdr.len = MCLBYTES; 1045 m_adj(m, RTK_ETHER_ALIGN); 1046 1047 map = sc->rtk_ldata.rtk_rx_dmamap[idx]; 1048 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1049 BUS_DMA_READ|BUS_DMA_NOWAIT); 1050 1051 if (error) 1052 goto out; 1053 1054 d = &sc->rtk_ldata.rtk_rx_list[idx]; 1055 if (le32toh(d->rtk_cmdstat) & RTK_RDESC_STAT_OWN) 1056 goto out; 1057 1058 cmdstat = map->dm_segs[0].ds_len; 1059 d->rtk_bufaddr_lo = htole32(RTK_ADDR_LO(map->dm_segs[0].ds_addr)); 1060 d->rtk_bufaddr_hi = htole32(RTK_ADDR_HI(map->dm_segs[0].ds_addr)); 1061 if (idx == (RTK_RX_DESC_CNT - 1)) 1062 cmdstat |= RTK_RDESC_CMD_EOR; 1063 d->rtk_cmdstat = htole32(cmdstat); 1064 1065 sc->rtk_ldata.rtk_rx_list[idx].rtk_cmdstat |= 1066 htole32(RTK_RDESC_CMD_OWN); 1067 sc->rtk_ldata.rtk_rx_mbuf[idx] = m; 1068 1069 bus_dmamap_sync(sc->sc_dmat, sc->rtk_ldata.rtk_rx_dmamap[idx], 0, 1070 sc->rtk_ldata.rtk_rx_dmamap[idx]->dm_mapsize, 1071 BUS_DMASYNC_PREREAD); 1072 1073 return 0; 1074 out: 1075 if (n != NULL) 1076 m_freem(n); 1077 return ENOMEM; 1078 } 1079 1080 static int 1081 re_tx_list_init(struct rtk_softc *sc) 1082 { 1083 int i; 1084 1085 memset(sc->rtk_ldata.rtk_tx_list, 0, RTK_TX_LIST_SZ(sc)); 1086 for (i = 0; i < RTK_TX_QLEN; i++) { 1087 sc->rtk_ldata.rtk_txq[i].txq_mbuf = NULL; 1088 } 1089 1090 bus_dmamap_sync(sc->sc_dmat, 1091 sc->rtk_ldata.rtk_tx_list_map, 0, 1092 sc->rtk_ldata.rtk_tx_list_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1093 sc->rtk_ldata.rtk_txq_prodidx = 0; 1094 sc->rtk_ldata.rtk_txq_considx = 0; 1095 sc->rtk_ldata.rtk_tx_free = RTK_TX_DESC_CNT(sc); 1096 sc->rtk_ldata.rtk_tx_nextfree = 0; 1097 1098 return 0; 1099 } 1100 1101 static int 1102 re_rx_list_init(struct rtk_softc *sc) 1103 { 1104 int i; 1105 1106 memset((char *)sc->rtk_ldata.rtk_rx_list, 0, RTK_RX_LIST_SZ); 1107 memset((char *)&sc->rtk_ldata.rtk_rx_mbuf, 0, 1108 (RTK_RX_DESC_CNT * sizeof(struct mbuf *))); 1109 1110 for (i = 0; i < RTK_RX_DESC_CNT; i++) { 1111 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1112 return ENOBUFS; 1113 } 1114 1115 /* Flush the RX descriptors */ 1116 1117 bus_dmamap_sync(sc->sc_dmat, 1118 sc->rtk_ldata.rtk_rx_list_map, 1119 0, sc->rtk_ldata.rtk_rx_list_map->dm_mapsize, 1120 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1121 1122 sc->rtk_ldata.rtk_rx_prodidx = 0; 1123 sc->rtk_head = sc->rtk_tail = NULL; 1124 1125 return 0; 1126 } 1127 1128 /* 1129 * RX handler for C+ and 8169. For the gigE chips, we support 1130 * the reception of jumbo frames that have been fragmented 1131 * across multiple 2K mbuf cluster buffers. 1132 */ 1133 static void 1134 re_rxeof(struct rtk_softc *sc) 1135 { 1136 struct mbuf *m; 1137 struct ifnet *ifp; 1138 int i, total_len; 1139 struct rtk_desc *cur_rx; 1140 u_int32_t rxstat, rxvlan; 1141 1142 ifp = &sc->ethercom.ec_if; 1143 i = sc->rtk_ldata.rtk_rx_prodidx; 1144 1145 /* Invalidate the descriptor memory */ 1146 1147 bus_dmamap_sync(sc->sc_dmat, 1148 sc->rtk_ldata.rtk_rx_list_map, 1149 0, sc->rtk_ldata.rtk_rx_list_map->dm_mapsize, 1150 BUS_DMASYNC_POSTREAD); 1151 1152 while (!RTK_OWN(&sc->rtk_ldata.rtk_rx_list[i])) { 1153 1154 cur_rx = &sc->rtk_ldata.rtk_rx_list[i]; 1155 m = sc->rtk_ldata.rtk_rx_mbuf[i]; 1156 total_len = RTK_RXBYTES(cur_rx); 1157 rxstat = le32toh(cur_rx->rtk_cmdstat); 1158 rxvlan = le32toh(cur_rx->rtk_vlanctl); 1159 1160 /* Invalidate the RX mbuf and unload its map */ 1161 1162 bus_dmamap_sync(sc->sc_dmat, 1163 sc->rtk_ldata.rtk_rx_dmamap[i], 1164 0, sc->rtk_ldata.rtk_rx_dmamap[i]->dm_mapsize, 1165 BUS_DMASYNC_POSTREAD); 1166 bus_dmamap_unload(sc->sc_dmat, 1167 sc->rtk_ldata.rtk_rx_dmamap[i]); 1168 1169 if (!(rxstat & RTK_RDESC_STAT_EOF)) { 1170 m->m_len = MCLBYTES - RTK_ETHER_ALIGN; 1171 if (sc->rtk_head == NULL) 1172 sc->rtk_head = sc->rtk_tail = m; 1173 else { 1174 m->m_flags &= ~M_PKTHDR; 1175 sc->rtk_tail->m_next = m; 1176 sc->rtk_tail = m; 1177 } 1178 re_newbuf(sc, i, NULL); 1179 RTK_RX_DESC_INC(sc, i); 1180 continue; 1181 } 1182 1183 /* 1184 * NOTE: for the 8139C+, the frame length field 1185 * is always 12 bits in size, but for the gigE chips, 1186 * it is 13 bits (since the max RX frame length is 16K). 1187 * Unfortunately, all 32 bits in the status word 1188 * were already used, so to make room for the extra 1189 * length bit, RealTek took out the 'frame alignment 1190 * error' bit and shifted the other status bits 1191 * over one slot. The OWN, EOR, FS and LS bits are 1192 * still in the same places. We have already extracted 1193 * the frame length and checked the OWN bit, so rather 1194 * than using an alternate bit mapping, we shift the 1195 * status bits one space to the right so we can evaluate 1196 * them using the 8169 status as though it was in the 1197 * same format as that of the 8139C+. 1198 */ 1199 if (sc->rtk_type == RTK_8169) 1200 rxstat >>= 1; 1201 1202 if (rxstat & RTK_RDESC_STAT_RXERRSUM) { 1203 ifp->if_ierrors++; 1204 /* 1205 * If this is part of a multi-fragment packet, 1206 * discard all the pieces. 1207 */ 1208 if (sc->rtk_head != NULL) { 1209 m_freem(sc->rtk_head); 1210 sc->rtk_head = sc->rtk_tail = NULL; 1211 } 1212 re_newbuf(sc, i, m); 1213 RTK_RX_DESC_INC(sc, i); 1214 continue; 1215 } 1216 1217 /* 1218 * If allocating a replacement mbuf fails, 1219 * reload the current one. 1220 */ 1221 1222 if (re_newbuf(sc, i, NULL)) { 1223 ifp->if_ierrors++; 1224 if (sc->rtk_head != NULL) { 1225 m_freem(sc->rtk_head); 1226 sc->rtk_head = sc->rtk_tail = NULL; 1227 } 1228 re_newbuf(sc, i, m); 1229 RTK_RX_DESC_INC(sc, i); 1230 continue; 1231 } 1232 1233 RTK_RX_DESC_INC(sc, i); 1234 1235 if (sc->rtk_head != NULL) { 1236 m->m_len = total_len % (MCLBYTES - RTK_ETHER_ALIGN); 1237 /* 1238 * Special case: if there's 4 bytes or less 1239 * in this buffer, the mbuf can be discarded: 1240 * the last 4 bytes is the CRC, which we don't 1241 * care about anyway. 1242 */ 1243 if (m->m_len <= ETHER_CRC_LEN) { 1244 sc->rtk_tail->m_len -= 1245 (ETHER_CRC_LEN - m->m_len); 1246 m_freem(m); 1247 } else { 1248 m->m_len -= ETHER_CRC_LEN; 1249 m->m_flags &= ~M_PKTHDR; 1250 sc->rtk_tail->m_next = m; 1251 } 1252 m = sc->rtk_head; 1253 sc->rtk_head = sc->rtk_tail = NULL; 1254 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1255 } else 1256 m->m_pkthdr.len = m->m_len = 1257 (total_len - ETHER_CRC_LEN); 1258 1259 ifp->if_ipackets++; 1260 m->m_pkthdr.rcvif = ifp; 1261 1262 /* Do RX checksumming if enabled */ 1263 1264 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) { 1265 1266 /* Check IP header checksum */ 1267 if (rxstat & RTK_RDESC_STAT_PROTOID) 1268 m->m_pkthdr.csum_flags |= M_CSUM_IPv4;; 1269 if (rxstat & RTK_RDESC_STAT_IPSUMBAD) 1270 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1271 } 1272 1273 /* Check TCP/UDP checksum */ 1274 if (RTK_TCPPKT(rxstat) && 1275 (ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx)) { 1276 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1277 if (rxstat & RTK_RDESC_STAT_TCPSUMBAD) 1278 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1279 } 1280 if (RTK_UDPPKT(rxstat) && 1281 (ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx)) { 1282 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1283 if (rxstat & RTK_RDESC_STAT_UDPSUMBAD) 1284 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1285 } 1286 1287 #ifdef RE_VLAN 1288 if (rxvlan & RTK_RDESC_VLANCTL_TAG) { 1289 VLAN_INPUT_TAG(ifp, m, 1290 be16toh(rxvlan & RTK_RDESC_VLANCTL_DATA), 1291 continue); 1292 } 1293 #endif 1294 #if NBPFILTER > 0 1295 if (ifp->if_bpf) 1296 bpf_mtap(ifp->if_bpf, m); 1297 #endif 1298 (*ifp->if_input)(ifp, m); 1299 } 1300 1301 /* Flush the RX DMA ring */ 1302 1303 bus_dmamap_sync(sc->sc_dmat, 1304 sc->rtk_ldata.rtk_rx_list_map, 1305 0, sc->rtk_ldata.rtk_rx_list_map->dm_mapsize, 1306 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1307 1308 sc->rtk_ldata.rtk_rx_prodidx = i; 1309 1310 return; 1311 } 1312 1313 static void 1314 re_txeof(struct rtk_softc *sc) 1315 { 1316 struct ifnet *ifp; 1317 int idx; 1318 1319 ifp = &sc->ethercom.ec_if; 1320 idx = sc->rtk_ldata.rtk_txq_considx; 1321 1322 /* Invalidate the TX descriptor list */ 1323 1324 bus_dmamap_sync(sc->sc_dmat, 1325 sc->rtk_ldata.rtk_tx_list_map, 1326 0, sc->rtk_ldata.rtk_tx_list_map->dm_mapsize, 1327 BUS_DMASYNC_POSTREAD); 1328 1329 while (/* CONSTCOND */ 1) { 1330 struct rtk_txq *txq = &sc->rtk_ldata.rtk_txq[idx]; 1331 int descidx; 1332 u_int32_t txstat; 1333 1334 if (txq->txq_mbuf == NULL) { 1335 KASSERT(idx == sc->rtk_ldata.rtk_txq_prodidx); 1336 break; 1337 } 1338 1339 descidx = txq->txq_descidx; 1340 txstat = 1341 le32toh(sc->rtk_ldata.rtk_tx_list[descidx].rtk_cmdstat); 1342 KASSERT((txstat & RTK_TDESC_CMD_EOF) != 0); 1343 if (txstat & RTK_TDESC_CMD_OWN) 1344 break; 1345 1346 sc->rtk_ldata.rtk_tx_free += txq->txq_dmamap->dm_nsegs; 1347 KASSERT(sc->rtk_ldata.rtk_tx_free <= RTK_TX_DESC_CNT(sc)); 1348 bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap); 1349 m_freem(txq->txq_mbuf); 1350 txq->txq_mbuf = NULL; 1351 1352 if (txstat & (RTK_TDESC_STAT_EXCESSCOL | RTK_TDESC_STAT_COLCNT)) 1353 ifp->if_collisions++; 1354 if (txstat & RTK_TDESC_STAT_TXERRSUM) 1355 ifp->if_oerrors++; 1356 else 1357 ifp->if_opackets++; 1358 1359 idx = (idx + 1) % RTK_TX_QLEN; 1360 } 1361 1362 /* No changes made to the TX ring, so no flush needed */ 1363 1364 if (idx != sc->rtk_ldata.rtk_txq_considx) { 1365 sc->rtk_ldata.rtk_txq_considx = idx; 1366 ifp->if_flags &= ~IFF_OACTIVE; 1367 ifp->if_timer = 0; 1368 } 1369 1370 /* 1371 * If not all descriptors have been released reaped yet, 1372 * reload the timer so that we will eventually get another 1373 * interrupt that will cause us to re-enter this routine. 1374 * This is done in case the transmitter has gone idle. 1375 */ 1376 if (sc->rtk_ldata.rtk_tx_free != RTK_TX_DESC_CNT(sc)) 1377 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1378 1379 return; 1380 } 1381 1382 /* 1383 * Stop all chip I/O so that the kernel's probe routines don't 1384 * get confused by errant DMAs when rebooting. 1385 */ 1386 static void 1387 re_shutdown(void *vsc) 1388 1389 { 1390 struct rtk_softc *sc = (struct rtk_softc *)vsc; 1391 1392 re_stop(&sc->ethercom.ec_if, 0); 1393 } 1394 1395 1396 static void 1397 re_tick(void *xsc) 1398 { 1399 struct rtk_softc *sc = xsc; 1400 int s; 1401 1402 /*XXX: just return for 8169S/8110S with rev 2 or newer phy */ 1403 s = splnet(); 1404 1405 mii_tick(&sc->mii); 1406 splx(s); 1407 1408 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1409 } 1410 1411 #ifdef DEVICE_POLLING 1412 static void 1413 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1414 { 1415 struct rtk_softc *sc = ifp->if_softc; 1416 1417 RTK_LOCK(sc); 1418 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1419 ether_poll_deregister(ifp); 1420 cmd = POLL_DEREGISTER; 1421 } 1422 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1423 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS); 1424 goto done; 1425 } 1426 1427 sc->rxcycles = count; 1428 re_rxeof(sc); 1429 re_txeof(sc); 1430 1431 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 1432 (*ifp->if_start)(ifp); 1433 1434 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1435 u_int16_t status; 1436 1437 status = CSR_READ_2(sc, RTK_ISR); 1438 if (status == 0xffff) 1439 goto done; 1440 if (status) 1441 CSR_WRITE_2(sc, RTK_ISR, status); 1442 1443 /* 1444 * XXX check behaviour on receiver stalls. 1445 */ 1446 1447 if (status & RTK_ISR_SYSTEM_ERR) { 1448 re_reset(sc); 1449 re_init(sc); 1450 } 1451 } 1452 done: 1453 RTK_UNLOCK(sc); 1454 } 1455 #endif /* DEVICE_POLLING */ 1456 1457 int 1458 re_intr(void *arg) 1459 { 1460 struct rtk_softc *sc = arg; 1461 struct ifnet *ifp; 1462 u_int16_t status; 1463 int handled = 0; 1464 1465 ifp = &sc->ethercom.ec_if; 1466 1467 if (!(ifp->if_flags & IFF_UP)) 1468 return 0; 1469 1470 #ifdef DEVICE_POLLING 1471 if (ifp->if_flags & IFF_POLLING) 1472 goto done; 1473 if ((ifp->if_capenable & IFCAP_POLLING) && 1474 ether_poll_register(re_poll, ifp)) { /* ok, disable interrupts */ 1475 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1476 re_poll(ifp, 0, 1); 1477 goto done; 1478 } 1479 #endif /* DEVICE_POLLING */ 1480 1481 for (;;) { 1482 1483 status = CSR_READ_2(sc, RTK_ISR); 1484 /* If the card has gone away the read returns 0xffff. */ 1485 if (status == 0xffff) 1486 break; 1487 if (status) { 1488 handled = 1; 1489 CSR_WRITE_2(sc, RTK_ISR, status); 1490 } 1491 1492 if ((status & RTK_INTRS_CPLUS) == 0) 1493 break; 1494 1495 if ((status & RTK_ISR_RX_OK) || 1496 (status & RTK_ISR_RX_ERR)) 1497 re_rxeof(sc); 1498 1499 if ((status & RTK_ISR_TIMEOUT_EXPIRED) || 1500 (status & RTK_ISR_TX_ERR) || 1501 (status & RTK_ISR_TX_DESC_UNAVAIL)) 1502 re_txeof(sc); 1503 1504 if (status & RTK_ISR_SYSTEM_ERR) { 1505 re_reset(sc); 1506 re_init(ifp); 1507 } 1508 1509 if (status & RTK_ISR_LINKCHG) { 1510 callout_stop(&sc->rtk_tick_ch); 1511 re_tick(sc); 1512 } 1513 } 1514 1515 if (ifp->if_flags & IFF_UP) /* kludge for interrupt during re_init() */ 1516 if (IFQ_IS_EMPTY(&ifp->if_snd) == 0) 1517 (*ifp->if_start)(ifp); 1518 1519 #ifdef DEVICE_POLLING 1520 done: 1521 #endif 1522 1523 return handled; 1524 } 1525 1526 static int 1527 re_encap(struct rtk_softc *sc, struct mbuf *m, int *idx) 1528 { 1529 bus_dmamap_t map; 1530 int error, i, startidx, curidx; 1531 #ifdef RE_VLAN 1532 struct m_tag *mtag; 1533 #endif 1534 struct rtk_desc *d; 1535 u_int32_t cmdstat, rtk_flags; 1536 struct rtk_txq *txq; 1537 1538 if (sc->rtk_ldata.rtk_tx_free <= 4) { 1539 return EFBIG; 1540 } 1541 1542 /* 1543 * Set up checksum offload. Note: checksum offload bits must 1544 * appear in all descriptors of a multi-descriptor transmit 1545 * attempt. (This is according to testing done with an 8169 1546 * chip. I'm not sure if this is a requirement or a bug.) 1547 */ 1548 1549 if ((m->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0) { 1550 u_int32_t segsz = m->m_pkthdr.segsz; 1551 1552 rtk_flags = RTK_TDESC_CMD_LGSEND | 1553 (segsz << RTK_TDESC_CMD_MSSVAL_SHIFT); 1554 } else { 1555 1556 /* 1557 * set RTK_TDESC_CMD_IPCSUM if any checksum offloading 1558 * is requested. otherwise, RTK_TDESC_CMD_TCPCSUM/ 1559 * RTK_TDESC_CMD_UDPCSUM doesn't make effects. 1560 */ 1561 1562 rtk_flags = 0; 1563 if ((m->m_pkthdr.csum_flags & 1564 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) != 0) { 1565 rtk_flags |= RTK_TDESC_CMD_IPCSUM; 1566 if (m->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1567 rtk_flags |= RTK_TDESC_CMD_TCPCSUM; 1568 } else if (m->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1569 rtk_flags |= RTK_TDESC_CMD_UDPCSUM; 1570 } 1571 } 1572 } 1573 1574 txq = &sc->rtk_ldata.rtk_txq[*idx]; 1575 map = txq->txq_dmamap; 1576 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1577 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1578 1579 if (error) { 1580 /* XXX try to defrag if EFBIG? */ 1581 1582 aprint_error("%s: can't map mbuf (error %d)\n", 1583 sc->sc_dev.dv_xname, error); 1584 1585 return error; 1586 } 1587 1588 if (map->dm_nsegs > sc->rtk_ldata.rtk_tx_free - 4) { 1589 error = EFBIG; 1590 goto fail_unload; 1591 } 1592 1593 /* 1594 * Make sure that the caches are synchronized before we 1595 * ask the chip to start DMA for the packet data. 1596 */ 1597 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1598 BUS_DMASYNC_PREWRITE); 1599 1600 /* 1601 * Map the segment array into descriptors. Note that we set the 1602 * start-of-frame and end-of-frame markers for either TX or RX, but 1603 * they really only have meaning in the TX case. (In the RX case, 1604 * it's the chip that tells us where packets begin and end.) 1605 * We also keep track of the end of the ring and set the 1606 * end-of-ring bits as needed, and we set the ownership bits 1607 * in all except the very first descriptor. (The caller will 1608 * set this descriptor later when it start transmission or 1609 * reception.) 1610 */ 1611 i = 0; 1612 curidx = startidx = sc->rtk_ldata.rtk_tx_nextfree; 1613 while (1) { 1614 d = &sc->rtk_ldata.rtk_tx_list[curidx]; 1615 if (le32toh(d->rtk_cmdstat) & RTK_TDESC_STAT_OWN) { 1616 while (i > 0) { 1617 sc->rtk_ldata.rtk_tx_list[ 1618 (curidx + RTK_TX_DESC_CNT(sc) - i) % 1619 RTK_TX_DESC_CNT(sc)].rtk_cmdstat = 0; 1620 i--; 1621 } 1622 error = ENOBUFS; 1623 goto fail_unload; 1624 } 1625 1626 cmdstat = map->dm_segs[i].ds_len; 1627 d->rtk_bufaddr_lo = 1628 htole32(RTK_ADDR_LO(map->dm_segs[i].ds_addr)); 1629 d->rtk_bufaddr_hi = 1630 htole32(RTK_ADDR_HI(map->dm_segs[i].ds_addr)); 1631 if (i == 0) 1632 cmdstat |= RTK_TDESC_CMD_SOF; 1633 else 1634 cmdstat |= RTK_TDESC_CMD_OWN; 1635 if (curidx == (RTK_TX_DESC_CNT(sc) - 1)) 1636 cmdstat |= RTK_TDESC_CMD_EOR; 1637 d->rtk_cmdstat = htole32(cmdstat | rtk_flags); 1638 i++; 1639 if (i == map->dm_nsegs) 1640 break; 1641 RTK_TX_DESC_INC(sc, curidx); 1642 } 1643 1644 d->rtk_cmdstat |= htole32(RTK_TDESC_CMD_EOF); 1645 1646 txq->txq_mbuf = m; 1647 sc->rtk_ldata.rtk_tx_free -= map->dm_nsegs; 1648 1649 /* 1650 * Set up hardware VLAN tagging. Note: vlan tag info must 1651 * appear in the first descriptor of a multi-descriptor 1652 * transmission attempt. 1653 */ 1654 1655 #ifdef RE_VLAN 1656 if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m)) != NULL) { 1657 sc->rtk_ldata.rtk_tx_list[startidx].rtk_vlanctl = 1658 htole32(htons(VLAN_TAG_VALUE(mtag)) | 1659 RTK_TDESC_VLANCTL_TAG); 1660 } 1661 #endif 1662 1663 /* Transfer ownership of packet to the chip. */ 1664 1665 sc->rtk_ldata.rtk_tx_list[curidx].rtk_cmdstat |= 1666 htole32(RTK_TDESC_CMD_OWN); 1667 if (startidx != curidx) 1668 sc->rtk_ldata.rtk_tx_list[startidx].rtk_cmdstat |= 1669 htole32(RTK_TDESC_CMD_OWN); 1670 1671 txq->txq_descidx = curidx; 1672 RTK_TX_DESC_INC(sc, curidx); 1673 sc->rtk_ldata.rtk_tx_nextfree = curidx; 1674 *idx = (*idx + 1) % RTK_TX_QLEN; 1675 1676 return 0; 1677 1678 fail_unload: 1679 bus_dmamap_unload(sc->sc_dmat, map); 1680 1681 return error; 1682 } 1683 1684 /* 1685 * Main transmit routine for C+ and gigE NICs. 1686 */ 1687 1688 static void 1689 re_start(struct ifnet *ifp) 1690 { 1691 struct rtk_softc *sc; 1692 int idx; 1693 1694 sc = ifp->if_softc; 1695 1696 idx = sc->rtk_ldata.rtk_txq_prodidx; 1697 while (/* CONSTCOND */ 1) { 1698 struct mbuf *m; 1699 int error; 1700 1701 IFQ_POLL(&ifp->if_snd, m); 1702 if (m == NULL) 1703 break; 1704 1705 if (sc->rtk_ldata.rtk_txq[idx].txq_mbuf != NULL) { 1706 KASSERT(idx == sc->rtk_ldata.rtk_txq_considx); 1707 ifp->if_flags |= IFF_OACTIVE; 1708 break; 1709 } 1710 1711 error = re_encap(sc, m, &idx); 1712 if (error == EFBIG && 1713 sc->rtk_ldata.rtk_tx_free == RTK_TX_DESC_CNT(sc)) { 1714 IFQ_DEQUEUE(&ifp->if_snd, m); 1715 m_freem(m); 1716 ifp->if_oerrors++; 1717 continue; 1718 } 1719 if (error) { 1720 ifp->if_flags |= IFF_OACTIVE; 1721 break; 1722 } 1723 1724 IFQ_DEQUEUE(&ifp->if_snd, m); 1725 1726 #if NBPFILTER > 0 1727 /* 1728 * If there's a BPF listener, bounce a copy of this frame 1729 * to him. 1730 */ 1731 if (ifp->if_bpf) 1732 bpf_mtap(ifp->if_bpf, m); 1733 #endif 1734 } 1735 1736 if (sc->rtk_ldata.rtk_txq_prodidx == idx) { 1737 return; 1738 } 1739 sc->rtk_ldata.rtk_txq_prodidx = idx; 1740 1741 /* Flush the TX descriptors */ 1742 1743 bus_dmamap_sync(sc->sc_dmat, 1744 sc->rtk_ldata.rtk_tx_list_map, 1745 0, sc->rtk_ldata.rtk_tx_list_map->dm_mapsize, 1746 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1747 1748 /* 1749 * RealTek put the TX poll request register in a different 1750 * location on the 8169 gigE chip. I don't know why. 1751 */ 1752 1753 if (sc->rtk_type == RTK_8169) 1754 CSR_WRITE_2(sc, RTK_GTXSTART, RTK_TXSTART_START); 1755 else 1756 CSR_WRITE_2(sc, RTK_TXSTART, RTK_TXSTART_START); 1757 1758 /* 1759 * Use the countdown timer for interrupt moderation. 1760 * 'TX done' interrupts are disabled. Instead, we reset the 1761 * countdown timer, which will begin counting until it hits 1762 * the value in the TIMERINT register, and then trigger an 1763 * interrupt. Each time we write to the TIMERCNT register, 1764 * the timer count is reset to 0. 1765 */ 1766 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1767 1768 /* 1769 * Set a timeout in case the chip goes out to lunch. 1770 */ 1771 ifp->if_timer = 5; 1772 1773 return; 1774 } 1775 1776 static int 1777 re_init(struct ifnet *ifp) 1778 { 1779 struct rtk_softc *sc = ifp->if_softc; 1780 u_int32_t rxcfg = 0; 1781 u_int32_t reg; 1782 int error; 1783 1784 if ((error = re_enable(sc)) != 0) 1785 goto out; 1786 1787 /* 1788 * Cancel pending I/O and free all RX/TX buffers. 1789 */ 1790 re_stop(ifp, 0); 1791 1792 /* 1793 * Enable C+ RX and TX mode, as well as VLAN stripping and 1794 * RX checksum offload. We must configure the C+ register 1795 * before all others. 1796 */ 1797 reg = 0; 1798 1799 /* 1800 * XXX: Realtek docs say bits 0 and 1 are reserved, for 8169S/8110S. 1801 * FreeBSD drivers set these bits anyway (for 8139C+?). 1802 * So far, it works. 1803 */ 1804 1805 /* 1806 * XXX: For 8169 and 8196S revs below 2, set bit 14. 1807 * For 8169S/8110S rev 2 and above, do not set bit 14. 1808 */ 1809 if (sc->rtk_type == RTK_8169 && sc->sc_rev == 1) 1810 reg |= (0x1 << 14) | RTK_CPLUSCMD_PCI_MRW;; 1811 1812 if (1) {/* not for 8169S ? */ 1813 reg |= 1814 #ifdef RE_VLAN 1815 RTK_CPLUSCMD_VLANSTRIP | 1816 #endif 1817 (ifp->if_capenable & 1818 (IFCAP_CSUM_IPv4_Rx | IFCAP_CSUM_TCPv4_Rx | 1819 IFCAP_CSUM_UDPv4_Rx) ? 1820 RTK_CPLUSCMD_RXCSUM_ENB : 0); 1821 } 1822 1823 CSR_WRITE_2(sc, RTK_CPLUS_CMD, 1824 reg | RTK_CPLUSCMD_RXENB | RTK_CPLUSCMD_TXENB); 1825 1826 /* XXX: from Realtek-supplied Linux driver. Wholly undocumented. */ 1827 if (sc->rtk_type == RTK_8169) 1828 CSR_WRITE_2(sc, RTK_CPLUS_CMD+0x2, 0x0000); 1829 1830 DELAY(10000); 1831 1832 /* 1833 * Init our MAC address. Even though the chipset 1834 * documentation doesn't mention it, we need to enter "Config 1835 * register write enable" mode to modify the ID registers. 1836 */ 1837 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_WRITECFG); 1838 memcpy(®, LLADDR(ifp->if_sadl), 4); 1839 CSR_WRITE_STREAM_4(sc, RTK_IDR0, reg); 1840 reg = 0; 1841 memcpy(®, LLADDR(ifp->if_sadl) + 4, 4); 1842 CSR_WRITE_STREAM_4(sc, RTK_IDR4, reg); 1843 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 1844 1845 /* 1846 * For C+ mode, initialize the RX descriptors and mbufs. 1847 */ 1848 re_rx_list_init(sc); 1849 re_tx_list_init(sc); 1850 1851 /* 1852 * Enable transmit and receive. 1853 */ 1854 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1855 1856 /* 1857 * Set the initial TX and RX configuration. 1858 */ 1859 if (sc->rtk_testmode) { 1860 if (sc->rtk_type == RTK_8169) 1861 CSR_WRITE_4(sc, RTK_TXCFG, 1862 RTK_TXCFG_CONFIG | RTK_LOOPTEST_ON); 1863 else 1864 CSR_WRITE_4(sc, RTK_TXCFG, 1865 RTK_TXCFG_CONFIG | RTK_LOOPTEST_ON_CPLUS); 1866 } else 1867 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG); 1868 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG); 1869 1870 /* Set the individual bit to receive frames for this host only. */ 1871 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 1872 rxcfg |= RTK_RXCFG_RX_INDIV; 1873 1874 /* If we want promiscuous mode, set the allframes bit. */ 1875 if (ifp->if_flags & IFF_PROMISC) 1876 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 1877 else 1878 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 1879 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1880 1881 /* 1882 * Set capture broadcast bit to capture broadcast frames. 1883 */ 1884 if (ifp->if_flags & IFF_BROADCAST) 1885 rxcfg |= RTK_RXCFG_RX_BROAD; 1886 else 1887 rxcfg &= ~RTK_RXCFG_RX_BROAD; 1888 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1889 1890 /* 1891 * Program the multicast filter, if necessary. 1892 */ 1893 rtk_setmulti(sc); 1894 1895 #ifdef DEVICE_POLLING 1896 /* 1897 * Disable interrupts if we are polling. 1898 */ 1899 if (ifp->if_flags & IFF_POLLING) 1900 CSR_WRITE_2(sc, RTK_IMR, 0); 1901 else /* otherwise ... */ 1902 #endif /* DEVICE_POLLING */ 1903 /* 1904 * Enable interrupts. 1905 */ 1906 if (sc->rtk_testmode) 1907 CSR_WRITE_2(sc, RTK_IMR, 0); 1908 else 1909 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS); 1910 1911 /* Start RX/TX process. */ 1912 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 1913 #ifdef notdef 1914 /* Enable receiver and transmitter. */ 1915 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1916 #endif 1917 /* 1918 * Load the addresses of the RX and TX lists into the chip. 1919 */ 1920 1921 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_HI, 1922 RTK_ADDR_HI(sc->rtk_ldata.rtk_rx_list_map->dm_segs[0].ds_addr)); 1923 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_LO, 1924 RTK_ADDR_LO(sc->rtk_ldata.rtk_rx_list_map->dm_segs[0].ds_addr)); 1925 1926 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_HI, 1927 RTK_ADDR_HI(sc->rtk_ldata.rtk_tx_list_map->dm_segs[0].ds_addr)); 1928 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_LO, 1929 RTK_ADDR_LO(sc->rtk_ldata.rtk_tx_list_map->dm_segs[0].ds_addr)); 1930 1931 CSR_WRITE_1(sc, RTK_EARLY_TX_THRESH, 16); 1932 1933 /* 1934 * Initialize the timer interrupt register so that 1935 * a timer interrupt will be generated once the timer 1936 * reaches a certain number of ticks. The timer is 1937 * reloaded on each transmit. This gives us TX interrupt 1938 * moderation, which dramatically improves TX frame rate. 1939 */ 1940 1941 if (sc->rtk_type == RTK_8169) 1942 CSR_WRITE_4(sc, RTK_TIMERINT_8169, 0x800); 1943 else 1944 CSR_WRITE_4(sc, RTK_TIMERINT, 0x400); 1945 1946 /* 1947 * For 8169 gigE NICs, set the max allowed RX packet 1948 * size so we can receive jumbo frames. 1949 */ 1950 if (sc->rtk_type == RTK_8169) 1951 CSR_WRITE_2(sc, RTK_MAXRXPKTLEN, 16383); 1952 1953 if (sc->rtk_testmode) 1954 return 0; 1955 1956 mii_mediachg(&sc->mii); 1957 1958 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD | RTK_CFG1_FULLDUPLEX); 1959 1960 ifp->if_flags |= IFF_RUNNING; 1961 ifp->if_flags &= ~IFF_OACTIVE; 1962 1963 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1964 1965 out: 1966 if (error) { 1967 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1968 ifp->if_timer = 0; 1969 aprint_error("%s: interface not running\n", 1970 sc->sc_dev.dv_xname); 1971 } 1972 1973 return error; 1974 1975 } 1976 1977 /* 1978 * Set media options. 1979 */ 1980 static int 1981 re_ifmedia_upd(struct ifnet *ifp) 1982 { 1983 struct rtk_softc *sc; 1984 1985 sc = ifp->if_softc; 1986 1987 return mii_mediachg(&sc->mii); 1988 } 1989 1990 /* 1991 * Report current media status. 1992 */ 1993 static void 1994 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1995 { 1996 struct rtk_softc *sc; 1997 1998 sc = ifp->if_softc; 1999 2000 mii_pollstat(&sc->mii); 2001 ifmr->ifm_active = sc->mii.mii_media_active; 2002 ifmr->ifm_status = sc->mii.mii_media_status; 2003 2004 return; 2005 } 2006 2007 static int 2008 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 2009 { 2010 struct rtk_softc *sc = ifp->if_softc; 2011 struct ifreq *ifr = (struct ifreq *) data; 2012 int s, error = 0; 2013 2014 s = splnet(); 2015 2016 switch (command) { 2017 case SIOCSIFMTU: 2018 if (ifr->ifr_mtu > RTK_JUMBO_MTU) 2019 error = EINVAL; 2020 ifp->if_mtu = ifr->ifr_mtu; 2021 break; 2022 case SIOCGIFMEDIA: 2023 case SIOCSIFMEDIA: 2024 error = ifmedia_ioctl(ifp, ifr, &sc->mii.mii_media, command); 2025 break; 2026 default: 2027 error = ether_ioctl(ifp, command, data); 2028 if (error == ENETRESET) { 2029 if (ifp->if_flags & IFF_RUNNING) 2030 rtk_setmulti(sc); 2031 error = 0; 2032 } 2033 break; 2034 } 2035 2036 splx(s); 2037 2038 return error; 2039 } 2040 2041 static void 2042 re_watchdog(struct ifnet *ifp) 2043 { 2044 struct rtk_softc *sc; 2045 int s; 2046 2047 sc = ifp->if_softc; 2048 s = splnet(); 2049 aprint_error("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 2050 ifp->if_oerrors++; 2051 2052 re_txeof(sc); 2053 re_rxeof(sc); 2054 2055 re_init(ifp); 2056 2057 splx(s); 2058 } 2059 2060 /* 2061 * Stop the adapter and free any mbufs allocated to the 2062 * RX and TX lists. 2063 */ 2064 static void 2065 re_stop(struct ifnet *ifp, int disable) 2066 { 2067 register int i; 2068 struct rtk_softc *sc = ifp->if_softc; 2069 2070 callout_stop(&sc->rtk_tick_ch); 2071 2072 #ifdef DEVICE_POLLING 2073 ether_poll_deregister(ifp); 2074 #endif /* DEVICE_POLLING */ 2075 2076 mii_down(&sc->mii); 2077 2078 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 2079 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 2080 2081 if (sc->rtk_head != NULL) { 2082 m_freem(sc->rtk_head); 2083 sc->rtk_head = sc->rtk_tail = NULL; 2084 } 2085 2086 /* Free the TX list buffers. */ 2087 for (i = 0; i < RTK_TX_QLEN; i++) { 2088 if (sc->rtk_ldata.rtk_txq[i].txq_mbuf != NULL) { 2089 bus_dmamap_unload(sc->sc_dmat, 2090 sc->rtk_ldata.rtk_txq[i].txq_dmamap); 2091 m_freem(sc->rtk_ldata.rtk_txq[i].txq_mbuf); 2092 sc->rtk_ldata.rtk_txq[i].txq_mbuf = NULL; 2093 } 2094 } 2095 2096 /* Free the RX list buffers. */ 2097 for (i = 0; i < RTK_RX_DESC_CNT; i++) { 2098 if (sc->rtk_ldata.rtk_rx_mbuf[i] != NULL) { 2099 bus_dmamap_unload(sc->sc_dmat, 2100 sc->rtk_ldata.rtk_rx_dmamap[i]); 2101 m_freem(sc->rtk_ldata.rtk_rx_mbuf[i]); 2102 sc->rtk_ldata.rtk_rx_mbuf[i] = NULL; 2103 } 2104 } 2105 2106 if (disable) 2107 re_disable(sc); 2108 2109 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2110 ifp->if_timer = 0; 2111 2112 return; 2113 } 2114