1 /* $NetBSD: rtl8169.c,v 1.103 2008/04/29 14:16:57 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998-2003 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.103 2008/04/29 14:16:57 tsutsui Exp $"); 37 /* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */ 38 39 /* 40 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 41 * 42 * Written by Bill Paul <wpaul@windriver.com> 43 * Senior Networking Software Engineer 44 * Wind River Systems 45 */ 46 47 /* 48 * This driver is designed to support RealTek's next generation of 49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 50 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 51 * and the RTL8110S. 52 * 53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 54 * with the older 8139 family, however it also supports a special 55 * C+ mode of operation that provides several new performance enhancing 56 * features. These include: 57 * 58 * o Descriptor based DMA mechanism. Each descriptor represents 59 * a single packet fragment. Data buffers may be aligned on 60 * any byte boundary. 61 * 62 * o 64-bit DMA 63 * 64 * o TCP/IP checksum offload for both RX and TX 65 * 66 * o High and normal priority transmit DMA rings 67 * 68 * o VLAN tag insertion and extraction 69 * 70 * o TCP large send (segmentation offload) 71 * 72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 73 * programming API is fairly straightforward. The RX filtering, EEPROM 74 * access and PHY access is the same as it is on the older 8139 series 75 * chips. 76 * 77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 78 * same programming API and feature set as the 8139C+ with the following 79 * differences and additions: 80 * 81 * o 1000Mbps mode 82 * 83 * o Jumbo frames 84 * 85 * o GMII and TBI ports/registers for interfacing with copper 86 * or fiber PHYs 87 * 88 * o RX and TX DMA rings can have up to 1024 descriptors 89 * (the 8139C+ allows a maximum of 64) 90 * 91 * o Slight differences in register layout from the 8139C+ 92 * 93 * The TX start and timer interrupt registers are at different locations 94 * on the 8169 than they are on the 8139C+. Also, the status word in the 95 * RX descriptor has a slightly different bit layout. The 8169 does not 96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 97 * copper gigE PHY. 98 * 99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 100 * (the 'S' stands for 'single-chip'). These devices have the same 101 * programming API as the older 8169, but also have some vendor-specific 102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 104 * 105 * This driver takes advantage of the RX and TX checksum offload and 106 * VLAN tag insertion/extraction features. It also implements TX 107 * interrupt moderation using the timer interrupt registers, which 108 * significantly reduces TX interrupt load. There is also support 109 * for jumbo frames, however the 8169/8169S/8110S can not transmit 110 * jumbo frames larger than 7.5K, so the max MTU possible with this 111 * driver is 7500 bytes. 112 */ 113 114 #include "bpfilter.h" 115 #include "vlan.h" 116 117 #include <sys/param.h> 118 #include <sys/endian.h> 119 #include <sys/systm.h> 120 #include <sys/sockio.h> 121 #include <sys/mbuf.h> 122 #include <sys/malloc.h> 123 #include <sys/kernel.h> 124 #include <sys/socket.h> 125 #include <sys/device.h> 126 127 #include <net/if.h> 128 #include <net/if_arp.h> 129 #include <net/if_dl.h> 130 #include <net/if_ether.h> 131 #include <net/if_media.h> 132 #include <net/if_vlanvar.h> 133 134 #include <netinet/in_systm.h> /* XXX for IP_MAXPACKET */ 135 #include <netinet/in.h> /* XXX for IP_MAXPACKET */ 136 #include <netinet/ip.h> /* XXX for IP_MAXPACKET */ 137 138 #if NBPFILTER > 0 139 #include <net/bpf.h> 140 #endif 141 142 #include <sys/bus.h> 143 144 #include <dev/mii/mii.h> 145 #include <dev/mii/miivar.h> 146 147 #include <dev/ic/rtl81x9reg.h> 148 #include <dev/ic/rtl81x9var.h> 149 150 #include <dev/ic/rtl8169var.h> 151 152 static inline void re_set_bufaddr(struct re_desc *, bus_addr_t); 153 154 static int re_newbuf(struct rtk_softc *, int, struct mbuf *); 155 static int re_rx_list_init(struct rtk_softc *); 156 static int re_tx_list_init(struct rtk_softc *); 157 static void re_rxeof(struct rtk_softc *); 158 static void re_txeof(struct rtk_softc *); 159 static void re_tick(void *); 160 static void re_start(struct ifnet *); 161 static int re_ioctl(struct ifnet *, u_long, void *); 162 static int re_init(struct ifnet *); 163 static void re_stop(struct ifnet *, int); 164 static void re_watchdog(struct ifnet *); 165 166 static int re_enable(struct rtk_softc *); 167 static void re_disable(struct rtk_softc *); 168 169 static int re_gmii_readreg(struct device *, int, int); 170 static void re_gmii_writereg(struct device *, int, int, int); 171 172 static int re_miibus_readreg(struct device *, int, int); 173 static void re_miibus_writereg(struct device *, int, int, int); 174 static void re_miibus_statchg(struct device *); 175 176 static void re_reset(struct rtk_softc *); 177 178 static inline void 179 re_set_bufaddr(struct re_desc *d, bus_addr_t addr) 180 { 181 182 d->re_bufaddr_lo = htole32((uint32_t)addr); 183 if (sizeof(bus_addr_t) == sizeof(uint64_t)) 184 d->re_bufaddr_hi = htole32((uint64_t)addr >> 32); 185 else 186 d->re_bufaddr_hi = 0; 187 } 188 189 static int 190 re_gmii_readreg(device_t dev, int phy, int reg) 191 { 192 struct rtk_softc *sc = device_private(dev); 193 uint32_t rval; 194 int i; 195 196 if (phy != 7) 197 return 0; 198 199 /* Let the rgephy driver read the GMEDIASTAT register */ 200 201 if (reg == RTK_GMEDIASTAT) { 202 rval = CSR_READ_1(sc, RTK_GMEDIASTAT); 203 return rval; 204 } 205 206 CSR_WRITE_4(sc, RTK_PHYAR, reg << 16); 207 DELAY(1000); 208 209 for (i = 0; i < RTK_TIMEOUT; i++) { 210 rval = CSR_READ_4(sc, RTK_PHYAR); 211 if (rval & RTK_PHYAR_BUSY) 212 break; 213 DELAY(100); 214 } 215 216 if (i == RTK_TIMEOUT) { 217 printf("%s: PHY read failed\n", device_xname(sc->sc_dev)); 218 return 0; 219 } 220 221 return rval & RTK_PHYAR_PHYDATA; 222 } 223 224 static void 225 re_gmii_writereg(device_t dev, int phy, int reg, int data) 226 { 227 struct rtk_softc *sc = device_private(dev); 228 uint32_t rval; 229 int i; 230 231 CSR_WRITE_4(sc, RTK_PHYAR, (reg << 16) | 232 (data & RTK_PHYAR_PHYDATA) | RTK_PHYAR_BUSY); 233 DELAY(1000); 234 235 for (i = 0; i < RTK_TIMEOUT; i++) { 236 rval = CSR_READ_4(sc, RTK_PHYAR); 237 if (!(rval & RTK_PHYAR_BUSY)) 238 break; 239 DELAY(100); 240 } 241 242 if (i == RTK_TIMEOUT) { 243 printf("%s: PHY write reg %x <- %x failed\n", 244 device_xname(sc->sc_dev), reg, data); 245 } 246 } 247 248 static int 249 re_miibus_readreg(device_t dev, int phy, int reg) 250 { 251 struct rtk_softc *sc = device_private(dev); 252 uint16_t rval = 0; 253 uint16_t re8139_reg = 0; 254 int s; 255 256 s = splnet(); 257 258 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 259 rval = re_gmii_readreg(dev, phy, reg); 260 splx(s); 261 return rval; 262 } 263 264 /* Pretend the internal PHY is only at address 0 */ 265 if (phy) { 266 splx(s); 267 return 0; 268 } 269 switch (reg) { 270 case MII_BMCR: 271 re8139_reg = RTK_BMCR; 272 break; 273 case MII_BMSR: 274 re8139_reg = RTK_BMSR; 275 break; 276 case MII_ANAR: 277 re8139_reg = RTK_ANAR; 278 break; 279 case MII_ANER: 280 re8139_reg = RTK_ANER; 281 break; 282 case MII_ANLPAR: 283 re8139_reg = RTK_LPAR; 284 break; 285 case MII_PHYIDR1: 286 case MII_PHYIDR2: 287 splx(s); 288 return 0; 289 /* 290 * Allow the rlphy driver to read the media status 291 * register. If we have a link partner which does not 292 * support NWAY, this is the register which will tell 293 * us the results of parallel detection. 294 */ 295 case RTK_MEDIASTAT: 296 rval = CSR_READ_1(sc, RTK_MEDIASTAT); 297 splx(s); 298 return rval; 299 default: 300 printf("%s: bad phy register\n", device_xname(sc->sc_dev)); 301 splx(s); 302 return 0; 303 } 304 rval = CSR_READ_2(sc, re8139_reg); 305 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0 && re8139_reg == RTK_BMCR) { 306 /* 8139C+ has different bit layout. */ 307 rval &= ~(BMCR_LOOP | BMCR_ISO); 308 } 309 splx(s); 310 return rval; 311 } 312 313 static void 314 re_miibus_writereg(device_t dev, int phy, int reg, int data) 315 { 316 struct rtk_softc *sc = device_private(dev); 317 uint16_t re8139_reg = 0; 318 int s; 319 320 s = splnet(); 321 322 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 323 re_gmii_writereg(dev, phy, reg, data); 324 splx(s); 325 return; 326 } 327 328 /* Pretend the internal PHY is only at address 0 */ 329 if (phy) { 330 splx(s); 331 return; 332 } 333 switch (reg) { 334 case MII_BMCR: 335 re8139_reg = RTK_BMCR; 336 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) { 337 /* 8139C+ has different bit layout. */ 338 data &= ~(BMCR_LOOP | BMCR_ISO); 339 } 340 break; 341 case MII_BMSR: 342 re8139_reg = RTK_BMSR; 343 break; 344 case MII_ANAR: 345 re8139_reg = RTK_ANAR; 346 break; 347 case MII_ANER: 348 re8139_reg = RTK_ANER; 349 break; 350 case MII_ANLPAR: 351 re8139_reg = RTK_LPAR; 352 break; 353 case MII_PHYIDR1: 354 case MII_PHYIDR2: 355 splx(s); 356 return; 357 break; 358 default: 359 printf("%s: bad phy register\n", device_xname(sc->sc_dev)); 360 splx(s); 361 return; 362 } 363 CSR_WRITE_2(sc, re8139_reg, data); 364 splx(s); 365 return; 366 } 367 368 static void 369 re_miibus_statchg(device_t dev) 370 { 371 372 return; 373 } 374 375 static void 376 re_reset(struct rtk_softc *sc) 377 { 378 int i; 379 380 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 381 382 for (i = 0; i < RTK_TIMEOUT; i++) { 383 DELAY(10); 384 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0) 385 break; 386 } 387 if (i == RTK_TIMEOUT) 388 printf("%s: reset never completed!\n", 389 device_xname(sc->sc_dev)); 390 391 /* 392 * NB: Realtek-supplied Linux driver does this only for 393 * MCFG_METHOD_2, which corresponds to sc->sc_rev == 2. 394 */ 395 if (1) /* XXX check softc flag for 8169s version */ 396 CSR_WRITE_1(sc, RTK_LDPS, 1); 397 398 } 399 400 /* 401 * The following routine is designed to test for a defect on some 402 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 403 * lines connected to the bus, however for a 32-bit only card, they 404 * should be pulled high. The result of this defect is that the 405 * NIC will not work right if you plug it into a 64-bit slot: DMA 406 * operations will be done with 64-bit transfers, which will fail 407 * because the 64-bit data lines aren't connected. 408 * 409 * There's no way to work around this (short of talking a soldering 410 * iron to the board), however we can detect it. The method we use 411 * here is to put the NIC into digital loopback mode, set the receiver 412 * to promiscuous mode, and then try to send a frame. We then compare 413 * the frame data we sent to what was received. If the data matches, 414 * then the NIC is working correctly, otherwise we know the user has 415 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 416 * slot. In the latter case, there's no way the NIC can work correctly, 417 * so we print out a message on the console and abort the device attach. 418 */ 419 420 int 421 re_diag(struct rtk_softc *sc) 422 { 423 struct ifnet *ifp = &sc->ethercom.ec_if; 424 struct mbuf *m0; 425 struct ether_header *eh; 426 struct re_rxsoft *rxs; 427 struct re_desc *cur_rx; 428 bus_dmamap_t dmamap; 429 uint16_t status; 430 uint32_t rxstat; 431 int total_len, i, s, error = 0; 432 static const uint8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 433 static const uint8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 434 435 /* Allocate a single mbuf */ 436 437 MGETHDR(m0, M_DONTWAIT, MT_DATA); 438 if (m0 == NULL) 439 return ENOBUFS; 440 441 /* 442 * Initialize the NIC in test mode. This sets the chip up 443 * so that it can send and receive frames, but performs the 444 * following special functions: 445 * - Puts receiver in promiscuous mode 446 * - Enables digital loopback mode 447 * - Leaves interrupts turned off 448 */ 449 450 ifp->if_flags |= IFF_PROMISC; 451 sc->re_testmode = 1; 452 re_init(ifp); 453 re_stop(ifp, 0); 454 DELAY(100000); 455 re_init(ifp); 456 457 /* Put some data in the mbuf */ 458 459 eh = mtod(m0, struct ether_header *); 460 memcpy(eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN); 461 memcpy(eh->ether_shost, (char *)&src, ETHER_ADDR_LEN); 462 eh->ether_type = htons(ETHERTYPE_IP); 463 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 464 465 /* 466 * Queue the packet, start transmission. 467 */ 468 469 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF); 470 s = splnet(); 471 IF_ENQUEUE(&ifp->if_snd, m0); 472 re_start(ifp); 473 splx(s); 474 m0 = NULL; 475 476 /* Wait for it to propagate through the chip */ 477 478 DELAY(100000); 479 for (i = 0; i < RTK_TIMEOUT; i++) { 480 status = CSR_READ_2(sc, RTK_ISR); 481 if ((status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) == 482 (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) 483 break; 484 DELAY(10); 485 } 486 if (i == RTK_TIMEOUT) { 487 aprint_error_dev(sc->sc_dev, 488 "diagnostic failed, failed to receive packet " 489 "in loopback mode\n"); 490 error = EIO; 491 goto done; 492 } 493 494 /* 495 * The packet should have been dumped into the first 496 * entry in the RX DMA ring. Grab it from there. 497 */ 498 499 rxs = &sc->re_ldata.re_rxsoft[0]; 500 dmamap = rxs->rxs_dmamap; 501 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 502 BUS_DMASYNC_POSTREAD); 503 bus_dmamap_unload(sc->sc_dmat, dmamap); 504 505 m0 = rxs->rxs_mbuf; 506 rxs->rxs_mbuf = NULL; 507 eh = mtod(m0, struct ether_header *); 508 509 RE_RXDESCSYNC(sc, 0, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 510 cur_rx = &sc->re_ldata.re_rx_list[0]; 511 rxstat = le32toh(cur_rx->re_cmdstat); 512 total_len = rxstat & sc->re_rxlenmask; 513 514 if (total_len != ETHER_MIN_LEN) { 515 aprint_error_dev(sc->sc_dev, 516 "diagnostic failed, received short packet\n"); 517 error = EIO; 518 goto done; 519 } 520 521 /* Test that the received packet data matches what we sent. */ 522 523 if (memcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 524 memcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 525 ntohs(eh->ether_type) != ETHERTYPE_IP) { 526 aprint_error_dev(sc->sc_dev, "WARNING, DMA FAILURE!\n"); 527 aprint_error_dev(sc->sc_dev, "expected TX data: %s", 528 ether_sprintf(dst)); 529 aprint_error("/%s/0x%x\n", ether_sprintf(src), ETHERTYPE_IP); 530 aprint_error_dev(sc->sc_dev, "received RX data: %s", 531 ether_sprintf(eh->ether_dhost)); 532 aprint_error("/%s/0x%x\n", ether_sprintf(eh->ether_shost), 533 ntohs(eh->ether_type)); 534 aprint_error_dev(sc->sc_dev, 535 "You may have a defective 32-bit NIC plugged " 536 "into a 64-bit PCI slot.\n"); 537 aprint_error_dev(sc->sc_dev, 538 "Please re-install the NIC in a 32-bit slot " 539 "for proper operation.\n"); 540 aprint_error_dev(sc->sc_dev, 541 "Read the re(4) man page for more details.\n"); 542 error = EIO; 543 } 544 545 done: 546 /* Turn interface off, release resources */ 547 548 sc->re_testmode = 0; 549 ifp->if_flags &= ~IFF_PROMISC; 550 re_stop(ifp, 0); 551 if (m0 != NULL) 552 m_freem(m0); 553 554 return error; 555 } 556 557 558 /* 559 * Attach the interface. Allocate softc structures, do ifmedia 560 * setup and ethernet/BPF attach. 561 */ 562 void 563 re_attach(struct rtk_softc *sc) 564 { 565 uint8_t eaddr[ETHER_ADDR_LEN]; 566 uint16_t val; 567 struct ifnet *ifp; 568 int error = 0, i, addr_len; 569 570 /* Reset the adapter. */ 571 re_reset(sc); 572 573 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 574 addr_len = RTK_EEADDR_LEN1; 575 else 576 addr_len = RTK_EEADDR_LEN0; 577 578 /* 579 * Get station address from the EEPROM. 580 */ 581 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 582 val = rtk_read_eeprom(sc, RTK_EE_EADDR0 + i, addr_len); 583 eaddr[(i * 2) + 0] = val & 0xff; 584 eaddr[(i * 2) + 1] = val >> 8; 585 } 586 587 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 588 uint32_t hwrev; 589 590 /* Revision of 8169/8169S/8110s in bits 30..26, 23 */ 591 hwrev = CSR_READ_4(sc, RTK_TXCFG) & RTK_TXCFG_HWREV; 592 /* These rev numbers are taken from Realtek's driver */ 593 if ( hwrev == RTK_HWREV_8100E_SPIN2) { 594 sc->sc_rev = 15; 595 } else if (hwrev == RTK_HWREV_8100E) { 596 sc->sc_rev = 14; 597 } else if (hwrev == RTK_HWREV_8101E) { 598 sc->sc_rev = 13; 599 } else if (hwrev == RTK_HWREV_8168_SPIN2 || 600 hwrev == RTK_HWREV_8168_SPIN3) { 601 sc->sc_rev = 12; 602 } else if (hwrev == RTK_HWREV_8168_SPIN1) { 603 sc->sc_rev = 11; 604 } else if (hwrev == RTK_HWREV_8169_8110SC) { 605 sc->sc_rev = 5; 606 } else if (hwrev == RTK_HWREV_8169_8110SB) { 607 sc->sc_rev = 4; 608 } else if (hwrev == RTK_HWREV_8169S) { 609 sc->sc_rev = 3; 610 } else if (hwrev == RTK_HWREV_8110S) { 611 sc->sc_rev = 2; 612 } else if (hwrev == RTK_HWREV_8169) { 613 sc->sc_rev = 1; 614 sc->sc_quirk |= RTKQ_8169NONS; 615 } else { 616 aprint_normal_dev(sc->sc_dev, 617 "Unknown revision (0x%08x)\n", hwrev); 618 /* assume the latest one */ 619 sc->sc_rev = 15; 620 } 621 622 /* Set RX length mask */ 623 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 624 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8169; 625 } else { 626 /* Set RX length mask */ 627 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 628 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8139; 629 } 630 631 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 632 ether_sprintf(eaddr)); 633 634 if (sc->re_ldata.re_tx_desc_cnt > 635 PAGE_SIZE / sizeof(struct re_desc)) { 636 sc->re_ldata.re_tx_desc_cnt = 637 PAGE_SIZE / sizeof(struct re_desc); 638 } 639 640 aprint_verbose_dev(sc->sc_dev, "using %d tx descriptors\n", 641 sc->re_ldata.re_tx_desc_cnt); 642 KASSERT(RE_NEXT_TX_DESC(sc, RE_TX_DESC_CNT(sc) - 1) == 0); 643 644 /* Allocate DMA'able memory for the TX ring */ 645 if ((error = bus_dmamem_alloc(sc->sc_dmat, RE_TX_LIST_SZ(sc), 646 RE_RING_ALIGN, 0, &sc->re_ldata.re_tx_listseg, 1, 647 &sc->re_ldata.re_tx_listnseg, BUS_DMA_NOWAIT)) != 0) { 648 aprint_error_dev(sc->sc_dev, 649 "can't allocate tx listseg, error = %d\n", error); 650 goto fail_0; 651 } 652 653 /* Load the map for the TX ring. */ 654 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_tx_listseg, 655 sc->re_ldata.re_tx_listnseg, RE_TX_LIST_SZ(sc), 656 (void **)&sc->re_ldata.re_tx_list, 657 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) { 658 aprint_error_dev(sc->sc_dev, 659 "can't map tx list, error = %d\n", error); 660 goto fail_1; 661 } 662 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc)); 663 664 if ((error = bus_dmamap_create(sc->sc_dmat, RE_TX_LIST_SZ(sc), 1, 665 RE_TX_LIST_SZ(sc), 0, 0, 666 &sc->re_ldata.re_tx_list_map)) != 0) { 667 aprint_error_dev(sc->sc_dev, 668 "can't create tx list map, error = %d\n", error); 669 goto fail_2; 670 } 671 672 673 if ((error = bus_dmamap_load(sc->sc_dmat, 674 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list, 675 RE_TX_LIST_SZ(sc), NULL, BUS_DMA_NOWAIT)) != 0) { 676 aprint_error_dev(sc->sc_dev, 677 "can't load tx list, error = %d\n", error); 678 goto fail_3; 679 } 680 681 /* Create DMA maps for TX buffers */ 682 for (i = 0; i < RE_TX_QLEN; i++) { 683 error = bus_dmamap_create(sc->sc_dmat, 684 round_page(IP_MAXPACKET), 685 RE_TX_DESC_CNT(sc), RE_TDESC_CMD_FRAGLEN, 686 0, 0, &sc->re_ldata.re_txq[i].txq_dmamap); 687 if (error) { 688 aprint_error_dev(sc->sc_dev, 689 "can't create DMA map for TX\n"); 690 goto fail_4; 691 } 692 } 693 694 /* Allocate DMA'able memory for the RX ring */ 695 /* XXX see also a comment about RE_RX_DMAMEM_SZ in rtl81x9var.h */ 696 if ((error = bus_dmamem_alloc(sc->sc_dmat, 697 RE_RX_DMAMEM_SZ, RE_RING_ALIGN, 0, &sc->re_ldata.re_rx_listseg, 1, 698 &sc->re_ldata.re_rx_listnseg, BUS_DMA_NOWAIT)) != 0) { 699 aprint_error_dev(sc->sc_dev, 700 "can't allocate rx listseg, error = %d\n", error); 701 goto fail_4; 702 } 703 704 /* Load the map for the RX ring. */ 705 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_rx_listseg, 706 sc->re_ldata.re_rx_listnseg, RE_RX_DMAMEM_SZ, 707 (void **)&sc->re_ldata.re_rx_list, 708 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) { 709 aprint_error_dev(sc->sc_dev, 710 "can't map rx list, error = %d\n", error); 711 goto fail_5; 712 } 713 memset(sc->re_ldata.re_rx_list, 0, RE_RX_DMAMEM_SZ); 714 715 if ((error = bus_dmamap_create(sc->sc_dmat, 716 RE_RX_DMAMEM_SZ, 1, RE_RX_DMAMEM_SZ, 0, 0, 717 &sc->re_ldata.re_rx_list_map)) != 0) { 718 aprint_error_dev(sc->sc_dev, 719 "can't create rx list map, error = %d\n", error); 720 goto fail_6; 721 } 722 723 if ((error = bus_dmamap_load(sc->sc_dmat, 724 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list, 725 RE_RX_DMAMEM_SZ, NULL, BUS_DMA_NOWAIT)) != 0) { 726 aprint_error_dev(sc->sc_dev, 727 "can't load rx list, error = %d\n", error); 728 goto fail_7; 729 } 730 731 /* Create DMA maps for RX buffers */ 732 for (i = 0; i < RE_RX_DESC_CNT; i++) { 733 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 734 0, 0, &sc->re_ldata.re_rxsoft[i].rxs_dmamap); 735 if (error) { 736 aprint_error_dev(sc->sc_dev, 737 "can't create DMA map for RX\n"); 738 goto fail_8; 739 } 740 } 741 742 /* 743 * Record interface as attached. From here, we should not fail. 744 */ 745 sc->sc_flags |= RTK_ATTACHED; 746 747 ifp = &sc->ethercom.ec_if; 748 ifp->if_softc = sc; 749 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 750 ifp->if_mtu = ETHERMTU; 751 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 752 ifp->if_ioctl = re_ioctl; 753 sc->ethercom.ec_capabilities |= 754 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 755 ifp->if_start = re_start; 756 ifp->if_stop = re_stop; 757 758 /* 759 * IFCAP_CSUM_IPv4_Tx on re(4) is broken for small packets, 760 * so we have a workaround to handle the bug by padding 761 * such packets manually. 762 */ 763 ifp->if_capabilities |= 764 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 765 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 766 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 767 IFCAP_TSOv4; 768 ifp->if_watchdog = re_watchdog; 769 ifp->if_init = re_init; 770 ifp->if_snd.ifq_maxlen = RE_IFQ_MAXLEN; 771 ifp->if_capenable = ifp->if_capabilities; 772 IFQ_SET_READY(&ifp->if_snd); 773 774 callout_init(&sc->rtk_tick_ch, 0); 775 776 /* Do MII setup */ 777 sc->mii.mii_ifp = ifp; 778 sc->mii.mii_readreg = re_miibus_readreg; 779 sc->mii.mii_writereg = re_miibus_writereg; 780 sc->mii.mii_statchg = re_miibus_statchg; 781 sc->ethercom.ec_mii = &sc->mii; 782 ifmedia_init(&sc->mii.mii_media, IFM_IMASK, ether_mediachange, 783 ether_mediastatus); 784 mii_attach(sc->sc_dev, &sc->mii, 0xffffffff, MII_PHY_ANY, 785 MII_OFFSET_ANY, 0); 786 ifmedia_set(&sc->mii.mii_media, IFM_ETHER | IFM_AUTO); 787 788 /* 789 * Call MI attach routine. 790 */ 791 if_attach(ifp); 792 ether_ifattach(ifp, eaddr); 793 794 return; 795 796 fail_8: 797 /* Destroy DMA maps for RX buffers. */ 798 for (i = 0; i < RE_RX_DESC_CNT; i++) 799 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL) 800 bus_dmamap_destroy(sc->sc_dmat, 801 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 802 803 /* Free DMA'able memory for the RX ring. */ 804 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 805 fail_7: 806 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 807 fail_6: 808 bus_dmamem_unmap(sc->sc_dmat, 809 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ); 810 fail_5: 811 bus_dmamem_free(sc->sc_dmat, 812 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg); 813 814 fail_4: 815 /* Destroy DMA maps for TX buffers. */ 816 for (i = 0; i < RE_TX_QLEN; i++) 817 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL) 818 bus_dmamap_destroy(sc->sc_dmat, 819 sc->re_ldata.re_txq[i].txq_dmamap); 820 821 /* Free DMA'able memory for the TX ring. */ 822 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 823 fail_3: 824 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 825 fail_2: 826 bus_dmamem_unmap(sc->sc_dmat, 827 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 828 fail_1: 829 bus_dmamem_free(sc->sc_dmat, 830 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg); 831 fail_0: 832 return; 833 } 834 835 836 /* 837 * re_activate: 838 * Handle device activation/deactivation requests. 839 */ 840 int 841 re_activate(device_t self, enum devact act) 842 { 843 struct rtk_softc *sc = device_private(self); 844 int s, error = 0; 845 846 s = splnet(); 847 switch (act) { 848 case DVACT_ACTIVATE: 849 error = EOPNOTSUPP; 850 break; 851 case DVACT_DEACTIVATE: 852 mii_activate(&sc->mii, act, MII_PHY_ANY, MII_OFFSET_ANY); 853 if_deactivate(&sc->ethercom.ec_if); 854 break; 855 } 856 splx(s); 857 858 return error; 859 } 860 861 /* 862 * re_detach: 863 * Detach a rtk interface. 864 */ 865 int 866 re_detach(struct rtk_softc *sc) 867 { 868 struct ifnet *ifp = &sc->ethercom.ec_if; 869 int i; 870 871 /* 872 * Succeed now if there isn't any work to do. 873 */ 874 if ((sc->sc_flags & RTK_ATTACHED) == 0) 875 return 0; 876 877 /* Unhook our tick handler. */ 878 callout_stop(&sc->rtk_tick_ch); 879 880 /* Detach all PHYs. */ 881 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 882 883 /* Delete all remaining media. */ 884 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY); 885 886 ether_ifdetach(ifp); 887 if_detach(ifp); 888 889 /* Destroy DMA maps for RX buffers. */ 890 for (i = 0; i < RE_RX_DESC_CNT; i++) 891 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL) 892 bus_dmamap_destroy(sc->sc_dmat, 893 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 894 895 /* Free DMA'able memory for the RX ring. */ 896 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 897 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 898 bus_dmamem_unmap(sc->sc_dmat, 899 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ); 900 bus_dmamem_free(sc->sc_dmat, 901 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg); 902 903 /* Destroy DMA maps for TX buffers. */ 904 for (i = 0; i < RE_TX_QLEN; i++) 905 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL) 906 bus_dmamap_destroy(sc->sc_dmat, 907 sc->re_ldata.re_txq[i].txq_dmamap); 908 909 /* Free DMA'able memory for the TX ring. */ 910 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 911 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 912 bus_dmamem_unmap(sc->sc_dmat, 913 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 914 bus_dmamem_free(sc->sc_dmat, 915 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg); 916 917 return 0; 918 } 919 920 /* 921 * re_enable: 922 * Enable the RTL81X9 chip. 923 */ 924 static int 925 re_enable(struct rtk_softc *sc) 926 { 927 928 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 929 if ((*sc->sc_enable)(sc) != 0) { 930 printf("%s: device enable failed\n", 931 device_xname(sc->sc_dev)); 932 return EIO; 933 } 934 sc->sc_flags |= RTK_ENABLED; 935 } 936 return 0; 937 } 938 939 /* 940 * re_disable: 941 * Disable the RTL81X9 chip. 942 */ 943 static void 944 re_disable(struct rtk_softc *sc) 945 { 946 947 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 948 (*sc->sc_disable)(sc); 949 sc->sc_flags &= ~RTK_ENABLED; 950 } 951 } 952 953 static int 954 re_newbuf(struct rtk_softc *sc, int idx, struct mbuf *m) 955 { 956 struct mbuf *n = NULL; 957 bus_dmamap_t map; 958 struct re_desc *d; 959 struct re_rxsoft *rxs; 960 uint32_t cmdstat; 961 int error; 962 963 if (m == NULL) { 964 MGETHDR(n, M_DONTWAIT, MT_DATA); 965 if (n == NULL) 966 return ENOBUFS; 967 968 MCLGET(n, M_DONTWAIT); 969 if ((n->m_flags & M_EXT) == 0) { 970 m_freem(n); 971 return ENOBUFS; 972 } 973 m = n; 974 } else 975 m->m_data = m->m_ext.ext_buf; 976 977 /* 978 * Initialize mbuf length fields and fixup 979 * alignment so that the frame payload is 980 * longword aligned. 981 */ 982 m->m_len = m->m_pkthdr.len = MCLBYTES - RE_ETHER_ALIGN; 983 m->m_data += RE_ETHER_ALIGN; 984 985 rxs = &sc->re_ldata.re_rxsoft[idx]; 986 map = rxs->rxs_dmamap; 987 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 988 BUS_DMA_READ|BUS_DMA_NOWAIT); 989 990 if (error) 991 goto out; 992 993 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 994 BUS_DMASYNC_PREREAD); 995 996 d = &sc->re_ldata.re_rx_list[idx]; 997 #ifdef DIAGNOSTIC 998 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 999 cmdstat = le32toh(d->re_cmdstat); 1000 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1001 if (cmdstat & RE_RDESC_STAT_OWN) { 1002 panic("%s: tried to map busy RX descriptor", 1003 device_xname(sc->sc_dev)); 1004 } 1005 #endif 1006 1007 rxs->rxs_mbuf = m; 1008 1009 d->re_vlanctl = 0; 1010 cmdstat = map->dm_segs[0].ds_len; 1011 if (idx == (RE_RX_DESC_CNT - 1)) 1012 cmdstat |= RE_RDESC_CMD_EOR; 1013 re_set_bufaddr(d, map->dm_segs[0].ds_addr); 1014 d->re_cmdstat = htole32(cmdstat); 1015 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1016 cmdstat |= RE_RDESC_CMD_OWN; 1017 d->re_cmdstat = htole32(cmdstat); 1018 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1019 1020 return 0; 1021 out: 1022 if (n != NULL) 1023 m_freem(n); 1024 return ENOMEM; 1025 } 1026 1027 static int 1028 re_tx_list_init(struct rtk_softc *sc) 1029 { 1030 int i; 1031 1032 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc)); 1033 for (i = 0; i < RE_TX_QLEN; i++) { 1034 sc->re_ldata.re_txq[i].txq_mbuf = NULL; 1035 } 1036 1037 bus_dmamap_sync(sc->sc_dmat, 1038 sc->re_ldata.re_tx_list_map, 0, 1039 sc->re_ldata.re_tx_list_map->dm_mapsize, 1040 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1041 sc->re_ldata.re_txq_prodidx = 0; 1042 sc->re_ldata.re_txq_considx = 0; 1043 sc->re_ldata.re_txq_free = RE_TX_QLEN; 1044 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT(sc); 1045 sc->re_ldata.re_tx_nextfree = 0; 1046 1047 return 0; 1048 } 1049 1050 static int 1051 re_rx_list_init(struct rtk_softc *sc) 1052 { 1053 int i; 1054 1055 memset(sc->re_ldata.re_rx_list, 0, RE_RX_LIST_SZ); 1056 1057 for (i = 0; i < RE_RX_DESC_CNT; i++) { 1058 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1059 return ENOBUFS; 1060 } 1061 1062 sc->re_ldata.re_rx_prodidx = 0; 1063 sc->re_head = sc->re_tail = NULL; 1064 1065 return 0; 1066 } 1067 1068 /* 1069 * RX handler for C+ and 8169. For the gigE chips, we support 1070 * the reception of jumbo frames that have been fragmented 1071 * across multiple 2K mbuf cluster buffers. 1072 */ 1073 static void 1074 re_rxeof(struct rtk_softc *sc) 1075 { 1076 struct mbuf *m; 1077 struct ifnet *ifp; 1078 int i, total_len; 1079 struct re_desc *cur_rx; 1080 struct re_rxsoft *rxs; 1081 uint32_t rxstat, rxvlan; 1082 1083 ifp = &sc->ethercom.ec_if; 1084 1085 for (i = sc->re_ldata.re_rx_prodidx;; i = RE_NEXT_RX_DESC(sc, i)) { 1086 cur_rx = &sc->re_ldata.re_rx_list[i]; 1087 RE_RXDESCSYNC(sc, i, 1088 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1089 rxstat = le32toh(cur_rx->re_cmdstat); 1090 rxvlan = le32toh(cur_rx->re_vlanctl); 1091 RE_RXDESCSYNC(sc, i, BUS_DMASYNC_PREREAD); 1092 if ((rxstat & RE_RDESC_STAT_OWN) != 0) { 1093 break; 1094 } 1095 total_len = rxstat & sc->re_rxlenmask; 1096 rxs = &sc->re_ldata.re_rxsoft[i]; 1097 m = rxs->rxs_mbuf; 1098 1099 /* Invalidate the RX mbuf and unload its map */ 1100 1101 bus_dmamap_sync(sc->sc_dmat, 1102 rxs->rxs_dmamap, 0, rxs->rxs_dmamap->dm_mapsize, 1103 BUS_DMASYNC_POSTREAD); 1104 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1105 1106 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1107 m->m_len = MCLBYTES - RE_ETHER_ALIGN; 1108 if (sc->re_head == NULL) 1109 sc->re_head = sc->re_tail = m; 1110 else { 1111 m->m_flags &= ~M_PKTHDR; 1112 sc->re_tail->m_next = m; 1113 sc->re_tail = m; 1114 } 1115 re_newbuf(sc, i, NULL); 1116 continue; 1117 } 1118 1119 /* 1120 * NOTE: for the 8139C+, the frame length field 1121 * is always 12 bits in size, but for the gigE chips, 1122 * it is 13 bits (since the max RX frame length is 16K). 1123 * Unfortunately, all 32 bits in the status word 1124 * were already used, so to make room for the extra 1125 * length bit, RealTek took out the 'frame alignment 1126 * error' bit and shifted the other status bits 1127 * over one slot. The OWN, EOR, FS and LS bits are 1128 * still in the same places. We have already extracted 1129 * the frame length and checked the OWN bit, so rather 1130 * than using an alternate bit mapping, we shift the 1131 * status bits one space to the right so we can evaluate 1132 * them using the 8169 status as though it was in the 1133 * same format as that of the 8139C+. 1134 */ 1135 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) 1136 rxstat >>= 1; 1137 1138 if (__predict_false((rxstat & RE_RDESC_STAT_RXERRSUM) != 0)) { 1139 #ifdef RE_DEBUG 1140 printf("%s: RX error (rxstat = 0x%08x)", 1141 device_xname(sc->sc_dev), rxstat); 1142 if (rxstat & RE_RDESC_STAT_FRALIGN) 1143 printf(", frame alignment error"); 1144 if (rxstat & RE_RDESC_STAT_BUFOFLOW) 1145 printf(", out of buffer space"); 1146 if (rxstat & RE_RDESC_STAT_FIFOOFLOW) 1147 printf(", FIFO overrun"); 1148 if (rxstat & RE_RDESC_STAT_GIANT) 1149 printf(", giant packet"); 1150 if (rxstat & RE_RDESC_STAT_RUNT) 1151 printf(", runt packet"); 1152 if (rxstat & RE_RDESC_STAT_CRCERR) 1153 printf(", CRC error"); 1154 printf("\n"); 1155 #endif 1156 ifp->if_ierrors++; 1157 /* 1158 * If this is part of a multi-fragment packet, 1159 * discard all the pieces. 1160 */ 1161 if (sc->re_head != NULL) { 1162 m_freem(sc->re_head); 1163 sc->re_head = sc->re_tail = NULL; 1164 } 1165 re_newbuf(sc, i, m); 1166 continue; 1167 } 1168 1169 /* 1170 * If allocating a replacement mbuf fails, 1171 * reload the current one. 1172 */ 1173 1174 if (__predict_false(re_newbuf(sc, i, NULL) != 0)) { 1175 ifp->if_ierrors++; 1176 if (sc->re_head != NULL) { 1177 m_freem(sc->re_head); 1178 sc->re_head = sc->re_tail = NULL; 1179 } 1180 re_newbuf(sc, i, m); 1181 continue; 1182 } 1183 1184 if (sc->re_head != NULL) { 1185 m->m_len = total_len % (MCLBYTES - RE_ETHER_ALIGN); 1186 /* 1187 * Special case: if there's 4 bytes or less 1188 * in this buffer, the mbuf can be discarded: 1189 * the last 4 bytes is the CRC, which we don't 1190 * care about anyway. 1191 */ 1192 if (m->m_len <= ETHER_CRC_LEN) { 1193 sc->re_tail->m_len -= 1194 (ETHER_CRC_LEN - m->m_len); 1195 m_freem(m); 1196 } else { 1197 m->m_len -= ETHER_CRC_LEN; 1198 m->m_flags &= ~M_PKTHDR; 1199 sc->re_tail->m_next = m; 1200 } 1201 m = sc->re_head; 1202 sc->re_head = sc->re_tail = NULL; 1203 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1204 } else 1205 m->m_pkthdr.len = m->m_len = 1206 (total_len - ETHER_CRC_LEN); 1207 1208 ifp->if_ipackets++; 1209 m->m_pkthdr.rcvif = ifp; 1210 1211 /* Do RX checksumming */ 1212 1213 /* Check IP header checksum */ 1214 if (rxstat & RE_RDESC_STAT_PROTOID) { 1215 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1216 if (rxstat & RE_RDESC_STAT_IPSUMBAD) 1217 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1218 } 1219 1220 /* Check TCP/UDP checksum */ 1221 if (RE_TCPPKT(rxstat)) { 1222 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1223 if (rxstat & RE_RDESC_STAT_TCPSUMBAD) 1224 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1225 } else if (RE_UDPPKT(rxstat)) { 1226 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1227 if (rxstat & RE_RDESC_STAT_UDPSUMBAD) 1228 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1229 } 1230 1231 if (rxvlan & RE_RDESC_VLANCTL_TAG) { 1232 VLAN_INPUT_TAG(ifp, m, 1233 bswap16(rxvlan & RE_RDESC_VLANCTL_DATA), 1234 continue); 1235 } 1236 #if NBPFILTER > 0 1237 if (ifp->if_bpf) 1238 bpf_mtap(ifp->if_bpf, m); 1239 #endif 1240 (*ifp->if_input)(ifp, m); 1241 } 1242 1243 sc->re_ldata.re_rx_prodidx = i; 1244 } 1245 1246 static void 1247 re_txeof(struct rtk_softc *sc) 1248 { 1249 struct ifnet *ifp; 1250 struct re_txq *txq; 1251 uint32_t txstat; 1252 int idx, descidx; 1253 1254 ifp = &sc->ethercom.ec_if; 1255 1256 for (idx = sc->re_ldata.re_txq_considx; 1257 sc->re_ldata.re_txq_free < RE_TX_QLEN; 1258 idx = RE_NEXT_TXQ(sc, idx), sc->re_ldata.re_txq_free++) { 1259 txq = &sc->re_ldata.re_txq[idx]; 1260 KASSERT(txq->txq_mbuf != NULL); 1261 1262 descidx = txq->txq_descidx; 1263 RE_TXDESCSYNC(sc, descidx, 1264 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1265 txstat = 1266 le32toh(sc->re_ldata.re_tx_list[descidx].re_cmdstat); 1267 RE_TXDESCSYNC(sc, descidx, BUS_DMASYNC_PREREAD); 1268 KASSERT((txstat & RE_TDESC_CMD_EOF) != 0); 1269 if (txstat & RE_TDESC_CMD_OWN) { 1270 break; 1271 } 1272 1273 sc->re_ldata.re_tx_free += txq->txq_nsegs; 1274 KASSERT(sc->re_ldata.re_tx_free <= RE_TX_DESC_CNT(sc)); 1275 bus_dmamap_sync(sc->sc_dmat, txq->txq_dmamap, 1276 0, txq->txq_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1277 bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap); 1278 m_freem(txq->txq_mbuf); 1279 txq->txq_mbuf = NULL; 1280 1281 if (txstat & (RE_TDESC_STAT_EXCESSCOL | RE_TDESC_STAT_COLCNT)) 1282 ifp->if_collisions++; 1283 if (txstat & RE_TDESC_STAT_TXERRSUM) 1284 ifp->if_oerrors++; 1285 else 1286 ifp->if_opackets++; 1287 } 1288 1289 sc->re_ldata.re_txq_considx = idx; 1290 1291 if (sc->re_ldata.re_txq_free > RE_NTXDESC_RSVD) 1292 ifp->if_flags &= ~IFF_OACTIVE; 1293 1294 /* 1295 * If not all descriptors have been released reaped yet, 1296 * reload the timer so that we will eventually get another 1297 * interrupt that will cause us to re-enter this routine. 1298 * This is done in case the transmitter has gone idle. 1299 */ 1300 if (sc->re_ldata.re_txq_free < RE_TX_QLEN) { 1301 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1302 if ((sc->sc_quirk & RTKQ_PCIE) != 0) { 1303 /* 1304 * Some chips will ignore a second TX request 1305 * issued while an existing transmission is in 1306 * progress. If the transmitter goes idle but 1307 * there are still packets waiting to be sent, 1308 * we need to restart the channel here to flush 1309 * them out. This only seems to be required with 1310 * the PCIe devices. 1311 */ 1312 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START); 1313 } 1314 } else 1315 ifp->if_timer = 0; 1316 } 1317 1318 static void 1319 re_tick(void *arg) 1320 { 1321 struct rtk_softc *sc = arg; 1322 int s; 1323 1324 /*XXX: just return for 8169S/8110S with rev 2 or newer phy */ 1325 s = splnet(); 1326 1327 mii_tick(&sc->mii); 1328 splx(s); 1329 1330 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1331 } 1332 1333 int 1334 re_intr(void *arg) 1335 { 1336 struct rtk_softc *sc = arg; 1337 struct ifnet *ifp; 1338 uint16_t status; 1339 int handled = 0; 1340 1341 if (!device_has_power(sc->sc_dev)) 1342 return 0; 1343 1344 ifp = &sc->ethercom.ec_if; 1345 1346 if ((ifp->if_flags & IFF_UP) == 0) 1347 return 0; 1348 1349 for (;;) { 1350 1351 status = CSR_READ_2(sc, RTK_ISR); 1352 /* If the card has gone away the read returns 0xffff. */ 1353 if (status == 0xffff) 1354 break; 1355 if (status) { 1356 handled = 1; 1357 CSR_WRITE_2(sc, RTK_ISR, status); 1358 } 1359 1360 if ((status & RTK_INTRS_CPLUS) == 0) 1361 break; 1362 1363 if (status & (RTK_ISR_RX_OK | RTK_ISR_RX_ERR)) 1364 re_rxeof(sc); 1365 1366 if (status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_TX_ERR | 1367 RTK_ISR_TX_DESC_UNAVAIL)) 1368 re_txeof(sc); 1369 1370 if (status & RTK_ISR_SYSTEM_ERR) { 1371 re_init(ifp); 1372 } 1373 1374 if (status & RTK_ISR_LINKCHG) { 1375 callout_stop(&sc->rtk_tick_ch); 1376 re_tick(sc); 1377 } 1378 } 1379 1380 if (handled && !IFQ_IS_EMPTY(&ifp->if_snd)) 1381 re_start(ifp); 1382 1383 return handled; 1384 } 1385 1386 1387 1388 /* 1389 * Main transmit routine for C+ and gigE NICs. 1390 */ 1391 1392 static void 1393 re_start(struct ifnet *ifp) 1394 { 1395 struct rtk_softc *sc; 1396 struct mbuf *m; 1397 bus_dmamap_t map; 1398 struct re_txq *txq; 1399 struct re_desc *d; 1400 struct m_tag *mtag; 1401 uint32_t cmdstat, re_flags, vlanctl; 1402 int ofree, idx, error, nsegs, seg; 1403 int startdesc, curdesc, lastdesc; 1404 bool pad; 1405 1406 sc = ifp->if_softc; 1407 ofree = sc->re_ldata.re_txq_free; 1408 1409 for (idx = sc->re_ldata.re_txq_prodidx;; idx = RE_NEXT_TXQ(sc, idx)) { 1410 1411 IFQ_POLL(&ifp->if_snd, m); 1412 if (m == NULL) 1413 break; 1414 1415 if (sc->re_ldata.re_txq_free == 0 || 1416 sc->re_ldata.re_tx_free == 0) { 1417 /* no more free slots left */ 1418 ifp->if_flags |= IFF_OACTIVE; 1419 break; 1420 } 1421 1422 /* 1423 * Set up checksum offload. Note: checksum offload bits must 1424 * appear in all descriptors of a multi-descriptor transmit 1425 * attempt. (This is according to testing done with an 8169 1426 * chip. I'm not sure if this is a requirement or a bug.) 1427 */ 1428 1429 if ((m->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0) { 1430 uint32_t segsz = m->m_pkthdr.segsz; 1431 1432 re_flags = RE_TDESC_CMD_LGSEND | 1433 (segsz << RE_TDESC_CMD_MSSVAL_SHIFT); 1434 } else { 1435 /* 1436 * set RE_TDESC_CMD_IPCSUM if any checksum offloading 1437 * is requested. otherwise, RE_TDESC_CMD_TCPCSUM/ 1438 * RE_TDESC_CMD_UDPCSUM doesn't make effects. 1439 */ 1440 re_flags = 0; 1441 if ((m->m_pkthdr.csum_flags & 1442 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1443 != 0) { 1444 re_flags |= RE_TDESC_CMD_IPCSUM; 1445 if (m->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1446 re_flags |= RE_TDESC_CMD_TCPCSUM; 1447 } else if (m->m_pkthdr.csum_flags & 1448 M_CSUM_UDPv4) { 1449 re_flags |= RE_TDESC_CMD_UDPCSUM; 1450 } 1451 } 1452 } 1453 1454 txq = &sc->re_ldata.re_txq[idx]; 1455 map = txq->txq_dmamap; 1456 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1457 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1458 1459 if (__predict_false(error)) { 1460 /* XXX try to defrag if EFBIG? */ 1461 printf("%s: can't map mbuf (error %d)\n", 1462 device_xname(sc->sc_dev), error); 1463 1464 IFQ_DEQUEUE(&ifp->if_snd, m); 1465 m_freem(m); 1466 ifp->if_oerrors++; 1467 continue; 1468 } 1469 1470 nsegs = map->dm_nsegs; 1471 pad = false; 1472 if (__predict_false(m->m_pkthdr.len <= RE_IP4CSUMTX_PADLEN && 1473 (re_flags & RE_TDESC_CMD_IPCSUM) != 0)) { 1474 pad = true; 1475 nsegs++; 1476 } 1477 1478 if (nsegs > sc->re_ldata.re_tx_free) { 1479 /* 1480 * Not enough free descriptors to transmit this packet. 1481 */ 1482 ifp->if_flags |= IFF_OACTIVE; 1483 bus_dmamap_unload(sc->sc_dmat, map); 1484 break; 1485 } 1486 1487 IFQ_DEQUEUE(&ifp->if_snd, m); 1488 1489 /* 1490 * Make sure that the caches are synchronized before we 1491 * ask the chip to start DMA for the packet data. 1492 */ 1493 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1494 BUS_DMASYNC_PREWRITE); 1495 1496 /* 1497 * Set up hardware VLAN tagging. Note: vlan tag info must 1498 * appear in all descriptors of a multi-descriptor 1499 * transmission attempt. 1500 */ 1501 vlanctl = 0; 1502 if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m)) != NULL) 1503 vlanctl = bswap16(VLAN_TAG_VALUE(mtag)) | 1504 RE_TDESC_VLANCTL_TAG; 1505 1506 /* 1507 * Map the segment array into descriptors. 1508 * Note that we set the start-of-frame and 1509 * end-of-frame markers for either TX or RX, 1510 * but they really only have meaning in the TX case. 1511 * (In the RX case, it's the chip that tells us 1512 * where packets begin and end.) 1513 * We also keep track of the end of the ring 1514 * and set the end-of-ring bits as needed, 1515 * and we set the ownership bits in all except 1516 * the very first descriptor. (The caller will 1517 * set this descriptor later when it start 1518 * transmission or reception.) 1519 */ 1520 curdesc = startdesc = sc->re_ldata.re_tx_nextfree; 1521 lastdesc = -1; 1522 for (seg = 0; seg < map->dm_nsegs; 1523 seg++, curdesc = RE_NEXT_TX_DESC(sc, curdesc)) { 1524 d = &sc->re_ldata.re_tx_list[curdesc]; 1525 #ifdef DIAGNOSTIC 1526 RE_TXDESCSYNC(sc, curdesc, 1527 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1528 cmdstat = le32toh(d->re_cmdstat); 1529 RE_TXDESCSYNC(sc, curdesc, BUS_DMASYNC_PREREAD); 1530 if (cmdstat & RE_TDESC_STAT_OWN) { 1531 panic("%s: tried to map busy TX descriptor", 1532 device_xname(sc->sc_dev)); 1533 } 1534 #endif 1535 1536 d->re_vlanctl = htole32(vlanctl); 1537 re_set_bufaddr(d, map->dm_segs[seg].ds_addr); 1538 cmdstat = re_flags | map->dm_segs[seg].ds_len; 1539 if (seg == 0) 1540 cmdstat |= RE_TDESC_CMD_SOF; 1541 else 1542 cmdstat |= RE_TDESC_CMD_OWN; 1543 if (curdesc == (RE_TX_DESC_CNT(sc) - 1)) 1544 cmdstat |= RE_TDESC_CMD_EOR; 1545 if (seg == nsegs - 1) { 1546 cmdstat |= RE_TDESC_CMD_EOF; 1547 lastdesc = curdesc; 1548 } 1549 d->re_cmdstat = htole32(cmdstat); 1550 RE_TXDESCSYNC(sc, curdesc, 1551 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1552 } 1553 if (__predict_false(pad)) { 1554 bus_addr_t paddaddr; 1555 1556 d = &sc->re_ldata.re_tx_list[curdesc]; 1557 d->re_vlanctl = htole32(vlanctl); 1558 paddaddr = RE_TXPADDADDR(sc); 1559 re_set_bufaddr(d, paddaddr); 1560 cmdstat = re_flags | 1561 RE_TDESC_CMD_OWN | RE_TDESC_CMD_EOF | 1562 (RE_IP4CSUMTX_PADLEN + 1 - m->m_pkthdr.len); 1563 if (curdesc == (RE_TX_DESC_CNT(sc) - 1)) 1564 cmdstat |= RE_TDESC_CMD_EOR; 1565 d->re_cmdstat = htole32(cmdstat); 1566 RE_TXDESCSYNC(sc, curdesc, 1567 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1568 lastdesc = curdesc; 1569 curdesc = RE_NEXT_TX_DESC(sc, curdesc); 1570 } 1571 KASSERT(lastdesc != -1); 1572 1573 /* Transfer ownership of packet to the chip. */ 1574 1575 sc->re_ldata.re_tx_list[startdesc].re_cmdstat |= 1576 htole32(RE_TDESC_CMD_OWN); 1577 RE_TXDESCSYNC(sc, startdesc, 1578 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1579 1580 /* update info of TX queue and descriptors */ 1581 txq->txq_mbuf = m; 1582 txq->txq_descidx = lastdesc; 1583 txq->txq_nsegs = nsegs; 1584 1585 sc->re_ldata.re_txq_free--; 1586 sc->re_ldata.re_tx_free -= nsegs; 1587 sc->re_ldata.re_tx_nextfree = curdesc; 1588 1589 #if NBPFILTER > 0 1590 /* 1591 * If there's a BPF listener, bounce a copy of this frame 1592 * to him. 1593 */ 1594 if (ifp->if_bpf) 1595 bpf_mtap(ifp->if_bpf, m); 1596 #endif 1597 } 1598 1599 if (sc->re_ldata.re_txq_free < ofree) { 1600 /* 1601 * TX packets are enqueued. 1602 */ 1603 sc->re_ldata.re_txq_prodidx = idx; 1604 1605 /* 1606 * Start the transmitter to poll. 1607 * 1608 * RealTek put the TX poll request register in a different 1609 * location on the 8169 gigE chip. I don't know why. 1610 */ 1611 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) 1612 CSR_WRITE_1(sc, RTK_TXSTART, RTK_TXSTART_START); 1613 else 1614 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START); 1615 1616 /* 1617 * Use the countdown timer for interrupt moderation. 1618 * 'TX done' interrupts are disabled. Instead, we reset the 1619 * countdown timer, which will begin counting until it hits 1620 * the value in the TIMERINT register, and then trigger an 1621 * interrupt. Each time we write to the TIMERCNT register, 1622 * the timer count is reset to 0. 1623 */ 1624 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1625 1626 /* 1627 * Set a timeout in case the chip goes out to lunch. 1628 */ 1629 ifp->if_timer = 5; 1630 } 1631 } 1632 1633 static int 1634 re_init(struct ifnet *ifp) 1635 { 1636 struct rtk_softc *sc = ifp->if_softc; 1637 const uint8_t *enaddr; 1638 uint32_t rxcfg = 0; 1639 uint32_t reg; 1640 int error; 1641 1642 if ((error = re_enable(sc)) != 0) 1643 goto out; 1644 1645 /* 1646 * Cancel pending I/O and free all RX/TX buffers. 1647 */ 1648 re_stop(ifp, 0); 1649 1650 re_reset(sc); 1651 1652 /* 1653 * Enable C+ RX and TX mode, as well as VLAN stripping and 1654 * RX checksum offload. We must configure the C+ register 1655 * before all others. 1656 */ 1657 reg = 0; 1658 1659 /* 1660 * XXX: Realtek docs say bits 0 and 1 are reserved, for 8169S/8110S. 1661 * FreeBSD drivers set these bits anyway (for 8139C+?). 1662 * So far, it works. 1663 */ 1664 1665 /* 1666 * XXX: For old 8169 set bit 14. 1667 * For 8169S/8110S and above, do not set bit 14. 1668 */ 1669 if ((sc->sc_quirk & RTKQ_8169NONS) != 0) 1670 reg |= (0x1 << 14) | RTK_CPLUSCMD_PCI_MRW;; 1671 1672 if (1) {/* not for 8169S ? */ 1673 reg |= 1674 RTK_CPLUSCMD_VLANSTRIP | 1675 (ifp->if_capenable & 1676 (IFCAP_CSUM_IPv4_Rx | IFCAP_CSUM_TCPv4_Rx | 1677 IFCAP_CSUM_UDPv4_Rx) ? 1678 RTK_CPLUSCMD_RXCSUM_ENB : 0); 1679 } 1680 1681 CSR_WRITE_2(sc, RTK_CPLUS_CMD, 1682 reg | RTK_CPLUSCMD_RXENB | RTK_CPLUSCMD_TXENB); 1683 1684 /* XXX: from Realtek-supplied Linux driver. Wholly undocumented. */ 1685 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) 1686 CSR_WRITE_2(sc, RTK_IM, 0x0000); 1687 1688 DELAY(10000); 1689 1690 /* 1691 * Init our MAC address. Even though the chipset 1692 * documentation doesn't mention it, we need to enter "Config 1693 * register write enable" mode to modify the ID registers. 1694 */ 1695 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_WRITECFG); 1696 enaddr = CLLADDR(ifp->if_sadl); 1697 reg = enaddr[0] | (enaddr[1] << 8) | 1698 (enaddr[2] << 16) | (enaddr[3] << 24); 1699 CSR_WRITE_4(sc, RTK_IDR0, reg); 1700 reg = enaddr[4] | (enaddr[5] << 8); 1701 CSR_WRITE_4(sc, RTK_IDR4, reg); 1702 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 1703 1704 /* 1705 * For C+ mode, initialize the RX descriptors and mbufs. 1706 */ 1707 re_rx_list_init(sc); 1708 re_tx_list_init(sc); 1709 1710 /* 1711 * Load the addresses of the RX and TX lists into the chip. 1712 */ 1713 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_HI, 1714 RE_ADDR_HI(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr)); 1715 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_LO, 1716 RE_ADDR_LO(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr)); 1717 1718 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_HI, 1719 RE_ADDR_HI(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr)); 1720 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_LO, 1721 RE_ADDR_LO(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr)); 1722 1723 /* 1724 * Enable transmit and receive. 1725 */ 1726 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1727 1728 /* 1729 * Set the initial TX and RX configuration. 1730 */ 1731 if (sc->re_testmode && (sc->sc_quirk & RTKQ_8169NONS) != 0) { 1732 /* test mode is needed only for old 8169 */ 1733 CSR_WRITE_4(sc, RTK_TXCFG, 1734 RE_TXCFG_CONFIG | RTK_LOOPTEST_ON); 1735 } else 1736 CSR_WRITE_4(sc, RTK_TXCFG, RE_TXCFG_CONFIG); 1737 1738 CSR_WRITE_1(sc, RTK_EARLY_TX_THRESH, 16); 1739 1740 CSR_WRITE_4(sc, RTK_RXCFG, RE_RXCFG_CONFIG); 1741 1742 /* Set the individual bit to receive frames for this host only. */ 1743 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 1744 rxcfg |= RTK_RXCFG_RX_INDIV; 1745 1746 /* If we want promiscuous mode, set the allframes bit. */ 1747 if (ifp->if_flags & IFF_PROMISC) 1748 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 1749 else 1750 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 1751 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1752 1753 /* 1754 * Set capture broadcast bit to capture broadcast frames. 1755 */ 1756 if (ifp->if_flags & IFF_BROADCAST) 1757 rxcfg |= RTK_RXCFG_RX_BROAD; 1758 else 1759 rxcfg &= ~RTK_RXCFG_RX_BROAD; 1760 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1761 1762 /* 1763 * Program the multicast filter, if necessary. 1764 */ 1765 rtk_setmulti(sc); 1766 1767 /* 1768 * Enable interrupts. 1769 */ 1770 if (sc->re_testmode) 1771 CSR_WRITE_2(sc, RTK_IMR, 0); 1772 else 1773 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS); 1774 1775 /* Start RX/TX process. */ 1776 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 1777 #ifdef notdef 1778 /* Enable receiver and transmitter. */ 1779 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1780 #endif 1781 1782 /* 1783 * Initialize the timer interrupt register so that 1784 * a timer interrupt will be generated once the timer 1785 * reaches a certain number of ticks. The timer is 1786 * reloaded on each transmit. This gives us TX interrupt 1787 * moderation, which dramatically improves TX frame rate. 1788 */ 1789 1790 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) 1791 CSR_WRITE_4(sc, RTK_TIMERINT, 0x400); 1792 else { 1793 CSR_WRITE_4(sc, RTK_TIMERINT_8169, 0x800); 1794 1795 /* 1796 * For 8169 gigE NICs, set the max allowed RX packet 1797 * size so we can receive jumbo frames. 1798 */ 1799 CSR_WRITE_2(sc, RTK_MAXRXPKTLEN, 16383); 1800 } 1801 1802 if (sc->re_testmode) 1803 return 0; 1804 1805 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD); 1806 1807 ifp->if_flags |= IFF_RUNNING; 1808 ifp->if_flags &= ~IFF_OACTIVE; 1809 1810 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1811 1812 out: 1813 if (error) { 1814 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1815 ifp->if_timer = 0; 1816 printf("%s: interface not running\n", 1817 device_xname(sc->sc_dev)); 1818 } 1819 1820 return error; 1821 } 1822 1823 static int 1824 re_ioctl(struct ifnet *ifp, u_long command, void *data) 1825 { 1826 struct rtk_softc *sc = ifp->if_softc; 1827 struct ifreq *ifr = data; 1828 int s, error = 0; 1829 1830 s = splnet(); 1831 1832 switch (command) { 1833 case SIOCSIFMTU: 1834 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO) 1835 error = EINVAL; 1836 else if ((error = ifioctl_common(ifp, command, data)) == 1837 ENETRESET) 1838 error = 0; 1839 break; 1840 default: 1841 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1842 break; 1843 1844 error = 0; 1845 1846 if (command == SIOCSIFCAP) 1847 error = (*ifp->if_init)(ifp); 1848 else if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1849 ; 1850 else if (ifp->if_flags & IFF_RUNNING) 1851 rtk_setmulti(sc); 1852 break; 1853 } 1854 1855 splx(s); 1856 1857 return error; 1858 } 1859 1860 static void 1861 re_watchdog(struct ifnet *ifp) 1862 { 1863 struct rtk_softc *sc; 1864 int s; 1865 1866 sc = ifp->if_softc; 1867 s = splnet(); 1868 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1869 ifp->if_oerrors++; 1870 1871 re_txeof(sc); 1872 re_rxeof(sc); 1873 1874 re_init(ifp); 1875 1876 splx(s); 1877 } 1878 1879 /* 1880 * Stop the adapter and free any mbufs allocated to the 1881 * RX and TX lists. 1882 */ 1883 static void 1884 re_stop(struct ifnet *ifp, int disable) 1885 { 1886 int i; 1887 struct rtk_softc *sc = ifp->if_softc; 1888 1889 callout_stop(&sc->rtk_tick_ch); 1890 1891 mii_down(&sc->mii); 1892 1893 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 1894 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1895 1896 if (sc->re_head != NULL) { 1897 m_freem(sc->re_head); 1898 sc->re_head = sc->re_tail = NULL; 1899 } 1900 1901 /* Free the TX list buffers. */ 1902 for (i = 0; i < RE_TX_QLEN; i++) { 1903 if (sc->re_ldata.re_txq[i].txq_mbuf != NULL) { 1904 bus_dmamap_unload(sc->sc_dmat, 1905 sc->re_ldata.re_txq[i].txq_dmamap); 1906 m_freem(sc->re_ldata.re_txq[i].txq_mbuf); 1907 sc->re_ldata.re_txq[i].txq_mbuf = NULL; 1908 } 1909 } 1910 1911 /* Free the RX list buffers. */ 1912 for (i = 0; i < RE_RX_DESC_CNT; i++) { 1913 if (sc->re_ldata.re_rxsoft[i].rxs_mbuf != NULL) { 1914 bus_dmamap_unload(sc->sc_dmat, 1915 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 1916 m_freem(sc->re_ldata.re_rxsoft[i].rxs_mbuf); 1917 sc->re_ldata.re_rxsoft[i].rxs_mbuf = NULL; 1918 } 1919 } 1920 1921 if (disable) 1922 re_disable(sc); 1923 1924 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1925 ifp->if_timer = 0; 1926 } 1927