1 /* $NetBSD: rtl8169.c,v 1.177 2024/07/05 04:31:51 rin Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998-2003 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.177 2024/07/05 04:31:51 rin Exp $"); 37 /* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */ 38 39 /* 40 * RealTek 8139C+/8169/8169S/8168/8110S PCI NIC driver 41 * 42 * Written by Bill Paul <wpaul@windriver.com> 43 * Senior Networking Software Engineer 44 * Wind River Systems 45 */ 46 47 /* 48 * This driver is designed to support RealTek's next generation of 49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 50 * six devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 51 * RTL8110S, the RTL8168 and the RTL8111. 52 * 53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 54 * with the older 8139 family, however it also supports a special 55 * C+ mode of operation that provides several new performance enhancing 56 * features. These include: 57 * 58 * o Descriptor based DMA mechanism. Each descriptor represents 59 * a single packet fragment. Data buffers may be aligned on 60 * any byte boundary. 61 * 62 * o 64-bit DMA 63 * 64 * o TCP/IP checksum offload for both RX and TX 65 * 66 * o High and normal priority transmit DMA rings 67 * 68 * o VLAN tag insertion and extraction 69 * 70 * o TCP large send (segmentation offload) 71 * 72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 73 * programming API is fairly straightforward. The RX filtering, EEPROM 74 * access and PHY access is the same as it is on the older 8139 series 75 * chips. 76 * 77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 78 * same programming API and feature set as the 8139C+ with the following 79 * differences and additions: 80 * 81 * o 1000Mbps mode 82 * 83 * o Jumbo frames 84 * 85 * o GMII and TBI ports/registers for interfacing with copper 86 * or fiber PHYs 87 * 88 * o RX and TX DMA rings can have up to 1024 descriptors 89 * (the 8139C+ allows a maximum of 64) 90 * 91 * o Slight differences in register layout from the 8139C+ 92 * 93 * The TX start and timer interrupt registers are at different locations 94 * on the 8169 than they are on the 8139C+. Also, the status word in the 95 * RX descriptor has a slightly different bit layout. The 8169 does not 96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 97 * copper gigE PHY. 98 * 99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 100 * (the 'S' stands for 'single-chip'). These devices have the same 101 * programming API as the older 8169, but also have some vendor-specific 102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 104 * 105 * This driver takes advantage of the RX and TX checksum offload and 106 * VLAN tag insertion/extraction features. It also implements TX 107 * interrupt moderation using the timer interrupt registers, which 108 * significantly reduces TX interrupt load. There is also support 109 * for jumbo frames, however the 8169/8169S/8110S can not transmit 110 * jumbo frames larger than 7.5K, so the max MTU possible with this 111 * driver is 7500 bytes. 112 */ 113 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/kernel.h> 121 #include <sys/socket.h> 122 #include <sys/device.h> 123 124 #include <net/if.h> 125 #include <net/if_arp.h> 126 #include <net/if_dl.h> 127 #include <net/if_ether.h> 128 #include <net/if_media.h> 129 #include <net/if_vlanvar.h> 130 131 #include <netinet/in_systm.h> /* XXX for IP_MAXPACKET */ 132 #include <netinet/in.h> /* XXX for IP_MAXPACKET */ 133 #include <netinet/ip.h> /* XXX for IP_MAXPACKET */ 134 135 #include <net/bpf.h> 136 #include <sys/rndsource.h> 137 138 #include <sys/bus.h> 139 140 #include <dev/mii/mii.h> 141 #include <dev/mii/miivar.h> 142 143 #include <dev/ic/rtl81x9reg.h> 144 #include <dev/ic/rtl81x9var.h> 145 146 #include <dev/ic/rtl8169var.h> 147 148 static inline void re_set_bufaddr(struct re_desc *, bus_addr_t); 149 150 static int re_newbuf(struct rtk_softc *, int, struct mbuf *); 151 static int re_rx_list_init(struct rtk_softc *); 152 static int re_tx_list_init(struct rtk_softc *); 153 static void re_rxeof(struct rtk_softc *); 154 static void re_txeof(struct rtk_softc *); 155 static void re_tick(void *); 156 static void re_start(struct ifnet *); 157 static int re_ioctl(struct ifnet *, u_long, void *); 158 static int re_init(struct ifnet *); 159 static void re_stop(struct ifnet *, int); 160 static void re_watchdog(struct ifnet *); 161 162 static int re_enable(struct rtk_softc *); 163 static void re_disable(struct rtk_softc *); 164 165 static int re_gmii_readreg(device_t, int, int, uint16_t *); 166 static int re_gmii_writereg(device_t, int, int, uint16_t); 167 168 static int re_miibus_readreg(device_t, int, int, uint16_t *); 169 static int re_miibus_writereg(device_t, int, int, uint16_t); 170 static void re_miibus_statchg(struct ifnet *); 171 172 static void re_reset(struct rtk_softc *); 173 174 static const struct re_revision { 175 uint32_t re_chipid; 176 const char *re_name; 177 } re_revisions[] = { 178 { RTK_HWREV_8100, "RTL8100" }, 179 { RTK_HWREV_8100E, "RTL8100E" }, 180 { RTK_HWREV_8100E_SPIN2, "RTL8100E 2" }, 181 { RTK_HWREV_8101, "RTL8101" }, 182 { RTK_HWREV_8101E, "RTL8101E" }, 183 { RTK_HWREV_8102E, "RTL8102E" }, 184 { RTK_HWREV_8106E, "RTL8106E" }, 185 { RTK_HWREV_8401E, "RTL8401E" }, 186 { RTK_HWREV_8402, "RTL8402" }, 187 { RTK_HWREV_8411, "RTL8411" }, 188 { RTK_HWREV_8411B, "RTL8411B" }, 189 { RTK_HWREV_8102EL, "RTL8102EL" }, 190 { RTK_HWREV_8102EL_SPIN1, "RTL8102EL 1" }, 191 { RTK_HWREV_8103E, "RTL8103E" }, 192 { RTK_HWREV_8110S, "RTL8110S" }, 193 { RTK_HWREV_8139CPLUS, "RTL8139C+" }, 194 { RTK_HWREV_8168B_SPIN1, "RTL8168 1" }, 195 { RTK_HWREV_8168B_SPIN2, "RTL8168 2" }, 196 { RTK_HWREV_8168B_SPIN3, "RTL8168 3" }, 197 { RTK_HWREV_8168C, "RTL8168C/8111C" }, 198 { RTK_HWREV_8168C_SPIN2, "RTL8168C/8111C" }, 199 { RTK_HWREV_8168CP, "RTL8168CP/8111CP" }, 200 { RTK_HWREV_8168F, "RTL8168F/8111F" }, 201 { RTK_HWREV_8168G, "RTL8168G/8111G" }, 202 { RTK_HWREV_8168GU, "RTL8168GU/8111GU" }, 203 { RTK_HWREV_8168H, "RTL8168H/8111H" }, 204 { RTK_HWREV_8105E, "RTL8105E" }, 205 { RTK_HWREV_8105E_SPIN1, "RTL8105E" }, 206 { RTK_HWREV_8168D, "RTL8168D/8111D" }, 207 { RTK_HWREV_8168DP, "RTL8168DP/8111DP" }, 208 { RTK_HWREV_8168E, "RTL8168E/8111E" }, 209 { RTK_HWREV_8168E_VL, "RTL8168E/8111E-VL" }, 210 { RTK_HWREV_8168EP, "RTL8168EP/8111EP" }, 211 { RTK_HWREV_8168FP, "RTL8168FP/8117" }, 212 { RTK_HWREV_8169, "RTL8169" }, 213 { RTK_HWREV_8169_8110SB, "RTL8169/8110SB" }, 214 { RTK_HWREV_8169_8110SBL, "RTL8169SBL" }, 215 { RTK_HWREV_8169_8110SC, "RTL8169/8110SCd" }, 216 { RTK_HWREV_8169_8110SCE, "RTL8169/8110SCe" }, 217 { RTK_HWREV_8169S, "RTL8169S" }, 218 219 { 0, NULL } 220 }; 221 222 static inline void 223 re_set_bufaddr(struct re_desc *d, bus_addr_t addr) 224 { 225 226 d->re_bufaddr_lo = htole32(RE_ADDR_LO(addr)); 227 d->re_bufaddr_hi = htole32(RE_ADDR_HI(addr)); 228 } 229 230 static int 231 re_gmii_readreg(device_t dev, int phy, int reg, uint16_t *val) 232 { 233 struct rtk_softc *sc = device_private(dev); 234 uint32_t data; 235 int i; 236 237 if (phy != 7) 238 return -1; 239 240 /* Let the rgephy driver read the GMEDIASTAT register */ 241 242 if (reg == RTK_GMEDIASTAT) { 243 *val = CSR_READ_1(sc, RTK_GMEDIASTAT); 244 return 0; 245 } 246 247 CSR_WRITE_4(sc, RTK_PHYAR, reg << 16); 248 DELAY(1000); 249 250 for (i = 0; i < RTK_TIMEOUT; i++) { 251 data = CSR_READ_4(sc, RTK_PHYAR); 252 if (data & RTK_PHYAR_BUSY) 253 break; 254 DELAY(100); 255 } 256 257 if (i == RTK_TIMEOUT) { 258 printf("%s: PHY read failed\n", device_xname(sc->sc_dev)); 259 return ETIMEDOUT; 260 } 261 262 *val = data & RTK_PHYAR_PHYDATA; 263 return 0; 264 } 265 266 static int 267 re_gmii_writereg(device_t dev, int phy, int reg, uint16_t val) 268 { 269 struct rtk_softc *sc = device_private(dev); 270 uint32_t data; 271 int i; 272 273 CSR_WRITE_4(sc, RTK_PHYAR, (reg << 16) | 274 (val & RTK_PHYAR_PHYDATA) | RTK_PHYAR_BUSY); 275 DELAY(1000); 276 277 for (i = 0; i < RTK_TIMEOUT; i++) { 278 data = CSR_READ_4(sc, RTK_PHYAR); 279 if (!(data & RTK_PHYAR_BUSY)) 280 break; 281 DELAY(100); 282 } 283 284 if (i == RTK_TIMEOUT) { 285 printf("%s: PHY write reg %x <- %hx failed\n", 286 device_xname(sc->sc_dev), reg, val); 287 return ETIMEDOUT; 288 } 289 290 return 0; 291 } 292 293 static int 294 re_miibus_readreg(device_t dev, int phy, int reg, uint16_t *val) 295 { 296 struct rtk_softc *sc = device_private(dev); 297 uint16_t re8139_reg = 0; 298 int s, rv = 0; 299 300 s = splnet(); 301 302 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 303 rv = re_gmii_readreg(dev, phy, reg, val); 304 splx(s); 305 return rv; 306 } 307 308 /* Pretend the internal PHY is only at address 0 */ 309 if (phy) { 310 splx(s); 311 return -1; 312 } 313 switch (reg) { 314 case MII_BMCR: 315 re8139_reg = RTK_BMCR; 316 break; 317 case MII_BMSR: 318 re8139_reg = RTK_BMSR; 319 break; 320 case MII_ANAR: 321 re8139_reg = RTK_ANAR; 322 break; 323 case MII_ANER: 324 re8139_reg = RTK_ANER; 325 break; 326 case MII_ANLPAR: 327 re8139_reg = RTK_LPAR; 328 break; 329 case MII_PHYIDR1: 330 case MII_PHYIDR2: 331 *val = 0; 332 splx(s); 333 return 0; 334 /* 335 * Allow the rlphy driver to read the media status 336 * register. If we have a link partner which does not 337 * support NWAY, this is the register which will tell 338 * us the results of parallel detection. 339 */ 340 case RTK_MEDIASTAT: 341 *val = CSR_READ_1(sc, RTK_MEDIASTAT); 342 splx(s); 343 return 0; 344 default: 345 printf("%s: bad phy register\n", device_xname(sc->sc_dev)); 346 splx(s); 347 return -1; 348 } 349 *val = CSR_READ_2(sc, re8139_reg); 350 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0 && re8139_reg == RTK_BMCR) { 351 /* 8139C+ has different bit layout. */ 352 *val &= ~(BMCR_LOOP | BMCR_ISO); 353 } 354 splx(s); 355 return 0; 356 } 357 358 static int 359 re_miibus_writereg(device_t dev, int phy, int reg, uint16_t val) 360 { 361 struct rtk_softc *sc = device_private(dev); 362 uint16_t re8139_reg = 0; 363 int s, rv; 364 365 s = splnet(); 366 367 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 368 rv = re_gmii_writereg(dev, phy, reg, val); 369 splx(s); 370 return rv; 371 } 372 373 /* Pretend the internal PHY is only at address 0 */ 374 if (phy) { 375 splx(s); 376 return -1; 377 } 378 switch (reg) { 379 case MII_BMCR: 380 re8139_reg = RTK_BMCR; 381 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) { 382 /* 8139C+ has different bit layout. */ 383 val &= ~(BMCR_LOOP | BMCR_ISO); 384 } 385 break; 386 case MII_BMSR: 387 re8139_reg = RTK_BMSR; 388 break; 389 case MII_ANAR: 390 re8139_reg = RTK_ANAR; 391 break; 392 case MII_ANER: 393 re8139_reg = RTK_ANER; 394 break; 395 case MII_ANLPAR: 396 re8139_reg = RTK_LPAR; 397 break; 398 case MII_PHYIDR1: 399 case MII_PHYIDR2: 400 splx(s); 401 return 0; 402 break; 403 default: 404 printf("%s: bad phy register\n", device_xname(sc->sc_dev)); 405 splx(s); 406 return -1; 407 } 408 CSR_WRITE_2(sc, re8139_reg, val); 409 splx(s); 410 return 0; 411 } 412 413 static void 414 re_miibus_statchg(struct ifnet *ifp) 415 { 416 417 return; 418 } 419 420 static void 421 re_reset(struct rtk_softc *sc) 422 { 423 int i; 424 425 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 426 427 for (i = 0; i < RTK_TIMEOUT; i++) { 428 DELAY(10); 429 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0) 430 break; 431 } 432 if (i == RTK_TIMEOUT) 433 printf("%s: reset never completed!\n", 434 device_xname(sc->sc_dev)); 435 436 /* 437 * NB: Realtek-supplied FreeBSD driver does this only for MACFG_3, 438 * but also says "Rtl8169s sigle chip detected". 439 */ 440 if ((sc->sc_quirk & RTKQ_MACLDPS) != 0) 441 CSR_WRITE_1(sc, RTK_LDPS, 1); 442 443 } 444 445 /* 446 * The following routine is designed to test for a defect on some 447 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 448 * lines connected to the bus, however for a 32-bit only card, they 449 * should be pulled high. The result of this defect is that the 450 * NIC will not work right if you plug it into a 64-bit slot: DMA 451 * operations will be done with 64-bit transfers, which will fail 452 * because the 64-bit data lines aren't connected. 453 * 454 * There's no way to work around this (short of talking a soldering 455 * iron to the board), however we can detect it. The method we use 456 * here is to put the NIC into digital loopback mode, set the receiver 457 * to promiscuous mode, and then try to send a frame. We then compare 458 * the frame data we sent to what was received. If the data matches, 459 * then the NIC is working correctly, otherwise we know the user has 460 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 461 * slot. In the latter case, there's no way the NIC can work correctly, 462 * so we print out a message on the console and abort the device attach. 463 */ 464 465 int 466 re_diag(struct rtk_softc *sc) 467 { 468 struct ifnet *ifp = &sc->ethercom.ec_if; 469 struct mbuf *m0; 470 struct ether_header *eh; 471 struct re_rxsoft *rxs; 472 struct re_desc *cur_rx; 473 bus_dmamap_t dmamap; 474 uint16_t status; 475 uint32_t rxstat; 476 int total_len, i, s, error = 0; 477 static const uint8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 478 static const uint8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 479 480 /* Allocate a single mbuf */ 481 482 MGETHDR(m0, M_DONTWAIT, MT_DATA); 483 if (m0 == NULL) 484 return ENOBUFS; 485 486 /* 487 * Initialize the NIC in test mode. This sets the chip up 488 * so that it can send and receive frames, but performs the 489 * following special functions: 490 * - Puts receiver in promiscuous mode 491 * - Enables digital loopback mode 492 * - Leaves interrupts turned off 493 */ 494 495 ifp->if_flags |= IFF_PROMISC; 496 sc->re_testmode = 1; 497 re_init(ifp); 498 re_stop(ifp, 0); 499 DELAY(100000); 500 re_init(ifp); 501 502 /* Put some data in the mbuf */ 503 504 eh = mtod(m0, struct ether_header *); 505 memcpy(eh->ether_dhost, &dst, ETHER_ADDR_LEN); 506 memcpy(eh->ether_shost, &src, ETHER_ADDR_LEN); 507 eh->ether_type = htons(ETHERTYPE_IP); 508 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 509 510 /* 511 * Queue the packet, start transmission. 512 */ 513 514 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF); 515 s = splnet(); 516 IF_ENQUEUE(&ifp->if_snd, m0); 517 re_start(ifp); 518 splx(s); 519 m0 = NULL; 520 521 /* Wait for it to propagate through the chip */ 522 523 DELAY(100000); 524 for (i = 0; i < RTK_TIMEOUT; i++) { 525 status = CSR_READ_2(sc, RTK_ISR); 526 if ((status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) == 527 (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) 528 break; 529 DELAY(10); 530 } 531 if (i == RTK_TIMEOUT) { 532 aprint_error_dev(sc->sc_dev, 533 "diagnostic failed, failed to receive packet " 534 "in loopback mode\n"); 535 error = EIO; 536 goto done; 537 } 538 539 /* 540 * The packet should have been dumped into the first 541 * entry in the RX DMA ring. Grab it from there. 542 */ 543 544 rxs = &sc->re_ldata.re_rxsoft[0]; 545 dmamap = rxs->rxs_dmamap; 546 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 547 BUS_DMASYNC_POSTREAD); 548 bus_dmamap_unload(sc->sc_dmat, dmamap); 549 550 m0 = rxs->rxs_mbuf; 551 rxs->rxs_mbuf = NULL; 552 eh = mtod(m0, struct ether_header *); 553 554 RE_RXDESCSYNC(sc, 0, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 555 cur_rx = &sc->re_ldata.re_rx_list[0]; 556 rxstat = le32toh(cur_rx->re_cmdstat); 557 total_len = rxstat & sc->re_rxlenmask; 558 559 if (total_len != ETHER_MIN_LEN) { 560 aprint_error_dev(sc->sc_dev, 561 "diagnostic failed, received short packet\n"); 562 error = EIO; 563 goto done; 564 } 565 566 /* Test that the received packet data matches what we sent. */ 567 568 if (memcmp(&eh->ether_dhost, &dst, ETHER_ADDR_LEN) || 569 memcmp(&eh->ether_shost, &src, ETHER_ADDR_LEN) || 570 ntohs(eh->ether_type) != ETHERTYPE_IP) { 571 aprint_error_dev(sc->sc_dev, "WARNING, DMA FAILURE!\n" 572 "expected TX data: %s/%s/0x%x\n" 573 "received RX data: %s/%s/0x%x\n" 574 "You may have a defective 32-bit NIC plugged " 575 "into a 64-bit PCI slot.\n" 576 "Please re-install the NIC in a 32-bit slot " 577 "for proper operation.\n" 578 "Read the re(4) man page for more details.\n" , 579 ether_sprintf(dst), ether_sprintf(src), ETHERTYPE_IP, 580 ether_sprintf(eh->ether_dhost), 581 ether_sprintf(eh->ether_shost), ntohs(eh->ether_type)); 582 error = EIO; 583 } 584 585 done: 586 /* Turn interface off, release resources */ 587 588 sc->re_testmode = 0; 589 ifp->if_flags &= ~IFF_PROMISC; 590 re_stop(ifp, 0); 591 m_freem(m0); 592 593 return error; 594 } 595 596 597 /* 598 * Attach the interface. Allocate softc structures, do ifmedia 599 * setup and ethernet/BPF attach. 600 */ 601 void 602 re_attach(struct rtk_softc *sc) 603 { 604 uint8_t eaddr[ETHER_ADDR_LEN]; 605 struct ifnet *ifp; 606 struct mii_data *mii = &sc->mii; 607 int error = 0, i; 608 const struct re_revision *rr; 609 const char *re_name = NULL; 610 611 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 612 /* Revision of 8169/8169S/8110s in bits 30..26, 23 */ 613 sc->sc_hwrev = CSR_READ_4(sc, RTK_TXCFG) & RTK_TXCFG_HWREV; 614 615 for (rr = re_revisions; rr->re_name != NULL; rr++) { 616 if (rr->re_chipid == sc->sc_hwrev) 617 re_name = rr->re_name; 618 } 619 620 if (re_name == NULL) 621 aprint_normal_dev(sc->sc_dev, 622 "unknown ASIC (0x%04x)\n", sc->sc_hwrev >> 16); 623 else 624 aprint_normal_dev(sc->sc_dev, 625 "%s (0x%04x)\n", re_name, sc->sc_hwrev >> 16); 626 627 switch (sc->sc_hwrev) { 628 case RTK_HWREV_8169: 629 sc->sc_quirk |= RTKQ_8169NONS; 630 break; 631 case RTK_HWREV_8169S: 632 case RTK_HWREV_8110S: 633 case RTK_HWREV_8169_8110SB: 634 case RTK_HWREV_8169_8110SBL: 635 case RTK_HWREV_8169_8110SC: 636 sc->sc_quirk |= RTKQ_MACLDPS; 637 break; 638 case RTK_HWREV_8168B_SPIN1: 639 case RTK_HWREV_8168B_SPIN2: 640 case RTK_HWREV_8168B_SPIN3: 641 sc->sc_quirk |= RTKQ_MACSTAT; 642 break; 643 case RTK_HWREV_8168C: 644 case RTK_HWREV_8168C_SPIN2: 645 case RTK_HWREV_8168CP: 646 case RTK_HWREV_8168D: 647 case RTK_HWREV_8168DP: 648 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 649 RTKQ_MACSTAT | RTKQ_CMDSTOP; 650 /* 651 * From FreeBSD driver: 652 * 653 * These (8168/8111) controllers support jumbo frame 654 * but it seems that enabling it requires touching 655 * additional magic registers. Depending on MAC 656 * revisions some controllers need to disable 657 * checksum offload. So disable jumbo frame until 658 * I have better idea what it really requires to 659 * make it support. 660 * RTL8168C/CP : supports up to 6KB jumbo frame. 661 * RTL8111C/CP : supports up to 9KB jumbo frame. 662 */ 663 sc->sc_quirk |= RTKQ_NOJUMBO; 664 break; 665 case RTK_HWREV_8168E: 666 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 667 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_PHYWAKE_PM | 668 RTKQ_NOJUMBO; 669 break; 670 case RTK_HWREV_8168E_VL: 671 case RTK_HWREV_8168F: 672 case RTK_HWREV_8411: 673 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 674 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO; 675 break; 676 case RTK_HWREV_8168EP: 677 case RTK_HWREV_8168FP: 678 case RTK_HWREV_8168G: 679 case RTK_HWREV_8168GU: 680 case RTK_HWREV_8168H: 681 case RTK_HWREV_8411B: 682 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 683 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO | 684 RTKQ_RXDV_GATED | RTKQ_TXRXEN_LATER; 685 break; 686 case RTK_HWREV_8100E: 687 case RTK_HWREV_8100E_SPIN2: 688 case RTK_HWREV_8101E: 689 sc->sc_quirk |= RTKQ_NOJUMBO; 690 break; 691 case RTK_HWREV_8102E: 692 case RTK_HWREV_8102EL: 693 case RTK_HWREV_8102EL_SPIN1: 694 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 695 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO; 696 break; 697 case RTK_HWREV_8103E: 698 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 699 RTKQ_MACSTAT | RTKQ_CMDSTOP; 700 break; 701 case RTK_HWREV_8401E: 702 case RTK_HWREV_8105E: 703 case RTK_HWREV_8105E_SPIN1: /* XXX */ 704 case RTK_HWREV_8106E: 705 sc->sc_quirk |= RTKQ_PHYWAKE_PM | 706 RTKQ_DESCV2 | RTKQ_NOEECMD | RTKQ_MACSTAT | 707 RTKQ_CMDSTOP; 708 break; 709 case RTK_HWREV_8402: 710 sc->sc_quirk |= RTKQ_PHYWAKE_PM | 711 RTKQ_DESCV2 | RTKQ_NOEECMD | RTKQ_MACSTAT | 712 RTKQ_CMDSTOP; /* CMDSTOP_WAIT_TXQ */ 713 break; 714 default: 715 /* assume the latest features */ 716 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD; 717 sc->sc_quirk |= RTKQ_NOJUMBO; 718 } 719 720 /* Set RX length mask */ 721 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 722 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8169; 723 } else { 724 sc->sc_quirk |= RTKQ_NOJUMBO; 725 726 /* Set RX length mask */ 727 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 728 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8139; 729 } 730 731 /* Reset the adapter. */ 732 re_reset(sc); 733 734 /* 735 * RTL81x9 chips automatically read EEPROM to init MAC address, 736 * and some NAS override its MAC address per own configuration, 737 * so no need to explicitly read EEPROM and set ID registers. 738 */ 739 #ifdef RE_USE_EECMD 740 if ((sc->sc_quirk & RTKQ_NOEECMD) != 0) { 741 /* 742 * Get station address from ID registers. 743 */ 744 for (i = 0; i < ETHER_ADDR_LEN; i++) 745 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i); 746 } else { 747 uint16_t val; 748 int addr_len; 749 750 /* 751 * Get station address from the EEPROM. 752 */ 753 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 754 addr_len = RTK_EEADDR_LEN1; 755 else 756 addr_len = RTK_EEADDR_LEN0; 757 758 /* 759 * Get station address from the EEPROM. 760 */ 761 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 762 val = rtk_read_eeprom(sc, RTK_EE_EADDR0 + i, addr_len); 763 eaddr[(i * 2) + 0] = val & 0xff; 764 eaddr[(i * 2) + 1] = val >> 8; 765 } 766 } 767 #else 768 /* 769 * Get station address from ID registers. 770 */ 771 for (i = 0; i < ETHER_ADDR_LEN; i++) 772 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i); 773 #endif 774 775 /* Take PHY out of power down mode. */ 776 if ((sc->sc_quirk & RTKQ_PHYWAKE_PM) != 0) 777 CSR_WRITE_1(sc, RTK_PMCH, CSR_READ_1(sc, RTK_PMCH) | 0x80); 778 779 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 780 ether_sprintf(eaddr)); 781 782 if (sc->re_ldata.re_tx_desc_cnt > 783 PAGE_SIZE / sizeof(struct re_desc)) { 784 sc->re_ldata.re_tx_desc_cnt = 785 PAGE_SIZE / sizeof(struct re_desc); 786 } 787 788 aprint_verbose_dev(sc->sc_dev, "using %d tx descriptors\n", 789 sc->re_ldata.re_tx_desc_cnt); 790 KASSERT(RE_NEXT_TX_DESC(sc, RE_TX_DESC_CNT(sc) - 1) == 0); 791 792 /* Allocate DMA'able memory for the TX ring */ 793 if ((error = bus_dmamem_alloc(sc->sc_dmat, RE_TX_LIST_SZ(sc), 794 RE_RING_ALIGN, 0, &sc->re_ldata.re_tx_listseg, 1, 795 &sc->re_ldata.re_tx_listnseg, BUS_DMA_NOWAIT)) != 0) { 796 aprint_error_dev(sc->sc_dev, 797 "can't allocate tx listseg, error = %d\n", error); 798 goto fail_0; 799 } 800 801 /* Load the map for the TX ring. */ 802 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_tx_listseg, 803 sc->re_ldata.re_tx_listnseg, RE_TX_LIST_SZ(sc), 804 (void **)&sc->re_ldata.re_tx_list, 805 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) { 806 aprint_error_dev(sc->sc_dev, 807 "can't map tx list, error = %d\n", error); 808 goto fail_1; 809 } 810 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc)); 811 812 if ((error = bus_dmamap_create(sc->sc_dmat, RE_TX_LIST_SZ(sc), 1, 813 RE_TX_LIST_SZ(sc), 0, 0, 814 &sc->re_ldata.re_tx_list_map)) != 0) { 815 aprint_error_dev(sc->sc_dev, 816 "can't create tx list map, error = %d\n", error); 817 goto fail_2; 818 } 819 820 821 if ((error = bus_dmamap_load(sc->sc_dmat, 822 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list, 823 RE_TX_LIST_SZ(sc), NULL, BUS_DMA_NOWAIT)) != 0) { 824 aprint_error_dev(sc->sc_dev, 825 "can't load tx list, error = %d\n", error); 826 goto fail_3; 827 } 828 829 /* Create DMA maps for TX buffers */ 830 for (i = 0; i < RE_TX_QLEN; i++) { 831 error = bus_dmamap_create(sc->sc_dmat, 832 round_page(IP_MAXPACKET), 833 RE_TX_DESC_CNT(sc), RE_TDESC_CMD_FRAGLEN, 834 0, 0, &sc->re_ldata.re_txq[i].txq_dmamap); 835 if (error) { 836 aprint_error_dev(sc->sc_dev, 837 "can't create DMA map for TX\n"); 838 goto fail_4; 839 } 840 } 841 842 /* Allocate DMA'able memory for the RX ring */ 843 /* XXX see also a comment about RE_RX_DMAMEM_SZ in rtl81x9var.h */ 844 if ((error = bus_dmamem_alloc(sc->sc_dmat, 845 RE_RX_DMAMEM_SZ, RE_RING_ALIGN, 0, &sc->re_ldata.re_rx_listseg, 1, 846 &sc->re_ldata.re_rx_listnseg, BUS_DMA_NOWAIT)) != 0) { 847 aprint_error_dev(sc->sc_dev, 848 "can't allocate rx listseg, error = %d\n", error); 849 goto fail_4; 850 } 851 852 /* Load the map for the RX ring. */ 853 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_rx_listseg, 854 sc->re_ldata.re_rx_listnseg, RE_RX_DMAMEM_SZ, 855 (void **)&sc->re_ldata.re_rx_list, 856 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) { 857 aprint_error_dev(sc->sc_dev, 858 "can't map rx list, error = %d\n", error); 859 goto fail_5; 860 } 861 memset(sc->re_ldata.re_rx_list, 0, RE_RX_DMAMEM_SZ); 862 863 if ((error = bus_dmamap_create(sc->sc_dmat, 864 RE_RX_DMAMEM_SZ, 1, RE_RX_DMAMEM_SZ, 0, 0, 865 &sc->re_ldata.re_rx_list_map)) != 0) { 866 aprint_error_dev(sc->sc_dev, 867 "can't create rx list map, error = %d\n", error); 868 goto fail_6; 869 } 870 871 if ((error = bus_dmamap_load(sc->sc_dmat, 872 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list, 873 RE_RX_DMAMEM_SZ, NULL, BUS_DMA_NOWAIT)) != 0) { 874 aprint_error_dev(sc->sc_dev, 875 "can't load rx list, error = %d\n", error); 876 goto fail_7; 877 } 878 879 /* Create DMA maps for RX buffers */ 880 for (i = 0; i < RE_RX_DESC_CNT; i++) { 881 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 882 0, 0, &sc->re_ldata.re_rxsoft[i].rxs_dmamap); 883 if (error) { 884 aprint_error_dev(sc->sc_dev, 885 "can't create DMA map for RX\n"); 886 goto fail_8; 887 } 888 } 889 890 /* 891 * Record interface as attached. From here, we should not fail. 892 */ 893 sc->sc_flags |= RTK_ATTACHED; 894 895 ifp = &sc->ethercom.ec_if; 896 ifp->if_softc = sc; 897 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 898 ifp->if_mtu = ETHERMTU; 899 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 900 ifp->if_ioctl = re_ioctl; 901 sc->ethercom.ec_capabilities |= 902 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 903 ifp->if_start = re_start; 904 ifp->if_stop = re_stop; 905 906 /* 907 * IFCAP_CSUM_IPv4_Tx on re(4) is broken for small packets, 908 * so we have a workaround to handle the bug by padding 909 * such packets manually. 910 */ 911 ifp->if_capabilities |= 912 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 913 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 914 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 915 IFCAP_TSOv4; 916 917 ifp->if_watchdog = re_watchdog; 918 ifp->if_init = re_init; 919 ifp->if_snd.ifq_maxlen = RE_IFQ_MAXLEN; 920 ifp->if_capenable = ifp->if_capabilities; 921 IFQ_SET_READY(&ifp->if_snd); 922 923 callout_init(&sc->rtk_tick_ch, 0); 924 callout_setfunc(&sc->rtk_tick_ch, re_tick, sc); 925 926 /* Do MII setup */ 927 mii->mii_ifp = ifp; 928 mii->mii_readreg = re_miibus_readreg; 929 mii->mii_writereg = re_miibus_writereg; 930 mii->mii_statchg = re_miibus_statchg; 931 sc->ethercom.ec_mii = mii; 932 ifmedia_init(&mii->mii_media, IFM_IMASK, ether_mediachange, 933 ether_mediastatus); 934 mii_attach(sc->sc_dev, mii, 0xffffffff, MII_PHY_ANY, 935 MII_OFFSET_ANY, 0); 936 ifmedia_set(&mii->mii_media, IFM_ETHER | IFM_AUTO); 937 938 /* 939 * Call MI attach routine. 940 */ 941 if_attach(ifp); 942 if_deferred_start_init(ifp, NULL); 943 ether_ifattach(ifp, eaddr); 944 945 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 946 RND_TYPE_NET, RND_FLAG_DEFAULT); 947 948 if (pmf_device_register(sc->sc_dev, NULL, NULL)) 949 pmf_class_network_register(sc->sc_dev, ifp); 950 else 951 aprint_error_dev(sc->sc_dev, 952 "couldn't establish power handler\n"); 953 954 return; 955 956 fail_8: 957 /* Destroy DMA maps for RX buffers. */ 958 for (i = 0; i < RE_RX_DESC_CNT; i++) 959 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL) 960 bus_dmamap_destroy(sc->sc_dmat, 961 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 962 963 /* Free DMA'able memory for the RX ring. */ 964 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 965 fail_7: 966 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 967 fail_6: 968 bus_dmamem_unmap(sc->sc_dmat, 969 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ); 970 fail_5: 971 bus_dmamem_free(sc->sc_dmat, 972 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg); 973 974 fail_4: 975 /* Destroy DMA maps for TX buffers. */ 976 for (i = 0; i < RE_TX_QLEN; i++) 977 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL) 978 bus_dmamap_destroy(sc->sc_dmat, 979 sc->re_ldata.re_txq[i].txq_dmamap); 980 981 /* Free DMA'able memory for the TX ring. */ 982 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 983 fail_3: 984 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 985 fail_2: 986 bus_dmamem_unmap(sc->sc_dmat, 987 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 988 fail_1: 989 bus_dmamem_free(sc->sc_dmat, 990 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg); 991 fail_0: 992 return; 993 } 994 995 996 /* 997 * re_activate: 998 * Handle device activation/deactivation requests. 999 */ 1000 int 1001 re_activate(device_t self, enum devact act) 1002 { 1003 struct rtk_softc *sc = device_private(self); 1004 1005 switch (act) { 1006 case DVACT_DEACTIVATE: 1007 if_deactivate(&sc->ethercom.ec_if); 1008 return 0; 1009 default: 1010 return EOPNOTSUPP; 1011 } 1012 } 1013 1014 /* 1015 * re_detach: 1016 * Detach a rtk interface. 1017 */ 1018 int 1019 re_detach(struct rtk_softc *sc) 1020 { 1021 struct ifnet *ifp = &sc->ethercom.ec_if; 1022 int i; 1023 1024 /* 1025 * Succeed now if there isn't any work to do. 1026 */ 1027 if ((sc->sc_flags & RTK_ATTACHED) == 0) 1028 return 0; 1029 1030 /* Unhook our tick handler. */ 1031 callout_stop(&sc->rtk_tick_ch); 1032 1033 /* Detach all PHYs. */ 1034 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 1035 1036 rnd_detach_source(&sc->rnd_source); 1037 ether_ifdetach(ifp); 1038 if_detach(ifp); 1039 1040 /* Delete all remaining media. */ 1041 ifmedia_fini(&sc->mii.mii_media); 1042 1043 /* Destroy DMA maps for RX buffers. */ 1044 for (i = 0; i < RE_RX_DESC_CNT; i++) 1045 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL) 1046 bus_dmamap_destroy(sc->sc_dmat, 1047 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 1048 1049 /* Free DMA'able memory for the RX ring. */ 1050 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 1051 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 1052 bus_dmamem_unmap(sc->sc_dmat, 1053 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ); 1054 bus_dmamem_free(sc->sc_dmat, 1055 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg); 1056 1057 /* Destroy DMA maps for TX buffers. */ 1058 for (i = 0; i < RE_TX_QLEN; i++) 1059 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL) 1060 bus_dmamap_destroy(sc->sc_dmat, 1061 sc->re_ldata.re_txq[i].txq_dmamap); 1062 1063 /* Free DMA'able memory for the TX ring. */ 1064 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 1065 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 1066 bus_dmamem_unmap(sc->sc_dmat, 1067 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 1068 bus_dmamem_free(sc->sc_dmat, 1069 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg); 1070 1071 pmf_device_deregister(sc->sc_dev); 1072 1073 /* we don't want to run again */ 1074 sc->sc_flags &= ~RTK_ATTACHED; 1075 1076 return 0; 1077 } 1078 1079 /* 1080 * re_enable: 1081 * Enable the RTL81X9 chip. 1082 */ 1083 static int 1084 re_enable(struct rtk_softc *sc) 1085 { 1086 1087 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 1088 if ((*sc->sc_enable)(sc) != 0) { 1089 printf("%s: device enable failed\n", 1090 device_xname(sc->sc_dev)); 1091 return EIO; 1092 } 1093 sc->sc_flags |= RTK_ENABLED; 1094 } 1095 return 0; 1096 } 1097 1098 /* 1099 * re_disable: 1100 * Disable the RTL81X9 chip. 1101 */ 1102 static void 1103 re_disable(struct rtk_softc *sc) 1104 { 1105 1106 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 1107 (*sc->sc_disable)(sc); 1108 sc->sc_flags &= ~RTK_ENABLED; 1109 } 1110 } 1111 1112 static int 1113 re_newbuf(struct rtk_softc *sc, int idx, struct mbuf *m) 1114 { 1115 struct mbuf *n = NULL; 1116 bus_dmamap_t map; 1117 struct re_desc *d; 1118 struct re_rxsoft *rxs; 1119 uint32_t cmdstat; 1120 int error; 1121 1122 if (m == NULL) { 1123 MGETHDR(n, M_DONTWAIT, MT_DATA); 1124 if (n == NULL) 1125 return ENOBUFS; 1126 1127 MCLAIM(n, &sc->ethercom.ec_rx_mowner); 1128 MCLGET(n, M_DONTWAIT); 1129 if ((n->m_flags & M_EXT) == 0) { 1130 m_freem(n); 1131 return ENOBUFS; 1132 } 1133 m = n; 1134 } else 1135 m->m_data = m->m_ext.ext_buf; 1136 1137 /* 1138 * Initialize mbuf length fields and fixup 1139 * alignment so that the frame payload is 1140 * longword aligned. 1141 */ 1142 m->m_len = m->m_pkthdr.len = MCLBYTES - RE_ETHER_ALIGN; 1143 m->m_data += RE_ETHER_ALIGN; 1144 1145 rxs = &sc->re_ldata.re_rxsoft[idx]; 1146 map = rxs->rxs_dmamap; 1147 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1148 BUS_DMA_READ|BUS_DMA_NOWAIT); 1149 1150 if (error) 1151 goto out; 1152 1153 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1154 BUS_DMASYNC_PREREAD); 1155 1156 d = &sc->re_ldata.re_rx_list[idx]; 1157 #ifdef DIAGNOSTIC 1158 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1159 cmdstat = le32toh(d->re_cmdstat); 1160 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1161 if (cmdstat & RE_RDESC_STAT_OWN) { 1162 panic("%s: tried to map busy RX descriptor", 1163 device_xname(sc->sc_dev)); 1164 } 1165 #endif 1166 1167 rxs->rxs_mbuf = m; 1168 1169 d->re_vlanctl = 0; 1170 cmdstat = map->dm_segs[0].ds_len; 1171 if (idx == (RE_RX_DESC_CNT - 1)) 1172 cmdstat |= RE_RDESC_CMD_EOR; 1173 re_set_bufaddr(d, map->dm_segs[0].ds_addr); 1174 d->re_cmdstat = htole32(cmdstat); 1175 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1176 cmdstat |= RE_RDESC_CMD_OWN; 1177 d->re_cmdstat = htole32(cmdstat); 1178 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1179 1180 return 0; 1181 out: 1182 m_freem(n); 1183 return ENOMEM; 1184 } 1185 1186 static int 1187 re_tx_list_init(struct rtk_softc *sc) 1188 { 1189 int i; 1190 1191 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc)); 1192 for (i = 0; i < RE_TX_QLEN; i++) { 1193 sc->re_ldata.re_txq[i].txq_mbuf = NULL; 1194 } 1195 1196 bus_dmamap_sync(sc->sc_dmat, 1197 sc->re_ldata.re_tx_list_map, 0, 1198 sc->re_ldata.re_tx_list_map->dm_mapsize, 1199 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1200 sc->re_ldata.re_txq_prodidx = 0; 1201 sc->re_ldata.re_txq_considx = 0; 1202 sc->re_ldata.re_txq_free = RE_TX_QLEN; 1203 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT(sc); 1204 sc->re_ldata.re_tx_nextfree = 0; 1205 1206 return 0; 1207 } 1208 1209 static int 1210 re_rx_list_init(struct rtk_softc *sc) 1211 { 1212 int i; 1213 1214 memset(sc->re_ldata.re_rx_list, 0, RE_RX_LIST_SZ); 1215 1216 for (i = 0; i < RE_RX_DESC_CNT; i++) { 1217 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1218 return ENOBUFS; 1219 } 1220 1221 sc->re_ldata.re_rx_prodidx = 0; 1222 sc->re_head = sc->re_tail = NULL; 1223 1224 return 0; 1225 } 1226 1227 /* 1228 * RX handler for C+ and 8169. For the gigE chips, we support 1229 * the reception of jumbo frames that have been fragmented 1230 * across multiple 2K mbuf cluster buffers. 1231 */ 1232 static void 1233 re_rxeof(struct rtk_softc *sc) 1234 { 1235 struct mbuf *m; 1236 struct ifnet *ifp; 1237 int i, total_len; 1238 struct re_desc *cur_rx; 1239 struct re_rxsoft *rxs; 1240 uint32_t rxstat, rxvlan; 1241 1242 ifp = &sc->ethercom.ec_if; 1243 1244 for (i = sc->re_ldata.re_rx_prodidx;; i = RE_NEXT_RX_DESC(sc, i)) { 1245 cur_rx = &sc->re_ldata.re_rx_list[i]; 1246 RE_RXDESCSYNC(sc, i, 1247 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1248 rxstat = le32toh(cur_rx->re_cmdstat); 1249 rxvlan = le32toh(cur_rx->re_vlanctl); 1250 RE_RXDESCSYNC(sc, i, BUS_DMASYNC_PREREAD); 1251 if ((rxstat & RE_RDESC_STAT_OWN) != 0) { 1252 break; 1253 } 1254 total_len = rxstat & sc->re_rxlenmask; 1255 rxs = &sc->re_ldata.re_rxsoft[i]; 1256 m = rxs->rxs_mbuf; 1257 1258 /* Invalidate the RX mbuf and unload its map */ 1259 1260 bus_dmamap_sync(sc->sc_dmat, 1261 rxs->rxs_dmamap, 0, rxs->rxs_dmamap->dm_mapsize, 1262 BUS_DMASYNC_POSTREAD); 1263 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1264 1265 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1266 m->m_len = MCLBYTES - RE_ETHER_ALIGN; 1267 if (sc->re_head == NULL) 1268 sc->re_head = sc->re_tail = m; 1269 else { 1270 m_remove_pkthdr(m); 1271 sc->re_tail->m_next = m; 1272 sc->re_tail = m; 1273 } 1274 re_newbuf(sc, i, NULL); 1275 continue; 1276 } 1277 1278 /* 1279 * NOTE: for the 8139C+, the frame length field 1280 * is always 12 bits in size, but for the gigE chips, 1281 * it is 13 bits (since the max RX frame length is 16K). 1282 * Unfortunately, all 32 bits in the status word 1283 * were already used, so to make room for the extra 1284 * length bit, RealTek took out the 'frame alignment 1285 * error' bit and shifted the other status bits 1286 * over one slot. The OWN, EOR, FS and LS bits are 1287 * still in the same places. We have already extracted 1288 * the frame length and checked the OWN bit, so rather 1289 * than using an alternate bit mapping, we shift the 1290 * status bits one space to the right so we can evaluate 1291 * them using the 8169 status as though it was in the 1292 * same format as that of the 8139C+. 1293 */ 1294 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) 1295 rxstat >>= 1; 1296 1297 if (__predict_false((rxstat & RE_RDESC_STAT_RXERRSUM) != 0)) { 1298 #ifdef RE_DEBUG 1299 printf("%s: RX error (rxstat = 0x%08x)", 1300 device_xname(sc->sc_dev), rxstat); 1301 if (rxstat & RE_RDESC_STAT_FRALIGN) 1302 printf(", frame alignment error"); 1303 if (rxstat & RE_RDESC_STAT_BUFOFLOW) 1304 printf(", out of buffer space"); 1305 if (rxstat & RE_RDESC_STAT_FIFOOFLOW) 1306 printf(", FIFO overrun"); 1307 if (rxstat & RE_RDESC_STAT_GIANT) 1308 printf(", giant packet"); 1309 if (rxstat & RE_RDESC_STAT_RUNT) 1310 printf(", runt packet"); 1311 if (rxstat & RE_RDESC_STAT_CRCERR) 1312 printf(", CRC error"); 1313 printf("\n"); 1314 #endif 1315 if_statinc(ifp, if_ierrors); 1316 /* 1317 * If this is part of a multi-fragment packet, 1318 * discard all the pieces. 1319 */ 1320 if (sc->re_head != NULL) { 1321 m_freem(sc->re_head); 1322 sc->re_head = sc->re_tail = NULL; 1323 } 1324 re_newbuf(sc, i, m); 1325 continue; 1326 } 1327 1328 /* 1329 * If allocating a replacement mbuf fails, 1330 * reload the current one. 1331 */ 1332 1333 if (__predict_false(re_newbuf(sc, i, NULL) != 0)) { 1334 if_statinc(ifp, if_ierrors); 1335 if (sc->re_head != NULL) { 1336 m_freem(sc->re_head); 1337 sc->re_head = sc->re_tail = NULL; 1338 } 1339 re_newbuf(sc, i, m); 1340 continue; 1341 } 1342 1343 if (sc->re_head != NULL) { 1344 m->m_len = total_len % (MCLBYTES - RE_ETHER_ALIGN); 1345 /* 1346 * Special case: if there's 4 bytes or less 1347 * in this buffer, the mbuf can be discarded: 1348 * the last 4 bytes is the CRC, which we don't 1349 * care about anyway. 1350 */ 1351 if (m->m_len <= ETHER_CRC_LEN) { 1352 sc->re_tail->m_len -= 1353 (ETHER_CRC_LEN - m->m_len); 1354 m_freem(m); 1355 } else { 1356 m->m_len -= ETHER_CRC_LEN; 1357 m_remove_pkthdr(m); 1358 sc->re_tail->m_next = m; 1359 } 1360 m = sc->re_head; 1361 sc->re_head = sc->re_tail = NULL; 1362 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1363 } else 1364 m->m_pkthdr.len = m->m_len = 1365 (total_len - ETHER_CRC_LEN); 1366 1367 m_set_rcvif(m, ifp); 1368 1369 /* Do RX checksumming */ 1370 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) { 1371 /* Check IP header checksum */ 1372 if ((rxstat & RE_RDESC_STAT_PROTOID) != 0) { 1373 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1374 if (rxstat & RE_RDESC_STAT_IPSUMBAD) 1375 m->m_pkthdr.csum_flags |= 1376 M_CSUM_IPv4_BAD; 1377 1378 /* Check TCP/UDP checksum */ 1379 if (RE_TCPPKT(rxstat)) { 1380 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1381 if (rxstat & RE_RDESC_STAT_TCPSUMBAD) 1382 m->m_pkthdr.csum_flags |= 1383 M_CSUM_TCP_UDP_BAD; 1384 } else if (RE_UDPPKT(rxstat)) { 1385 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1386 if (rxstat & RE_RDESC_STAT_UDPSUMBAD) { 1387 /* 1388 * XXX: 8139C+ thinks UDP csum 1389 * 0xFFFF is bad, force software 1390 * calculation. 1391 */ 1392 if (sc->sc_quirk & RTKQ_8139CPLUS) 1393 m->m_pkthdr.csum_flags 1394 &= ~M_CSUM_UDPv4; 1395 else 1396 m->m_pkthdr.csum_flags 1397 |= M_CSUM_TCP_UDP_BAD; 1398 } 1399 } 1400 } 1401 } else { 1402 /* Check IPv4 header checksum */ 1403 if ((rxvlan & RE_RDESC_VLANCTL_IPV4) != 0) { 1404 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1405 if (rxstat & RE_RDESC_STAT_IPSUMBAD) 1406 m->m_pkthdr.csum_flags |= 1407 M_CSUM_IPv4_BAD; 1408 1409 /* Check TCPv4/UDPv4 checksum */ 1410 if (RE_TCPPKT(rxstat)) { 1411 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1412 if (rxstat & RE_RDESC_STAT_TCPSUMBAD) 1413 m->m_pkthdr.csum_flags |= 1414 M_CSUM_TCP_UDP_BAD; 1415 } else if (RE_UDPPKT(rxstat)) { 1416 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1417 if (rxstat & RE_RDESC_STAT_UDPSUMBAD) 1418 m->m_pkthdr.csum_flags |= 1419 M_CSUM_TCP_UDP_BAD; 1420 } 1421 } 1422 /* XXX Check TCPv6/UDPv6 checksum? */ 1423 } 1424 1425 if (rxvlan & RE_RDESC_VLANCTL_TAG) { 1426 vlan_set_tag(m, 1427 bswap16(rxvlan & RE_RDESC_VLANCTL_DATA)); 1428 } 1429 if_percpuq_enqueue(ifp->if_percpuq, m); 1430 } 1431 1432 sc->re_ldata.re_rx_prodidx = i; 1433 } 1434 1435 static void 1436 re_txeof(struct rtk_softc *sc) 1437 { 1438 struct ifnet *ifp; 1439 struct re_txq *txq; 1440 uint32_t txstat; 1441 int idx, descidx; 1442 1443 ifp = &sc->ethercom.ec_if; 1444 1445 for (idx = sc->re_ldata.re_txq_considx; 1446 sc->re_ldata.re_txq_free < RE_TX_QLEN; 1447 idx = RE_NEXT_TXQ(sc, idx), sc->re_ldata.re_txq_free++) { 1448 txq = &sc->re_ldata.re_txq[idx]; 1449 KASSERT(txq->txq_mbuf != NULL); 1450 1451 descidx = txq->txq_descidx; 1452 RE_TXDESCSYNC(sc, descidx, 1453 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1454 txstat = 1455 le32toh(sc->re_ldata.re_tx_list[descidx].re_cmdstat); 1456 RE_TXDESCSYNC(sc, descidx, BUS_DMASYNC_PREREAD); 1457 KASSERT((txstat & RE_TDESC_CMD_EOF) != 0); 1458 if (txstat & RE_TDESC_CMD_OWN) { 1459 break; 1460 } 1461 1462 sc->re_ldata.re_tx_free += txq->txq_nsegs; 1463 KASSERT(sc->re_ldata.re_tx_free <= RE_TX_DESC_CNT(sc)); 1464 bus_dmamap_sync(sc->sc_dmat, txq->txq_dmamap, 1465 0, txq->txq_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1466 bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap); 1467 m_freem(txq->txq_mbuf); 1468 txq->txq_mbuf = NULL; 1469 1470 net_stat_ref_t nsr = IF_STAT_GETREF(ifp); 1471 if (txstat & (RE_TDESC_STAT_EXCESSCOL | RE_TDESC_STAT_COLCNT)) 1472 if_statinc_ref(ifp, nsr, if_collisions); 1473 if (txstat & RE_TDESC_STAT_TXERRSUM) 1474 if_statinc_ref(ifp, nsr, if_oerrors); 1475 else 1476 if_statinc_ref(ifp, nsr, if_opackets); 1477 IF_STAT_PUTREF(ifp); 1478 } 1479 1480 sc->re_ldata.re_txq_considx = idx; 1481 1482 if (sc->re_ldata.re_txq_free > RE_NTXDESC_RSVD) 1483 ifp->if_flags &= ~IFF_OACTIVE; 1484 1485 /* 1486 * If not all descriptors have been released reaped yet, 1487 * reload the timer so that we will eventually get another 1488 * interrupt that will cause us to re-enter this routine. 1489 * This is done in case the transmitter has gone idle. 1490 */ 1491 if (sc->re_ldata.re_txq_free < RE_TX_QLEN) { 1492 if ((sc->sc_quirk & RTKQ_IM_HW) == 0) 1493 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1494 if ((sc->sc_quirk & RTKQ_PCIE) != 0) { 1495 /* 1496 * Some chips will ignore a second TX request 1497 * issued while an existing transmission is in 1498 * progress. If the transmitter goes idle but 1499 * there are still packets waiting to be sent, 1500 * we need to restart the channel here to flush 1501 * them out. This only seems to be required with 1502 * the PCIe devices. 1503 */ 1504 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START); 1505 } 1506 } else 1507 ifp->if_timer = 0; 1508 } 1509 1510 static void 1511 re_tick(void *arg) 1512 { 1513 struct rtk_softc *sc = arg; 1514 int s; 1515 1516 /* XXX: just return for 8169S/8110S with rev 2 or newer phy */ 1517 s = splnet(); 1518 1519 mii_tick(&sc->mii); 1520 splx(s); 1521 1522 callout_schedule(&sc->rtk_tick_ch, hz); 1523 } 1524 1525 int 1526 re_intr(void *arg) 1527 { 1528 struct rtk_softc *sc = arg; 1529 struct ifnet *ifp; 1530 uint16_t status, rndstatus = 0; 1531 int handled = 0; 1532 1533 if (!device_has_power(sc->sc_dev)) 1534 return 0; 1535 1536 ifp = &sc->ethercom.ec_if; 1537 1538 if ((ifp->if_flags & IFF_UP) == 0) 1539 return 0; 1540 1541 const uint16_t status_mask = (sc->sc_quirk & RTKQ_IM_HW) ? 1542 RTK_INTRS_IM_HW : RTK_INTRS_CPLUS; 1543 1544 for (;;) { 1545 1546 status = CSR_READ_2(sc, RTK_ISR); 1547 /* If the card has gone away the read returns 0xffff. */ 1548 if (status == 0xffff) 1549 break; 1550 if (status != 0) { 1551 handled = 1; 1552 CSR_WRITE_2(sc, RTK_ISR, status); 1553 rndstatus = status; 1554 } 1555 1556 if ((status & status_mask) == 0) 1557 break; 1558 1559 if (status & (RTK_ISR_RX_OK | RTK_ISR_RX_ERR)) 1560 re_rxeof(sc); 1561 1562 if (status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_TX_ERR | 1563 RTK_ISR_TX_DESC_UNAVAIL | RTK_ISR_TX_OK)) 1564 re_txeof(sc); 1565 1566 if (status & RTK_ISR_SYSTEM_ERR) { 1567 re_init(ifp); 1568 } 1569 1570 if (status & RTK_ISR_LINKCHG) { 1571 callout_stop(&sc->rtk_tick_ch); 1572 re_tick(sc); 1573 } 1574 } 1575 1576 if (handled) 1577 if_schedule_deferred_start(ifp); 1578 1579 rnd_add_uint32(&sc->rnd_source, rndstatus); 1580 1581 return handled; 1582 } 1583 1584 1585 1586 /* 1587 * Main transmit routine for C+ and gigE NICs. 1588 */ 1589 1590 static void 1591 re_start(struct ifnet *ifp) 1592 { 1593 struct rtk_softc *sc; 1594 struct mbuf *m; 1595 bus_dmamap_t map; 1596 struct re_txq *txq; 1597 struct re_desc *d; 1598 uint32_t cmdstat, re_flags, vlanctl; 1599 int ofree, idx, error, nsegs, seg; 1600 int startdesc, curdesc, lastdesc; 1601 bool pad; 1602 1603 sc = ifp->if_softc; 1604 ofree = sc->re_ldata.re_txq_free; 1605 1606 for (idx = sc->re_ldata.re_txq_prodidx;; idx = RE_NEXT_TXQ(sc, idx)) { 1607 1608 IFQ_POLL(&ifp->if_snd, m); 1609 if (m == NULL) 1610 break; 1611 1612 if (sc->re_ldata.re_txq_free == 0 || 1613 sc->re_ldata.re_tx_free == 0) { 1614 /* no more free slots left */ 1615 ifp->if_flags |= IFF_OACTIVE; 1616 break; 1617 } 1618 1619 /* 1620 * Set up checksum offload. Note: checksum offload bits must 1621 * appear in all descriptors of a multi-descriptor transmit 1622 * attempt. (This is according to testing done with an 8169 1623 * chip. I'm not sure if this is a requirement or a bug.) 1624 */ 1625 1626 vlanctl = 0; 1627 if ((m->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0) { 1628 uint32_t segsz = m->m_pkthdr.segsz; 1629 1630 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) { 1631 re_flags = RE_TDESC_CMD_LGSEND | 1632 (segsz << RE_TDESC_CMD_MSSVAL_SHIFT); 1633 } else { 1634 re_flags = RE_TDESC_CMD_LGSEND_V4; 1635 vlanctl |= 1636 (segsz << RE_TDESC_VLANCTL_MSSVAL_SHIFT); 1637 } 1638 } else { 1639 /* 1640 * set RE_TDESC_CMD_IPCSUM if any checksum offloading 1641 * is requested. otherwise, RE_TDESC_CMD_TCPCSUM/ 1642 * RE_TDESC_CMD_UDPCSUM doesn't make effects. 1643 */ 1644 re_flags = 0; 1645 if ((m->m_pkthdr.csum_flags & 1646 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1647 != 0) { 1648 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) { 1649 re_flags |= RE_TDESC_CMD_IPCSUM; 1650 if (m->m_pkthdr.csum_flags & 1651 M_CSUM_TCPv4) { 1652 re_flags |= 1653 RE_TDESC_CMD_TCPCSUM; 1654 } else if (m->m_pkthdr.csum_flags & 1655 M_CSUM_UDPv4) { 1656 re_flags |= 1657 RE_TDESC_CMD_UDPCSUM; 1658 } 1659 } else { 1660 vlanctl |= RE_TDESC_VLANCTL_IPCSUM; 1661 if (m->m_pkthdr.csum_flags & 1662 M_CSUM_TCPv4) { 1663 vlanctl |= 1664 RE_TDESC_VLANCTL_TCPCSUM; 1665 } else if (m->m_pkthdr.csum_flags & 1666 M_CSUM_UDPv4) { 1667 vlanctl |= 1668 RE_TDESC_VLANCTL_UDPCSUM; 1669 } 1670 } 1671 } 1672 } 1673 1674 txq = &sc->re_ldata.re_txq[idx]; 1675 map = txq->txq_dmamap; 1676 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1677 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1678 1679 if (__predict_false(error)) { 1680 /* XXX try to defrag if EFBIG? */ 1681 printf("%s: can't map mbuf (error %d)\n", 1682 device_xname(sc->sc_dev), error); 1683 1684 IFQ_DEQUEUE(&ifp->if_snd, m); 1685 m_freem(m); 1686 if_statinc(ifp, if_oerrors); 1687 continue; 1688 } 1689 1690 nsegs = map->dm_nsegs; 1691 pad = false; 1692 if (__predict_false(m->m_pkthdr.len <= RE_IP4CSUMTX_PADLEN && 1693 (re_flags & RE_TDESC_CMD_IPCSUM) != 0 && 1694 (sc->sc_quirk & RTKQ_DESCV2) == 0)) { 1695 pad = true; 1696 nsegs++; 1697 } 1698 1699 if (nsegs > sc->re_ldata.re_tx_free) { 1700 /* 1701 * Not enough free descriptors to transmit this packet. 1702 */ 1703 ifp->if_flags |= IFF_OACTIVE; 1704 bus_dmamap_unload(sc->sc_dmat, map); 1705 break; 1706 } 1707 1708 IFQ_DEQUEUE(&ifp->if_snd, m); 1709 1710 /* 1711 * Make sure that the caches are synchronized before we 1712 * ask the chip to start DMA for the packet data. 1713 */ 1714 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1715 BUS_DMASYNC_PREWRITE); 1716 1717 /* 1718 * Set up hardware VLAN tagging. Note: vlan tag info must 1719 * appear in all descriptors of a multi-descriptor 1720 * transmission attempt. 1721 */ 1722 if (vlan_has_tag(m)) 1723 vlanctl |= bswap16(vlan_get_tag(m)) | 1724 RE_TDESC_VLANCTL_TAG; 1725 1726 /* 1727 * Map the segment array into descriptors. 1728 * Note that we set the start-of-frame and 1729 * end-of-frame markers for either TX or RX, 1730 * but they really only have meaning in the TX case. 1731 * (In the RX case, it's the chip that tells us 1732 * where packets begin and end.) 1733 * We also keep track of the end of the ring 1734 * and set the end-of-ring bits as needed, 1735 * and we set the ownership bits in all except 1736 * the very first descriptor. (The caller will 1737 * set this descriptor later when it start 1738 * transmission or reception.) 1739 */ 1740 curdesc = startdesc = sc->re_ldata.re_tx_nextfree; 1741 lastdesc = -1; 1742 for (seg = 0; seg < map->dm_nsegs; 1743 seg++, curdesc = RE_NEXT_TX_DESC(sc, curdesc)) { 1744 d = &sc->re_ldata.re_tx_list[curdesc]; 1745 #ifdef DIAGNOSTIC 1746 RE_TXDESCSYNC(sc, curdesc, 1747 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1748 cmdstat = le32toh(d->re_cmdstat); 1749 RE_TXDESCSYNC(sc, curdesc, BUS_DMASYNC_PREREAD); 1750 if (cmdstat & RE_TDESC_STAT_OWN) { 1751 panic("%s: tried to map busy TX descriptor", 1752 device_xname(sc->sc_dev)); 1753 } 1754 #endif 1755 1756 d->re_vlanctl = htole32(vlanctl); 1757 re_set_bufaddr(d, map->dm_segs[seg].ds_addr); 1758 cmdstat = re_flags | map->dm_segs[seg].ds_len; 1759 if (seg == 0) 1760 cmdstat |= RE_TDESC_CMD_SOF; 1761 else 1762 cmdstat |= RE_TDESC_CMD_OWN; 1763 if (curdesc == (RE_TX_DESC_CNT(sc) - 1)) 1764 cmdstat |= RE_TDESC_CMD_EOR; 1765 if (seg == nsegs - 1) { 1766 cmdstat |= RE_TDESC_CMD_EOF; 1767 lastdesc = curdesc; 1768 } 1769 d->re_cmdstat = htole32(cmdstat); 1770 RE_TXDESCSYNC(sc, curdesc, 1771 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1772 } 1773 if (__predict_false(pad)) { 1774 d = &sc->re_ldata.re_tx_list[curdesc]; 1775 d->re_vlanctl = htole32(vlanctl); 1776 re_set_bufaddr(d, RE_TXPADDADDR(sc)); 1777 cmdstat = re_flags | 1778 RE_TDESC_CMD_OWN | RE_TDESC_CMD_EOF | 1779 (RE_IP4CSUMTX_PADLEN + 1 - m->m_pkthdr.len); 1780 if (curdesc == (RE_TX_DESC_CNT(sc) - 1)) 1781 cmdstat |= RE_TDESC_CMD_EOR; 1782 d->re_cmdstat = htole32(cmdstat); 1783 RE_TXDESCSYNC(sc, curdesc, 1784 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1785 lastdesc = curdesc; 1786 curdesc = RE_NEXT_TX_DESC(sc, curdesc); 1787 } 1788 KASSERT(lastdesc != -1); 1789 1790 /* Transfer ownership of packet to the chip. */ 1791 1792 sc->re_ldata.re_tx_list[startdesc].re_cmdstat |= 1793 htole32(RE_TDESC_CMD_OWN); 1794 RE_TXDESCSYNC(sc, startdesc, 1795 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1796 1797 /* update info of TX queue and descriptors */ 1798 txq->txq_mbuf = m; 1799 txq->txq_descidx = lastdesc; 1800 txq->txq_nsegs = nsegs; 1801 1802 sc->re_ldata.re_txq_free--; 1803 sc->re_ldata.re_tx_free -= nsegs; 1804 sc->re_ldata.re_tx_nextfree = curdesc; 1805 1806 /* 1807 * If there's a BPF listener, bounce a copy of this frame 1808 * to him. 1809 */ 1810 bpf_mtap(ifp, m, BPF_D_OUT); 1811 } 1812 1813 if (sc->re_ldata.re_txq_free < ofree) { 1814 /* 1815 * TX packets are enqueued. 1816 */ 1817 sc->re_ldata.re_txq_prodidx = idx; 1818 1819 /* 1820 * Start the transmitter to poll. 1821 * 1822 * RealTek put the TX poll request register in a different 1823 * location on the 8169 gigE chip. I don't know why. 1824 */ 1825 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) 1826 CSR_WRITE_1(sc, RTK_TXSTART, RTK_TXSTART_START); 1827 else 1828 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START); 1829 1830 if ((sc->sc_quirk & RTKQ_IM_HW) == 0) { 1831 /* 1832 * Use the countdown timer for interrupt moderation. 1833 * 'TX done' interrupts are disabled. Instead, we reset 1834 * the countdown timer, which will begin counting until 1835 * it hits the value in the TIMERINT register, and then 1836 * trigger an interrupt. Each time we write to the 1837 * TIMERCNT register, the timer count is reset to 0. 1838 */ 1839 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1840 } 1841 1842 /* 1843 * Set a timeout in case the chip goes out to lunch. 1844 */ 1845 ifp->if_timer = 5; 1846 } 1847 } 1848 1849 static int 1850 re_init(struct ifnet *ifp) 1851 { 1852 struct rtk_softc *sc = ifp->if_softc; 1853 uint32_t rxcfg = 0; 1854 uint16_t cfg; 1855 int error; 1856 #ifdef RE_USE_EECMD 1857 const uint8_t *enaddr; 1858 uint32_t reg; 1859 #endif 1860 1861 if ((error = re_enable(sc)) != 0) 1862 goto out; 1863 1864 /* 1865 * Cancel pending I/O and free all RX/TX buffers. 1866 */ 1867 re_stop(ifp, 0); 1868 1869 re_reset(sc); 1870 1871 /* 1872 * Enable C+ RX and TX mode, as well as VLAN stripping and 1873 * RX checksum offload. We must configure the C+ register 1874 * before all others. 1875 */ 1876 cfg = RE_CPLUSCMD_PCI_MRW; 1877 1878 /* 1879 * XXX: For old 8169 set bit 14. 1880 * For 8169S/8110S and above, do not set bit 14. 1881 */ 1882 if ((sc->sc_quirk & RTKQ_8169NONS) != 0) 1883 cfg |= (0x1 << 14); 1884 1885 if ((sc->ethercom.ec_capenable & ETHERCAP_VLAN_HWTAGGING) != 0) 1886 cfg |= RE_CPLUSCMD_VLANSTRIP; 1887 if ((ifp->if_capenable & (IFCAP_CSUM_IPv4_Rx | 1888 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) != 0) 1889 cfg |= RE_CPLUSCMD_RXCSUM_ENB; 1890 if ((sc->sc_quirk & RTKQ_MACSTAT) != 0) { 1891 cfg |= RE_CPLUSCMD_MACSTAT_DIS; 1892 cfg |= RE_CPLUSCMD_TXENB; 1893 } else 1894 cfg |= RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB; 1895 1896 CSR_WRITE_2(sc, RTK_CPLUS_CMD, cfg); 1897 1898 /* XXX: from Realtek-supplied Linux driver. Wholly undocumented. */ 1899 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 1900 if ((sc->sc_quirk & RTKQ_IM_HW) == 0) { 1901 CSR_WRITE_2(sc, RTK_IM, 0x0000); 1902 } else { 1903 CSR_WRITE_2(sc, RTK_IM, 0x5151); 1904 } 1905 } 1906 1907 DELAY(10000); 1908 1909 #ifdef RE_USE_EECMD 1910 /* 1911 * Init our MAC address. Even though the chipset 1912 * documentation doesn't mention it, we need to enter "Config 1913 * register write enable" mode to modify the ID registers. 1914 */ 1915 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_WRITECFG); 1916 enaddr = CLLADDR(ifp->if_sadl); 1917 reg = enaddr[0] | (enaddr[1] << 8) | 1918 (enaddr[2] << 16) | (enaddr[3] << 24); 1919 CSR_WRITE_4(sc, RTK_IDR0, reg); 1920 reg = enaddr[4] | (enaddr[5] << 8); 1921 CSR_WRITE_4(sc, RTK_IDR4, reg); 1922 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 1923 #endif 1924 1925 /* 1926 * For C+ mode, initialize the RX descriptors and mbufs. 1927 */ 1928 re_rx_list_init(sc); 1929 re_tx_list_init(sc); 1930 1931 /* 1932 * Load the addresses of the RX and TX lists into the chip. 1933 */ 1934 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_HI, 1935 RE_ADDR_HI(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr)); 1936 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_LO, 1937 RE_ADDR_LO(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr)); 1938 1939 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_HI, 1940 RE_ADDR_HI(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr)); 1941 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_LO, 1942 RE_ADDR_LO(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr)); 1943 1944 if (sc->sc_quirk & RTKQ_RXDV_GATED) { 1945 CSR_WRITE_4(sc, RTK_MISC, 1946 CSR_READ_4(sc, RTK_MISC) & ~RTK_MISC_RXDV_GATED_EN); 1947 } 1948 1949 /* 1950 * Enable transmit and receive. 1951 */ 1952 if ((sc->sc_quirk & RTKQ_TXRXEN_LATER) == 0) 1953 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1954 1955 /* 1956 * Set the initial TX and RX configuration. 1957 */ 1958 if (sc->re_testmode && (sc->sc_quirk & RTKQ_8169NONS) != 0) { 1959 /* test mode is needed only for old 8169 */ 1960 CSR_WRITE_4(sc, RTK_TXCFG, 1961 RE_TXCFG_CONFIG | RTK_LOOPTEST_ON); 1962 } else 1963 CSR_WRITE_4(sc, RTK_TXCFG, RE_TXCFG_CONFIG); 1964 1965 CSR_WRITE_1(sc, RTK_EARLY_TX_THRESH, 16); 1966 1967 CSR_WRITE_4(sc, RTK_RXCFG, RE_RXCFG_CONFIG); 1968 1969 /* Set the individual bit to receive frames for this host only. */ 1970 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 1971 rxcfg |= RTK_RXCFG_RX_INDIV; 1972 1973 /* If we want promiscuous mode, set the allframes bit. */ 1974 if (ifp->if_flags & IFF_PROMISC) 1975 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 1976 else 1977 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 1978 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1979 1980 /* 1981 * Set capture broadcast bit to capture broadcast frames. 1982 */ 1983 if (ifp->if_flags & IFF_BROADCAST) 1984 rxcfg |= RTK_RXCFG_RX_BROAD; 1985 else 1986 rxcfg &= ~RTK_RXCFG_RX_BROAD; 1987 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1988 1989 /* 1990 * Program the multicast filter, if necessary. 1991 */ 1992 rtk_setmulti(sc); 1993 1994 /* 1995 * some chips require to enable TX/RX *AFTER* TX/RX configuration 1996 */ 1997 if ((sc->sc_quirk & RTKQ_TXRXEN_LATER) != 0) 1998 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1999 2000 /* 2001 * Enable interrupts. 2002 */ 2003 if (sc->re_testmode) 2004 CSR_WRITE_2(sc, RTK_IMR, 0); 2005 else if ((sc->sc_quirk & RTKQ_IM_HW) != 0) 2006 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_IM_HW); 2007 else 2008 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS); 2009 2010 /* Start RX/TX process. */ 2011 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 2012 #ifdef notdef 2013 /* Enable receiver and transmitter. */ 2014 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 2015 #endif 2016 2017 /* 2018 * Initialize the timer interrupt register so that 2019 * a timer interrupt will be generated once the timer 2020 * reaches a certain number of ticks. The timer is 2021 * reloaded on each transmit. This gives us TX interrupt 2022 * moderation, which dramatically improves TX frame rate. 2023 */ 2024 2025 unsigned defer; /* timer interval / ns */ 2026 unsigned period; /* busclock period / ns */ 2027 2028 /* 2029 * Maximum frame rate 2030 * 1500 byte PDU -> 81274 Hz 2031 * 46 byte PDU -> 1488096 Hz 2032 * 2033 * Deferring interrupts by up to 128us needs descriptors for 2034 * 1500 byte PDU -> 10.4 frames 2035 * 46 byte PDU -> 190.4 frames 2036 * 2037 */ 2038 defer = 128000; 2039 2040 if ((sc->sc_quirk & RTKQ_IM_HW) != 0) { 2041 period = 1; 2042 defer = 0; 2043 } else if ((sc->sc_quirk & RTKQ_PCIE) != 0) { 2044 period = 8; 2045 } else { 2046 switch (CSR_READ_1(sc, RTK_CFG2_BUSFREQ) & 0x7) { 2047 case RTK_BUSFREQ_33MHZ: 2048 period = 30; 2049 break; 2050 case RTK_BUSFREQ_66MHZ: 2051 period = 15; 2052 break; 2053 default: 2054 /* lowest possible clock */ 2055 period = 60; 2056 break; 2057 } 2058 } 2059 2060 /* Timer Interrupt register address varies */ 2061 uint16_t re8139_reg; 2062 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) 2063 re8139_reg = RTK_TIMERINT; 2064 else 2065 re8139_reg = RTK_TIMERINT_8169; 2066 CSR_WRITE_4(sc, re8139_reg, defer / period); 2067 2068 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 2069 /* 2070 * For 8169 gigE NICs, set the max allowed RX packet 2071 * size so we can receive jumbo frames. 2072 */ 2073 CSR_WRITE_2(sc, RTK_MAXRXPKTLEN, 16383); 2074 } 2075 2076 if (sc->re_testmode) 2077 return 0; 2078 2079 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD); 2080 2081 ifp->if_flags |= IFF_RUNNING; 2082 ifp->if_flags &= ~IFF_OACTIVE; 2083 2084 callout_schedule(&sc->rtk_tick_ch, hz); 2085 2086 out: 2087 if (error) { 2088 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2089 ifp->if_timer = 0; 2090 printf("%s: interface not running\n", 2091 device_xname(sc->sc_dev)); 2092 } 2093 2094 return error; 2095 } 2096 2097 static int 2098 re_ioctl(struct ifnet *ifp, u_long command, void *data) 2099 { 2100 struct rtk_softc *sc = ifp->if_softc; 2101 struct ifreq *ifr = data; 2102 int s, error = 0; 2103 2104 s = splnet(); 2105 2106 switch (command) { 2107 case SIOCSIFMTU: 2108 /* 2109 * Disable jumbo frames if it's not supported. 2110 */ 2111 if ((sc->sc_quirk & RTKQ_NOJUMBO) != 0 && 2112 ifr->ifr_mtu > ETHERMTU) { 2113 error = EINVAL; 2114 break; 2115 } 2116 2117 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO) 2118 error = EINVAL; 2119 else if ((error = ifioctl_common(ifp, command, data)) == 2120 ENETRESET) 2121 error = 0; 2122 break; 2123 default: 2124 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 2125 break; 2126 2127 error = 0; 2128 2129 if (command == SIOCSIFCAP) 2130 error = if_init(ifp); 2131 else if (command != SIOCADDMULTI && command != SIOCDELMULTI) 2132 ; 2133 else if (ifp->if_flags & IFF_RUNNING) 2134 rtk_setmulti(sc); 2135 break; 2136 } 2137 2138 splx(s); 2139 2140 return error; 2141 } 2142 2143 static void 2144 re_watchdog(struct ifnet *ifp) 2145 { 2146 struct rtk_softc *sc; 2147 int s; 2148 2149 sc = ifp->if_softc; 2150 s = splnet(); 2151 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 2152 if_statinc(ifp, if_oerrors); 2153 2154 re_txeof(sc); 2155 re_rxeof(sc); 2156 2157 re_init(ifp); 2158 2159 splx(s); 2160 } 2161 2162 /* 2163 * Stop the adapter and free any mbufs allocated to the 2164 * RX and TX lists. 2165 */ 2166 static void 2167 re_stop(struct ifnet *ifp, int disable) 2168 { 2169 int i; 2170 struct rtk_softc *sc = ifp->if_softc; 2171 2172 callout_stop(&sc->rtk_tick_ch); 2173 2174 mii_down(&sc->mii); 2175 2176 if ((sc->sc_quirk & RTKQ_CMDSTOP) != 0) 2177 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_STOPREQ | RTK_CMD_TX_ENB | 2178 RTK_CMD_RX_ENB); 2179 else 2180 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 2181 DELAY(1000); 2182 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 2183 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF); 2184 2185 if (sc->re_head != NULL) { 2186 m_freem(sc->re_head); 2187 sc->re_head = sc->re_tail = NULL; 2188 } 2189 2190 /* Free the TX list buffers. */ 2191 for (i = 0; i < RE_TX_QLEN; i++) { 2192 if (sc->re_ldata.re_txq[i].txq_mbuf != NULL) { 2193 bus_dmamap_unload(sc->sc_dmat, 2194 sc->re_ldata.re_txq[i].txq_dmamap); 2195 m_freem(sc->re_ldata.re_txq[i].txq_mbuf); 2196 sc->re_ldata.re_txq[i].txq_mbuf = NULL; 2197 } 2198 } 2199 2200 /* Free the RX list buffers. */ 2201 for (i = 0; i < RE_RX_DESC_CNT; i++) { 2202 if (sc->re_ldata.re_rxsoft[i].rxs_mbuf != NULL) { 2203 bus_dmamap_unload(sc->sc_dmat, 2204 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 2205 m_freem(sc->re_ldata.re_rxsoft[i].rxs_mbuf); 2206 sc->re_ldata.re_rxsoft[i].rxs_mbuf = NULL; 2207 } 2208 } 2209 2210 if (disable) 2211 re_disable(sc); 2212 2213 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2214 ifp->if_timer = 0; 2215 } 2216