1 /* $NetBSD: rtl8169.c,v 1.20 2005/05/19 20:11:24 briggs Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998-2003 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 /* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */ 37 38 /* 39 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 40 * 41 * Written by Bill Paul <wpaul@windriver.com> 42 * Senior Networking Software Engineer 43 * Wind River Systems 44 */ 45 46 /* 47 * This driver is designed to support RealTek's next generation of 48 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 49 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 50 * and the RTL8110S. 51 * 52 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 53 * with the older 8139 family, however it also supports a special 54 * C+ mode of operation that provides several new performance enhancing 55 * features. These include: 56 * 57 * o Descriptor based DMA mechanism. Each descriptor represents 58 * a single packet fragment. Data buffers may be aligned on 59 * any byte boundary. 60 * 61 * o 64-bit DMA 62 * 63 * o TCP/IP checksum offload for both RX and TX 64 * 65 * o High and normal priority transmit DMA rings 66 * 67 * o VLAN tag insertion and extraction 68 * 69 * o TCP large send (segmentation offload) 70 * 71 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 72 * programming API is fairly straightforward. The RX filtering, EEPROM 73 * access and PHY access is the same as it is on the older 8139 series 74 * chips. 75 * 76 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 77 * same programming API and feature set as the 8139C+ with the following 78 * differences and additions: 79 * 80 * o 1000Mbps mode 81 * 82 * o Jumbo frames 83 * 84 * o GMII and TBI ports/registers for interfacing with copper 85 * or fiber PHYs 86 * 87 * o RX and TX DMA rings can have up to 1024 descriptors 88 * (the 8139C+ allows a maximum of 64) 89 * 90 * o Slight differences in register layout from the 8139C+ 91 * 92 * The TX start and timer interrupt registers are at different locations 93 * on the 8169 than they are on the 8139C+. Also, the status word in the 94 * RX descriptor has a slightly different bit layout. The 8169 does not 95 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 96 * copper gigE PHY. 97 * 98 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 99 * (the 'S' stands for 'single-chip'). These devices have the same 100 * programming API as the older 8169, but also have some vendor-specific 101 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 102 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 103 * 104 * This driver takes advantage of the RX and TX checksum offload and 105 * VLAN tag insertion/extraction features. It also implements TX 106 * interrupt moderation using the timer interrupt registers, which 107 * significantly reduces TX interrupt load. There is also support 108 * for jumbo frames, however the 8169/8169S/8110S can not transmit 109 * jumbo frames larger than 7.5K, so the max MTU possible with this 110 * driver is 7500 bytes. 111 */ 112 113 #include "bpfilter.h" 114 #include "vlan.h" 115 116 #include <sys/param.h> 117 #include <sys/endian.h> 118 #include <sys/systm.h> 119 #include <sys/sockio.h> 120 #include <sys/mbuf.h> 121 #include <sys/malloc.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/device.h> 125 126 #include <net/if.h> 127 #include <net/if_arp.h> 128 #include <net/if_dl.h> 129 #include <net/if_ether.h> 130 #include <net/if_media.h> 131 #include <net/if_vlanvar.h> 132 133 #include <netinet/in_systm.h> /* XXX for IP_MAXPACKET */ 134 #include <netinet/in.h> /* XXX for IP_MAXPACKET */ 135 #include <netinet/ip.h> /* XXX for IP_MAXPACKET */ 136 137 #if NBPFILTER > 0 138 #include <net/bpf.h> 139 #endif 140 141 #include <machine/bus.h> 142 143 #include <dev/mii/mii.h> 144 #include <dev/mii/miivar.h> 145 146 #include <dev/pci/pcireg.h> 147 #include <dev/pci/pcivar.h> 148 #include <dev/pci/pcidevs.h> 149 150 #include <dev/ic/rtl81x9reg.h> 151 #include <dev/ic/rtl81x9var.h> 152 153 #include <dev/ic/rtl8169var.h> 154 155 156 static int re_encap(struct rtk_softc *, struct mbuf *, int *); 157 158 static int re_newbuf(struct rtk_softc *, int, struct mbuf *); 159 static int re_rx_list_init(struct rtk_softc *); 160 static int re_tx_list_init(struct rtk_softc *); 161 static void re_rxeof(struct rtk_softc *); 162 static void re_txeof(struct rtk_softc *); 163 static void re_tick(void *); 164 static void re_start(struct ifnet *); 165 static int re_ioctl(struct ifnet *, u_long, caddr_t); 166 static int re_init(struct ifnet *); 167 static void re_stop(struct ifnet *, int); 168 static void re_watchdog(struct ifnet *); 169 170 static void re_shutdown(void *); 171 static int re_enable(struct rtk_softc *); 172 static void re_disable(struct rtk_softc *); 173 static void re_power(int, void *); 174 175 static int re_ifmedia_upd(struct ifnet *); 176 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *); 177 178 static int re_gmii_readreg(struct device *, int, int); 179 static void re_gmii_writereg(struct device *, int, int, int); 180 181 static int re_miibus_readreg(struct device *, int, int); 182 static void re_miibus_writereg(struct device *, int, int, int); 183 static void re_miibus_statchg(struct device *); 184 185 static void re_reset(struct rtk_softc *); 186 187 static int 188 re_gmii_readreg(struct device *self, int phy, int reg) 189 { 190 struct rtk_softc *sc = (void *)self; 191 u_int32_t rval; 192 int i; 193 194 if (phy != 7) 195 return 0; 196 197 /* Let the rgephy driver read the GMEDIASTAT register */ 198 199 if (reg == RTK_GMEDIASTAT) { 200 rval = CSR_READ_1(sc, RTK_GMEDIASTAT); 201 return rval; 202 } 203 204 CSR_WRITE_4(sc, RTK_PHYAR, reg << 16); 205 DELAY(1000); 206 207 for (i = 0; i < RTK_TIMEOUT; i++) { 208 rval = CSR_READ_4(sc, RTK_PHYAR); 209 if (rval & RTK_PHYAR_BUSY) 210 break; 211 DELAY(100); 212 } 213 214 if (i == RTK_TIMEOUT) { 215 aprint_error("%s: PHY read failed\n", sc->sc_dev.dv_xname); 216 return 0; 217 } 218 219 return rval & RTK_PHYAR_PHYDATA; 220 } 221 222 static void 223 re_gmii_writereg(struct device *dev, int phy, int reg, int data) 224 { 225 struct rtk_softc *sc = (void *)dev; 226 u_int32_t rval; 227 int i; 228 229 CSR_WRITE_4(sc, RTK_PHYAR, (reg << 16) | 230 (data & RTK_PHYAR_PHYDATA) | RTK_PHYAR_BUSY); 231 DELAY(1000); 232 233 for (i = 0; i < RTK_TIMEOUT; i++) { 234 rval = CSR_READ_4(sc, RTK_PHYAR); 235 if (!(rval & RTK_PHYAR_BUSY)) 236 break; 237 DELAY(100); 238 } 239 240 if (i == RTK_TIMEOUT) { 241 aprint_error("%s: PHY write reg %x <- %x failed\n", 242 sc->sc_dev.dv_xname, reg, data); 243 return; 244 } 245 246 return; 247 } 248 249 static int 250 re_miibus_readreg(struct device *dev, int phy, int reg) 251 { 252 struct rtk_softc *sc = (void *)dev; 253 u_int16_t rval = 0; 254 u_int16_t re8139_reg = 0; 255 int s; 256 257 s = splnet(); 258 259 if (sc->rtk_type == RTK_8169) { 260 rval = re_gmii_readreg(dev, phy, reg); 261 splx(s); 262 return rval; 263 } 264 265 /* Pretend the internal PHY is only at address 0 */ 266 if (phy) { 267 splx(s); 268 return 0; 269 } 270 switch (reg) { 271 case MII_BMCR: 272 re8139_reg = RTK_BMCR; 273 break; 274 case MII_BMSR: 275 re8139_reg = RTK_BMSR; 276 break; 277 case MII_ANAR: 278 re8139_reg = RTK_ANAR; 279 break; 280 case MII_ANER: 281 re8139_reg = RTK_ANER; 282 break; 283 case MII_ANLPAR: 284 re8139_reg = RTK_LPAR; 285 break; 286 case MII_PHYIDR1: 287 case MII_PHYIDR2: 288 splx(s); 289 return 0; 290 /* 291 * Allow the rlphy driver to read the media status 292 * register. If we have a link partner which does not 293 * support NWAY, this is the register which will tell 294 * us the results of parallel detection. 295 */ 296 case RTK_MEDIASTAT: 297 rval = CSR_READ_1(sc, RTK_MEDIASTAT); 298 splx(s); 299 return rval; 300 default: 301 aprint_error("%s: bad phy register\n", sc->sc_dev.dv_xname); 302 splx(s); 303 return 0; 304 } 305 rval = CSR_READ_2(sc, re8139_reg); 306 splx(s); 307 return rval; 308 } 309 310 static void 311 re_miibus_writereg(struct device *dev, int phy, int reg, int data) 312 { 313 struct rtk_softc *sc = (void *)dev; 314 u_int16_t re8139_reg = 0; 315 int s; 316 317 s = splnet(); 318 319 if (sc->rtk_type == RTK_8169) { 320 re_gmii_writereg(dev, phy, reg, data); 321 splx(s); 322 return; 323 } 324 325 /* Pretend the internal PHY is only at address 0 */ 326 if (phy) { 327 splx(s); 328 return; 329 } 330 switch (reg) { 331 case MII_BMCR: 332 re8139_reg = RTK_BMCR; 333 break; 334 case MII_BMSR: 335 re8139_reg = RTK_BMSR; 336 break; 337 case MII_ANAR: 338 re8139_reg = RTK_ANAR; 339 break; 340 case MII_ANER: 341 re8139_reg = RTK_ANER; 342 break; 343 case MII_ANLPAR: 344 re8139_reg = RTK_LPAR; 345 break; 346 case MII_PHYIDR1: 347 case MII_PHYIDR2: 348 splx(s); 349 return; 350 break; 351 default: 352 aprint_error("%s: bad phy register\n", sc->sc_dev.dv_xname); 353 splx(s); 354 return; 355 } 356 CSR_WRITE_2(sc, re8139_reg, data); 357 splx(s); 358 return; 359 } 360 361 static void 362 re_miibus_statchg(struct device *dev) 363 { 364 365 return; 366 } 367 368 static void 369 re_reset(struct rtk_softc *sc) 370 { 371 register int i; 372 373 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 374 375 for (i = 0; i < RTK_TIMEOUT; i++) { 376 DELAY(10); 377 if (!(CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET)) 378 break; 379 } 380 if (i == RTK_TIMEOUT) 381 aprint_error("%s: reset never completed!\n", 382 sc->sc_dev.dv_xname); 383 384 /* 385 * NB: Realtek-supplied Linux driver does this only for 386 * MCFG_METHOD_2, which corresponds to sc->sc_rev == 2. 387 */ 388 if (1) /* XXX check softc flag for 8169s version */ 389 CSR_WRITE_1(sc, 0x82, 1); 390 391 return; 392 } 393 394 /* 395 * The following routine is designed to test for a defect on some 396 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 397 * lines connected to the bus, however for a 32-bit only card, they 398 * should be pulled high. The result of this defect is that the 399 * NIC will not work right if you plug it into a 64-bit slot: DMA 400 * operations will be done with 64-bit transfers, which will fail 401 * because the 64-bit data lines aren't connected. 402 * 403 * There's no way to work around this (short of talking a soldering 404 * iron to the board), however we can detect it. The method we use 405 * here is to put the NIC into digital loopback mode, set the receiver 406 * to promiscuous mode, and then try to send a frame. We then compare 407 * the frame data we sent to what was received. If the data matches, 408 * then the NIC is working correctly, otherwise we know the user has 409 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 410 * slot. In the latter case, there's no way the NIC can work correctly, 411 * so we print out a message on the console and abort the device attach. 412 */ 413 414 int 415 re_diag(struct rtk_softc *sc) 416 { 417 struct ifnet *ifp = &sc->ethercom.ec_if; 418 struct mbuf *m0; 419 struct ether_header *eh; 420 struct rtk_desc *cur_rx; 421 bus_dmamap_t dmamap; 422 u_int16_t status; 423 u_int32_t rxstat; 424 int total_len, i, s, error = 0; 425 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 426 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 427 428 /* Allocate a single mbuf */ 429 430 MGETHDR(m0, M_DONTWAIT, MT_DATA); 431 if (m0 == NULL) 432 return ENOBUFS; 433 434 /* 435 * Initialize the NIC in test mode. This sets the chip up 436 * so that it can send and receive frames, but performs the 437 * following special functions: 438 * - Puts receiver in promiscuous mode 439 * - Enables digital loopback mode 440 * - Leaves interrupts turned off 441 */ 442 443 ifp->if_flags |= IFF_PROMISC; 444 sc->rtk_testmode = 1; 445 re_init(ifp); 446 re_stop(ifp, 0); 447 DELAY(100000); 448 re_init(ifp); 449 450 /* Put some data in the mbuf */ 451 452 eh = mtod(m0, struct ether_header *); 453 bcopy((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 454 bcopy((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 455 eh->ether_type = htons(ETHERTYPE_IP); 456 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 457 458 /* 459 * Queue the packet, start transmission. 460 */ 461 462 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF); 463 s = splnet(); 464 IF_ENQUEUE(&ifp->if_snd, m0); 465 re_start(ifp); 466 splx(s); 467 m0 = NULL; 468 469 /* Wait for it to propagate through the chip */ 470 471 DELAY(100000); 472 for (i = 0; i < RTK_TIMEOUT; i++) { 473 status = CSR_READ_2(sc, RTK_ISR); 474 if ((status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) == 475 (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) 476 break; 477 DELAY(10); 478 } 479 if (i == RTK_TIMEOUT) { 480 aprint_error("%s: diagnostic failed, failed to receive packet " 481 "in loopback mode\n", sc->sc_dev.dv_xname); 482 error = EIO; 483 goto done; 484 } 485 486 /* 487 * The packet should have been dumped into the first 488 * entry in the RX DMA ring. Grab it from there. 489 */ 490 491 dmamap = sc->rtk_ldata.rtk_rx_list_map; 492 bus_dmamap_sync(sc->sc_dmat, 493 dmamap, 0, dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 494 dmamap = sc->rtk_ldata.rtk_rx_dmamap[0]; 495 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 496 BUS_DMASYNC_POSTREAD); 497 bus_dmamap_unload(sc->sc_dmat, 498 sc->rtk_ldata.rtk_rx_dmamap[0]); 499 500 m0 = sc->rtk_ldata.rtk_rx_mbuf[0]; 501 sc->rtk_ldata.rtk_rx_mbuf[0] = NULL; 502 eh = mtod(m0, struct ether_header *); 503 504 cur_rx = &sc->rtk_ldata.rtk_rx_list[0]; 505 total_len = RTK_RXBYTES(cur_rx); 506 rxstat = le32toh(cur_rx->rtk_cmdstat); 507 508 if (total_len != ETHER_MIN_LEN) { 509 aprint_error("%s: diagnostic failed, received short packet\n", 510 sc->sc_dev.dv_xname); 511 error = EIO; 512 goto done; 513 } 514 515 /* Test that the received packet data matches what we sent. */ 516 517 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 518 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 519 ntohs(eh->ether_type) != ETHERTYPE_IP) { 520 aprint_error("%s: WARNING, DMA FAILURE!\n", 521 sc->sc_dev.dv_xname); 522 aprint_error("%s: expected TX data: %s", 523 sc->sc_dev.dv_xname, ether_sprintf(dst)); 524 aprint_error("/%s/0x%x\n", ether_sprintf(src), ETHERTYPE_IP); 525 aprint_error("%s: received RX data: %s", 526 sc->sc_dev.dv_xname, 527 ether_sprintf(eh->ether_dhost)); 528 aprint_error("/%s/0x%x\n", ether_sprintf(eh->ether_shost), 529 ntohs(eh->ether_type)); 530 aprint_error("%s: You may have a defective 32-bit NIC plugged " 531 "into a 64-bit PCI slot.\n", sc->sc_dev.dv_xname); 532 aprint_error("%s: Please re-install the NIC in a 32-bit slot " 533 "for proper operation.\n", sc->sc_dev.dv_xname); 534 aprint_error("%s: Read the re(4) man page for more details.\n", 535 sc->sc_dev.dv_xname); 536 error = EIO; 537 } 538 539 done: 540 /* Turn interface off, release resources */ 541 542 sc->rtk_testmode = 0; 543 ifp->if_flags &= ~IFF_PROMISC; 544 re_stop(ifp, 0); 545 if (m0 != NULL) 546 m_freem(m0); 547 548 return error; 549 } 550 551 552 /* 553 * Attach the interface. Allocate softc structures, do ifmedia 554 * setup and ethernet/BPF attach. 555 */ 556 void 557 re_attach(struct rtk_softc *sc) 558 { 559 u_char eaddr[ETHER_ADDR_LEN]; 560 u_int16_t val; 561 struct ifnet *ifp; 562 int error = 0, i, addr_len; 563 564 565 /* XXX JRS: bus-attach-independent code begins approximately here */ 566 567 /* Reset the adapter. */ 568 re_reset(sc); 569 570 if (sc->rtk_type == RTK_8169) { 571 uint32_t hwrev; 572 573 /* Revision of 8169/8169S/8110s in bits 30..26, 23 */ 574 hwrev = CSR_READ_4(sc, RTK_TXCFG) & 0x7c800000; 575 if (hwrev == (0x1 << 28)) { 576 sc->sc_rev = 4; 577 } else if (hwrev == (0x1 << 26)) { 578 sc->sc_rev = 3; 579 } else if (hwrev == (0x1 << 23)) { 580 sc->sc_rev = 2; 581 } else 582 sc->sc_rev = 1; 583 584 /* Set RX length mask */ 585 586 sc->rtk_rxlenmask = RTK_RDESC_STAT_GFRAGLEN; 587 588 /* Force station address autoload from the EEPROM */ 589 590 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_AUTOLOAD); 591 for (i = 0; i < RTK_TIMEOUT; i++) { 592 if (!(CSR_READ_1(sc, RTK_EECMD) & RTK_EEMODE_AUTOLOAD)) 593 break; 594 DELAY(100); 595 } 596 if (i == RTK_TIMEOUT) 597 aprint_error("%s: eeprom autoload timed out\n", 598 sc->sc_dev.dv_xname); 599 600 for (i = 0; i < ETHER_ADDR_LEN; i++) 601 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i); 602 603 sc->rtk_ldata.rtk_tx_desc_cnt = RTK_TX_DESC_CNT_8169; 604 } else { 605 606 /* Set RX length mask */ 607 608 sc->rtk_rxlenmask = RTK_RDESC_STAT_FRAGLEN; 609 610 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 611 addr_len = RTK_EEADDR_LEN1; 612 else 613 addr_len = RTK_EEADDR_LEN0; 614 615 /* 616 * Get station address from the EEPROM. 617 */ 618 for (i = 0; i < 3; i++) { 619 val = rtk_read_eeprom(sc, RTK_EE_EADDR0 + i, addr_len); 620 eaddr[(i * 2) + 0] = val & 0xff; 621 eaddr[(i * 2) + 1] = val >> 8; 622 } 623 624 sc->rtk_ldata.rtk_tx_desc_cnt = RTK_TX_DESC_CNT_8139; 625 } 626 627 aprint_normal("%s: Ethernet address %s\n", 628 sc->sc_dev.dv_xname, ether_sprintf(eaddr)); 629 630 if (sc->rtk_ldata.rtk_tx_desc_cnt > 631 PAGE_SIZE / sizeof(struct rtk_desc)) { 632 sc->rtk_ldata.rtk_tx_desc_cnt = 633 PAGE_SIZE / sizeof(struct rtk_desc); 634 } 635 636 aprint_verbose("%s: using %d tx descriptors\n", 637 sc->sc_dev.dv_xname, sc->rtk_ldata.rtk_tx_desc_cnt); 638 639 /* Allocate DMA'able memory for the TX ring */ 640 if ((error = bus_dmamem_alloc(sc->sc_dmat, RTK_TX_LIST_SZ(sc), 641 RTK_ETHER_ALIGN, 0, &sc->rtk_ldata.rtk_tx_listseg, 642 1, &sc->rtk_ldata.rtk_tx_listnseg, BUS_DMA_NOWAIT)) != 0) { 643 aprint_error("%s: can't allocate tx listseg, error = %d\n", 644 sc->sc_dev.dv_xname, error); 645 goto fail_0; 646 } 647 648 /* Load the map for the TX ring. */ 649 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->rtk_ldata.rtk_tx_listseg, 650 sc->rtk_ldata.rtk_tx_listnseg, RTK_TX_LIST_SZ(sc), 651 (caddr_t *)&sc->rtk_ldata.rtk_tx_list, 652 BUS_DMA_NOWAIT)) != 0) { 653 aprint_error("%s: can't map tx list, error = %d\n", 654 sc->sc_dev.dv_xname, error); 655 goto fail_1; 656 } 657 memset(sc->rtk_ldata.rtk_tx_list, 0, RTK_TX_LIST_SZ(sc)); 658 659 if ((error = bus_dmamap_create(sc->sc_dmat, RTK_TX_LIST_SZ(sc), 1, 660 RTK_TX_LIST_SZ(sc), 0, BUS_DMA_ALLOCNOW, 661 &sc->rtk_ldata.rtk_tx_list_map)) != 0) { 662 aprint_error("%s: can't create tx list map, error = %d\n", 663 sc->sc_dev.dv_xname, error); 664 goto fail_2; 665 } 666 667 668 if ((error = bus_dmamap_load(sc->sc_dmat, 669 sc->rtk_ldata.rtk_tx_list_map, sc->rtk_ldata.rtk_tx_list, 670 RTK_TX_LIST_SZ(sc), NULL, BUS_DMA_NOWAIT)) != 0) { 671 aprint_error("%s: can't load tx list, error = %d\n", 672 sc->sc_dev.dv_xname, error); 673 goto fail_3; 674 } 675 676 /* Create DMA maps for TX buffers */ 677 for (i = 0; i < RTK_TX_QLEN; i++) { 678 error = bus_dmamap_create(sc->sc_dmat, 679 round_page(IP_MAXPACKET), 680 RTK_TX_DESC_CNT(sc) - 4, RTK_TDESC_CMD_FRAGLEN, 681 0, BUS_DMA_ALLOCNOW, 682 &sc->rtk_ldata.rtk_txq[i].txq_dmamap); 683 if (error) { 684 aprint_error("%s: can't create DMA map for TX\n", 685 sc->sc_dev.dv_xname); 686 goto fail_4; 687 } 688 } 689 690 /* Allocate DMA'able memory for the RX ring */ 691 if ((error = bus_dmamem_alloc(sc->sc_dmat, RTK_RX_LIST_SZ, 692 RTK_RING_ALIGN, 0, &sc->rtk_ldata.rtk_rx_listseg, 1, 693 &sc->rtk_ldata.rtk_rx_listnseg, BUS_DMA_NOWAIT)) != 0) { 694 aprint_error("%s: can't allocate rx listseg, error = %d\n", 695 sc->sc_dev.dv_xname, error); 696 goto fail_4; 697 } 698 699 /* Load the map for the RX ring. */ 700 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->rtk_ldata.rtk_rx_listseg, 701 sc->rtk_ldata.rtk_rx_listnseg, RTK_RX_LIST_SZ, 702 (caddr_t *)&sc->rtk_ldata.rtk_rx_list, 703 BUS_DMA_NOWAIT)) != 0) { 704 aprint_error("%s: can't map rx list, error = %d\n", 705 sc->sc_dev.dv_xname, error); 706 goto fail_5; 707 } 708 memset(sc->rtk_ldata.rtk_rx_list, 0, RTK_RX_LIST_SZ); 709 710 if ((error = bus_dmamap_create(sc->sc_dmat, RTK_RX_LIST_SZ, 1, 711 RTK_RX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 712 &sc->rtk_ldata.rtk_rx_list_map)) != 0) { 713 aprint_error("%s: can't create rx list map, error = %d\n", 714 sc->sc_dev.dv_xname, error); 715 goto fail_6; 716 } 717 718 if ((error = bus_dmamap_load(sc->sc_dmat, 719 sc->rtk_ldata.rtk_rx_list_map, sc->rtk_ldata.rtk_rx_list, 720 RTK_RX_LIST_SZ, NULL, BUS_DMA_NOWAIT)) != 0) { 721 aprint_error("%s: can't load rx list, error = %d\n", 722 sc->sc_dev.dv_xname, error); 723 goto fail_7; 724 } 725 726 /* Create DMA maps for RX buffers */ 727 for (i = 0; i < RTK_RX_DESC_CNT; i++) { 728 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 729 0, BUS_DMA_ALLOCNOW, &sc->rtk_ldata.rtk_rx_dmamap[i]); 730 if (error) { 731 aprint_error("%s: can't create DMA map for RX\n", 732 sc->sc_dev.dv_xname); 733 goto fail_8; 734 } 735 } 736 737 /* 738 * Record interface as attached. From here, we should not fail. 739 */ 740 sc->sc_flags |= RTK_ATTACHED; 741 742 ifp = &sc->ethercom.ec_if; 743 ifp->if_softc = sc; 744 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 745 ifp->if_mtu = ETHERMTU; 746 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 747 ifp->if_ioctl = re_ioctl; 748 sc->ethercom.ec_capabilities |= 749 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 750 ifp->if_start = re_start; 751 ifp->if_stop = re_stop; 752 753 /* 754 * IFCAP_CSUM_IPv4_Tx seems broken for small packets. 755 */ 756 757 ifp->if_capabilities |= 758 /* IFCAP_CSUM_IPv4_Tx | */ IFCAP_CSUM_IPv4_Rx | 759 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 760 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 761 IFCAP_TSOv4; 762 ifp->if_watchdog = re_watchdog; 763 ifp->if_init = re_init; 764 if (sc->rtk_type == RTK_8169) 765 ifp->if_baudrate = 1000000000; 766 else 767 ifp->if_baudrate = 100000000; 768 ifp->if_snd.ifq_maxlen = RTK_IFQ_MAXLEN; 769 ifp->if_capenable = ifp->if_capabilities; 770 IFQ_SET_READY(&ifp->if_snd); 771 772 callout_init(&sc->rtk_tick_ch); 773 774 /* Do MII setup */ 775 sc->mii.mii_ifp = ifp; 776 sc->mii.mii_readreg = re_miibus_readreg; 777 sc->mii.mii_writereg = re_miibus_writereg; 778 sc->mii.mii_statchg = re_miibus_statchg; 779 ifmedia_init(&sc->mii.mii_media, IFM_IMASK, re_ifmedia_upd, 780 re_ifmedia_sts); 781 mii_attach(&sc->sc_dev, &sc->mii, 0xffffffff, MII_PHY_ANY, 782 MII_OFFSET_ANY, 0); 783 ifmedia_set(&sc->mii.mii_media, IFM_ETHER | IFM_AUTO); 784 785 /* 786 * Call MI attach routine. 787 */ 788 if_attach(ifp); 789 ether_ifattach(ifp, eaddr); 790 791 792 /* 793 * Make sure the interface is shutdown during reboot. 794 */ 795 sc->sc_sdhook = shutdownhook_establish(re_shutdown, sc); 796 if (sc->sc_sdhook == NULL) 797 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 798 sc->sc_dev.dv_xname); 799 /* 800 * Add a suspend hook to make sure we come back up after a 801 * resume. 802 */ 803 sc->sc_powerhook = powerhook_establish(re_power, sc); 804 if (sc->sc_powerhook == NULL) 805 aprint_error("%s: WARNING: unable to establish power hook\n", 806 sc->sc_dev.dv_xname); 807 808 809 return; 810 811 fail_8: 812 /* Destroy DMA maps for RX buffers. */ 813 for (i = 0; i < RTK_RX_DESC_CNT; i++) 814 if (sc->rtk_ldata.rtk_rx_dmamap[i] != NULL) 815 bus_dmamap_destroy(sc->sc_dmat, 816 sc->rtk_ldata.rtk_rx_dmamap[i]); 817 818 /* Free DMA'able memory for the RX ring. */ 819 bus_dmamap_unload(sc->sc_dmat, sc->rtk_ldata.rtk_rx_list_map); 820 fail_7: 821 bus_dmamap_destroy(sc->sc_dmat, sc->rtk_ldata.rtk_rx_list_map); 822 fail_6: 823 bus_dmamem_unmap(sc->sc_dmat, 824 (caddr_t)sc->rtk_ldata.rtk_rx_list, RTK_RX_LIST_SZ); 825 fail_5: 826 bus_dmamem_free(sc->sc_dmat, 827 &sc->rtk_ldata.rtk_rx_listseg, sc->rtk_ldata.rtk_rx_listnseg); 828 829 fail_4: 830 /* Destroy DMA maps for TX buffers. */ 831 for (i = 0; i < RTK_TX_QLEN; i++) 832 if (sc->rtk_ldata.rtk_txq[i].txq_dmamap != NULL) 833 bus_dmamap_destroy(sc->sc_dmat, 834 sc->rtk_ldata.rtk_txq[i].txq_dmamap); 835 836 /* Free DMA'able memory for the TX ring. */ 837 bus_dmamap_unload(sc->sc_dmat, sc->rtk_ldata.rtk_tx_list_map); 838 fail_3: 839 bus_dmamap_destroy(sc->sc_dmat, sc->rtk_ldata.rtk_tx_list_map); 840 fail_2: 841 bus_dmamem_unmap(sc->sc_dmat, 842 (caddr_t)sc->rtk_ldata.rtk_tx_list, RTK_TX_LIST_SZ(sc)); 843 fail_1: 844 bus_dmamem_free(sc->sc_dmat, 845 &sc->rtk_ldata.rtk_tx_listseg, sc->rtk_ldata.rtk_tx_listnseg); 846 fail_0: 847 return; 848 } 849 850 851 /* 852 * re_activate: 853 * Handle device activation/deactivation requests. 854 */ 855 int 856 re_activate(struct device *self, enum devact act) 857 { 858 struct rtk_softc *sc = (void *) self; 859 int s, error = 0; 860 861 s = splnet(); 862 switch (act) { 863 case DVACT_ACTIVATE: 864 error = EOPNOTSUPP; 865 break; 866 case DVACT_DEACTIVATE: 867 mii_activate(&sc->mii, act, MII_PHY_ANY, MII_OFFSET_ANY); 868 if_deactivate(&sc->ethercom.ec_if); 869 break; 870 } 871 splx(s); 872 873 return error; 874 } 875 876 /* 877 * re_detach: 878 * Detach a rtk interface. 879 */ 880 int 881 re_detach(struct rtk_softc *sc) 882 { 883 struct ifnet *ifp = &sc->ethercom.ec_if; 884 int i; 885 886 /* 887 * Succeed now if there isn't any work to do. 888 */ 889 if ((sc->sc_flags & RTK_ATTACHED) == 0) 890 return 0; 891 892 /* Unhook our tick handler. */ 893 callout_stop(&sc->rtk_tick_ch); 894 895 /* Detach all PHYs. */ 896 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 897 898 /* Delete all remaining media. */ 899 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY); 900 901 ether_ifdetach(ifp); 902 if_detach(ifp); 903 904 /* XXX undo re_allocmem() */ 905 906 /* Destroy DMA maps for RX buffers. */ 907 for (i = 0; i < RTK_RX_DESC_CNT; i++) 908 if (sc->rtk_ldata.rtk_rx_dmamap[i] != NULL) 909 bus_dmamap_destroy(sc->sc_dmat, 910 sc->rtk_ldata.rtk_rx_dmamap[i]); 911 912 /* Free DMA'able memory for the RX ring. */ 913 bus_dmamap_unload(sc->sc_dmat, sc->rtk_ldata.rtk_rx_list_map); 914 bus_dmamap_destroy(sc->sc_dmat, sc->rtk_ldata.rtk_rx_list_map); 915 bus_dmamem_unmap(sc->sc_dmat, 916 (caddr_t)sc->rtk_ldata.rtk_rx_list, RTK_RX_LIST_SZ); 917 bus_dmamem_free(sc->sc_dmat, 918 &sc->rtk_ldata.rtk_rx_listseg, sc->rtk_ldata.rtk_rx_listnseg); 919 920 /* Destroy DMA maps for TX buffers. */ 921 for (i = 0; i < RTK_TX_QLEN; i++) 922 if (sc->rtk_ldata.rtk_txq[i].txq_dmamap != NULL) 923 bus_dmamap_destroy(sc->sc_dmat, 924 sc->rtk_ldata.rtk_txq[i].txq_dmamap); 925 926 /* Free DMA'able memory for the TX ring. */ 927 bus_dmamap_unload(sc->sc_dmat, sc->rtk_ldata.rtk_tx_list_map); 928 bus_dmamap_destroy(sc->sc_dmat, sc->rtk_ldata.rtk_tx_list_map); 929 bus_dmamem_unmap(sc->sc_dmat, 930 (caddr_t)sc->rtk_ldata.rtk_tx_list, RTK_TX_LIST_SZ(sc)); 931 bus_dmamem_free(sc->sc_dmat, 932 &sc->rtk_ldata.rtk_tx_listseg, sc->rtk_ldata.rtk_tx_listnseg); 933 934 935 shutdownhook_disestablish(sc->sc_sdhook); 936 powerhook_disestablish(sc->sc_powerhook); 937 938 return 0; 939 } 940 941 /* 942 * re_enable: 943 * Enable the RTL81X9 chip. 944 */ 945 static int 946 re_enable(struct rtk_softc *sc) 947 { 948 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 949 if ((*sc->sc_enable)(sc) != 0) { 950 aprint_error("%s: device enable failed\n", 951 sc->sc_dev.dv_xname); 952 return EIO; 953 } 954 sc->sc_flags |= RTK_ENABLED; 955 } 956 return 0; 957 } 958 959 /* 960 * re_disable: 961 * Disable the RTL81X9 chip. 962 */ 963 static void 964 re_disable(struct rtk_softc *sc) 965 { 966 967 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 968 (*sc->sc_disable)(sc); 969 sc->sc_flags &= ~RTK_ENABLED; 970 } 971 } 972 973 /* 974 * re_power: 975 * Power management (suspend/resume) hook. 976 */ 977 void 978 re_power(int why, void *arg) 979 { 980 struct rtk_softc *sc = (void *) arg; 981 struct ifnet *ifp = &sc->ethercom.ec_if; 982 int s; 983 984 s = splnet(); 985 switch (why) { 986 case PWR_SUSPEND: 987 case PWR_STANDBY: 988 re_stop(ifp, 0); 989 if (sc->sc_power != NULL) 990 (*sc->sc_power)(sc, why); 991 break; 992 case PWR_RESUME: 993 if (ifp->if_flags & IFF_UP) { 994 if (sc->sc_power != NULL) 995 (*sc->sc_power)(sc, why); 996 re_init(ifp); 997 } 998 break; 999 case PWR_SOFTSUSPEND: 1000 case PWR_SOFTSTANDBY: 1001 case PWR_SOFTRESUME: 1002 break; 1003 } 1004 splx(s); 1005 } 1006 1007 1008 static int 1009 re_newbuf(struct rtk_softc *sc, int idx, struct mbuf *m) 1010 { 1011 struct mbuf *n = NULL; 1012 bus_dmamap_t map; 1013 struct rtk_desc *d; 1014 u_int32_t cmdstat; 1015 int error; 1016 1017 if (m == NULL) { 1018 MGETHDR(n, M_DONTWAIT, MT_DATA); 1019 if (n == NULL) 1020 return ENOBUFS; 1021 m = n; 1022 1023 MCLGET(m, M_DONTWAIT); 1024 if (!(m->m_flags & M_EXT)) { 1025 m_freem(m); 1026 return ENOBUFS; 1027 } 1028 } else 1029 m->m_data = m->m_ext.ext_buf; 1030 1031 /* 1032 * Initialize mbuf length fields and fixup 1033 * alignment so that the frame payload is 1034 * longword aligned. 1035 */ 1036 m->m_len = m->m_pkthdr.len = MCLBYTES; 1037 m_adj(m, RTK_ETHER_ALIGN); 1038 1039 map = sc->rtk_ldata.rtk_rx_dmamap[idx]; 1040 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT); 1041 1042 if (error) 1043 goto out; 1044 1045 d = &sc->rtk_ldata.rtk_rx_list[idx]; 1046 if (le32toh(d->rtk_cmdstat) & RTK_RDESC_STAT_OWN) 1047 goto out; 1048 1049 cmdstat = map->dm_segs[0].ds_len; 1050 d->rtk_bufaddr_lo = htole32(RTK_ADDR_LO(map->dm_segs[0].ds_addr)); 1051 d->rtk_bufaddr_hi = htole32(RTK_ADDR_HI(map->dm_segs[0].ds_addr)); 1052 if (idx == (RTK_RX_DESC_CNT - 1)) 1053 cmdstat |= RTK_RDESC_CMD_EOR; 1054 d->rtk_cmdstat = htole32(cmdstat); 1055 1056 sc->rtk_ldata.rtk_rx_list[idx].rtk_cmdstat |= 1057 htole32(RTK_RDESC_CMD_OWN); 1058 sc->rtk_ldata.rtk_rx_mbuf[idx] = m; 1059 1060 bus_dmamap_sync(sc->sc_dmat, sc->rtk_ldata.rtk_rx_dmamap[idx], 0, 1061 sc->rtk_ldata.rtk_rx_dmamap[idx]->dm_mapsize, 1062 BUS_DMASYNC_PREREAD); 1063 1064 return 0; 1065 out: 1066 if (n != NULL) 1067 m_freem(n); 1068 return ENOMEM; 1069 } 1070 1071 static int 1072 re_tx_list_init(struct rtk_softc *sc) 1073 { 1074 int i; 1075 1076 memset(sc->rtk_ldata.rtk_tx_list, 0, RTK_TX_LIST_SZ(sc)); 1077 for (i = 0; i < RTK_TX_QLEN; i++) { 1078 sc->rtk_ldata.rtk_txq[i].txq_mbuf = NULL; 1079 } 1080 1081 bus_dmamap_sync(sc->sc_dmat, 1082 sc->rtk_ldata.rtk_tx_list_map, 0, 1083 sc->rtk_ldata.rtk_tx_list_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1084 sc->rtk_ldata.rtk_txq_prodidx = 0; 1085 sc->rtk_ldata.rtk_txq_considx = 0; 1086 sc->rtk_ldata.rtk_tx_free = RTK_TX_DESC_CNT(sc); 1087 sc->rtk_ldata.rtk_tx_nextfree = 0; 1088 1089 return 0; 1090 } 1091 1092 static int 1093 re_rx_list_init(struct rtk_softc *sc) 1094 { 1095 int i; 1096 1097 memset((char *)sc->rtk_ldata.rtk_rx_list, 0, RTK_RX_LIST_SZ); 1098 memset((char *)&sc->rtk_ldata.rtk_rx_mbuf, 0, 1099 (RTK_RX_DESC_CNT * sizeof(struct mbuf *))); 1100 1101 for (i = 0; i < RTK_RX_DESC_CNT; i++) { 1102 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1103 return ENOBUFS; 1104 } 1105 1106 /* Flush the RX descriptors */ 1107 1108 bus_dmamap_sync(sc->sc_dmat, 1109 sc->rtk_ldata.rtk_rx_list_map, 1110 0, sc->rtk_ldata.rtk_rx_list_map->dm_mapsize, 1111 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1112 1113 sc->rtk_ldata.rtk_rx_prodidx = 0; 1114 sc->rtk_head = sc->rtk_tail = NULL; 1115 1116 return 0; 1117 } 1118 1119 /* 1120 * RX handler for C+ and 8169. For the gigE chips, we support 1121 * the reception of jumbo frames that have been fragmented 1122 * across multiple 2K mbuf cluster buffers. 1123 */ 1124 static void 1125 re_rxeof(struct rtk_softc *sc) 1126 { 1127 struct mbuf *m; 1128 struct ifnet *ifp; 1129 int i, total_len; 1130 struct rtk_desc *cur_rx; 1131 u_int32_t rxstat, rxvlan; 1132 1133 ifp = &sc->ethercom.ec_if; 1134 i = sc->rtk_ldata.rtk_rx_prodidx; 1135 1136 /* Invalidate the descriptor memory */ 1137 1138 bus_dmamap_sync(sc->sc_dmat, 1139 sc->rtk_ldata.rtk_rx_list_map, 1140 0, sc->rtk_ldata.rtk_rx_list_map->dm_mapsize, 1141 BUS_DMASYNC_POSTREAD); 1142 1143 while (!RTK_OWN(&sc->rtk_ldata.rtk_rx_list[i])) { 1144 1145 cur_rx = &sc->rtk_ldata.rtk_rx_list[i]; 1146 m = sc->rtk_ldata.rtk_rx_mbuf[i]; 1147 total_len = RTK_RXBYTES(cur_rx); 1148 rxstat = le32toh(cur_rx->rtk_cmdstat); 1149 rxvlan = le32toh(cur_rx->rtk_vlanctl); 1150 1151 /* Invalidate the RX mbuf and unload its map */ 1152 1153 bus_dmamap_sync(sc->sc_dmat, 1154 sc->rtk_ldata.rtk_rx_dmamap[i], 1155 0, sc->rtk_ldata.rtk_rx_dmamap[i]->dm_mapsize, 1156 BUS_DMASYNC_POSTREAD); 1157 bus_dmamap_unload(sc->sc_dmat, 1158 sc->rtk_ldata.rtk_rx_dmamap[i]); 1159 1160 if (!(rxstat & RTK_RDESC_STAT_EOF)) { 1161 m->m_len = MCLBYTES - RTK_ETHER_ALIGN; 1162 if (sc->rtk_head == NULL) 1163 sc->rtk_head = sc->rtk_tail = m; 1164 else { 1165 m->m_flags &= ~M_PKTHDR; 1166 sc->rtk_tail->m_next = m; 1167 sc->rtk_tail = m; 1168 } 1169 re_newbuf(sc, i, NULL); 1170 RTK_RX_DESC_INC(sc, i); 1171 continue; 1172 } 1173 1174 /* 1175 * NOTE: for the 8139C+, the frame length field 1176 * is always 12 bits in size, but for the gigE chips, 1177 * it is 13 bits (since the max RX frame length is 16K). 1178 * Unfortunately, all 32 bits in the status word 1179 * were already used, so to make room for the extra 1180 * length bit, RealTek took out the 'frame alignment 1181 * error' bit and shifted the other status bits 1182 * over one slot. The OWN, EOR, FS and LS bits are 1183 * still in the same places. We have already extracted 1184 * the frame length and checked the OWN bit, so rather 1185 * than using an alternate bit mapping, we shift the 1186 * status bits one space to the right so we can evaluate 1187 * them using the 8169 status as though it was in the 1188 * same format as that of the 8139C+. 1189 */ 1190 if (sc->rtk_type == RTK_8169) 1191 rxstat >>= 1; 1192 1193 if (rxstat & RTK_RDESC_STAT_RXERRSUM) { 1194 ifp->if_ierrors++; 1195 /* 1196 * If this is part of a multi-fragment packet, 1197 * discard all the pieces. 1198 */ 1199 if (sc->rtk_head != NULL) { 1200 m_freem(sc->rtk_head); 1201 sc->rtk_head = sc->rtk_tail = NULL; 1202 } 1203 re_newbuf(sc, i, m); 1204 RTK_RX_DESC_INC(sc, i); 1205 continue; 1206 } 1207 1208 /* 1209 * If allocating a replacement mbuf fails, 1210 * reload the current one. 1211 */ 1212 1213 if (re_newbuf(sc, i, NULL)) { 1214 ifp->if_ierrors++; 1215 if (sc->rtk_head != NULL) { 1216 m_freem(sc->rtk_head); 1217 sc->rtk_head = sc->rtk_tail = NULL; 1218 } 1219 re_newbuf(sc, i, m); 1220 RTK_RX_DESC_INC(sc, i); 1221 continue; 1222 } 1223 1224 RTK_RX_DESC_INC(sc, i); 1225 1226 if (sc->rtk_head != NULL) { 1227 m->m_len = total_len % (MCLBYTES - RTK_ETHER_ALIGN); 1228 /* 1229 * Special case: if there's 4 bytes or less 1230 * in this buffer, the mbuf can be discarded: 1231 * the last 4 bytes is the CRC, which we don't 1232 * care about anyway. 1233 */ 1234 if (m->m_len <= ETHER_CRC_LEN) { 1235 sc->rtk_tail->m_len -= 1236 (ETHER_CRC_LEN - m->m_len); 1237 m_freem(m); 1238 } else { 1239 m->m_len -= ETHER_CRC_LEN; 1240 m->m_flags &= ~M_PKTHDR; 1241 sc->rtk_tail->m_next = m; 1242 } 1243 m = sc->rtk_head; 1244 sc->rtk_head = sc->rtk_tail = NULL; 1245 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1246 } else 1247 m->m_pkthdr.len = m->m_len = 1248 (total_len - ETHER_CRC_LEN); 1249 1250 ifp->if_ipackets++; 1251 m->m_pkthdr.rcvif = ifp; 1252 1253 /* Do RX checksumming if enabled */ 1254 1255 if (ifp->if_capenable & IFCAP_CSUM_IPv4_Rx) { 1256 1257 /* Check IP header checksum */ 1258 if (rxstat & RTK_RDESC_STAT_PROTOID) 1259 m->m_pkthdr.csum_flags |= M_CSUM_IPv4;; 1260 if (rxstat & RTK_RDESC_STAT_IPSUMBAD) 1261 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1262 } 1263 1264 /* Check TCP/UDP checksum */ 1265 if (RTK_TCPPKT(rxstat) && 1266 (ifp->if_capenable & IFCAP_CSUM_TCPv4_Rx)) { 1267 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1268 if (rxstat & RTK_RDESC_STAT_TCPSUMBAD) 1269 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1270 } 1271 if (RTK_UDPPKT(rxstat) && 1272 (ifp->if_capenable & IFCAP_CSUM_UDPv4_Rx)) { 1273 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1274 if (rxstat & RTK_RDESC_STAT_UDPSUMBAD) 1275 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1276 } 1277 1278 if (rxvlan & RTK_RDESC_VLANCTL_TAG) { 1279 VLAN_INPUT_TAG(ifp, m, 1280 be16toh(rxvlan & RTK_RDESC_VLANCTL_DATA), 1281 continue); 1282 } 1283 #if NBPFILTER > 0 1284 if (ifp->if_bpf) 1285 bpf_mtap(ifp->if_bpf, m); 1286 #endif 1287 (*ifp->if_input)(ifp, m); 1288 } 1289 1290 /* Flush the RX DMA ring */ 1291 1292 bus_dmamap_sync(sc->sc_dmat, 1293 sc->rtk_ldata.rtk_rx_list_map, 1294 0, sc->rtk_ldata.rtk_rx_list_map->dm_mapsize, 1295 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1296 1297 sc->rtk_ldata.rtk_rx_prodidx = i; 1298 1299 return; 1300 } 1301 1302 static void 1303 re_txeof(struct rtk_softc *sc) 1304 { 1305 struct ifnet *ifp; 1306 int idx; 1307 1308 ifp = &sc->ethercom.ec_if; 1309 idx = sc->rtk_ldata.rtk_txq_considx; 1310 1311 /* Invalidate the TX descriptor list */ 1312 1313 bus_dmamap_sync(sc->sc_dmat, 1314 sc->rtk_ldata.rtk_tx_list_map, 1315 0, sc->rtk_ldata.rtk_tx_list_map->dm_mapsize, 1316 BUS_DMASYNC_POSTREAD); 1317 1318 while (/* CONSTCOND */ 1) { 1319 struct rtk_txq *txq = &sc->rtk_ldata.rtk_txq[idx]; 1320 int descidx; 1321 u_int32_t txstat; 1322 1323 if (txq->txq_mbuf == NULL) { 1324 KASSERT(idx == sc->rtk_ldata.rtk_txq_prodidx); 1325 break; 1326 } 1327 1328 descidx = txq->txq_descidx; 1329 txstat = 1330 le32toh(sc->rtk_ldata.rtk_tx_list[descidx].rtk_cmdstat); 1331 KASSERT((txstat & RTK_TDESC_CMD_EOF) != 0); 1332 if (txstat & RTK_TDESC_CMD_OWN) 1333 break; 1334 1335 sc->rtk_ldata.rtk_tx_free += txq->txq_dmamap->dm_nsegs; 1336 KASSERT(sc->rtk_ldata.rtk_tx_free <= RTK_TX_DESC_CNT(sc)); 1337 bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap); 1338 m_freem(txq->txq_mbuf); 1339 txq->txq_mbuf = NULL; 1340 1341 if (txstat & (RTK_TDESC_STAT_EXCESSCOL | RTK_TDESC_STAT_COLCNT)) 1342 ifp->if_collisions++; 1343 if (txstat & RTK_TDESC_STAT_TXERRSUM) 1344 ifp->if_oerrors++; 1345 else 1346 ifp->if_opackets++; 1347 1348 idx = (idx + 1) % RTK_TX_QLEN; 1349 } 1350 1351 /* No changes made to the TX ring, so no flush needed */ 1352 1353 if (idx != sc->rtk_ldata.rtk_txq_considx) { 1354 sc->rtk_ldata.rtk_txq_considx = idx; 1355 ifp->if_flags &= ~IFF_OACTIVE; 1356 ifp->if_timer = 0; 1357 } 1358 1359 /* 1360 * If not all descriptors have been released reaped yet, 1361 * reload the timer so that we will eventually get another 1362 * interrupt that will cause us to re-enter this routine. 1363 * This is done in case the transmitter has gone idle. 1364 */ 1365 if (sc->rtk_ldata.rtk_tx_free != RTK_TX_DESC_CNT(sc)) 1366 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1367 1368 return; 1369 } 1370 1371 /* 1372 * Stop all chip I/O so that the kernel's probe routines don't 1373 * get confused by errant DMAs when rebooting. 1374 */ 1375 static void 1376 re_shutdown(void *vsc) 1377 1378 { 1379 struct rtk_softc *sc = (struct rtk_softc *)vsc; 1380 1381 re_stop(&sc->ethercom.ec_if, 0); 1382 } 1383 1384 1385 static void 1386 re_tick(void *xsc) 1387 { 1388 struct rtk_softc *sc = xsc; 1389 int s; 1390 1391 /*XXX: just return for 8169S/8110S with rev 2 or newer phy */ 1392 s = splnet(); 1393 1394 mii_tick(&sc->mii); 1395 splx(s); 1396 1397 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1398 } 1399 1400 #ifdef DEVICE_POLLING 1401 static void 1402 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1403 { 1404 struct rtk_softc *sc = ifp->if_softc; 1405 1406 RTK_LOCK(sc); 1407 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1408 ether_poll_deregister(ifp); 1409 cmd = POLL_DEREGISTER; 1410 } 1411 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1412 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS); 1413 goto done; 1414 } 1415 1416 sc->rxcycles = count; 1417 re_rxeof(sc); 1418 re_txeof(sc); 1419 1420 if (ifp->if_snd.ifq_head != NULL) 1421 (*ifp->if_start)(ifp); 1422 1423 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1424 u_int16_t status; 1425 1426 status = CSR_READ_2(sc, RTK_ISR); 1427 if (status == 0xffff) 1428 goto done; 1429 if (status) 1430 CSR_WRITE_2(sc, RTK_ISR, status); 1431 1432 /* 1433 * XXX check behaviour on receiver stalls. 1434 */ 1435 1436 if (status & RTK_ISR_SYSTEM_ERR) { 1437 re_reset(sc); 1438 re_init(sc); 1439 } 1440 } 1441 done: 1442 RTK_UNLOCK(sc); 1443 } 1444 #endif /* DEVICE_POLLING */ 1445 1446 int 1447 re_intr(void *arg) 1448 { 1449 struct rtk_softc *sc = arg; 1450 struct ifnet *ifp; 1451 u_int16_t status; 1452 int handled = 0; 1453 1454 ifp = &sc->ethercom.ec_if; 1455 1456 if (!(ifp->if_flags & IFF_UP)) 1457 return 0; 1458 1459 #ifdef DEVICE_POLLING 1460 if (ifp->if_flags & IFF_POLLING) 1461 goto done; 1462 if ((ifp->if_capenable & IFCAP_POLLING) && 1463 ether_poll_register(re_poll, ifp)) { /* ok, disable interrupts */ 1464 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1465 re_poll(ifp, 0, 1); 1466 goto done; 1467 } 1468 #endif /* DEVICE_POLLING */ 1469 1470 for (;;) { 1471 1472 status = CSR_READ_2(sc, RTK_ISR); 1473 /* If the card has gone away the read returns 0xffff. */ 1474 if (status == 0xffff) 1475 break; 1476 if (status) { 1477 handled = 1; 1478 CSR_WRITE_2(sc, RTK_ISR, status); 1479 } 1480 1481 if ((status & RTK_INTRS_CPLUS) == 0) 1482 break; 1483 1484 if ((status & RTK_ISR_RX_OK) || 1485 (status & RTK_ISR_RX_ERR)) 1486 re_rxeof(sc); 1487 1488 if ((status & RTK_ISR_TIMEOUT_EXPIRED) || 1489 (status & RTK_ISR_TX_ERR) || 1490 (status & RTK_ISR_TX_DESC_UNAVAIL)) 1491 re_txeof(sc); 1492 1493 if (status & RTK_ISR_SYSTEM_ERR) { 1494 re_reset(sc); 1495 re_init(ifp); 1496 } 1497 1498 if (status & RTK_ISR_LINKCHG) { 1499 callout_stop(&sc->rtk_tick_ch); 1500 re_tick(sc); 1501 } 1502 } 1503 1504 if (ifp->if_flags & IFF_UP) /* kludge for interrupt during re_init() */ 1505 if (ifp->if_snd.ifq_head != NULL) 1506 (*ifp->if_start)(ifp); 1507 1508 #ifdef DEVICE_POLLING 1509 done: 1510 #endif 1511 1512 return handled; 1513 } 1514 1515 static int 1516 re_encap(struct rtk_softc *sc, struct mbuf *m, int *idx) 1517 { 1518 bus_dmamap_t map; 1519 int error, i, startidx, curidx; 1520 struct m_tag *mtag; 1521 struct rtk_desc *d; 1522 u_int32_t cmdstat, rtk_flags; 1523 struct rtk_txq *txq; 1524 1525 if (sc->rtk_ldata.rtk_tx_free <= 4) { 1526 return EFBIG; 1527 } 1528 1529 /* 1530 * Set up checksum offload. Note: checksum offload bits must 1531 * appear in all descriptors of a multi-descriptor transmit 1532 * attempt. (This is according to testing done with an 8169 1533 * chip. I'm not sure if this is a requirement or a bug.) 1534 */ 1535 1536 if ((m->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0) { 1537 u_int32_t segsz = m->m_pkthdr.segsz; 1538 1539 rtk_flags = RTK_TDESC_CMD_LGSEND | 1540 (segsz << RTK_TDESC_CMD_MSSVAL_SHIFT); 1541 } else { 1542 1543 /* 1544 * set RTK_TDESC_CMD_IPCSUM if any checksum offloading 1545 * is requested. otherwise, RTK_TDESC_CMD_TCPCSUM/ 1546 * RTK_TDESC_CMD_UDPCSUM doesn't make effects. 1547 */ 1548 1549 rtk_flags = 0; 1550 if ((m->m_pkthdr.csum_flags & 1551 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) != 0) { 1552 rtk_flags |= RTK_TDESC_CMD_IPCSUM; 1553 if (m->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1554 rtk_flags |= RTK_TDESC_CMD_TCPCSUM; 1555 } else if (m->m_pkthdr.csum_flags & M_CSUM_UDPv4) { 1556 rtk_flags |= RTK_TDESC_CMD_UDPCSUM; 1557 } 1558 } 1559 } 1560 1561 txq = &sc->rtk_ldata.rtk_txq[*idx]; 1562 map = txq->txq_dmamap; 1563 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT); 1564 1565 if (error) { 1566 /* XXX try to defrag if EFBIG? */ 1567 1568 aprint_error("%s: can't map mbuf (error %d)\n", 1569 sc->sc_dev.dv_xname, error); 1570 1571 return error; 1572 } 1573 1574 if (map->dm_nsegs > sc->rtk_ldata.rtk_tx_free - 4) { 1575 error = EFBIG; 1576 goto fail_unload; 1577 } 1578 1579 /* 1580 * Make sure that the caches are synchronized before we 1581 * ask the chip to start DMA for the packet data. 1582 */ 1583 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1584 BUS_DMASYNC_PREWRITE); 1585 1586 /* 1587 * Map the segment array into descriptors. Note that we set the 1588 * start-of-frame and end-of-frame markers for either TX or RX, but 1589 * they really only have meaning in the TX case. (In the RX case, 1590 * it's the chip that tells us where packets begin and end.) 1591 * We also keep track of the end of the ring and set the 1592 * end-of-ring bits as needed, and we set the ownership bits 1593 * in all except the very first descriptor. (The caller will 1594 * set this descriptor later when it start transmission or 1595 * reception.) 1596 */ 1597 i = 0; 1598 curidx = startidx = sc->rtk_ldata.rtk_tx_nextfree; 1599 while (1) { 1600 d = &sc->rtk_ldata.rtk_tx_list[curidx]; 1601 if (le32toh(d->rtk_cmdstat) & RTK_TDESC_STAT_OWN) { 1602 while (i > 0) { 1603 sc->rtk_ldata.rtk_tx_list[ 1604 (curidx + RTK_TX_DESC_CNT(sc) - i) % 1605 RTK_TX_DESC_CNT(sc)].rtk_cmdstat = 0; 1606 i--; 1607 } 1608 error = ENOBUFS; 1609 goto fail_unload; 1610 } 1611 1612 cmdstat = map->dm_segs[i].ds_len; 1613 d->rtk_bufaddr_lo = 1614 htole32(RTK_ADDR_LO(map->dm_segs[i].ds_addr)); 1615 d->rtk_bufaddr_hi = 1616 htole32(RTK_ADDR_HI(map->dm_segs[i].ds_addr)); 1617 if (i == 0) 1618 cmdstat |= RTK_TDESC_CMD_SOF; 1619 else 1620 cmdstat |= RTK_TDESC_CMD_OWN; 1621 if (curidx == (RTK_TX_DESC_CNT(sc) - 1)) 1622 cmdstat |= RTK_TDESC_CMD_EOR; 1623 d->rtk_cmdstat = htole32(cmdstat | rtk_flags); 1624 i++; 1625 if (i == map->dm_nsegs) 1626 break; 1627 RTK_TX_DESC_INC(sc, curidx); 1628 } 1629 1630 d->rtk_cmdstat |= htole32(RTK_TDESC_CMD_EOF); 1631 1632 txq->txq_mbuf = m; 1633 sc->rtk_ldata.rtk_tx_free -= map->dm_nsegs; 1634 1635 /* 1636 * Set up hardware VLAN tagging. Note: vlan tag info must 1637 * appear in the first descriptor of a multi-descriptor 1638 * transmission attempt. 1639 */ 1640 1641 if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m)) != NULL) { 1642 sc->rtk_ldata.rtk_tx_list[startidx].rtk_vlanctl = 1643 htole32(htons(VLAN_TAG_VALUE(mtag)) | 1644 RTK_TDESC_VLANCTL_TAG); 1645 } 1646 1647 /* Transfer ownership of packet to the chip. */ 1648 1649 sc->rtk_ldata.rtk_tx_list[curidx].rtk_cmdstat |= 1650 htole32(RTK_TDESC_CMD_OWN); 1651 if (startidx != curidx) 1652 sc->rtk_ldata.rtk_tx_list[startidx].rtk_cmdstat |= 1653 htole32(RTK_TDESC_CMD_OWN); 1654 1655 txq->txq_descidx = curidx; 1656 RTK_TX_DESC_INC(sc, curidx); 1657 sc->rtk_ldata.rtk_tx_nextfree = curidx; 1658 *idx = (*idx + 1) % RTK_TX_QLEN; 1659 1660 return 0; 1661 1662 fail_unload: 1663 bus_dmamap_unload(sc->sc_dmat, map); 1664 1665 return error; 1666 } 1667 1668 /* 1669 * Main transmit routine for C+ and gigE NICs. 1670 */ 1671 1672 static void 1673 re_start(struct ifnet *ifp) 1674 { 1675 struct rtk_softc *sc; 1676 int idx; 1677 1678 sc = ifp->if_softc; 1679 1680 idx = sc->rtk_ldata.rtk_txq_prodidx; 1681 while (/* CONSTCOND */ 1) { 1682 struct mbuf *m; 1683 int error; 1684 1685 IFQ_POLL(&ifp->if_snd, m); 1686 if (m == NULL) 1687 break; 1688 1689 if (sc->rtk_ldata.rtk_txq[idx].txq_mbuf != NULL) { 1690 KASSERT(idx == sc->rtk_ldata.rtk_txq_considx); 1691 ifp->if_flags |= IFF_OACTIVE; 1692 break; 1693 } 1694 1695 error = re_encap(sc, m, &idx); 1696 if (error == EFBIG && 1697 sc->rtk_ldata.rtk_tx_free == RTK_TX_DESC_CNT(sc)) { 1698 IFQ_DEQUEUE(&ifp->if_snd, m); 1699 m_freem(m); 1700 ifp->if_oerrors++; 1701 continue; 1702 } 1703 if (error) { 1704 ifp->if_flags |= IFF_OACTIVE; 1705 break; 1706 } 1707 1708 IFQ_DEQUEUE(&ifp->if_snd, m); 1709 1710 #if NBPFILTER > 0 1711 /* 1712 * If there's a BPF listener, bounce a copy of this frame 1713 * to him. 1714 */ 1715 if (ifp->if_bpf) 1716 bpf_mtap(ifp->if_bpf, m); 1717 #endif 1718 } 1719 1720 if (sc->rtk_ldata.rtk_txq_prodidx == idx) { 1721 return; 1722 } 1723 sc->rtk_ldata.rtk_txq_prodidx = idx; 1724 1725 /* Flush the TX descriptors */ 1726 1727 bus_dmamap_sync(sc->sc_dmat, 1728 sc->rtk_ldata.rtk_tx_list_map, 1729 0, sc->rtk_ldata.rtk_tx_list_map->dm_mapsize, 1730 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1731 1732 /* 1733 * RealTek put the TX poll request register in a different 1734 * location on the 8169 gigE chip. I don't know why. 1735 */ 1736 1737 if (sc->rtk_type == RTK_8169) 1738 CSR_WRITE_2(sc, RTK_GTXSTART, RTK_TXSTART_START); 1739 else 1740 CSR_WRITE_2(sc, RTK_TXSTART, RTK_TXSTART_START); 1741 1742 /* 1743 * Use the countdown timer for interrupt moderation. 1744 * 'TX done' interrupts are disabled. Instead, we reset the 1745 * countdown timer, which will begin counting until it hits 1746 * the value in the TIMERINT register, and then trigger an 1747 * interrupt. Each time we write to the TIMERCNT register, 1748 * the timer count is reset to 0. 1749 */ 1750 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1751 1752 /* 1753 * Set a timeout in case the chip goes out to lunch. 1754 */ 1755 ifp->if_timer = 5; 1756 1757 return; 1758 } 1759 1760 static int 1761 re_init(struct ifnet *ifp) 1762 { 1763 struct rtk_softc *sc = ifp->if_softc; 1764 u_int32_t rxcfg = 0; 1765 u_int32_t reg; 1766 int error; 1767 1768 if ((error = re_enable(sc)) != 0) 1769 goto out; 1770 1771 /* 1772 * Cancel pending I/O and free all RX/TX buffers. 1773 */ 1774 re_stop(ifp, 0); 1775 1776 /* 1777 * Enable C+ RX and TX mode, as well as VLAN stripping and 1778 * RX checksum offload. We must configure the C+ register 1779 * before all others. 1780 */ 1781 reg = 0; 1782 1783 /* 1784 * XXX: Realtek docs say bits 0 and 1 are reserved, for 8169S/8110S. 1785 * FreeBSD drivers set these bits anyway (for 8139C+?). 1786 * So far, it works. 1787 */ 1788 1789 /* 1790 * XXX: For 8169 and 8196S revs below 2, set bit 14. 1791 * For 8169S/8110S rev 2 and above, do not set bit 14. 1792 */ 1793 if (sc->rtk_type == RTK_8169 && sc->sc_rev == 1) 1794 reg |= (0x1 << 14) | RTK_CPLUSCMD_PCI_MRW;; 1795 1796 if (1) {/* not for 8169S ? */ 1797 reg |= RTK_CPLUSCMD_VLANSTRIP | 1798 (ifp->if_capenable & 1799 (IFCAP_CSUM_IPv4_Rx | IFCAP_CSUM_TCPv4_Rx | 1800 IFCAP_CSUM_UDPv4_Rx) ? 1801 RTK_CPLUSCMD_RXCSUM_ENB : 0); 1802 } 1803 1804 CSR_WRITE_2(sc, RTK_CPLUS_CMD, 1805 reg | RTK_CPLUSCMD_RXENB | RTK_CPLUSCMD_TXENB); 1806 1807 /* XXX: from Realtek-supplied Linux driver. Wholly undocumented. */ 1808 if (sc->rtk_type == RTK_8169) 1809 CSR_WRITE_2(sc, RTK_CPLUS_CMD+0x2, 0x0000); 1810 1811 DELAY(10000); 1812 1813 /* 1814 * Init our MAC address. Even though the chipset 1815 * documentation doesn't mention it, we need to enter "Config 1816 * register write enable" mode to modify the ID registers. 1817 */ 1818 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_WRITECFG); 1819 memcpy(®, LLADDR(ifp->if_sadl), 4); 1820 CSR_WRITE_STREAM_4(sc, RTK_IDR0, reg); 1821 reg = 0; 1822 memcpy(®, LLADDR(ifp->if_sadl) + 4, 4); 1823 CSR_WRITE_STREAM_4(sc, RTK_IDR4, reg); 1824 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 1825 1826 /* 1827 * For C+ mode, initialize the RX descriptors and mbufs. 1828 */ 1829 re_rx_list_init(sc); 1830 re_tx_list_init(sc); 1831 1832 /* 1833 * Enable transmit and receive. 1834 */ 1835 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1836 1837 /* 1838 * Set the initial TX and RX configuration. 1839 */ 1840 if (sc->rtk_testmode) { 1841 if (sc->rtk_type == RTK_8169) 1842 CSR_WRITE_4(sc, RTK_TXCFG, 1843 RTK_TXCFG_CONFIG | RTK_LOOPTEST_ON); 1844 else 1845 CSR_WRITE_4(sc, RTK_TXCFG, 1846 RTK_TXCFG_CONFIG | RTK_LOOPTEST_ON_CPLUS); 1847 } else 1848 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG); 1849 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG); 1850 1851 /* Set the individual bit to receive frames for this host only. */ 1852 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 1853 rxcfg |= RTK_RXCFG_RX_INDIV; 1854 1855 /* If we want promiscuous mode, set the allframes bit. */ 1856 if (ifp->if_flags & IFF_PROMISC) 1857 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 1858 else 1859 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 1860 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1861 1862 /* 1863 * Set capture broadcast bit to capture broadcast frames. 1864 */ 1865 if (ifp->if_flags & IFF_BROADCAST) 1866 rxcfg |= RTK_RXCFG_RX_BROAD; 1867 else 1868 rxcfg &= ~RTK_RXCFG_RX_BROAD; 1869 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1870 1871 /* 1872 * Program the multicast filter, if necessary. 1873 */ 1874 rtk_setmulti(sc); 1875 1876 #ifdef DEVICE_POLLING 1877 /* 1878 * Disable interrupts if we are polling. 1879 */ 1880 if (ifp->if_flags & IFF_POLLING) 1881 CSR_WRITE_2(sc, RTK_IMR, 0); 1882 else /* otherwise ... */ 1883 #endif /* DEVICE_POLLING */ 1884 /* 1885 * Enable interrupts. 1886 */ 1887 if (sc->rtk_testmode) 1888 CSR_WRITE_2(sc, RTK_IMR, 0); 1889 else 1890 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS); 1891 1892 /* Start RX/TX process. */ 1893 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 1894 #ifdef notdef 1895 /* Enable receiver and transmitter. */ 1896 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1897 #endif 1898 /* 1899 * Load the addresses of the RX and TX lists into the chip. 1900 */ 1901 1902 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_HI, 1903 RTK_ADDR_HI(sc->rtk_ldata.rtk_rx_list_map->dm_segs[0].ds_addr)); 1904 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_LO, 1905 RTK_ADDR_LO(sc->rtk_ldata.rtk_rx_list_map->dm_segs[0].ds_addr)); 1906 1907 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_HI, 1908 RTK_ADDR_HI(sc->rtk_ldata.rtk_tx_list_map->dm_segs[0].ds_addr)); 1909 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_LO, 1910 RTK_ADDR_LO(sc->rtk_ldata.rtk_tx_list_map->dm_segs[0].ds_addr)); 1911 1912 CSR_WRITE_1(sc, RTK_EARLY_TX_THRESH, 16); 1913 1914 /* 1915 * Initialize the timer interrupt register so that 1916 * a timer interrupt will be generated once the timer 1917 * reaches a certain number of ticks. The timer is 1918 * reloaded on each transmit. This gives us TX interrupt 1919 * moderation, which dramatically improves TX frame rate. 1920 */ 1921 1922 if (sc->rtk_type == RTK_8169) 1923 CSR_WRITE_4(sc, RTK_TIMERINT_8169, 0x800); 1924 else 1925 CSR_WRITE_4(sc, RTK_TIMERINT, 0x400); 1926 1927 /* 1928 * For 8169 gigE NICs, set the max allowed RX packet 1929 * size so we can receive jumbo frames. 1930 */ 1931 if (sc->rtk_type == RTK_8169) 1932 CSR_WRITE_2(sc, RTK_MAXRXPKTLEN, 16383); 1933 1934 if (sc->rtk_testmode) 1935 return 0; 1936 1937 mii_mediachg(&sc->mii); 1938 1939 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD | RTK_CFG1_FULLDUPLEX); 1940 1941 ifp->if_flags |= IFF_RUNNING; 1942 ifp->if_flags &= ~IFF_OACTIVE; 1943 1944 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1945 1946 out: 1947 if (error) { 1948 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1949 ifp->if_timer = 0; 1950 aprint_error("%s: interface not running\n", 1951 sc->sc_dev.dv_xname); 1952 } 1953 1954 return error; 1955 1956 } 1957 1958 /* 1959 * Set media options. 1960 */ 1961 static int 1962 re_ifmedia_upd(struct ifnet *ifp) 1963 { 1964 struct rtk_softc *sc; 1965 1966 sc = ifp->if_softc; 1967 1968 return mii_mediachg(&sc->mii); 1969 } 1970 1971 /* 1972 * Report current media status. 1973 */ 1974 static void 1975 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1976 { 1977 struct rtk_softc *sc; 1978 1979 sc = ifp->if_softc; 1980 1981 mii_pollstat(&sc->mii); 1982 ifmr->ifm_active = sc->mii.mii_media_active; 1983 ifmr->ifm_status = sc->mii.mii_media_status; 1984 1985 return; 1986 } 1987 1988 static int 1989 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1990 { 1991 struct rtk_softc *sc = ifp->if_softc; 1992 struct ifreq *ifr = (struct ifreq *) data; 1993 int s, error = 0; 1994 1995 s = splnet(); 1996 1997 switch (command) { 1998 case SIOCSIFMTU: 1999 if (ifr->ifr_mtu > RTK_JUMBO_MTU) 2000 error = EINVAL; 2001 ifp->if_mtu = ifr->ifr_mtu; 2002 break; 2003 case SIOCGIFMEDIA: 2004 case SIOCSIFMEDIA: 2005 error = ifmedia_ioctl(ifp, ifr, &sc->mii.mii_media, command); 2006 break; 2007 default: 2008 error = ether_ioctl(ifp, command, data); 2009 if (error == ENETRESET) { 2010 if (ifp->if_flags & IFF_RUNNING) 2011 rtk_setmulti(sc); 2012 error = 0; 2013 } 2014 break; 2015 } 2016 2017 splx(s); 2018 2019 return error; 2020 } 2021 2022 static void 2023 re_watchdog(struct ifnet *ifp) 2024 { 2025 struct rtk_softc *sc; 2026 int s; 2027 2028 sc = ifp->if_softc; 2029 s = splnet(); 2030 aprint_error("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 2031 ifp->if_oerrors++; 2032 2033 re_txeof(sc); 2034 re_rxeof(sc); 2035 2036 re_init(ifp); 2037 2038 splx(s); 2039 } 2040 2041 /* 2042 * Stop the adapter and free any mbufs allocated to the 2043 * RX and TX lists. 2044 */ 2045 static void 2046 re_stop(struct ifnet *ifp, int disable) 2047 { 2048 register int i; 2049 struct rtk_softc *sc = ifp->if_softc; 2050 2051 callout_stop(&sc->rtk_tick_ch); 2052 2053 #ifdef DEVICE_POLLING 2054 ether_poll_deregister(ifp); 2055 #endif /* DEVICE_POLLING */ 2056 2057 mii_down(&sc->mii); 2058 2059 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 2060 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 2061 2062 if (sc->rtk_head != NULL) { 2063 m_freem(sc->rtk_head); 2064 sc->rtk_head = sc->rtk_tail = NULL; 2065 } 2066 2067 /* Free the TX list buffers. */ 2068 for (i = 0; i < RTK_TX_QLEN; i++) { 2069 if (sc->rtk_ldata.rtk_txq[i].txq_mbuf != NULL) { 2070 bus_dmamap_unload(sc->sc_dmat, 2071 sc->rtk_ldata.rtk_txq[i].txq_dmamap); 2072 m_freem(sc->rtk_ldata.rtk_txq[i].txq_mbuf); 2073 sc->rtk_ldata.rtk_txq[i].txq_mbuf = NULL; 2074 } 2075 } 2076 2077 /* Free the RX list buffers. */ 2078 for (i = 0; i < RTK_RX_DESC_CNT; i++) { 2079 if (sc->rtk_ldata.rtk_rx_mbuf[i] != NULL) { 2080 bus_dmamap_unload(sc->sc_dmat, 2081 sc->rtk_ldata.rtk_rx_dmamap[i]); 2082 m_freem(sc->rtk_ldata.rtk_rx_mbuf[i]); 2083 sc->rtk_ldata.rtk_rx_mbuf[i] = NULL; 2084 } 2085 } 2086 2087 if (disable) 2088 re_disable(sc); 2089 2090 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2091 ifp->if_timer = 0; 2092 2093 return; 2094 } 2095