1 /* $NetBSD: rtl8169.c,v 1.135 2012/03/02 16:23:40 nonaka Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998-2003 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.135 2012/03/02 16:23:40 nonaka Exp $"); 37 /* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */ 38 39 /* 40 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 41 * 42 * Written by Bill Paul <wpaul@windriver.com> 43 * Senior Networking Software Engineer 44 * Wind River Systems 45 */ 46 47 /* 48 * This driver is designed to support RealTek's next generation of 49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 50 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 51 * and the RTL8110S. 52 * 53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 54 * with the older 8139 family, however it also supports a special 55 * C+ mode of operation that provides several new performance enhancing 56 * features. These include: 57 * 58 * o Descriptor based DMA mechanism. Each descriptor represents 59 * a single packet fragment. Data buffers may be aligned on 60 * any byte boundary. 61 * 62 * o 64-bit DMA 63 * 64 * o TCP/IP checksum offload for both RX and TX 65 * 66 * o High and normal priority transmit DMA rings 67 * 68 * o VLAN tag insertion and extraction 69 * 70 * o TCP large send (segmentation offload) 71 * 72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 73 * programming API is fairly straightforward. The RX filtering, EEPROM 74 * access and PHY access is the same as it is on the older 8139 series 75 * chips. 76 * 77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 78 * same programming API and feature set as the 8139C+ with the following 79 * differences and additions: 80 * 81 * o 1000Mbps mode 82 * 83 * o Jumbo frames 84 * 85 * o GMII and TBI ports/registers for interfacing with copper 86 * or fiber PHYs 87 * 88 * o RX and TX DMA rings can have up to 1024 descriptors 89 * (the 8139C+ allows a maximum of 64) 90 * 91 * o Slight differences in register layout from the 8139C+ 92 * 93 * The TX start and timer interrupt registers are at different locations 94 * on the 8169 than they are on the 8139C+. Also, the status word in the 95 * RX descriptor has a slightly different bit layout. The 8169 does not 96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 97 * copper gigE PHY. 98 * 99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 100 * (the 'S' stands for 'single-chip'). These devices have the same 101 * programming API as the older 8169, but also have some vendor-specific 102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 104 * 105 * This driver takes advantage of the RX and TX checksum offload and 106 * VLAN tag insertion/extraction features. It also implements TX 107 * interrupt moderation using the timer interrupt registers, which 108 * significantly reduces TX interrupt load. There is also support 109 * for jumbo frames, however the 8169/8169S/8110S can not transmit 110 * jumbo frames larger than 7.5K, so the max MTU possible with this 111 * driver is 7500 bytes. 112 */ 113 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/kernel.h> 122 #include <sys/socket.h> 123 #include <sys/device.h> 124 125 #include <net/if.h> 126 #include <net/if_arp.h> 127 #include <net/if_dl.h> 128 #include <net/if_ether.h> 129 #include <net/if_media.h> 130 #include <net/if_vlanvar.h> 131 132 #include <netinet/in_systm.h> /* XXX for IP_MAXPACKET */ 133 #include <netinet/in.h> /* XXX for IP_MAXPACKET */ 134 #include <netinet/ip.h> /* XXX for IP_MAXPACKET */ 135 136 #include <net/bpf.h> 137 138 #include <sys/bus.h> 139 140 #include <dev/mii/mii.h> 141 #include <dev/mii/miivar.h> 142 143 #include <dev/ic/rtl81x9reg.h> 144 #include <dev/ic/rtl81x9var.h> 145 146 #include <dev/ic/rtl8169var.h> 147 148 static inline void re_set_bufaddr(struct re_desc *, bus_addr_t); 149 150 static int re_newbuf(struct rtk_softc *, int, struct mbuf *); 151 static int re_rx_list_init(struct rtk_softc *); 152 static int re_tx_list_init(struct rtk_softc *); 153 static void re_rxeof(struct rtk_softc *); 154 static void re_txeof(struct rtk_softc *); 155 static void re_tick(void *); 156 static void re_start(struct ifnet *); 157 static int re_ioctl(struct ifnet *, u_long, void *); 158 static int re_init(struct ifnet *); 159 static void re_stop(struct ifnet *, int); 160 static void re_watchdog(struct ifnet *); 161 162 static int re_enable(struct rtk_softc *); 163 static void re_disable(struct rtk_softc *); 164 165 static int re_gmii_readreg(device_t, int, int); 166 static void re_gmii_writereg(device_t, int, int, int); 167 168 static int re_miibus_readreg(device_t, int, int); 169 static void re_miibus_writereg(device_t, int, int, int); 170 static void re_miibus_statchg(device_t); 171 172 static void re_reset(struct rtk_softc *); 173 174 static inline void 175 re_set_bufaddr(struct re_desc *d, bus_addr_t addr) 176 { 177 178 d->re_bufaddr_lo = htole32((uint32_t)addr); 179 if (sizeof(bus_addr_t) == sizeof(uint64_t)) 180 d->re_bufaddr_hi = htole32((uint64_t)addr >> 32); 181 else 182 d->re_bufaddr_hi = 0; 183 } 184 185 static int 186 re_gmii_readreg(device_t dev, int phy, int reg) 187 { 188 struct rtk_softc *sc = device_private(dev); 189 uint32_t rval; 190 int i; 191 192 if (phy != 7) 193 return 0; 194 195 /* Let the rgephy driver read the GMEDIASTAT register */ 196 197 if (reg == RTK_GMEDIASTAT) { 198 rval = CSR_READ_1(sc, RTK_GMEDIASTAT); 199 return rval; 200 } 201 202 CSR_WRITE_4(sc, RTK_PHYAR, reg << 16); 203 DELAY(1000); 204 205 for (i = 0; i < RTK_TIMEOUT; i++) { 206 rval = CSR_READ_4(sc, RTK_PHYAR); 207 if (rval & RTK_PHYAR_BUSY) 208 break; 209 DELAY(100); 210 } 211 212 if (i == RTK_TIMEOUT) { 213 printf("%s: PHY read failed\n", device_xname(sc->sc_dev)); 214 return 0; 215 } 216 217 return rval & RTK_PHYAR_PHYDATA; 218 } 219 220 static void 221 re_gmii_writereg(device_t dev, int phy, int reg, int data) 222 { 223 struct rtk_softc *sc = device_private(dev); 224 uint32_t rval; 225 int i; 226 227 CSR_WRITE_4(sc, RTK_PHYAR, (reg << 16) | 228 (data & RTK_PHYAR_PHYDATA) | RTK_PHYAR_BUSY); 229 DELAY(1000); 230 231 for (i = 0; i < RTK_TIMEOUT; i++) { 232 rval = CSR_READ_4(sc, RTK_PHYAR); 233 if (!(rval & RTK_PHYAR_BUSY)) 234 break; 235 DELAY(100); 236 } 237 238 if (i == RTK_TIMEOUT) { 239 printf("%s: PHY write reg %x <- %x failed\n", 240 device_xname(sc->sc_dev), reg, data); 241 } 242 } 243 244 static int 245 re_miibus_readreg(device_t dev, int phy, int reg) 246 { 247 struct rtk_softc *sc = device_private(dev); 248 uint16_t rval = 0; 249 uint16_t re8139_reg = 0; 250 int s; 251 252 s = splnet(); 253 254 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 255 rval = re_gmii_readreg(dev, phy, reg); 256 splx(s); 257 return rval; 258 } 259 260 /* Pretend the internal PHY is only at address 0 */ 261 if (phy) { 262 splx(s); 263 return 0; 264 } 265 switch (reg) { 266 case MII_BMCR: 267 re8139_reg = RTK_BMCR; 268 break; 269 case MII_BMSR: 270 re8139_reg = RTK_BMSR; 271 break; 272 case MII_ANAR: 273 re8139_reg = RTK_ANAR; 274 break; 275 case MII_ANER: 276 re8139_reg = RTK_ANER; 277 break; 278 case MII_ANLPAR: 279 re8139_reg = RTK_LPAR; 280 break; 281 case MII_PHYIDR1: 282 case MII_PHYIDR2: 283 splx(s); 284 return 0; 285 /* 286 * Allow the rlphy driver to read the media status 287 * register. If we have a link partner which does not 288 * support NWAY, this is the register which will tell 289 * us the results of parallel detection. 290 */ 291 case RTK_MEDIASTAT: 292 rval = CSR_READ_1(sc, RTK_MEDIASTAT); 293 splx(s); 294 return rval; 295 default: 296 printf("%s: bad phy register\n", device_xname(sc->sc_dev)); 297 splx(s); 298 return 0; 299 } 300 rval = CSR_READ_2(sc, re8139_reg); 301 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0 && re8139_reg == RTK_BMCR) { 302 /* 8139C+ has different bit layout. */ 303 rval &= ~(BMCR_LOOP | BMCR_ISO); 304 } 305 splx(s); 306 return rval; 307 } 308 309 static void 310 re_miibus_writereg(device_t dev, int phy, int reg, int data) 311 { 312 struct rtk_softc *sc = device_private(dev); 313 uint16_t re8139_reg = 0; 314 int s; 315 316 s = splnet(); 317 318 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 319 re_gmii_writereg(dev, phy, reg, data); 320 splx(s); 321 return; 322 } 323 324 /* Pretend the internal PHY is only at address 0 */ 325 if (phy) { 326 splx(s); 327 return; 328 } 329 switch (reg) { 330 case MII_BMCR: 331 re8139_reg = RTK_BMCR; 332 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) { 333 /* 8139C+ has different bit layout. */ 334 data &= ~(BMCR_LOOP | BMCR_ISO); 335 } 336 break; 337 case MII_BMSR: 338 re8139_reg = RTK_BMSR; 339 break; 340 case MII_ANAR: 341 re8139_reg = RTK_ANAR; 342 break; 343 case MII_ANER: 344 re8139_reg = RTK_ANER; 345 break; 346 case MII_ANLPAR: 347 re8139_reg = RTK_LPAR; 348 break; 349 case MII_PHYIDR1: 350 case MII_PHYIDR2: 351 splx(s); 352 return; 353 break; 354 default: 355 printf("%s: bad phy register\n", device_xname(sc->sc_dev)); 356 splx(s); 357 return; 358 } 359 CSR_WRITE_2(sc, re8139_reg, data); 360 splx(s); 361 return; 362 } 363 364 static void 365 re_miibus_statchg(device_t dev) 366 { 367 368 return; 369 } 370 371 static void 372 re_reset(struct rtk_softc *sc) 373 { 374 int i; 375 376 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 377 378 for (i = 0; i < RTK_TIMEOUT; i++) { 379 DELAY(10); 380 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0) 381 break; 382 } 383 if (i == RTK_TIMEOUT) 384 printf("%s: reset never completed!\n", 385 device_xname(sc->sc_dev)); 386 387 /* 388 * NB: Realtek-supplied FreeBSD driver does this only for MACFG_3, 389 * but also says "Rtl8169s sigle chip detected". 390 */ 391 if ((sc->sc_quirk & RTKQ_MACLDPS) != 0) 392 CSR_WRITE_1(sc, RTK_LDPS, 1); 393 394 } 395 396 /* 397 * The following routine is designed to test for a defect on some 398 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 399 * lines connected to the bus, however for a 32-bit only card, they 400 * should be pulled high. The result of this defect is that the 401 * NIC will not work right if you plug it into a 64-bit slot: DMA 402 * operations will be done with 64-bit transfers, which will fail 403 * because the 64-bit data lines aren't connected. 404 * 405 * There's no way to work around this (short of talking a soldering 406 * iron to the board), however we can detect it. The method we use 407 * here is to put the NIC into digital loopback mode, set the receiver 408 * to promiscuous mode, and then try to send a frame. We then compare 409 * the frame data we sent to what was received. If the data matches, 410 * then the NIC is working correctly, otherwise we know the user has 411 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 412 * slot. In the latter case, there's no way the NIC can work correctly, 413 * so we print out a message on the console and abort the device attach. 414 */ 415 416 int 417 re_diag(struct rtk_softc *sc) 418 { 419 struct ifnet *ifp = &sc->ethercom.ec_if; 420 struct mbuf *m0; 421 struct ether_header *eh; 422 struct re_rxsoft *rxs; 423 struct re_desc *cur_rx; 424 bus_dmamap_t dmamap; 425 uint16_t status; 426 uint32_t rxstat; 427 int total_len, i, s, error = 0; 428 static const uint8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 429 static const uint8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 430 431 /* Allocate a single mbuf */ 432 433 MGETHDR(m0, M_DONTWAIT, MT_DATA); 434 if (m0 == NULL) 435 return ENOBUFS; 436 437 /* 438 * Initialize the NIC in test mode. This sets the chip up 439 * so that it can send and receive frames, but performs the 440 * following special functions: 441 * - Puts receiver in promiscuous mode 442 * - Enables digital loopback mode 443 * - Leaves interrupts turned off 444 */ 445 446 ifp->if_flags |= IFF_PROMISC; 447 sc->re_testmode = 1; 448 re_init(ifp); 449 re_stop(ifp, 0); 450 DELAY(100000); 451 re_init(ifp); 452 453 /* Put some data in the mbuf */ 454 455 eh = mtod(m0, struct ether_header *); 456 memcpy(eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN); 457 memcpy(eh->ether_shost, (char *)&src, ETHER_ADDR_LEN); 458 eh->ether_type = htons(ETHERTYPE_IP); 459 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 460 461 /* 462 * Queue the packet, start transmission. 463 */ 464 465 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF); 466 s = splnet(); 467 IF_ENQUEUE(&ifp->if_snd, m0); 468 re_start(ifp); 469 splx(s); 470 m0 = NULL; 471 472 /* Wait for it to propagate through the chip */ 473 474 DELAY(100000); 475 for (i = 0; i < RTK_TIMEOUT; i++) { 476 status = CSR_READ_2(sc, RTK_ISR); 477 if ((status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) == 478 (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) 479 break; 480 DELAY(10); 481 } 482 if (i == RTK_TIMEOUT) { 483 aprint_error_dev(sc->sc_dev, 484 "diagnostic failed, failed to receive packet " 485 "in loopback mode\n"); 486 error = EIO; 487 goto done; 488 } 489 490 /* 491 * The packet should have been dumped into the first 492 * entry in the RX DMA ring. Grab it from there. 493 */ 494 495 rxs = &sc->re_ldata.re_rxsoft[0]; 496 dmamap = rxs->rxs_dmamap; 497 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 498 BUS_DMASYNC_POSTREAD); 499 bus_dmamap_unload(sc->sc_dmat, dmamap); 500 501 m0 = rxs->rxs_mbuf; 502 rxs->rxs_mbuf = NULL; 503 eh = mtod(m0, struct ether_header *); 504 505 RE_RXDESCSYNC(sc, 0, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 506 cur_rx = &sc->re_ldata.re_rx_list[0]; 507 rxstat = le32toh(cur_rx->re_cmdstat); 508 total_len = rxstat & sc->re_rxlenmask; 509 510 if (total_len != ETHER_MIN_LEN) { 511 aprint_error_dev(sc->sc_dev, 512 "diagnostic failed, received short packet\n"); 513 error = EIO; 514 goto done; 515 } 516 517 /* Test that the received packet data matches what we sent. */ 518 519 if (memcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 520 memcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 521 ntohs(eh->ether_type) != ETHERTYPE_IP) { 522 aprint_error_dev(sc->sc_dev, "WARNING, DMA FAILURE!\n" 523 "expected TX data: %s/%s/0x%x\n" 524 "received RX data: %s/%s/0x%x\n" 525 "You may have a defective 32-bit NIC plugged " 526 "into a 64-bit PCI slot.\n" 527 "Please re-install the NIC in a 32-bit slot " 528 "for proper operation.\n" 529 "Read the re(4) man page for more details.\n" , 530 ether_sprintf(dst), ether_sprintf(src), ETHERTYPE_IP, 531 ether_sprintf(eh->ether_dhost), 532 ether_sprintf(eh->ether_shost), ntohs(eh->ether_type)); 533 error = EIO; 534 } 535 536 done: 537 /* Turn interface off, release resources */ 538 539 sc->re_testmode = 0; 540 ifp->if_flags &= ~IFF_PROMISC; 541 re_stop(ifp, 0); 542 if (m0 != NULL) 543 m_freem(m0); 544 545 return error; 546 } 547 548 549 /* 550 * Attach the interface. Allocate softc structures, do ifmedia 551 * setup and ethernet/BPF attach. 552 */ 553 void 554 re_attach(struct rtk_softc *sc) 555 { 556 uint8_t eaddr[ETHER_ADDR_LEN]; 557 uint16_t val; 558 struct ifnet *ifp; 559 int error = 0, i, addr_len; 560 561 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 562 uint32_t hwrev; 563 564 /* Revision of 8169/8169S/8110s in bits 30..26, 23 */ 565 hwrev = CSR_READ_4(sc, RTK_TXCFG) & RTK_TXCFG_HWREV; 566 switch (hwrev) { 567 case RTK_HWREV_8169: 568 sc->sc_quirk |= RTKQ_8169NONS; 569 break; 570 case RTK_HWREV_8169S: 571 case RTK_HWREV_8110S: 572 case RTK_HWREV_8169_8110SB: 573 case RTK_HWREV_8169_8110SBL: 574 case RTK_HWREV_8169_8110SC: 575 sc->sc_quirk |= RTKQ_MACLDPS; 576 break; 577 case RTK_HWREV_8168_SPIN1: 578 case RTK_HWREV_8168_SPIN2: 579 case RTK_HWREV_8168_SPIN3: 580 sc->sc_quirk |= RTKQ_MACSTAT; 581 break; 582 case RTK_HWREV_8168C: 583 case RTK_HWREV_8168C_SPIN2: 584 case RTK_HWREV_8168CP: 585 case RTK_HWREV_8168D: 586 case RTK_HWREV_8168DP: 587 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 588 RTKQ_MACSTAT | RTKQ_CMDSTOP; 589 /* 590 * From FreeBSD driver: 591 * 592 * These (8168/8111) controllers support jumbo frame 593 * but it seems that enabling it requires touching 594 * additional magic registers. Depending on MAC 595 * revisions some controllers need to disable 596 * checksum offload. So disable jumbo frame until 597 * I have better idea what it really requires to 598 * make it support. 599 * RTL8168C/CP : supports up to 6KB jumbo frame. 600 * RTL8111C/CP : supports up to 9KB jumbo frame. 601 */ 602 sc->sc_quirk |= RTKQ_NOJUMBO; 603 break; 604 case RTK_HWREV_8168E: 605 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 606 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_PHYWAKE_PM | 607 RTKQ_NOJUMBO; 608 break; 609 case RTK_HWREV_8168E_VL: 610 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 611 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO; 612 break; 613 case RTK_HWREV_8100E: 614 case RTK_HWREV_8100E_SPIN2: 615 case RTK_HWREV_8101E: 616 sc->sc_quirk |= RTKQ_NOJUMBO; 617 break; 618 case RTK_HWREV_8102E: 619 case RTK_HWREV_8102EL: 620 case RTK_HWREV_8103E: 621 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 622 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO; 623 break; 624 default: 625 aprint_normal_dev(sc->sc_dev, 626 "Unknown revision (0x%08x)\n", hwrev); 627 /* assume the latest features */ 628 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD; 629 sc->sc_quirk |= RTKQ_NOJUMBO; 630 } 631 632 /* Set RX length mask */ 633 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 634 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8169; 635 } else { 636 sc->sc_quirk |= RTKQ_NOJUMBO; 637 638 /* Set RX length mask */ 639 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 640 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8139; 641 } 642 643 /* Reset the adapter. */ 644 re_reset(sc); 645 646 if ((sc->sc_quirk & RTKQ_NOEECMD) != 0) { 647 /* 648 * Get station address from ID registers. 649 */ 650 for (i = 0; i < ETHER_ADDR_LEN; i++) 651 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i); 652 } else { 653 /* 654 * Get station address from the EEPROM. 655 */ 656 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 657 addr_len = RTK_EEADDR_LEN1; 658 else 659 addr_len = RTK_EEADDR_LEN0; 660 661 /* 662 * Get station address from the EEPROM. 663 */ 664 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 665 val = rtk_read_eeprom(sc, RTK_EE_EADDR0 + i, addr_len); 666 eaddr[(i * 2) + 0] = val & 0xff; 667 eaddr[(i * 2) + 1] = val >> 8; 668 } 669 } 670 671 /* Take PHY out of power down mode. */ 672 if ((sc->sc_quirk & RTKQ_PHYWAKE_PM) != 0) 673 CSR_WRITE_1(sc, RTK_PMCH, CSR_READ_1(sc, RTK_PMCH) | 0x80); 674 675 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 676 ether_sprintf(eaddr)); 677 678 if (sc->re_ldata.re_tx_desc_cnt > 679 PAGE_SIZE / sizeof(struct re_desc)) { 680 sc->re_ldata.re_tx_desc_cnt = 681 PAGE_SIZE / sizeof(struct re_desc); 682 } 683 684 aprint_verbose_dev(sc->sc_dev, "using %d tx descriptors\n", 685 sc->re_ldata.re_tx_desc_cnt); 686 KASSERT(RE_NEXT_TX_DESC(sc, RE_TX_DESC_CNT(sc) - 1) == 0); 687 688 /* Allocate DMA'able memory for the TX ring */ 689 if ((error = bus_dmamem_alloc(sc->sc_dmat, RE_TX_LIST_SZ(sc), 690 RE_RING_ALIGN, 0, &sc->re_ldata.re_tx_listseg, 1, 691 &sc->re_ldata.re_tx_listnseg, BUS_DMA_NOWAIT)) != 0) { 692 aprint_error_dev(sc->sc_dev, 693 "can't allocate tx listseg, error = %d\n", error); 694 goto fail_0; 695 } 696 697 /* Load the map for the TX ring. */ 698 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_tx_listseg, 699 sc->re_ldata.re_tx_listnseg, RE_TX_LIST_SZ(sc), 700 (void **)&sc->re_ldata.re_tx_list, 701 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) { 702 aprint_error_dev(sc->sc_dev, 703 "can't map tx list, error = %d\n", error); 704 goto fail_1; 705 } 706 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc)); 707 708 if ((error = bus_dmamap_create(sc->sc_dmat, RE_TX_LIST_SZ(sc), 1, 709 RE_TX_LIST_SZ(sc), 0, 0, 710 &sc->re_ldata.re_tx_list_map)) != 0) { 711 aprint_error_dev(sc->sc_dev, 712 "can't create tx list map, error = %d\n", error); 713 goto fail_2; 714 } 715 716 717 if ((error = bus_dmamap_load(sc->sc_dmat, 718 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list, 719 RE_TX_LIST_SZ(sc), NULL, BUS_DMA_NOWAIT)) != 0) { 720 aprint_error_dev(sc->sc_dev, 721 "can't load tx list, error = %d\n", error); 722 goto fail_3; 723 } 724 725 /* Create DMA maps for TX buffers */ 726 for (i = 0; i < RE_TX_QLEN; i++) { 727 error = bus_dmamap_create(sc->sc_dmat, 728 round_page(IP_MAXPACKET), 729 RE_TX_DESC_CNT(sc), RE_TDESC_CMD_FRAGLEN, 730 0, 0, &sc->re_ldata.re_txq[i].txq_dmamap); 731 if (error) { 732 aprint_error_dev(sc->sc_dev, 733 "can't create DMA map for TX\n"); 734 goto fail_4; 735 } 736 } 737 738 /* Allocate DMA'able memory for the RX ring */ 739 /* XXX see also a comment about RE_RX_DMAMEM_SZ in rtl81x9var.h */ 740 if ((error = bus_dmamem_alloc(sc->sc_dmat, 741 RE_RX_DMAMEM_SZ, RE_RING_ALIGN, 0, &sc->re_ldata.re_rx_listseg, 1, 742 &sc->re_ldata.re_rx_listnseg, BUS_DMA_NOWAIT)) != 0) { 743 aprint_error_dev(sc->sc_dev, 744 "can't allocate rx listseg, error = %d\n", error); 745 goto fail_4; 746 } 747 748 /* Load the map for the RX ring. */ 749 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_rx_listseg, 750 sc->re_ldata.re_rx_listnseg, RE_RX_DMAMEM_SZ, 751 (void **)&sc->re_ldata.re_rx_list, 752 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) { 753 aprint_error_dev(sc->sc_dev, 754 "can't map rx list, error = %d\n", error); 755 goto fail_5; 756 } 757 memset(sc->re_ldata.re_rx_list, 0, RE_RX_DMAMEM_SZ); 758 759 if ((error = bus_dmamap_create(sc->sc_dmat, 760 RE_RX_DMAMEM_SZ, 1, RE_RX_DMAMEM_SZ, 0, 0, 761 &sc->re_ldata.re_rx_list_map)) != 0) { 762 aprint_error_dev(sc->sc_dev, 763 "can't create rx list map, error = %d\n", error); 764 goto fail_6; 765 } 766 767 if ((error = bus_dmamap_load(sc->sc_dmat, 768 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list, 769 RE_RX_DMAMEM_SZ, NULL, BUS_DMA_NOWAIT)) != 0) { 770 aprint_error_dev(sc->sc_dev, 771 "can't load rx list, error = %d\n", error); 772 goto fail_7; 773 } 774 775 /* Create DMA maps for RX buffers */ 776 for (i = 0; i < RE_RX_DESC_CNT; i++) { 777 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 778 0, 0, &sc->re_ldata.re_rxsoft[i].rxs_dmamap); 779 if (error) { 780 aprint_error_dev(sc->sc_dev, 781 "can't create DMA map for RX\n"); 782 goto fail_8; 783 } 784 } 785 786 /* 787 * Record interface as attached. From here, we should not fail. 788 */ 789 sc->sc_flags |= RTK_ATTACHED; 790 791 ifp = &sc->ethercom.ec_if; 792 ifp->if_softc = sc; 793 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 794 ifp->if_mtu = ETHERMTU; 795 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 796 ifp->if_ioctl = re_ioctl; 797 sc->ethercom.ec_capabilities |= 798 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 799 ifp->if_start = re_start; 800 ifp->if_stop = re_stop; 801 802 /* 803 * IFCAP_CSUM_IPv4_Tx on re(4) is broken for small packets, 804 * so we have a workaround to handle the bug by padding 805 * such packets manually. 806 */ 807 ifp->if_capabilities |= 808 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 809 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 810 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 811 IFCAP_TSOv4; 812 813 /* 814 * XXX 815 * Still have no idea how to make TSO work on 8168C, 8168CP, 816 * 8102E, 8111C and 8111CP. 817 */ 818 if ((sc->sc_quirk & RTKQ_DESCV2) != 0) 819 ifp->if_capabilities &= ~IFCAP_TSOv4; 820 821 ifp->if_watchdog = re_watchdog; 822 ifp->if_init = re_init; 823 ifp->if_snd.ifq_maxlen = RE_IFQ_MAXLEN; 824 ifp->if_capenable = ifp->if_capabilities; 825 IFQ_SET_READY(&ifp->if_snd); 826 827 callout_init(&sc->rtk_tick_ch, 0); 828 829 /* Do MII setup */ 830 sc->mii.mii_ifp = ifp; 831 sc->mii.mii_readreg = re_miibus_readreg; 832 sc->mii.mii_writereg = re_miibus_writereg; 833 sc->mii.mii_statchg = re_miibus_statchg; 834 sc->ethercom.ec_mii = &sc->mii; 835 ifmedia_init(&sc->mii.mii_media, IFM_IMASK, ether_mediachange, 836 ether_mediastatus); 837 mii_attach(sc->sc_dev, &sc->mii, 0xffffffff, MII_PHY_ANY, 838 MII_OFFSET_ANY, 0); 839 ifmedia_set(&sc->mii.mii_media, IFM_ETHER | IFM_AUTO); 840 841 /* 842 * Call MI attach routine. 843 */ 844 if_attach(ifp); 845 ether_ifattach(ifp, eaddr); 846 847 if (pmf_device_register(sc->sc_dev, NULL, NULL)) 848 pmf_class_network_register(sc->sc_dev, ifp); 849 else 850 aprint_error_dev(sc->sc_dev, 851 "couldn't establish power handler\n"); 852 853 return; 854 855 fail_8: 856 /* Destroy DMA maps for RX buffers. */ 857 for (i = 0; i < RE_RX_DESC_CNT; i++) 858 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL) 859 bus_dmamap_destroy(sc->sc_dmat, 860 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 861 862 /* Free DMA'able memory for the RX ring. */ 863 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 864 fail_7: 865 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 866 fail_6: 867 bus_dmamem_unmap(sc->sc_dmat, 868 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ); 869 fail_5: 870 bus_dmamem_free(sc->sc_dmat, 871 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg); 872 873 fail_4: 874 /* Destroy DMA maps for TX buffers. */ 875 for (i = 0; i < RE_TX_QLEN; i++) 876 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL) 877 bus_dmamap_destroy(sc->sc_dmat, 878 sc->re_ldata.re_txq[i].txq_dmamap); 879 880 /* Free DMA'able memory for the TX ring. */ 881 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 882 fail_3: 883 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 884 fail_2: 885 bus_dmamem_unmap(sc->sc_dmat, 886 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 887 fail_1: 888 bus_dmamem_free(sc->sc_dmat, 889 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg); 890 fail_0: 891 return; 892 } 893 894 895 /* 896 * re_activate: 897 * Handle device activation/deactivation requests. 898 */ 899 int 900 re_activate(device_t self, enum devact act) 901 { 902 struct rtk_softc *sc = device_private(self); 903 904 switch (act) { 905 case DVACT_DEACTIVATE: 906 if_deactivate(&sc->ethercom.ec_if); 907 return 0; 908 default: 909 return EOPNOTSUPP; 910 } 911 } 912 913 /* 914 * re_detach: 915 * Detach a rtk interface. 916 */ 917 int 918 re_detach(struct rtk_softc *sc) 919 { 920 struct ifnet *ifp = &sc->ethercom.ec_if; 921 int i; 922 923 /* 924 * Succeed now if there isn't any work to do. 925 */ 926 if ((sc->sc_flags & RTK_ATTACHED) == 0) 927 return 0; 928 929 /* Unhook our tick handler. */ 930 callout_stop(&sc->rtk_tick_ch); 931 932 /* Detach all PHYs. */ 933 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 934 935 /* Delete all remaining media. */ 936 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY); 937 938 ether_ifdetach(ifp); 939 if_detach(ifp); 940 941 /* Destroy DMA maps for RX buffers. */ 942 for (i = 0; i < RE_RX_DESC_CNT; i++) 943 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL) 944 bus_dmamap_destroy(sc->sc_dmat, 945 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 946 947 /* Free DMA'able memory for the RX ring. */ 948 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 949 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 950 bus_dmamem_unmap(sc->sc_dmat, 951 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ); 952 bus_dmamem_free(sc->sc_dmat, 953 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg); 954 955 /* Destroy DMA maps for TX buffers. */ 956 for (i = 0; i < RE_TX_QLEN; i++) 957 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL) 958 bus_dmamap_destroy(sc->sc_dmat, 959 sc->re_ldata.re_txq[i].txq_dmamap); 960 961 /* Free DMA'able memory for the TX ring. */ 962 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 963 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 964 bus_dmamem_unmap(sc->sc_dmat, 965 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 966 bus_dmamem_free(sc->sc_dmat, 967 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg); 968 969 pmf_device_deregister(sc->sc_dev); 970 971 /* we don't want to run again */ 972 sc->sc_flags &= ~RTK_ATTACHED; 973 974 return 0; 975 } 976 977 /* 978 * re_enable: 979 * Enable the RTL81X9 chip. 980 */ 981 static int 982 re_enable(struct rtk_softc *sc) 983 { 984 985 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 986 if ((*sc->sc_enable)(sc) != 0) { 987 printf("%s: device enable failed\n", 988 device_xname(sc->sc_dev)); 989 return EIO; 990 } 991 sc->sc_flags |= RTK_ENABLED; 992 } 993 return 0; 994 } 995 996 /* 997 * re_disable: 998 * Disable the RTL81X9 chip. 999 */ 1000 static void 1001 re_disable(struct rtk_softc *sc) 1002 { 1003 1004 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 1005 (*sc->sc_disable)(sc); 1006 sc->sc_flags &= ~RTK_ENABLED; 1007 } 1008 } 1009 1010 static int 1011 re_newbuf(struct rtk_softc *sc, int idx, struct mbuf *m) 1012 { 1013 struct mbuf *n = NULL; 1014 bus_dmamap_t map; 1015 struct re_desc *d; 1016 struct re_rxsoft *rxs; 1017 uint32_t cmdstat; 1018 int error; 1019 1020 if (m == NULL) { 1021 MGETHDR(n, M_DONTWAIT, MT_DATA); 1022 if (n == NULL) 1023 return ENOBUFS; 1024 1025 MCLGET(n, M_DONTWAIT); 1026 if ((n->m_flags & M_EXT) == 0) { 1027 m_freem(n); 1028 return ENOBUFS; 1029 } 1030 m = n; 1031 } else 1032 m->m_data = m->m_ext.ext_buf; 1033 1034 /* 1035 * Initialize mbuf length fields and fixup 1036 * alignment so that the frame payload is 1037 * longword aligned. 1038 */ 1039 m->m_len = m->m_pkthdr.len = MCLBYTES - RE_ETHER_ALIGN; 1040 m->m_data += RE_ETHER_ALIGN; 1041 1042 rxs = &sc->re_ldata.re_rxsoft[idx]; 1043 map = rxs->rxs_dmamap; 1044 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1045 BUS_DMA_READ|BUS_DMA_NOWAIT); 1046 1047 if (error) 1048 goto out; 1049 1050 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1051 BUS_DMASYNC_PREREAD); 1052 1053 d = &sc->re_ldata.re_rx_list[idx]; 1054 #ifdef DIAGNOSTIC 1055 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1056 cmdstat = le32toh(d->re_cmdstat); 1057 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1058 if (cmdstat & RE_RDESC_STAT_OWN) { 1059 panic("%s: tried to map busy RX descriptor", 1060 device_xname(sc->sc_dev)); 1061 } 1062 #endif 1063 1064 rxs->rxs_mbuf = m; 1065 1066 d->re_vlanctl = 0; 1067 cmdstat = map->dm_segs[0].ds_len; 1068 if (idx == (RE_RX_DESC_CNT - 1)) 1069 cmdstat |= RE_RDESC_CMD_EOR; 1070 re_set_bufaddr(d, map->dm_segs[0].ds_addr); 1071 d->re_cmdstat = htole32(cmdstat); 1072 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1073 cmdstat |= RE_RDESC_CMD_OWN; 1074 d->re_cmdstat = htole32(cmdstat); 1075 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1076 1077 return 0; 1078 out: 1079 if (n != NULL) 1080 m_freem(n); 1081 return ENOMEM; 1082 } 1083 1084 static int 1085 re_tx_list_init(struct rtk_softc *sc) 1086 { 1087 int i; 1088 1089 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc)); 1090 for (i = 0; i < RE_TX_QLEN; i++) { 1091 sc->re_ldata.re_txq[i].txq_mbuf = NULL; 1092 } 1093 1094 bus_dmamap_sync(sc->sc_dmat, 1095 sc->re_ldata.re_tx_list_map, 0, 1096 sc->re_ldata.re_tx_list_map->dm_mapsize, 1097 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1098 sc->re_ldata.re_txq_prodidx = 0; 1099 sc->re_ldata.re_txq_considx = 0; 1100 sc->re_ldata.re_txq_free = RE_TX_QLEN; 1101 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT(sc); 1102 sc->re_ldata.re_tx_nextfree = 0; 1103 1104 return 0; 1105 } 1106 1107 static int 1108 re_rx_list_init(struct rtk_softc *sc) 1109 { 1110 int i; 1111 1112 memset(sc->re_ldata.re_rx_list, 0, RE_RX_LIST_SZ); 1113 1114 for (i = 0; i < RE_RX_DESC_CNT; i++) { 1115 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1116 return ENOBUFS; 1117 } 1118 1119 sc->re_ldata.re_rx_prodidx = 0; 1120 sc->re_head = sc->re_tail = NULL; 1121 1122 return 0; 1123 } 1124 1125 /* 1126 * RX handler for C+ and 8169. For the gigE chips, we support 1127 * the reception of jumbo frames that have been fragmented 1128 * across multiple 2K mbuf cluster buffers. 1129 */ 1130 static void 1131 re_rxeof(struct rtk_softc *sc) 1132 { 1133 struct mbuf *m; 1134 struct ifnet *ifp; 1135 int i, total_len; 1136 struct re_desc *cur_rx; 1137 struct re_rxsoft *rxs; 1138 uint32_t rxstat, rxvlan; 1139 1140 ifp = &sc->ethercom.ec_if; 1141 1142 for (i = sc->re_ldata.re_rx_prodidx;; i = RE_NEXT_RX_DESC(sc, i)) { 1143 cur_rx = &sc->re_ldata.re_rx_list[i]; 1144 RE_RXDESCSYNC(sc, i, 1145 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1146 rxstat = le32toh(cur_rx->re_cmdstat); 1147 rxvlan = le32toh(cur_rx->re_vlanctl); 1148 RE_RXDESCSYNC(sc, i, BUS_DMASYNC_PREREAD); 1149 if ((rxstat & RE_RDESC_STAT_OWN) != 0) { 1150 break; 1151 } 1152 total_len = rxstat & sc->re_rxlenmask; 1153 rxs = &sc->re_ldata.re_rxsoft[i]; 1154 m = rxs->rxs_mbuf; 1155 1156 /* Invalidate the RX mbuf and unload its map */ 1157 1158 bus_dmamap_sync(sc->sc_dmat, 1159 rxs->rxs_dmamap, 0, rxs->rxs_dmamap->dm_mapsize, 1160 BUS_DMASYNC_POSTREAD); 1161 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1162 1163 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1164 m->m_len = MCLBYTES - RE_ETHER_ALIGN; 1165 if (sc->re_head == NULL) 1166 sc->re_head = sc->re_tail = m; 1167 else { 1168 m->m_flags &= ~M_PKTHDR; 1169 sc->re_tail->m_next = m; 1170 sc->re_tail = m; 1171 } 1172 re_newbuf(sc, i, NULL); 1173 continue; 1174 } 1175 1176 /* 1177 * NOTE: for the 8139C+, the frame length field 1178 * is always 12 bits in size, but for the gigE chips, 1179 * it is 13 bits (since the max RX frame length is 16K). 1180 * Unfortunately, all 32 bits in the status word 1181 * were already used, so to make room for the extra 1182 * length bit, RealTek took out the 'frame alignment 1183 * error' bit and shifted the other status bits 1184 * over one slot. The OWN, EOR, FS and LS bits are 1185 * still in the same places. We have already extracted 1186 * the frame length and checked the OWN bit, so rather 1187 * than using an alternate bit mapping, we shift the 1188 * status bits one space to the right so we can evaluate 1189 * them using the 8169 status as though it was in the 1190 * same format as that of the 8139C+. 1191 */ 1192 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) 1193 rxstat >>= 1; 1194 1195 if (__predict_false((rxstat & RE_RDESC_STAT_RXERRSUM) != 0)) { 1196 #ifdef RE_DEBUG 1197 printf("%s: RX error (rxstat = 0x%08x)", 1198 device_xname(sc->sc_dev), rxstat); 1199 if (rxstat & RE_RDESC_STAT_FRALIGN) 1200 printf(", frame alignment error"); 1201 if (rxstat & RE_RDESC_STAT_BUFOFLOW) 1202 printf(", out of buffer space"); 1203 if (rxstat & RE_RDESC_STAT_FIFOOFLOW) 1204 printf(", FIFO overrun"); 1205 if (rxstat & RE_RDESC_STAT_GIANT) 1206 printf(", giant packet"); 1207 if (rxstat & RE_RDESC_STAT_RUNT) 1208 printf(", runt packet"); 1209 if (rxstat & RE_RDESC_STAT_CRCERR) 1210 printf(", CRC error"); 1211 printf("\n"); 1212 #endif 1213 ifp->if_ierrors++; 1214 /* 1215 * If this is part of a multi-fragment packet, 1216 * discard all the pieces. 1217 */ 1218 if (sc->re_head != NULL) { 1219 m_freem(sc->re_head); 1220 sc->re_head = sc->re_tail = NULL; 1221 } 1222 re_newbuf(sc, i, m); 1223 continue; 1224 } 1225 1226 /* 1227 * If allocating a replacement mbuf fails, 1228 * reload the current one. 1229 */ 1230 1231 if (__predict_false(re_newbuf(sc, i, NULL) != 0)) { 1232 ifp->if_ierrors++; 1233 if (sc->re_head != NULL) { 1234 m_freem(sc->re_head); 1235 sc->re_head = sc->re_tail = NULL; 1236 } 1237 re_newbuf(sc, i, m); 1238 continue; 1239 } 1240 1241 if (sc->re_head != NULL) { 1242 m->m_len = total_len % (MCLBYTES - RE_ETHER_ALIGN); 1243 /* 1244 * Special case: if there's 4 bytes or less 1245 * in this buffer, the mbuf can be discarded: 1246 * the last 4 bytes is the CRC, which we don't 1247 * care about anyway. 1248 */ 1249 if (m->m_len <= ETHER_CRC_LEN) { 1250 sc->re_tail->m_len -= 1251 (ETHER_CRC_LEN - m->m_len); 1252 m_freem(m); 1253 } else { 1254 m->m_len -= ETHER_CRC_LEN; 1255 m->m_flags &= ~M_PKTHDR; 1256 sc->re_tail->m_next = m; 1257 } 1258 m = sc->re_head; 1259 sc->re_head = sc->re_tail = NULL; 1260 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1261 } else 1262 m->m_pkthdr.len = m->m_len = 1263 (total_len - ETHER_CRC_LEN); 1264 1265 ifp->if_ipackets++; 1266 m->m_pkthdr.rcvif = ifp; 1267 1268 /* Do RX checksumming */ 1269 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) { 1270 /* Check IP header checksum */ 1271 if ((rxstat & RE_RDESC_STAT_PROTOID) != 0) { 1272 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1273 if (rxstat & RE_RDESC_STAT_IPSUMBAD) 1274 m->m_pkthdr.csum_flags |= 1275 M_CSUM_IPv4_BAD; 1276 1277 /* Check TCP/UDP checksum */ 1278 if (RE_TCPPKT(rxstat)) { 1279 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1280 if (rxstat & RE_RDESC_STAT_TCPSUMBAD) 1281 m->m_pkthdr.csum_flags |= 1282 M_CSUM_TCP_UDP_BAD; 1283 } else if (RE_UDPPKT(rxstat)) { 1284 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1285 if (rxstat & RE_RDESC_STAT_UDPSUMBAD) 1286 m->m_pkthdr.csum_flags |= 1287 M_CSUM_TCP_UDP_BAD; 1288 } 1289 } 1290 } else { 1291 /* Check IPv4 header checksum */ 1292 if ((rxvlan & RE_RDESC_VLANCTL_IPV4) != 0) { 1293 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1294 if (rxstat & RE_RDESC_STAT_IPSUMBAD) 1295 m->m_pkthdr.csum_flags |= 1296 M_CSUM_IPv4_BAD; 1297 1298 /* Check TCPv4/UDPv4 checksum */ 1299 if (RE_TCPPKT(rxstat)) { 1300 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1301 if (rxstat & RE_RDESC_STAT_TCPSUMBAD) 1302 m->m_pkthdr.csum_flags |= 1303 M_CSUM_TCP_UDP_BAD; 1304 } else if (RE_UDPPKT(rxstat)) { 1305 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1306 if (rxstat & RE_RDESC_STAT_UDPSUMBAD) 1307 m->m_pkthdr.csum_flags |= 1308 M_CSUM_TCP_UDP_BAD; 1309 } 1310 } 1311 /* XXX Check TCPv6/UDPv6 checksum? */ 1312 } 1313 1314 if (rxvlan & RE_RDESC_VLANCTL_TAG) { 1315 VLAN_INPUT_TAG(ifp, m, 1316 bswap16(rxvlan & RE_RDESC_VLANCTL_DATA), 1317 continue); 1318 } 1319 bpf_mtap(ifp, m); 1320 (*ifp->if_input)(ifp, m); 1321 } 1322 1323 sc->re_ldata.re_rx_prodidx = i; 1324 } 1325 1326 static void 1327 re_txeof(struct rtk_softc *sc) 1328 { 1329 struct ifnet *ifp; 1330 struct re_txq *txq; 1331 uint32_t txstat; 1332 int idx, descidx; 1333 1334 ifp = &sc->ethercom.ec_if; 1335 1336 for (idx = sc->re_ldata.re_txq_considx; 1337 sc->re_ldata.re_txq_free < RE_TX_QLEN; 1338 idx = RE_NEXT_TXQ(sc, idx), sc->re_ldata.re_txq_free++) { 1339 txq = &sc->re_ldata.re_txq[idx]; 1340 KASSERT(txq->txq_mbuf != NULL); 1341 1342 descidx = txq->txq_descidx; 1343 RE_TXDESCSYNC(sc, descidx, 1344 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1345 txstat = 1346 le32toh(sc->re_ldata.re_tx_list[descidx].re_cmdstat); 1347 RE_TXDESCSYNC(sc, descidx, BUS_DMASYNC_PREREAD); 1348 KASSERT((txstat & RE_TDESC_CMD_EOF) != 0); 1349 if (txstat & RE_TDESC_CMD_OWN) { 1350 break; 1351 } 1352 1353 sc->re_ldata.re_tx_free += txq->txq_nsegs; 1354 KASSERT(sc->re_ldata.re_tx_free <= RE_TX_DESC_CNT(sc)); 1355 bus_dmamap_sync(sc->sc_dmat, txq->txq_dmamap, 1356 0, txq->txq_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1357 bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap); 1358 m_freem(txq->txq_mbuf); 1359 txq->txq_mbuf = NULL; 1360 1361 if (txstat & (RE_TDESC_STAT_EXCESSCOL | RE_TDESC_STAT_COLCNT)) 1362 ifp->if_collisions++; 1363 if (txstat & RE_TDESC_STAT_TXERRSUM) 1364 ifp->if_oerrors++; 1365 else 1366 ifp->if_opackets++; 1367 } 1368 1369 sc->re_ldata.re_txq_considx = idx; 1370 1371 if (sc->re_ldata.re_txq_free > RE_NTXDESC_RSVD) 1372 ifp->if_flags &= ~IFF_OACTIVE; 1373 1374 /* 1375 * If not all descriptors have been released reaped yet, 1376 * reload the timer so that we will eventually get another 1377 * interrupt that will cause us to re-enter this routine. 1378 * This is done in case the transmitter has gone idle. 1379 */ 1380 if (sc->re_ldata.re_txq_free < RE_TX_QLEN) { 1381 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1382 if ((sc->sc_quirk & RTKQ_PCIE) != 0) { 1383 /* 1384 * Some chips will ignore a second TX request 1385 * issued while an existing transmission is in 1386 * progress. If the transmitter goes idle but 1387 * there are still packets waiting to be sent, 1388 * we need to restart the channel here to flush 1389 * them out. This only seems to be required with 1390 * the PCIe devices. 1391 */ 1392 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START); 1393 } 1394 } else 1395 ifp->if_timer = 0; 1396 } 1397 1398 static void 1399 re_tick(void *arg) 1400 { 1401 struct rtk_softc *sc = arg; 1402 int s; 1403 1404 /* XXX: just return for 8169S/8110S with rev 2 or newer phy */ 1405 s = splnet(); 1406 1407 mii_tick(&sc->mii); 1408 splx(s); 1409 1410 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1411 } 1412 1413 int 1414 re_intr(void *arg) 1415 { 1416 struct rtk_softc *sc = arg; 1417 struct ifnet *ifp; 1418 uint16_t status; 1419 int handled = 0; 1420 1421 if (!device_has_power(sc->sc_dev)) 1422 return 0; 1423 1424 ifp = &sc->ethercom.ec_if; 1425 1426 if ((ifp->if_flags & IFF_UP) == 0) 1427 return 0; 1428 1429 for (;;) { 1430 1431 status = CSR_READ_2(sc, RTK_ISR); 1432 /* If the card has gone away the read returns 0xffff. */ 1433 if (status == 0xffff) 1434 break; 1435 if (status) { 1436 handled = 1; 1437 CSR_WRITE_2(sc, RTK_ISR, status); 1438 } 1439 1440 if ((status & RTK_INTRS_CPLUS) == 0) 1441 break; 1442 1443 if (status & (RTK_ISR_RX_OK | RTK_ISR_RX_ERR)) 1444 re_rxeof(sc); 1445 1446 if (status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_TX_ERR | 1447 RTK_ISR_TX_DESC_UNAVAIL)) 1448 re_txeof(sc); 1449 1450 if (status & RTK_ISR_SYSTEM_ERR) { 1451 re_init(ifp); 1452 } 1453 1454 if (status & RTK_ISR_LINKCHG) { 1455 callout_stop(&sc->rtk_tick_ch); 1456 re_tick(sc); 1457 } 1458 } 1459 1460 if (handled && !IFQ_IS_EMPTY(&ifp->if_snd)) 1461 re_start(ifp); 1462 1463 return handled; 1464 } 1465 1466 1467 1468 /* 1469 * Main transmit routine for C+ and gigE NICs. 1470 */ 1471 1472 static void 1473 re_start(struct ifnet *ifp) 1474 { 1475 struct rtk_softc *sc; 1476 struct mbuf *m; 1477 bus_dmamap_t map; 1478 struct re_txq *txq; 1479 struct re_desc *d; 1480 struct m_tag *mtag; 1481 uint32_t cmdstat, re_flags, vlanctl; 1482 int ofree, idx, error, nsegs, seg; 1483 int startdesc, curdesc, lastdesc; 1484 bool pad; 1485 1486 sc = ifp->if_softc; 1487 ofree = sc->re_ldata.re_txq_free; 1488 1489 for (idx = sc->re_ldata.re_txq_prodidx;; idx = RE_NEXT_TXQ(sc, idx)) { 1490 1491 IFQ_POLL(&ifp->if_snd, m); 1492 if (m == NULL) 1493 break; 1494 1495 if (sc->re_ldata.re_txq_free == 0 || 1496 sc->re_ldata.re_tx_free == 0) { 1497 /* no more free slots left */ 1498 ifp->if_flags |= IFF_OACTIVE; 1499 break; 1500 } 1501 1502 /* 1503 * Set up checksum offload. Note: checksum offload bits must 1504 * appear in all descriptors of a multi-descriptor transmit 1505 * attempt. (This is according to testing done with an 8169 1506 * chip. I'm not sure if this is a requirement or a bug.) 1507 */ 1508 1509 vlanctl = 0; 1510 if ((m->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0) { 1511 uint32_t segsz = m->m_pkthdr.segsz; 1512 1513 re_flags = RE_TDESC_CMD_LGSEND | 1514 (segsz << RE_TDESC_CMD_MSSVAL_SHIFT); 1515 } else { 1516 /* 1517 * set RE_TDESC_CMD_IPCSUM if any checksum offloading 1518 * is requested. otherwise, RE_TDESC_CMD_TCPCSUM/ 1519 * RE_TDESC_CMD_UDPCSUM doesn't make effects. 1520 */ 1521 re_flags = 0; 1522 if ((m->m_pkthdr.csum_flags & 1523 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1524 != 0) { 1525 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) { 1526 re_flags |= RE_TDESC_CMD_IPCSUM; 1527 if (m->m_pkthdr.csum_flags & 1528 M_CSUM_TCPv4) { 1529 re_flags |= 1530 RE_TDESC_CMD_TCPCSUM; 1531 } else if (m->m_pkthdr.csum_flags & 1532 M_CSUM_UDPv4) { 1533 re_flags |= 1534 RE_TDESC_CMD_UDPCSUM; 1535 } 1536 } else { 1537 vlanctl |= RE_TDESC_VLANCTL_IPCSUM; 1538 if (m->m_pkthdr.csum_flags & 1539 M_CSUM_TCPv4) { 1540 vlanctl |= 1541 RE_TDESC_VLANCTL_TCPCSUM; 1542 } else if (m->m_pkthdr.csum_flags & 1543 M_CSUM_UDPv4) { 1544 vlanctl |= 1545 RE_TDESC_VLANCTL_UDPCSUM; 1546 } 1547 } 1548 } 1549 } 1550 1551 txq = &sc->re_ldata.re_txq[idx]; 1552 map = txq->txq_dmamap; 1553 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1554 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1555 1556 if (__predict_false(error)) { 1557 /* XXX try to defrag if EFBIG? */ 1558 printf("%s: can't map mbuf (error %d)\n", 1559 device_xname(sc->sc_dev), error); 1560 1561 IFQ_DEQUEUE(&ifp->if_snd, m); 1562 m_freem(m); 1563 ifp->if_oerrors++; 1564 continue; 1565 } 1566 1567 nsegs = map->dm_nsegs; 1568 pad = false; 1569 if (__predict_false(m->m_pkthdr.len <= RE_IP4CSUMTX_PADLEN && 1570 (re_flags & RE_TDESC_CMD_IPCSUM) != 0 && 1571 (sc->sc_quirk & RTKQ_DESCV2) == 0)) { 1572 pad = true; 1573 nsegs++; 1574 } 1575 1576 if (nsegs > sc->re_ldata.re_tx_free) { 1577 /* 1578 * Not enough free descriptors to transmit this packet. 1579 */ 1580 ifp->if_flags |= IFF_OACTIVE; 1581 bus_dmamap_unload(sc->sc_dmat, map); 1582 break; 1583 } 1584 1585 IFQ_DEQUEUE(&ifp->if_snd, m); 1586 1587 /* 1588 * Make sure that the caches are synchronized before we 1589 * ask the chip to start DMA for the packet data. 1590 */ 1591 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1592 BUS_DMASYNC_PREWRITE); 1593 1594 /* 1595 * Set up hardware VLAN tagging. Note: vlan tag info must 1596 * appear in all descriptors of a multi-descriptor 1597 * transmission attempt. 1598 */ 1599 if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m)) != NULL) 1600 vlanctl |= bswap16(VLAN_TAG_VALUE(mtag)) | 1601 RE_TDESC_VLANCTL_TAG; 1602 1603 /* 1604 * Map the segment array into descriptors. 1605 * Note that we set the start-of-frame and 1606 * end-of-frame markers for either TX or RX, 1607 * but they really only have meaning in the TX case. 1608 * (In the RX case, it's the chip that tells us 1609 * where packets begin and end.) 1610 * We also keep track of the end of the ring 1611 * and set the end-of-ring bits as needed, 1612 * and we set the ownership bits in all except 1613 * the very first descriptor. (The caller will 1614 * set this descriptor later when it start 1615 * transmission or reception.) 1616 */ 1617 curdesc = startdesc = sc->re_ldata.re_tx_nextfree; 1618 lastdesc = -1; 1619 for (seg = 0; seg < map->dm_nsegs; 1620 seg++, curdesc = RE_NEXT_TX_DESC(sc, curdesc)) { 1621 d = &sc->re_ldata.re_tx_list[curdesc]; 1622 #ifdef DIAGNOSTIC 1623 RE_TXDESCSYNC(sc, curdesc, 1624 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1625 cmdstat = le32toh(d->re_cmdstat); 1626 RE_TXDESCSYNC(sc, curdesc, BUS_DMASYNC_PREREAD); 1627 if (cmdstat & RE_TDESC_STAT_OWN) { 1628 panic("%s: tried to map busy TX descriptor", 1629 device_xname(sc->sc_dev)); 1630 } 1631 #endif 1632 1633 d->re_vlanctl = htole32(vlanctl); 1634 re_set_bufaddr(d, map->dm_segs[seg].ds_addr); 1635 cmdstat = re_flags | map->dm_segs[seg].ds_len; 1636 if (seg == 0) 1637 cmdstat |= RE_TDESC_CMD_SOF; 1638 else 1639 cmdstat |= RE_TDESC_CMD_OWN; 1640 if (curdesc == (RE_TX_DESC_CNT(sc) - 1)) 1641 cmdstat |= RE_TDESC_CMD_EOR; 1642 if (seg == nsegs - 1) { 1643 cmdstat |= RE_TDESC_CMD_EOF; 1644 lastdesc = curdesc; 1645 } 1646 d->re_cmdstat = htole32(cmdstat); 1647 RE_TXDESCSYNC(sc, curdesc, 1648 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1649 } 1650 if (__predict_false(pad)) { 1651 d = &sc->re_ldata.re_tx_list[curdesc]; 1652 d->re_vlanctl = htole32(vlanctl); 1653 re_set_bufaddr(d, RE_TXPADDADDR(sc)); 1654 cmdstat = re_flags | 1655 RE_TDESC_CMD_OWN | RE_TDESC_CMD_EOF | 1656 (RE_IP4CSUMTX_PADLEN + 1 - m->m_pkthdr.len); 1657 if (curdesc == (RE_TX_DESC_CNT(sc) - 1)) 1658 cmdstat |= RE_TDESC_CMD_EOR; 1659 d->re_cmdstat = htole32(cmdstat); 1660 RE_TXDESCSYNC(sc, curdesc, 1661 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1662 lastdesc = curdesc; 1663 curdesc = RE_NEXT_TX_DESC(sc, curdesc); 1664 } 1665 KASSERT(lastdesc != -1); 1666 1667 /* Transfer ownership of packet to the chip. */ 1668 1669 sc->re_ldata.re_tx_list[startdesc].re_cmdstat |= 1670 htole32(RE_TDESC_CMD_OWN); 1671 RE_TXDESCSYNC(sc, startdesc, 1672 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1673 1674 /* update info of TX queue and descriptors */ 1675 txq->txq_mbuf = m; 1676 txq->txq_descidx = lastdesc; 1677 txq->txq_nsegs = nsegs; 1678 1679 sc->re_ldata.re_txq_free--; 1680 sc->re_ldata.re_tx_free -= nsegs; 1681 sc->re_ldata.re_tx_nextfree = curdesc; 1682 1683 /* 1684 * If there's a BPF listener, bounce a copy of this frame 1685 * to him. 1686 */ 1687 bpf_mtap(ifp, m); 1688 } 1689 1690 if (sc->re_ldata.re_txq_free < ofree) { 1691 /* 1692 * TX packets are enqueued. 1693 */ 1694 sc->re_ldata.re_txq_prodidx = idx; 1695 1696 /* 1697 * Start the transmitter to poll. 1698 * 1699 * RealTek put the TX poll request register in a different 1700 * location on the 8169 gigE chip. I don't know why. 1701 */ 1702 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) 1703 CSR_WRITE_1(sc, RTK_TXSTART, RTK_TXSTART_START); 1704 else 1705 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START); 1706 1707 /* 1708 * Use the countdown timer for interrupt moderation. 1709 * 'TX done' interrupts are disabled. Instead, we reset the 1710 * countdown timer, which will begin counting until it hits 1711 * the value in the TIMERINT register, and then trigger an 1712 * interrupt. Each time we write to the TIMERCNT register, 1713 * the timer count is reset to 0. 1714 */ 1715 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1716 1717 /* 1718 * Set a timeout in case the chip goes out to lunch. 1719 */ 1720 ifp->if_timer = 5; 1721 } 1722 } 1723 1724 static int 1725 re_init(struct ifnet *ifp) 1726 { 1727 struct rtk_softc *sc = ifp->if_softc; 1728 const uint8_t *enaddr; 1729 uint32_t rxcfg = 0; 1730 uint32_t reg; 1731 uint16_t cfg; 1732 int error; 1733 1734 if ((error = re_enable(sc)) != 0) 1735 goto out; 1736 1737 /* 1738 * Cancel pending I/O and free all RX/TX buffers. 1739 */ 1740 re_stop(ifp, 0); 1741 1742 re_reset(sc); 1743 1744 /* 1745 * Enable C+ RX and TX mode, as well as VLAN stripping and 1746 * RX checksum offload. We must configure the C+ register 1747 * before all others. 1748 */ 1749 cfg = RE_CPLUSCMD_PCI_MRW; 1750 1751 /* 1752 * XXX: For old 8169 set bit 14. 1753 * For 8169S/8110S and above, do not set bit 14. 1754 */ 1755 if ((sc->sc_quirk & RTKQ_8169NONS) != 0) 1756 cfg |= (0x1 << 14); 1757 1758 if ((sc->ethercom.ec_capenable & ETHERCAP_VLAN_HWTAGGING) != 0) 1759 cfg |= RE_CPLUSCMD_VLANSTRIP; 1760 if ((ifp->if_capenable & (IFCAP_CSUM_IPv4_Rx | 1761 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) != 0) 1762 cfg |= RE_CPLUSCMD_RXCSUM_ENB; 1763 if ((sc->sc_quirk & RTKQ_MACSTAT) != 0) { 1764 cfg |= RE_CPLUSCMD_MACSTAT_DIS; 1765 cfg |= RE_CPLUSCMD_TXENB; 1766 } else 1767 cfg |= RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB; 1768 1769 CSR_WRITE_2(sc, RTK_CPLUS_CMD, cfg); 1770 1771 /* XXX: from Realtek-supplied Linux driver. Wholly undocumented. */ 1772 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) 1773 CSR_WRITE_2(sc, RTK_IM, 0x0000); 1774 1775 DELAY(10000); 1776 1777 /* 1778 * Init our MAC address. Even though the chipset 1779 * documentation doesn't mention it, we need to enter "Config 1780 * register write enable" mode to modify the ID registers. 1781 */ 1782 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_WRITECFG); 1783 enaddr = CLLADDR(ifp->if_sadl); 1784 reg = enaddr[0] | (enaddr[1] << 8) | 1785 (enaddr[2] << 16) | (enaddr[3] << 24); 1786 CSR_WRITE_4(sc, RTK_IDR0, reg); 1787 reg = enaddr[4] | (enaddr[5] << 8); 1788 CSR_WRITE_4(sc, RTK_IDR4, reg); 1789 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 1790 1791 /* 1792 * For C+ mode, initialize the RX descriptors and mbufs. 1793 */ 1794 re_rx_list_init(sc); 1795 re_tx_list_init(sc); 1796 1797 /* 1798 * Load the addresses of the RX and TX lists into the chip. 1799 */ 1800 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_HI, 1801 RE_ADDR_HI(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr)); 1802 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_LO, 1803 RE_ADDR_LO(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr)); 1804 1805 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_HI, 1806 RE_ADDR_HI(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr)); 1807 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_LO, 1808 RE_ADDR_LO(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr)); 1809 1810 /* 1811 * Enable transmit and receive. 1812 */ 1813 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1814 1815 /* 1816 * Set the initial TX and RX configuration. 1817 */ 1818 if (sc->re_testmode && (sc->sc_quirk & RTKQ_8169NONS) != 0) { 1819 /* test mode is needed only for old 8169 */ 1820 CSR_WRITE_4(sc, RTK_TXCFG, 1821 RE_TXCFG_CONFIG | RTK_LOOPTEST_ON); 1822 } else 1823 CSR_WRITE_4(sc, RTK_TXCFG, RE_TXCFG_CONFIG); 1824 1825 CSR_WRITE_1(sc, RTK_EARLY_TX_THRESH, 16); 1826 1827 CSR_WRITE_4(sc, RTK_RXCFG, RE_RXCFG_CONFIG); 1828 1829 /* Set the individual bit to receive frames for this host only. */ 1830 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 1831 rxcfg |= RTK_RXCFG_RX_INDIV; 1832 1833 /* If we want promiscuous mode, set the allframes bit. */ 1834 if (ifp->if_flags & IFF_PROMISC) 1835 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 1836 else 1837 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 1838 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1839 1840 /* 1841 * Set capture broadcast bit to capture broadcast frames. 1842 */ 1843 if (ifp->if_flags & IFF_BROADCAST) 1844 rxcfg |= RTK_RXCFG_RX_BROAD; 1845 else 1846 rxcfg &= ~RTK_RXCFG_RX_BROAD; 1847 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1848 1849 /* 1850 * Program the multicast filter, if necessary. 1851 */ 1852 rtk_setmulti(sc); 1853 1854 /* 1855 * Enable interrupts. 1856 */ 1857 if (sc->re_testmode) 1858 CSR_WRITE_2(sc, RTK_IMR, 0); 1859 else 1860 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS); 1861 1862 /* Start RX/TX process. */ 1863 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 1864 #ifdef notdef 1865 /* Enable receiver and transmitter. */ 1866 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1867 #endif 1868 1869 /* 1870 * Initialize the timer interrupt register so that 1871 * a timer interrupt will be generated once the timer 1872 * reaches a certain number of ticks. The timer is 1873 * reloaded on each transmit. This gives us TX interrupt 1874 * moderation, which dramatically improves TX frame rate. 1875 */ 1876 1877 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) 1878 CSR_WRITE_4(sc, RTK_TIMERINT, 0x400); 1879 else { 1880 CSR_WRITE_4(sc, RTK_TIMERINT_8169, 0x800); 1881 1882 /* 1883 * For 8169 gigE NICs, set the max allowed RX packet 1884 * size so we can receive jumbo frames. 1885 */ 1886 CSR_WRITE_2(sc, RTK_MAXRXPKTLEN, 16383); 1887 } 1888 1889 if (sc->re_testmode) 1890 return 0; 1891 1892 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD); 1893 1894 ifp->if_flags |= IFF_RUNNING; 1895 ifp->if_flags &= ~IFF_OACTIVE; 1896 1897 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1898 1899 out: 1900 if (error) { 1901 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1902 ifp->if_timer = 0; 1903 printf("%s: interface not running\n", 1904 device_xname(sc->sc_dev)); 1905 } 1906 1907 return error; 1908 } 1909 1910 static int 1911 re_ioctl(struct ifnet *ifp, u_long command, void *data) 1912 { 1913 struct rtk_softc *sc = ifp->if_softc; 1914 struct ifreq *ifr = data; 1915 int s, error = 0; 1916 1917 s = splnet(); 1918 1919 switch (command) { 1920 case SIOCSIFMTU: 1921 /* 1922 * Disable jumbo frames if it's not supported. 1923 */ 1924 if ((sc->sc_quirk & RTKQ_NOJUMBO) != 0 && 1925 ifr->ifr_mtu > ETHERMTU) { 1926 error = EINVAL; 1927 break; 1928 } 1929 1930 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO) 1931 error = EINVAL; 1932 else if ((error = ifioctl_common(ifp, command, data)) == 1933 ENETRESET) 1934 error = 0; 1935 break; 1936 default: 1937 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1938 break; 1939 1940 error = 0; 1941 1942 if (command == SIOCSIFCAP) 1943 error = (*ifp->if_init)(ifp); 1944 else if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1945 ; 1946 else if (ifp->if_flags & IFF_RUNNING) 1947 rtk_setmulti(sc); 1948 break; 1949 } 1950 1951 splx(s); 1952 1953 return error; 1954 } 1955 1956 static void 1957 re_watchdog(struct ifnet *ifp) 1958 { 1959 struct rtk_softc *sc; 1960 int s; 1961 1962 sc = ifp->if_softc; 1963 s = splnet(); 1964 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1965 ifp->if_oerrors++; 1966 1967 re_txeof(sc); 1968 re_rxeof(sc); 1969 1970 re_init(ifp); 1971 1972 splx(s); 1973 } 1974 1975 /* 1976 * Stop the adapter and free any mbufs allocated to the 1977 * RX and TX lists. 1978 */ 1979 static void 1980 re_stop(struct ifnet *ifp, int disable) 1981 { 1982 int i; 1983 struct rtk_softc *sc = ifp->if_softc; 1984 1985 callout_stop(&sc->rtk_tick_ch); 1986 1987 mii_down(&sc->mii); 1988 1989 if ((sc->sc_quirk & RTKQ_CMDSTOP) != 0) 1990 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_STOPREQ | RTK_CMD_TX_ENB | 1991 RTK_CMD_RX_ENB); 1992 else 1993 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 1994 DELAY(1000); 1995 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1996 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF); 1997 1998 if (sc->re_head != NULL) { 1999 m_freem(sc->re_head); 2000 sc->re_head = sc->re_tail = NULL; 2001 } 2002 2003 /* Free the TX list buffers. */ 2004 for (i = 0; i < RE_TX_QLEN; i++) { 2005 if (sc->re_ldata.re_txq[i].txq_mbuf != NULL) { 2006 bus_dmamap_unload(sc->sc_dmat, 2007 sc->re_ldata.re_txq[i].txq_dmamap); 2008 m_freem(sc->re_ldata.re_txq[i].txq_mbuf); 2009 sc->re_ldata.re_txq[i].txq_mbuf = NULL; 2010 } 2011 } 2012 2013 /* Free the RX list buffers. */ 2014 for (i = 0; i < RE_RX_DESC_CNT; i++) { 2015 if (sc->re_ldata.re_rxsoft[i].rxs_mbuf != NULL) { 2016 bus_dmamap_unload(sc->sc_dmat, 2017 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 2018 m_freem(sc->re_ldata.re_rxsoft[i].rxs_mbuf); 2019 sc->re_ldata.re_rxsoft[i].rxs_mbuf = NULL; 2020 } 2021 } 2022 2023 if (disable) 2024 re_disable(sc); 2025 2026 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2027 ifp->if_timer = 0; 2028 } 2029