1 /* $NetBSD: rtl8169.c,v 1.116 2009/04/13 12:38:06 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998-2003 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.116 2009/04/13 12:38:06 tsutsui Exp $"); 37 /* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */ 38 39 /* 40 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 41 * 42 * Written by Bill Paul <wpaul@windriver.com> 43 * Senior Networking Software Engineer 44 * Wind River Systems 45 */ 46 47 /* 48 * This driver is designed to support RealTek's next generation of 49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 50 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 51 * and the RTL8110S. 52 * 53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 54 * with the older 8139 family, however it also supports a special 55 * C+ mode of operation that provides several new performance enhancing 56 * features. These include: 57 * 58 * o Descriptor based DMA mechanism. Each descriptor represents 59 * a single packet fragment. Data buffers may be aligned on 60 * any byte boundary. 61 * 62 * o 64-bit DMA 63 * 64 * o TCP/IP checksum offload for both RX and TX 65 * 66 * o High and normal priority transmit DMA rings 67 * 68 * o VLAN tag insertion and extraction 69 * 70 * o TCP large send (segmentation offload) 71 * 72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 73 * programming API is fairly straightforward. The RX filtering, EEPROM 74 * access and PHY access is the same as it is on the older 8139 series 75 * chips. 76 * 77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 78 * same programming API and feature set as the 8139C+ with the following 79 * differences and additions: 80 * 81 * o 1000Mbps mode 82 * 83 * o Jumbo frames 84 * 85 * o GMII and TBI ports/registers for interfacing with copper 86 * or fiber PHYs 87 * 88 * o RX and TX DMA rings can have up to 1024 descriptors 89 * (the 8139C+ allows a maximum of 64) 90 * 91 * o Slight differences in register layout from the 8139C+ 92 * 93 * The TX start and timer interrupt registers are at different locations 94 * on the 8169 than they are on the 8139C+. Also, the status word in the 95 * RX descriptor has a slightly different bit layout. The 8169 does not 96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 97 * copper gigE PHY. 98 * 99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 100 * (the 'S' stands for 'single-chip'). These devices have the same 101 * programming API as the older 8169, but also have some vendor-specific 102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 104 * 105 * This driver takes advantage of the RX and TX checksum offload and 106 * VLAN tag insertion/extraction features. It also implements TX 107 * interrupt moderation using the timer interrupt registers, which 108 * significantly reduces TX interrupt load. There is also support 109 * for jumbo frames, however the 8169/8169S/8110S can not transmit 110 * jumbo frames larger than 7.5K, so the max MTU possible with this 111 * driver is 7500 bytes. 112 */ 113 114 #include "bpfilter.h" 115 #include "vlan.h" 116 117 #include <sys/param.h> 118 #include <sys/endian.h> 119 #include <sys/systm.h> 120 #include <sys/sockio.h> 121 #include <sys/mbuf.h> 122 #include <sys/malloc.h> 123 #include <sys/kernel.h> 124 #include <sys/socket.h> 125 #include <sys/device.h> 126 127 #include <net/if.h> 128 #include <net/if_arp.h> 129 #include <net/if_dl.h> 130 #include <net/if_ether.h> 131 #include <net/if_media.h> 132 #include <net/if_vlanvar.h> 133 134 #include <netinet/in_systm.h> /* XXX for IP_MAXPACKET */ 135 #include <netinet/in.h> /* XXX for IP_MAXPACKET */ 136 #include <netinet/ip.h> /* XXX for IP_MAXPACKET */ 137 138 #if NBPFILTER > 0 139 #include <net/bpf.h> 140 #endif 141 142 #include <sys/bus.h> 143 144 #include <dev/mii/mii.h> 145 #include <dev/mii/miivar.h> 146 147 #include <dev/ic/rtl81x9reg.h> 148 #include <dev/ic/rtl81x9var.h> 149 150 #include <dev/ic/rtl8169var.h> 151 152 static inline void re_set_bufaddr(struct re_desc *, bus_addr_t); 153 154 static int re_newbuf(struct rtk_softc *, int, struct mbuf *); 155 static int re_rx_list_init(struct rtk_softc *); 156 static int re_tx_list_init(struct rtk_softc *); 157 static void re_rxeof(struct rtk_softc *); 158 static void re_txeof(struct rtk_softc *); 159 static void re_tick(void *); 160 static void re_start(struct ifnet *); 161 static int re_ioctl(struct ifnet *, u_long, void *); 162 static int re_init(struct ifnet *); 163 static void re_stop(struct ifnet *, int); 164 static void re_watchdog(struct ifnet *); 165 166 static int re_enable(struct rtk_softc *); 167 static void re_disable(struct rtk_softc *); 168 169 static int re_gmii_readreg(struct device *, int, int); 170 static void re_gmii_writereg(struct device *, int, int, int); 171 172 static int re_miibus_readreg(struct device *, int, int); 173 static void re_miibus_writereg(struct device *, int, int, int); 174 static void re_miibus_statchg(struct device *); 175 176 static void re_reset(struct rtk_softc *); 177 178 static inline void 179 re_set_bufaddr(struct re_desc *d, bus_addr_t addr) 180 { 181 182 d->re_bufaddr_lo = htole32((uint32_t)addr); 183 if (sizeof(bus_addr_t) == sizeof(uint64_t)) 184 d->re_bufaddr_hi = htole32((uint64_t)addr >> 32); 185 else 186 d->re_bufaddr_hi = 0; 187 } 188 189 static int 190 re_gmii_readreg(device_t dev, int phy, int reg) 191 { 192 struct rtk_softc *sc = device_private(dev); 193 uint32_t rval; 194 int i; 195 196 if (phy != 7) 197 return 0; 198 199 /* Let the rgephy driver read the GMEDIASTAT register */ 200 201 if (reg == RTK_GMEDIASTAT) { 202 rval = CSR_READ_1(sc, RTK_GMEDIASTAT); 203 return rval; 204 } 205 206 CSR_WRITE_4(sc, RTK_PHYAR, reg << 16); 207 DELAY(1000); 208 209 for (i = 0; i < RTK_TIMEOUT; i++) { 210 rval = CSR_READ_4(sc, RTK_PHYAR); 211 if (rval & RTK_PHYAR_BUSY) 212 break; 213 DELAY(100); 214 } 215 216 if (i == RTK_TIMEOUT) { 217 printf("%s: PHY read failed\n", device_xname(sc->sc_dev)); 218 return 0; 219 } 220 221 return rval & RTK_PHYAR_PHYDATA; 222 } 223 224 static void 225 re_gmii_writereg(device_t dev, int phy, int reg, int data) 226 { 227 struct rtk_softc *sc = device_private(dev); 228 uint32_t rval; 229 int i; 230 231 CSR_WRITE_4(sc, RTK_PHYAR, (reg << 16) | 232 (data & RTK_PHYAR_PHYDATA) | RTK_PHYAR_BUSY); 233 DELAY(1000); 234 235 for (i = 0; i < RTK_TIMEOUT; i++) { 236 rval = CSR_READ_4(sc, RTK_PHYAR); 237 if (!(rval & RTK_PHYAR_BUSY)) 238 break; 239 DELAY(100); 240 } 241 242 if (i == RTK_TIMEOUT) { 243 printf("%s: PHY write reg %x <- %x failed\n", 244 device_xname(sc->sc_dev), reg, data); 245 } 246 } 247 248 static int 249 re_miibus_readreg(device_t dev, int phy, int reg) 250 { 251 struct rtk_softc *sc = device_private(dev); 252 uint16_t rval = 0; 253 uint16_t re8139_reg = 0; 254 int s; 255 256 s = splnet(); 257 258 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 259 rval = re_gmii_readreg(dev, phy, reg); 260 splx(s); 261 return rval; 262 } 263 264 /* Pretend the internal PHY is only at address 0 */ 265 if (phy) { 266 splx(s); 267 return 0; 268 } 269 switch (reg) { 270 case MII_BMCR: 271 re8139_reg = RTK_BMCR; 272 break; 273 case MII_BMSR: 274 re8139_reg = RTK_BMSR; 275 break; 276 case MII_ANAR: 277 re8139_reg = RTK_ANAR; 278 break; 279 case MII_ANER: 280 re8139_reg = RTK_ANER; 281 break; 282 case MII_ANLPAR: 283 re8139_reg = RTK_LPAR; 284 break; 285 case MII_PHYIDR1: 286 case MII_PHYIDR2: 287 splx(s); 288 return 0; 289 /* 290 * Allow the rlphy driver to read the media status 291 * register. If we have a link partner which does not 292 * support NWAY, this is the register which will tell 293 * us the results of parallel detection. 294 */ 295 case RTK_MEDIASTAT: 296 rval = CSR_READ_1(sc, RTK_MEDIASTAT); 297 splx(s); 298 return rval; 299 default: 300 printf("%s: bad phy register\n", device_xname(sc->sc_dev)); 301 splx(s); 302 return 0; 303 } 304 rval = CSR_READ_2(sc, re8139_reg); 305 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0 && re8139_reg == RTK_BMCR) { 306 /* 8139C+ has different bit layout. */ 307 rval &= ~(BMCR_LOOP | BMCR_ISO); 308 } 309 splx(s); 310 return rval; 311 } 312 313 static void 314 re_miibus_writereg(device_t dev, int phy, int reg, int data) 315 { 316 struct rtk_softc *sc = device_private(dev); 317 uint16_t re8139_reg = 0; 318 int s; 319 320 s = splnet(); 321 322 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 323 re_gmii_writereg(dev, phy, reg, data); 324 splx(s); 325 return; 326 } 327 328 /* Pretend the internal PHY is only at address 0 */ 329 if (phy) { 330 splx(s); 331 return; 332 } 333 switch (reg) { 334 case MII_BMCR: 335 re8139_reg = RTK_BMCR; 336 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) { 337 /* 8139C+ has different bit layout. */ 338 data &= ~(BMCR_LOOP | BMCR_ISO); 339 } 340 break; 341 case MII_BMSR: 342 re8139_reg = RTK_BMSR; 343 break; 344 case MII_ANAR: 345 re8139_reg = RTK_ANAR; 346 break; 347 case MII_ANER: 348 re8139_reg = RTK_ANER; 349 break; 350 case MII_ANLPAR: 351 re8139_reg = RTK_LPAR; 352 break; 353 case MII_PHYIDR1: 354 case MII_PHYIDR2: 355 splx(s); 356 return; 357 break; 358 default: 359 printf("%s: bad phy register\n", device_xname(sc->sc_dev)); 360 splx(s); 361 return; 362 } 363 CSR_WRITE_2(sc, re8139_reg, data); 364 splx(s); 365 return; 366 } 367 368 static void 369 re_miibus_statchg(device_t dev) 370 { 371 372 return; 373 } 374 375 static void 376 re_reset(struct rtk_softc *sc) 377 { 378 int i; 379 380 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 381 382 for (i = 0; i < RTK_TIMEOUT; i++) { 383 DELAY(10); 384 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0) 385 break; 386 } 387 if (i == RTK_TIMEOUT) 388 printf("%s: reset never completed!\n", 389 device_xname(sc->sc_dev)); 390 391 /* 392 * NB: Realtek-supplied FreeBSD driver does this only for MACFG_3, 393 * but also says "Rtl8169s sigle chip detected". 394 */ 395 if ((sc->sc_quirk & RTKQ_MACLDPS) != 0) 396 CSR_WRITE_1(sc, RTK_LDPS, 1); 397 398 } 399 400 /* 401 * The following routine is designed to test for a defect on some 402 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 403 * lines connected to the bus, however for a 32-bit only card, they 404 * should be pulled high. The result of this defect is that the 405 * NIC will not work right if you plug it into a 64-bit slot: DMA 406 * operations will be done with 64-bit transfers, which will fail 407 * because the 64-bit data lines aren't connected. 408 * 409 * There's no way to work around this (short of talking a soldering 410 * iron to the board), however we can detect it. The method we use 411 * here is to put the NIC into digital loopback mode, set the receiver 412 * to promiscuous mode, and then try to send a frame. We then compare 413 * the frame data we sent to what was received. If the data matches, 414 * then the NIC is working correctly, otherwise we know the user has 415 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 416 * slot. In the latter case, there's no way the NIC can work correctly, 417 * so we print out a message on the console and abort the device attach. 418 */ 419 420 int 421 re_diag(struct rtk_softc *sc) 422 { 423 struct ifnet *ifp = &sc->ethercom.ec_if; 424 struct mbuf *m0; 425 struct ether_header *eh; 426 struct re_rxsoft *rxs; 427 struct re_desc *cur_rx; 428 bus_dmamap_t dmamap; 429 uint16_t status; 430 uint32_t rxstat; 431 int total_len, i, s, error = 0; 432 static const uint8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 433 static const uint8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 434 435 /* Allocate a single mbuf */ 436 437 MGETHDR(m0, M_DONTWAIT, MT_DATA); 438 if (m0 == NULL) 439 return ENOBUFS; 440 441 /* 442 * Initialize the NIC in test mode. This sets the chip up 443 * so that it can send and receive frames, but performs the 444 * following special functions: 445 * - Puts receiver in promiscuous mode 446 * - Enables digital loopback mode 447 * - Leaves interrupts turned off 448 */ 449 450 ifp->if_flags |= IFF_PROMISC; 451 sc->re_testmode = 1; 452 re_init(ifp); 453 re_stop(ifp, 0); 454 DELAY(100000); 455 re_init(ifp); 456 457 /* Put some data in the mbuf */ 458 459 eh = mtod(m0, struct ether_header *); 460 memcpy(eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN); 461 memcpy(eh->ether_shost, (char *)&src, ETHER_ADDR_LEN); 462 eh->ether_type = htons(ETHERTYPE_IP); 463 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 464 465 /* 466 * Queue the packet, start transmission. 467 */ 468 469 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF); 470 s = splnet(); 471 IF_ENQUEUE(&ifp->if_snd, m0); 472 re_start(ifp); 473 splx(s); 474 m0 = NULL; 475 476 /* Wait for it to propagate through the chip */ 477 478 DELAY(100000); 479 for (i = 0; i < RTK_TIMEOUT; i++) { 480 status = CSR_READ_2(sc, RTK_ISR); 481 if ((status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) == 482 (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) 483 break; 484 DELAY(10); 485 } 486 if (i == RTK_TIMEOUT) { 487 aprint_error_dev(sc->sc_dev, 488 "diagnostic failed, failed to receive packet " 489 "in loopback mode\n"); 490 error = EIO; 491 goto done; 492 } 493 494 /* 495 * The packet should have been dumped into the first 496 * entry in the RX DMA ring. Grab it from there. 497 */ 498 499 rxs = &sc->re_ldata.re_rxsoft[0]; 500 dmamap = rxs->rxs_dmamap; 501 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 502 BUS_DMASYNC_POSTREAD); 503 bus_dmamap_unload(sc->sc_dmat, dmamap); 504 505 m0 = rxs->rxs_mbuf; 506 rxs->rxs_mbuf = NULL; 507 eh = mtod(m0, struct ether_header *); 508 509 RE_RXDESCSYNC(sc, 0, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 510 cur_rx = &sc->re_ldata.re_rx_list[0]; 511 rxstat = le32toh(cur_rx->re_cmdstat); 512 total_len = rxstat & sc->re_rxlenmask; 513 514 if (total_len != ETHER_MIN_LEN) { 515 aprint_error_dev(sc->sc_dev, 516 "diagnostic failed, received short packet\n"); 517 error = EIO; 518 goto done; 519 } 520 521 /* Test that the received packet data matches what we sent. */ 522 523 if (memcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 524 memcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 525 ntohs(eh->ether_type) != ETHERTYPE_IP) { 526 aprint_error_dev(sc->sc_dev, "WARNING, DMA FAILURE!\n" 527 "expected TX data: %s/%s/0x%x\n" 528 "received RX data: %s/%s/0x%x\n" 529 "You may have a defective 32-bit NIC plugged " 530 "into a 64-bit PCI slot.\n" 531 "Please re-install the NIC in a 32-bit slot " 532 "for proper operation.\n" 533 "Read the re(4) man page for more details.\n" , 534 ether_sprintf(dst), ether_sprintf(src), ETHERTYPE_IP, 535 ether_sprintf(eh->ether_dhost), 536 ether_sprintf(eh->ether_shost), ntohs(eh->ether_type)); 537 error = EIO; 538 } 539 540 done: 541 /* Turn interface off, release resources */ 542 543 sc->re_testmode = 0; 544 ifp->if_flags &= ~IFF_PROMISC; 545 re_stop(ifp, 0); 546 if (m0 != NULL) 547 m_freem(m0); 548 549 return error; 550 } 551 552 553 /* 554 * Attach the interface. Allocate softc structures, do ifmedia 555 * setup and ethernet/BPF attach. 556 */ 557 void 558 re_attach(struct rtk_softc *sc) 559 { 560 uint8_t eaddr[ETHER_ADDR_LEN]; 561 uint16_t val; 562 struct ifnet *ifp; 563 int error = 0, i, addr_len; 564 565 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 566 uint32_t hwrev; 567 568 /* Revision of 8169/8169S/8110s in bits 30..26, 23 */ 569 hwrev = CSR_READ_4(sc, RTK_TXCFG) & RTK_TXCFG_HWREV; 570 /* These rev numbers are taken from Realtek's driver */ 571 switch (hwrev) { 572 case RTK_HWREV_8169: 573 /* XXX not in the Realtek driver */ 574 sc->sc_rev = 1; 575 sc->sc_quirk |= RTKQ_8169NONS; 576 break; 577 case RTK_HWREV_8169S: 578 case RTK_HWREV_8110S: 579 sc->sc_rev = 3; 580 sc->sc_quirk |= RTKQ_MACLDPS; 581 break; 582 case RTK_HWREV_8169_8110SB: 583 sc->sc_rev = 4; 584 sc->sc_quirk |= RTKQ_MACLDPS; 585 break; 586 case RTK_HWREV_8169_8110SC: 587 sc->sc_rev = 5; 588 sc->sc_quirk |= RTKQ_MACLDPS; 589 break; 590 case RTK_HWREV_8101E: 591 sc->sc_rev = 11; 592 sc->sc_quirk |= RTKQ_NOJUMBO; 593 break; 594 case RTK_HWREV_8168_SPIN1: 595 sc->sc_rev = 21; 596 break; 597 case RTK_HWREV_8168_SPIN2: 598 sc->sc_rev = 22; 599 break; 600 case RTK_HWREV_8168_SPIN3: 601 sc->sc_rev = 23; 602 break; 603 case RTK_HWREV_8168C: 604 case RTK_HWREV_8168C_SPIN2: 605 case RTK_HWREV_8168CP: 606 case RTK_HWREV_8168D: 607 sc->sc_rev = 24; 608 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD; 609 /* 610 * From FreeBSD driver: 611 * 612 * These (8168/8111) controllers support jumbo frame 613 * but it seems that enabling it requires touching 614 * additional magic registers. Depending on MAC 615 * revisions some controllers need to disable 616 * checksum offload. So disable jumbo frame until 617 * I have better idea what it really requires to 618 * make it support. 619 * RTL8168C/CP : supports up to 6KB jumbo frame. 620 * RTL8111C/CP : supports up to 9KB jumbo frame. 621 */ 622 sc->sc_quirk |= RTKQ_NOJUMBO; 623 break; 624 case RTK_HWREV_8102E: 625 case RTK_HWREV_8102EL: 626 case RTK_HWREV_8102EL_SPIN2: 627 sc->sc_rev = 25; 628 sc->sc_quirk |= 629 RTKQ_DESCV2 | RTKQ_NOEECMD | RTKQ_NOJUMBO; 630 break; 631 case RTK_HWREV_8100E: 632 case RTK_HWREV_8100E_SPIN2: 633 /* XXX not in the Realtek driver */ 634 sc->sc_rev = 0; 635 sc->sc_quirk |= RTKQ_NOJUMBO; 636 break; 637 default: 638 aprint_normal_dev(sc->sc_dev, 639 "Unknown revision (0x%08x)\n", hwrev); 640 sc->sc_rev = 0; 641 /* assume the latest features */ 642 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD; 643 sc->sc_quirk |= RTKQ_NOJUMBO; 644 } 645 646 /* Set RX length mask */ 647 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 648 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8169; 649 } else { 650 sc->sc_quirk |= RTKQ_NOJUMBO; 651 652 /* Set RX length mask */ 653 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 654 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8139; 655 } 656 657 /* Reset the adapter. */ 658 re_reset(sc); 659 660 if ((sc->sc_quirk & RTKQ_NOEECMD) != 0) { 661 /* 662 * Get station address from ID registers. 663 */ 664 for (i = 0; i < ETHER_ADDR_LEN; i++) 665 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i); 666 } else { 667 /* 668 * Get station address from the EEPROM. 669 */ 670 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 671 addr_len = RTK_EEADDR_LEN1; 672 else 673 addr_len = RTK_EEADDR_LEN0; 674 675 /* 676 * Get station address from the EEPROM. 677 */ 678 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 679 val = rtk_read_eeprom(sc, RTK_EE_EADDR0 + i, addr_len); 680 eaddr[(i * 2) + 0] = val & 0xff; 681 eaddr[(i * 2) + 1] = val >> 8; 682 } 683 } 684 685 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 686 ether_sprintf(eaddr)); 687 688 if (sc->re_ldata.re_tx_desc_cnt > 689 PAGE_SIZE / sizeof(struct re_desc)) { 690 sc->re_ldata.re_tx_desc_cnt = 691 PAGE_SIZE / sizeof(struct re_desc); 692 } 693 694 aprint_verbose_dev(sc->sc_dev, "using %d tx descriptors\n", 695 sc->re_ldata.re_tx_desc_cnt); 696 KASSERT(RE_NEXT_TX_DESC(sc, RE_TX_DESC_CNT(sc) - 1) == 0); 697 698 /* Allocate DMA'able memory for the TX ring */ 699 if ((error = bus_dmamem_alloc(sc->sc_dmat, RE_TX_LIST_SZ(sc), 700 RE_RING_ALIGN, 0, &sc->re_ldata.re_tx_listseg, 1, 701 &sc->re_ldata.re_tx_listnseg, BUS_DMA_NOWAIT)) != 0) { 702 aprint_error_dev(sc->sc_dev, 703 "can't allocate tx listseg, error = %d\n", error); 704 goto fail_0; 705 } 706 707 /* Load the map for the TX ring. */ 708 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_tx_listseg, 709 sc->re_ldata.re_tx_listnseg, RE_TX_LIST_SZ(sc), 710 (void **)&sc->re_ldata.re_tx_list, 711 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) { 712 aprint_error_dev(sc->sc_dev, 713 "can't map tx list, error = %d\n", error); 714 goto fail_1; 715 } 716 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc)); 717 718 if ((error = bus_dmamap_create(sc->sc_dmat, RE_TX_LIST_SZ(sc), 1, 719 RE_TX_LIST_SZ(sc), 0, 0, 720 &sc->re_ldata.re_tx_list_map)) != 0) { 721 aprint_error_dev(sc->sc_dev, 722 "can't create tx list map, error = %d\n", error); 723 goto fail_2; 724 } 725 726 727 if ((error = bus_dmamap_load(sc->sc_dmat, 728 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list, 729 RE_TX_LIST_SZ(sc), NULL, BUS_DMA_NOWAIT)) != 0) { 730 aprint_error_dev(sc->sc_dev, 731 "can't load tx list, error = %d\n", error); 732 goto fail_3; 733 } 734 735 /* Create DMA maps for TX buffers */ 736 for (i = 0; i < RE_TX_QLEN; i++) { 737 error = bus_dmamap_create(sc->sc_dmat, 738 round_page(IP_MAXPACKET), 739 RE_TX_DESC_CNT(sc), RE_TDESC_CMD_FRAGLEN, 740 0, 0, &sc->re_ldata.re_txq[i].txq_dmamap); 741 if (error) { 742 aprint_error_dev(sc->sc_dev, 743 "can't create DMA map for TX\n"); 744 goto fail_4; 745 } 746 } 747 748 /* Allocate DMA'able memory for the RX ring */ 749 /* XXX see also a comment about RE_RX_DMAMEM_SZ in rtl81x9var.h */ 750 if ((error = bus_dmamem_alloc(sc->sc_dmat, 751 RE_RX_DMAMEM_SZ, RE_RING_ALIGN, 0, &sc->re_ldata.re_rx_listseg, 1, 752 &sc->re_ldata.re_rx_listnseg, BUS_DMA_NOWAIT)) != 0) { 753 aprint_error_dev(sc->sc_dev, 754 "can't allocate rx listseg, error = %d\n", error); 755 goto fail_4; 756 } 757 758 /* Load the map for the RX ring. */ 759 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_rx_listseg, 760 sc->re_ldata.re_rx_listnseg, RE_RX_DMAMEM_SZ, 761 (void **)&sc->re_ldata.re_rx_list, 762 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) { 763 aprint_error_dev(sc->sc_dev, 764 "can't map rx list, error = %d\n", error); 765 goto fail_5; 766 } 767 memset(sc->re_ldata.re_rx_list, 0, RE_RX_DMAMEM_SZ); 768 769 if ((error = bus_dmamap_create(sc->sc_dmat, 770 RE_RX_DMAMEM_SZ, 1, RE_RX_DMAMEM_SZ, 0, 0, 771 &sc->re_ldata.re_rx_list_map)) != 0) { 772 aprint_error_dev(sc->sc_dev, 773 "can't create rx list map, error = %d\n", error); 774 goto fail_6; 775 } 776 777 if ((error = bus_dmamap_load(sc->sc_dmat, 778 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list, 779 RE_RX_DMAMEM_SZ, NULL, BUS_DMA_NOWAIT)) != 0) { 780 aprint_error_dev(sc->sc_dev, 781 "can't load rx list, error = %d\n", error); 782 goto fail_7; 783 } 784 785 /* Create DMA maps for RX buffers */ 786 for (i = 0; i < RE_RX_DESC_CNT; i++) { 787 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 788 0, 0, &sc->re_ldata.re_rxsoft[i].rxs_dmamap); 789 if (error) { 790 aprint_error_dev(sc->sc_dev, 791 "can't create DMA map for RX\n"); 792 goto fail_8; 793 } 794 } 795 796 /* 797 * Record interface as attached. From here, we should not fail. 798 */ 799 sc->sc_flags |= RTK_ATTACHED; 800 801 ifp = &sc->ethercom.ec_if; 802 ifp->if_softc = sc; 803 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 804 ifp->if_mtu = ETHERMTU; 805 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 806 ifp->if_ioctl = re_ioctl; 807 sc->ethercom.ec_capabilities |= 808 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 809 ifp->if_start = re_start; 810 ifp->if_stop = re_stop; 811 812 /* 813 * IFCAP_CSUM_IPv4_Tx on re(4) is broken for small packets, 814 * so we have a workaround to handle the bug by padding 815 * such packets manually. 816 */ 817 ifp->if_capabilities |= 818 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 819 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 820 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 821 IFCAP_TSOv4; 822 823 /* 824 * XXX 825 * Still have no idea how to make TSO work on 8168C, 8168CP, 826 * 8102E, 8111C and 8111CP. 827 */ 828 if ((sc->sc_quirk & RTKQ_DESCV2) != 0) 829 ifp->if_capabilities &= ~IFCAP_TSOv4; 830 831 ifp->if_watchdog = re_watchdog; 832 ifp->if_init = re_init; 833 ifp->if_snd.ifq_maxlen = RE_IFQ_MAXLEN; 834 ifp->if_capenable = ifp->if_capabilities; 835 IFQ_SET_READY(&ifp->if_snd); 836 837 callout_init(&sc->rtk_tick_ch, 0); 838 839 /* Do MII setup */ 840 sc->mii.mii_ifp = ifp; 841 sc->mii.mii_readreg = re_miibus_readreg; 842 sc->mii.mii_writereg = re_miibus_writereg; 843 sc->mii.mii_statchg = re_miibus_statchg; 844 sc->ethercom.ec_mii = &sc->mii; 845 ifmedia_init(&sc->mii.mii_media, IFM_IMASK, ether_mediachange, 846 ether_mediastatus); 847 mii_attach(sc->sc_dev, &sc->mii, 0xffffffff, MII_PHY_ANY, 848 MII_OFFSET_ANY, 0); 849 ifmedia_set(&sc->mii.mii_media, IFM_ETHER | IFM_AUTO); 850 851 /* 852 * Call MI attach routine. 853 */ 854 if_attach(ifp); 855 ether_ifattach(ifp, eaddr); 856 857 return; 858 859 fail_8: 860 /* Destroy DMA maps for RX buffers. */ 861 for (i = 0; i < RE_RX_DESC_CNT; i++) 862 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL) 863 bus_dmamap_destroy(sc->sc_dmat, 864 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 865 866 /* Free DMA'able memory for the RX ring. */ 867 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 868 fail_7: 869 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 870 fail_6: 871 bus_dmamem_unmap(sc->sc_dmat, 872 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ); 873 fail_5: 874 bus_dmamem_free(sc->sc_dmat, 875 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg); 876 877 fail_4: 878 /* Destroy DMA maps for TX buffers. */ 879 for (i = 0; i < RE_TX_QLEN; i++) 880 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL) 881 bus_dmamap_destroy(sc->sc_dmat, 882 sc->re_ldata.re_txq[i].txq_dmamap); 883 884 /* Free DMA'able memory for the TX ring. */ 885 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 886 fail_3: 887 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 888 fail_2: 889 bus_dmamem_unmap(sc->sc_dmat, 890 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 891 fail_1: 892 bus_dmamem_free(sc->sc_dmat, 893 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg); 894 fail_0: 895 return; 896 } 897 898 899 /* 900 * re_activate: 901 * Handle device activation/deactivation requests. 902 */ 903 int 904 re_activate(device_t self, enum devact act) 905 { 906 struct rtk_softc *sc = device_private(self); 907 int s, error = 0; 908 909 s = splnet(); 910 switch (act) { 911 case DVACT_ACTIVATE: 912 error = EOPNOTSUPP; 913 break; 914 case DVACT_DEACTIVATE: 915 mii_activate(&sc->mii, act, MII_PHY_ANY, MII_OFFSET_ANY); 916 if_deactivate(&sc->ethercom.ec_if); 917 break; 918 } 919 splx(s); 920 921 return error; 922 } 923 924 /* 925 * re_detach: 926 * Detach a rtk interface. 927 */ 928 int 929 re_detach(struct rtk_softc *sc) 930 { 931 struct ifnet *ifp = &sc->ethercom.ec_if; 932 int i; 933 934 /* 935 * Succeed now if there isn't any work to do. 936 */ 937 if ((sc->sc_flags & RTK_ATTACHED) == 0) 938 return 0; 939 940 /* Unhook our tick handler. */ 941 callout_stop(&sc->rtk_tick_ch); 942 943 /* Detach all PHYs. */ 944 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 945 946 /* Delete all remaining media. */ 947 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY); 948 949 ether_ifdetach(ifp); 950 if_detach(ifp); 951 952 /* Destroy DMA maps for RX buffers. */ 953 for (i = 0; i < RE_RX_DESC_CNT; i++) 954 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL) 955 bus_dmamap_destroy(sc->sc_dmat, 956 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 957 958 /* Free DMA'able memory for the RX ring. */ 959 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 960 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 961 bus_dmamem_unmap(sc->sc_dmat, 962 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ); 963 bus_dmamem_free(sc->sc_dmat, 964 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg); 965 966 /* Destroy DMA maps for TX buffers. */ 967 for (i = 0; i < RE_TX_QLEN; i++) 968 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL) 969 bus_dmamap_destroy(sc->sc_dmat, 970 sc->re_ldata.re_txq[i].txq_dmamap); 971 972 /* Free DMA'able memory for the TX ring. */ 973 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 974 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 975 bus_dmamem_unmap(sc->sc_dmat, 976 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 977 bus_dmamem_free(sc->sc_dmat, 978 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg); 979 980 return 0; 981 } 982 983 /* 984 * re_enable: 985 * Enable the RTL81X9 chip. 986 */ 987 static int 988 re_enable(struct rtk_softc *sc) 989 { 990 991 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 992 if ((*sc->sc_enable)(sc) != 0) { 993 printf("%s: device enable failed\n", 994 device_xname(sc->sc_dev)); 995 return EIO; 996 } 997 sc->sc_flags |= RTK_ENABLED; 998 } 999 return 0; 1000 } 1001 1002 /* 1003 * re_disable: 1004 * Disable the RTL81X9 chip. 1005 */ 1006 static void 1007 re_disable(struct rtk_softc *sc) 1008 { 1009 1010 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 1011 (*sc->sc_disable)(sc); 1012 sc->sc_flags &= ~RTK_ENABLED; 1013 } 1014 } 1015 1016 static int 1017 re_newbuf(struct rtk_softc *sc, int idx, struct mbuf *m) 1018 { 1019 struct mbuf *n = NULL; 1020 bus_dmamap_t map; 1021 struct re_desc *d; 1022 struct re_rxsoft *rxs; 1023 uint32_t cmdstat; 1024 int error; 1025 1026 if (m == NULL) { 1027 MGETHDR(n, M_DONTWAIT, MT_DATA); 1028 if (n == NULL) 1029 return ENOBUFS; 1030 1031 MCLGET(n, M_DONTWAIT); 1032 if ((n->m_flags & M_EXT) == 0) { 1033 m_freem(n); 1034 return ENOBUFS; 1035 } 1036 m = n; 1037 } else 1038 m->m_data = m->m_ext.ext_buf; 1039 1040 /* 1041 * Initialize mbuf length fields and fixup 1042 * alignment so that the frame payload is 1043 * longword aligned. 1044 */ 1045 m->m_len = m->m_pkthdr.len = MCLBYTES - RE_ETHER_ALIGN; 1046 m->m_data += RE_ETHER_ALIGN; 1047 1048 rxs = &sc->re_ldata.re_rxsoft[idx]; 1049 map = rxs->rxs_dmamap; 1050 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1051 BUS_DMA_READ|BUS_DMA_NOWAIT); 1052 1053 if (error) 1054 goto out; 1055 1056 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1057 BUS_DMASYNC_PREREAD); 1058 1059 d = &sc->re_ldata.re_rx_list[idx]; 1060 #ifdef DIAGNOSTIC 1061 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1062 cmdstat = le32toh(d->re_cmdstat); 1063 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1064 if (cmdstat & RE_RDESC_STAT_OWN) { 1065 panic("%s: tried to map busy RX descriptor", 1066 device_xname(sc->sc_dev)); 1067 } 1068 #endif 1069 1070 rxs->rxs_mbuf = m; 1071 1072 d->re_vlanctl = 0; 1073 cmdstat = map->dm_segs[0].ds_len; 1074 if (idx == (RE_RX_DESC_CNT - 1)) 1075 cmdstat |= RE_RDESC_CMD_EOR; 1076 re_set_bufaddr(d, map->dm_segs[0].ds_addr); 1077 d->re_cmdstat = htole32(cmdstat); 1078 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1079 cmdstat |= RE_RDESC_CMD_OWN; 1080 d->re_cmdstat = htole32(cmdstat); 1081 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1082 1083 return 0; 1084 out: 1085 if (n != NULL) 1086 m_freem(n); 1087 return ENOMEM; 1088 } 1089 1090 static int 1091 re_tx_list_init(struct rtk_softc *sc) 1092 { 1093 int i; 1094 1095 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc)); 1096 for (i = 0; i < RE_TX_QLEN; i++) { 1097 sc->re_ldata.re_txq[i].txq_mbuf = NULL; 1098 } 1099 1100 bus_dmamap_sync(sc->sc_dmat, 1101 sc->re_ldata.re_tx_list_map, 0, 1102 sc->re_ldata.re_tx_list_map->dm_mapsize, 1103 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1104 sc->re_ldata.re_txq_prodidx = 0; 1105 sc->re_ldata.re_txq_considx = 0; 1106 sc->re_ldata.re_txq_free = RE_TX_QLEN; 1107 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT(sc); 1108 sc->re_ldata.re_tx_nextfree = 0; 1109 1110 return 0; 1111 } 1112 1113 static int 1114 re_rx_list_init(struct rtk_softc *sc) 1115 { 1116 int i; 1117 1118 memset(sc->re_ldata.re_rx_list, 0, RE_RX_LIST_SZ); 1119 1120 for (i = 0; i < RE_RX_DESC_CNT; i++) { 1121 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1122 return ENOBUFS; 1123 } 1124 1125 sc->re_ldata.re_rx_prodidx = 0; 1126 sc->re_head = sc->re_tail = NULL; 1127 1128 return 0; 1129 } 1130 1131 /* 1132 * RX handler for C+ and 8169. For the gigE chips, we support 1133 * the reception of jumbo frames that have been fragmented 1134 * across multiple 2K mbuf cluster buffers. 1135 */ 1136 static void 1137 re_rxeof(struct rtk_softc *sc) 1138 { 1139 struct mbuf *m; 1140 struct ifnet *ifp; 1141 int i, total_len; 1142 struct re_desc *cur_rx; 1143 struct re_rxsoft *rxs; 1144 uint32_t rxstat, rxvlan; 1145 1146 ifp = &sc->ethercom.ec_if; 1147 1148 for (i = sc->re_ldata.re_rx_prodidx;; i = RE_NEXT_RX_DESC(sc, i)) { 1149 cur_rx = &sc->re_ldata.re_rx_list[i]; 1150 RE_RXDESCSYNC(sc, i, 1151 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1152 rxstat = le32toh(cur_rx->re_cmdstat); 1153 rxvlan = le32toh(cur_rx->re_vlanctl); 1154 RE_RXDESCSYNC(sc, i, BUS_DMASYNC_PREREAD); 1155 if ((rxstat & RE_RDESC_STAT_OWN) != 0) { 1156 break; 1157 } 1158 total_len = rxstat & sc->re_rxlenmask; 1159 rxs = &sc->re_ldata.re_rxsoft[i]; 1160 m = rxs->rxs_mbuf; 1161 1162 /* Invalidate the RX mbuf and unload its map */ 1163 1164 bus_dmamap_sync(sc->sc_dmat, 1165 rxs->rxs_dmamap, 0, rxs->rxs_dmamap->dm_mapsize, 1166 BUS_DMASYNC_POSTREAD); 1167 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1168 1169 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1170 m->m_len = MCLBYTES - RE_ETHER_ALIGN; 1171 if (sc->re_head == NULL) 1172 sc->re_head = sc->re_tail = m; 1173 else { 1174 m->m_flags &= ~M_PKTHDR; 1175 sc->re_tail->m_next = m; 1176 sc->re_tail = m; 1177 } 1178 re_newbuf(sc, i, NULL); 1179 continue; 1180 } 1181 1182 /* 1183 * NOTE: for the 8139C+, the frame length field 1184 * is always 12 bits in size, but for the gigE chips, 1185 * it is 13 bits (since the max RX frame length is 16K). 1186 * Unfortunately, all 32 bits in the status word 1187 * were already used, so to make room for the extra 1188 * length bit, RealTek took out the 'frame alignment 1189 * error' bit and shifted the other status bits 1190 * over one slot. The OWN, EOR, FS and LS bits are 1191 * still in the same places. We have already extracted 1192 * the frame length and checked the OWN bit, so rather 1193 * than using an alternate bit mapping, we shift the 1194 * status bits one space to the right so we can evaluate 1195 * them using the 8169 status as though it was in the 1196 * same format as that of the 8139C+. 1197 */ 1198 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) 1199 rxstat >>= 1; 1200 1201 if (__predict_false((rxstat & RE_RDESC_STAT_RXERRSUM) != 0)) { 1202 #ifdef RE_DEBUG 1203 printf("%s: RX error (rxstat = 0x%08x)", 1204 device_xname(sc->sc_dev), rxstat); 1205 if (rxstat & RE_RDESC_STAT_FRALIGN) 1206 printf(", frame alignment error"); 1207 if (rxstat & RE_RDESC_STAT_BUFOFLOW) 1208 printf(", out of buffer space"); 1209 if (rxstat & RE_RDESC_STAT_FIFOOFLOW) 1210 printf(", FIFO overrun"); 1211 if (rxstat & RE_RDESC_STAT_GIANT) 1212 printf(", giant packet"); 1213 if (rxstat & RE_RDESC_STAT_RUNT) 1214 printf(", runt packet"); 1215 if (rxstat & RE_RDESC_STAT_CRCERR) 1216 printf(", CRC error"); 1217 printf("\n"); 1218 #endif 1219 ifp->if_ierrors++; 1220 /* 1221 * If this is part of a multi-fragment packet, 1222 * discard all the pieces. 1223 */ 1224 if (sc->re_head != NULL) { 1225 m_freem(sc->re_head); 1226 sc->re_head = sc->re_tail = NULL; 1227 } 1228 re_newbuf(sc, i, m); 1229 continue; 1230 } 1231 1232 /* 1233 * If allocating a replacement mbuf fails, 1234 * reload the current one. 1235 */ 1236 1237 if (__predict_false(re_newbuf(sc, i, NULL) != 0)) { 1238 ifp->if_ierrors++; 1239 if (sc->re_head != NULL) { 1240 m_freem(sc->re_head); 1241 sc->re_head = sc->re_tail = NULL; 1242 } 1243 re_newbuf(sc, i, m); 1244 continue; 1245 } 1246 1247 if (sc->re_head != NULL) { 1248 m->m_len = total_len % (MCLBYTES - RE_ETHER_ALIGN); 1249 /* 1250 * Special case: if there's 4 bytes or less 1251 * in this buffer, the mbuf can be discarded: 1252 * the last 4 bytes is the CRC, which we don't 1253 * care about anyway. 1254 */ 1255 if (m->m_len <= ETHER_CRC_LEN) { 1256 sc->re_tail->m_len -= 1257 (ETHER_CRC_LEN - m->m_len); 1258 m_freem(m); 1259 } else { 1260 m->m_len -= ETHER_CRC_LEN; 1261 m->m_flags &= ~M_PKTHDR; 1262 sc->re_tail->m_next = m; 1263 } 1264 m = sc->re_head; 1265 sc->re_head = sc->re_tail = NULL; 1266 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1267 } else 1268 m->m_pkthdr.len = m->m_len = 1269 (total_len - ETHER_CRC_LEN); 1270 1271 ifp->if_ipackets++; 1272 m->m_pkthdr.rcvif = ifp; 1273 1274 /* Do RX checksumming */ 1275 1276 /* Check IP header checksum */ 1277 if ((rxstat & RE_RDESC_STAT_PROTOID) != 0 && 1278 ((sc->sc_quirk & RTKQ_DESCV2) == 0 || 1279 (rxvlan & RE_RDESC_VLANCTL_IPV4) != 0)) { 1280 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1281 if (rxstat & RE_RDESC_STAT_IPSUMBAD) 1282 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1283 } 1284 1285 /* Check TCP/UDP checksum */ 1286 if (RE_TCPPKT(rxstat)) { 1287 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1288 if (rxstat & RE_RDESC_STAT_TCPSUMBAD) 1289 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1290 } else if (RE_UDPPKT(rxstat)) { 1291 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1292 if (rxstat & RE_RDESC_STAT_UDPSUMBAD) 1293 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1294 } 1295 1296 if (rxvlan & RE_RDESC_VLANCTL_TAG) { 1297 VLAN_INPUT_TAG(ifp, m, 1298 bswap16(rxvlan & RE_RDESC_VLANCTL_DATA), 1299 continue); 1300 } 1301 #if NBPFILTER > 0 1302 if (ifp->if_bpf) 1303 bpf_mtap(ifp->if_bpf, m); 1304 #endif 1305 (*ifp->if_input)(ifp, m); 1306 } 1307 1308 sc->re_ldata.re_rx_prodidx = i; 1309 } 1310 1311 static void 1312 re_txeof(struct rtk_softc *sc) 1313 { 1314 struct ifnet *ifp; 1315 struct re_txq *txq; 1316 uint32_t txstat; 1317 int idx, descidx; 1318 1319 ifp = &sc->ethercom.ec_if; 1320 1321 for (idx = sc->re_ldata.re_txq_considx; 1322 sc->re_ldata.re_txq_free < RE_TX_QLEN; 1323 idx = RE_NEXT_TXQ(sc, idx), sc->re_ldata.re_txq_free++) { 1324 txq = &sc->re_ldata.re_txq[idx]; 1325 KASSERT(txq->txq_mbuf != NULL); 1326 1327 descidx = txq->txq_descidx; 1328 RE_TXDESCSYNC(sc, descidx, 1329 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1330 txstat = 1331 le32toh(sc->re_ldata.re_tx_list[descidx].re_cmdstat); 1332 RE_TXDESCSYNC(sc, descidx, BUS_DMASYNC_PREREAD); 1333 KASSERT((txstat & RE_TDESC_CMD_EOF) != 0); 1334 if (txstat & RE_TDESC_CMD_OWN) { 1335 break; 1336 } 1337 1338 sc->re_ldata.re_tx_free += txq->txq_nsegs; 1339 KASSERT(sc->re_ldata.re_tx_free <= RE_TX_DESC_CNT(sc)); 1340 bus_dmamap_sync(sc->sc_dmat, txq->txq_dmamap, 1341 0, txq->txq_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1342 bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap); 1343 m_freem(txq->txq_mbuf); 1344 txq->txq_mbuf = NULL; 1345 1346 if (txstat & (RE_TDESC_STAT_EXCESSCOL | RE_TDESC_STAT_COLCNT)) 1347 ifp->if_collisions++; 1348 if (txstat & RE_TDESC_STAT_TXERRSUM) 1349 ifp->if_oerrors++; 1350 else 1351 ifp->if_opackets++; 1352 } 1353 1354 sc->re_ldata.re_txq_considx = idx; 1355 1356 if (sc->re_ldata.re_txq_free > RE_NTXDESC_RSVD) 1357 ifp->if_flags &= ~IFF_OACTIVE; 1358 1359 /* 1360 * If not all descriptors have been released reaped yet, 1361 * reload the timer so that we will eventually get another 1362 * interrupt that will cause us to re-enter this routine. 1363 * This is done in case the transmitter has gone idle. 1364 */ 1365 if (sc->re_ldata.re_txq_free < RE_TX_QLEN) { 1366 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1367 if ((sc->sc_quirk & RTKQ_PCIE) != 0) { 1368 /* 1369 * Some chips will ignore a second TX request 1370 * issued while an existing transmission is in 1371 * progress. If the transmitter goes idle but 1372 * there are still packets waiting to be sent, 1373 * we need to restart the channel here to flush 1374 * them out. This only seems to be required with 1375 * the PCIe devices. 1376 */ 1377 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START); 1378 } 1379 } else 1380 ifp->if_timer = 0; 1381 } 1382 1383 static void 1384 re_tick(void *arg) 1385 { 1386 struct rtk_softc *sc = arg; 1387 int s; 1388 1389 /*XXX: just return for 8169S/8110S with rev 2 or newer phy */ 1390 s = splnet(); 1391 1392 mii_tick(&sc->mii); 1393 splx(s); 1394 1395 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1396 } 1397 1398 int 1399 re_intr(void *arg) 1400 { 1401 struct rtk_softc *sc = arg; 1402 struct ifnet *ifp; 1403 uint16_t status; 1404 int handled = 0; 1405 1406 if (!device_has_power(sc->sc_dev)) 1407 return 0; 1408 1409 ifp = &sc->ethercom.ec_if; 1410 1411 if ((ifp->if_flags & IFF_UP) == 0) 1412 return 0; 1413 1414 for (;;) { 1415 1416 status = CSR_READ_2(sc, RTK_ISR); 1417 /* If the card has gone away the read returns 0xffff. */ 1418 if (status == 0xffff) 1419 break; 1420 if (status) { 1421 handled = 1; 1422 CSR_WRITE_2(sc, RTK_ISR, status); 1423 } 1424 1425 if ((status & RTK_INTRS_CPLUS) == 0) 1426 break; 1427 1428 if (status & (RTK_ISR_RX_OK | RTK_ISR_RX_ERR)) 1429 re_rxeof(sc); 1430 1431 if (status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_TX_ERR | 1432 RTK_ISR_TX_DESC_UNAVAIL)) 1433 re_txeof(sc); 1434 1435 if (status & RTK_ISR_SYSTEM_ERR) { 1436 re_init(ifp); 1437 } 1438 1439 if (status & RTK_ISR_LINKCHG) { 1440 callout_stop(&sc->rtk_tick_ch); 1441 re_tick(sc); 1442 } 1443 } 1444 1445 if (handled && !IFQ_IS_EMPTY(&ifp->if_snd)) 1446 re_start(ifp); 1447 1448 return handled; 1449 } 1450 1451 1452 1453 /* 1454 * Main transmit routine for C+ and gigE NICs. 1455 */ 1456 1457 static void 1458 re_start(struct ifnet *ifp) 1459 { 1460 struct rtk_softc *sc; 1461 struct mbuf *m; 1462 bus_dmamap_t map; 1463 struct re_txq *txq; 1464 struct re_desc *d; 1465 struct m_tag *mtag; 1466 uint32_t cmdstat, re_flags, vlanctl; 1467 int ofree, idx, error, nsegs, seg; 1468 int startdesc, curdesc, lastdesc; 1469 bool pad; 1470 1471 sc = ifp->if_softc; 1472 ofree = sc->re_ldata.re_txq_free; 1473 1474 for (idx = sc->re_ldata.re_txq_prodidx;; idx = RE_NEXT_TXQ(sc, idx)) { 1475 1476 IFQ_POLL(&ifp->if_snd, m); 1477 if (m == NULL) 1478 break; 1479 1480 if (sc->re_ldata.re_txq_free == 0 || 1481 sc->re_ldata.re_tx_free == 0) { 1482 /* no more free slots left */ 1483 ifp->if_flags |= IFF_OACTIVE; 1484 break; 1485 } 1486 1487 /* 1488 * Set up checksum offload. Note: checksum offload bits must 1489 * appear in all descriptors of a multi-descriptor transmit 1490 * attempt. (This is according to testing done with an 8169 1491 * chip. I'm not sure if this is a requirement or a bug.) 1492 */ 1493 1494 vlanctl = 0; 1495 if ((m->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0) { 1496 uint32_t segsz = m->m_pkthdr.segsz; 1497 1498 re_flags = RE_TDESC_CMD_LGSEND | 1499 (segsz << RE_TDESC_CMD_MSSVAL_SHIFT); 1500 } else { 1501 /* 1502 * set RE_TDESC_CMD_IPCSUM if any checksum offloading 1503 * is requested. otherwise, RE_TDESC_CMD_TCPCSUM/ 1504 * RE_TDESC_CMD_UDPCSUM doesn't make effects. 1505 */ 1506 re_flags = 0; 1507 if ((m->m_pkthdr.csum_flags & 1508 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1509 != 0) { 1510 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) { 1511 re_flags |= RE_TDESC_CMD_IPCSUM; 1512 if (m->m_pkthdr.csum_flags & 1513 M_CSUM_TCPv4) { 1514 re_flags |= 1515 RE_TDESC_CMD_TCPCSUM; 1516 } else if (m->m_pkthdr.csum_flags & 1517 M_CSUM_UDPv4) { 1518 re_flags |= 1519 RE_TDESC_CMD_UDPCSUM; 1520 } 1521 } else { 1522 vlanctl |= RE_TDESC_VLANCTL_IPCSUM; 1523 if (m->m_pkthdr.csum_flags & 1524 M_CSUM_TCPv4) { 1525 vlanctl |= 1526 RE_TDESC_VLANCTL_TCPCSUM; 1527 } else if (m->m_pkthdr.csum_flags & 1528 M_CSUM_UDPv4) { 1529 vlanctl |= 1530 RE_TDESC_VLANCTL_UDPCSUM; 1531 } 1532 } 1533 } 1534 } 1535 1536 txq = &sc->re_ldata.re_txq[idx]; 1537 map = txq->txq_dmamap; 1538 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1539 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1540 1541 if (__predict_false(error)) { 1542 /* XXX try to defrag if EFBIG? */ 1543 printf("%s: can't map mbuf (error %d)\n", 1544 device_xname(sc->sc_dev), error); 1545 1546 IFQ_DEQUEUE(&ifp->if_snd, m); 1547 m_freem(m); 1548 ifp->if_oerrors++; 1549 continue; 1550 } 1551 1552 nsegs = map->dm_nsegs; 1553 pad = false; 1554 if (__predict_false(m->m_pkthdr.len <= RE_IP4CSUMTX_PADLEN && 1555 (re_flags & RE_TDESC_CMD_IPCSUM) != 0 && 1556 (sc->sc_quirk & RTKQ_DESCV2) == 0)) { 1557 pad = true; 1558 nsegs++; 1559 } 1560 1561 if (nsegs > sc->re_ldata.re_tx_free) { 1562 /* 1563 * Not enough free descriptors to transmit this packet. 1564 */ 1565 ifp->if_flags |= IFF_OACTIVE; 1566 bus_dmamap_unload(sc->sc_dmat, map); 1567 break; 1568 } 1569 1570 IFQ_DEQUEUE(&ifp->if_snd, m); 1571 1572 /* 1573 * Make sure that the caches are synchronized before we 1574 * ask the chip to start DMA for the packet data. 1575 */ 1576 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1577 BUS_DMASYNC_PREWRITE); 1578 1579 /* 1580 * Set up hardware VLAN tagging. Note: vlan tag info must 1581 * appear in all descriptors of a multi-descriptor 1582 * transmission attempt. 1583 */ 1584 if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m)) != NULL) 1585 vlanctl |= bswap16(VLAN_TAG_VALUE(mtag)) | 1586 RE_TDESC_VLANCTL_TAG; 1587 1588 /* 1589 * Map the segment array into descriptors. 1590 * Note that we set the start-of-frame and 1591 * end-of-frame markers for either TX or RX, 1592 * but they really only have meaning in the TX case. 1593 * (In the RX case, it's the chip that tells us 1594 * where packets begin and end.) 1595 * We also keep track of the end of the ring 1596 * and set the end-of-ring bits as needed, 1597 * and we set the ownership bits in all except 1598 * the very first descriptor. (The caller will 1599 * set this descriptor later when it start 1600 * transmission or reception.) 1601 */ 1602 curdesc = startdesc = sc->re_ldata.re_tx_nextfree; 1603 lastdesc = -1; 1604 for (seg = 0; seg < map->dm_nsegs; 1605 seg++, curdesc = RE_NEXT_TX_DESC(sc, curdesc)) { 1606 d = &sc->re_ldata.re_tx_list[curdesc]; 1607 #ifdef DIAGNOSTIC 1608 RE_TXDESCSYNC(sc, curdesc, 1609 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1610 cmdstat = le32toh(d->re_cmdstat); 1611 RE_TXDESCSYNC(sc, curdesc, BUS_DMASYNC_PREREAD); 1612 if (cmdstat & RE_TDESC_STAT_OWN) { 1613 panic("%s: tried to map busy TX descriptor", 1614 device_xname(sc->sc_dev)); 1615 } 1616 #endif 1617 1618 d->re_vlanctl = htole32(vlanctl); 1619 re_set_bufaddr(d, map->dm_segs[seg].ds_addr); 1620 cmdstat = re_flags | map->dm_segs[seg].ds_len; 1621 if (seg == 0) 1622 cmdstat |= RE_TDESC_CMD_SOF; 1623 else 1624 cmdstat |= RE_TDESC_CMD_OWN; 1625 if (curdesc == (RE_TX_DESC_CNT(sc) - 1)) 1626 cmdstat |= RE_TDESC_CMD_EOR; 1627 if (seg == nsegs - 1) { 1628 cmdstat |= RE_TDESC_CMD_EOF; 1629 lastdesc = curdesc; 1630 } 1631 d->re_cmdstat = htole32(cmdstat); 1632 RE_TXDESCSYNC(sc, curdesc, 1633 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1634 } 1635 if (__predict_false(pad)) { 1636 bus_addr_t paddaddr; 1637 1638 d = &sc->re_ldata.re_tx_list[curdesc]; 1639 d->re_vlanctl = htole32(vlanctl); 1640 paddaddr = RE_TXPADDADDR(sc); 1641 re_set_bufaddr(d, paddaddr); 1642 cmdstat = re_flags | 1643 RE_TDESC_CMD_OWN | RE_TDESC_CMD_EOF | 1644 (RE_IP4CSUMTX_PADLEN + 1 - m->m_pkthdr.len); 1645 if (curdesc == (RE_TX_DESC_CNT(sc) - 1)) 1646 cmdstat |= RE_TDESC_CMD_EOR; 1647 d->re_cmdstat = htole32(cmdstat); 1648 RE_TXDESCSYNC(sc, curdesc, 1649 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1650 lastdesc = curdesc; 1651 curdesc = RE_NEXT_TX_DESC(sc, curdesc); 1652 } 1653 KASSERT(lastdesc != -1); 1654 1655 /* Transfer ownership of packet to the chip. */ 1656 1657 sc->re_ldata.re_tx_list[startdesc].re_cmdstat |= 1658 htole32(RE_TDESC_CMD_OWN); 1659 RE_TXDESCSYNC(sc, startdesc, 1660 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1661 1662 /* update info of TX queue and descriptors */ 1663 txq->txq_mbuf = m; 1664 txq->txq_descidx = lastdesc; 1665 txq->txq_nsegs = nsegs; 1666 1667 sc->re_ldata.re_txq_free--; 1668 sc->re_ldata.re_tx_free -= nsegs; 1669 sc->re_ldata.re_tx_nextfree = curdesc; 1670 1671 #if NBPFILTER > 0 1672 /* 1673 * If there's a BPF listener, bounce a copy of this frame 1674 * to him. 1675 */ 1676 if (ifp->if_bpf) 1677 bpf_mtap(ifp->if_bpf, m); 1678 #endif 1679 } 1680 1681 if (sc->re_ldata.re_txq_free < ofree) { 1682 /* 1683 * TX packets are enqueued. 1684 */ 1685 sc->re_ldata.re_txq_prodidx = idx; 1686 1687 /* 1688 * Start the transmitter to poll. 1689 * 1690 * RealTek put the TX poll request register in a different 1691 * location on the 8169 gigE chip. I don't know why. 1692 */ 1693 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) 1694 CSR_WRITE_1(sc, RTK_TXSTART, RTK_TXSTART_START); 1695 else 1696 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START); 1697 1698 /* 1699 * Use the countdown timer for interrupt moderation. 1700 * 'TX done' interrupts are disabled. Instead, we reset the 1701 * countdown timer, which will begin counting until it hits 1702 * the value in the TIMERINT register, and then trigger an 1703 * interrupt. Each time we write to the TIMERCNT register, 1704 * the timer count is reset to 0. 1705 */ 1706 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1707 1708 /* 1709 * Set a timeout in case the chip goes out to lunch. 1710 */ 1711 ifp->if_timer = 5; 1712 } 1713 } 1714 1715 static int 1716 re_init(struct ifnet *ifp) 1717 { 1718 struct rtk_softc *sc = ifp->if_softc; 1719 const uint8_t *enaddr; 1720 uint32_t rxcfg = 0; 1721 uint32_t reg; 1722 int error; 1723 1724 if ((error = re_enable(sc)) != 0) 1725 goto out; 1726 1727 /* 1728 * Cancel pending I/O and free all RX/TX buffers. 1729 */ 1730 re_stop(ifp, 0); 1731 1732 re_reset(sc); 1733 1734 /* 1735 * Enable C+ RX and TX mode, as well as VLAN stripping and 1736 * RX checksum offload. We must configure the C+ register 1737 * before all others. 1738 */ 1739 reg = 0; 1740 1741 /* 1742 * XXX: Realtek docs say bits 0 and 1 are reserved, for 8169S/8110S. 1743 * FreeBSD drivers set these bits anyway (for 8139C+?). 1744 * So far, it works. 1745 */ 1746 1747 /* 1748 * XXX: For old 8169 set bit 14. 1749 * For 8169S/8110S and above, do not set bit 14. 1750 */ 1751 if ((sc->sc_quirk & RTKQ_8169NONS) != 0) 1752 reg |= (0x1 << 14) | RTK_CPLUSCMD_PCI_MRW; 1753 1754 if (1) {/* not for 8169S ? */ 1755 reg |= 1756 RTK_CPLUSCMD_VLANSTRIP | 1757 (ifp->if_capenable & 1758 (IFCAP_CSUM_IPv4_Rx | IFCAP_CSUM_TCPv4_Rx | 1759 IFCAP_CSUM_UDPv4_Rx) ? 1760 RTK_CPLUSCMD_RXCSUM_ENB : 0); 1761 } 1762 1763 CSR_WRITE_2(sc, RTK_CPLUS_CMD, 1764 reg | RTK_CPLUSCMD_RXENB | RTK_CPLUSCMD_TXENB); 1765 1766 /* XXX: from Realtek-supplied Linux driver. Wholly undocumented. */ 1767 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) 1768 CSR_WRITE_2(sc, RTK_IM, 0x0000); 1769 1770 DELAY(10000); 1771 1772 /* 1773 * Init our MAC address. Even though the chipset 1774 * documentation doesn't mention it, we need to enter "Config 1775 * register write enable" mode to modify the ID registers. 1776 */ 1777 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_WRITECFG); 1778 enaddr = CLLADDR(ifp->if_sadl); 1779 reg = enaddr[0] | (enaddr[1] << 8) | 1780 (enaddr[2] << 16) | (enaddr[3] << 24); 1781 CSR_WRITE_4(sc, RTK_IDR0, reg); 1782 reg = enaddr[4] | (enaddr[5] << 8); 1783 CSR_WRITE_4(sc, RTK_IDR4, reg); 1784 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 1785 1786 /* 1787 * For C+ mode, initialize the RX descriptors and mbufs. 1788 */ 1789 re_rx_list_init(sc); 1790 re_tx_list_init(sc); 1791 1792 /* 1793 * Load the addresses of the RX and TX lists into the chip. 1794 */ 1795 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_HI, 1796 RE_ADDR_HI(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr)); 1797 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_LO, 1798 RE_ADDR_LO(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr)); 1799 1800 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_HI, 1801 RE_ADDR_HI(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr)); 1802 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_LO, 1803 RE_ADDR_LO(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr)); 1804 1805 /* 1806 * Enable transmit and receive. 1807 */ 1808 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1809 1810 /* 1811 * Set the initial TX and RX configuration. 1812 */ 1813 if (sc->re_testmode && (sc->sc_quirk & RTKQ_8169NONS) != 0) { 1814 /* test mode is needed only for old 8169 */ 1815 CSR_WRITE_4(sc, RTK_TXCFG, 1816 RE_TXCFG_CONFIG | RTK_LOOPTEST_ON); 1817 } else 1818 CSR_WRITE_4(sc, RTK_TXCFG, RE_TXCFG_CONFIG); 1819 1820 CSR_WRITE_1(sc, RTK_EARLY_TX_THRESH, 16); 1821 1822 CSR_WRITE_4(sc, RTK_RXCFG, RE_RXCFG_CONFIG); 1823 1824 /* Set the individual bit to receive frames for this host only. */ 1825 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 1826 rxcfg |= RTK_RXCFG_RX_INDIV; 1827 1828 /* If we want promiscuous mode, set the allframes bit. */ 1829 if (ifp->if_flags & IFF_PROMISC) 1830 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 1831 else 1832 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 1833 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1834 1835 /* 1836 * Set capture broadcast bit to capture broadcast frames. 1837 */ 1838 if (ifp->if_flags & IFF_BROADCAST) 1839 rxcfg |= RTK_RXCFG_RX_BROAD; 1840 else 1841 rxcfg &= ~RTK_RXCFG_RX_BROAD; 1842 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1843 1844 /* 1845 * Program the multicast filter, if necessary. 1846 */ 1847 rtk_setmulti(sc); 1848 1849 /* 1850 * Enable interrupts. 1851 */ 1852 if (sc->re_testmode) 1853 CSR_WRITE_2(sc, RTK_IMR, 0); 1854 else 1855 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS); 1856 1857 /* Start RX/TX process. */ 1858 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 1859 #ifdef notdef 1860 /* Enable receiver and transmitter. */ 1861 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1862 #endif 1863 1864 /* 1865 * Initialize the timer interrupt register so that 1866 * a timer interrupt will be generated once the timer 1867 * reaches a certain number of ticks. The timer is 1868 * reloaded on each transmit. This gives us TX interrupt 1869 * moderation, which dramatically improves TX frame rate. 1870 */ 1871 1872 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) 1873 CSR_WRITE_4(sc, RTK_TIMERINT, 0x400); 1874 else { 1875 CSR_WRITE_4(sc, RTK_TIMERINT_8169, 0x800); 1876 1877 /* 1878 * For 8169 gigE NICs, set the max allowed RX packet 1879 * size so we can receive jumbo frames. 1880 */ 1881 CSR_WRITE_2(sc, RTK_MAXRXPKTLEN, 16383); 1882 } 1883 1884 if (sc->re_testmode) 1885 return 0; 1886 1887 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD); 1888 1889 ifp->if_flags |= IFF_RUNNING; 1890 ifp->if_flags &= ~IFF_OACTIVE; 1891 1892 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1893 1894 out: 1895 if (error) { 1896 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1897 ifp->if_timer = 0; 1898 printf("%s: interface not running\n", 1899 device_xname(sc->sc_dev)); 1900 } 1901 1902 return error; 1903 } 1904 1905 static int 1906 re_ioctl(struct ifnet *ifp, u_long command, void *data) 1907 { 1908 struct rtk_softc *sc = ifp->if_softc; 1909 struct ifreq *ifr = data; 1910 int s, error = 0; 1911 1912 s = splnet(); 1913 1914 switch (command) { 1915 case SIOCSIFMTU: 1916 /* 1917 * Disable jumbo frames if it's not supported. 1918 */ 1919 if ((sc->sc_quirk & RTKQ_NOJUMBO) != 0 && 1920 ifr->ifr_mtu > ETHERMTU) { 1921 error = EINVAL; 1922 break; 1923 } 1924 1925 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO) 1926 error = EINVAL; 1927 else if ((error = ifioctl_common(ifp, command, data)) == 1928 ENETRESET) 1929 error = 0; 1930 break; 1931 default: 1932 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1933 break; 1934 1935 error = 0; 1936 1937 if (command == SIOCSIFCAP) 1938 error = (*ifp->if_init)(ifp); 1939 else if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1940 ; 1941 else if (ifp->if_flags & IFF_RUNNING) 1942 rtk_setmulti(sc); 1943 break; 1944 } 1945 1946 splx(s); 1947 1948 return error; 1949 } 1950 1951 static void 1952 re_watchdog(struct ifnet *ifp) 1953 { 1954 struct rtk_softc *sc; 1955 int s; 1956 1957 sc = ifp->if_softc; 1958 s = splnet(); 1959 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1960 ifp->if_oerrors++; 1961 1962 re_txeof(sc); 1963 re_rxeof(sc); 1964 1965 re_init(ifp); 1966 1967 splx(s); 1968 } 1969 1970 /* 1971 * Stop the adapter and free any mbufs allocated to the 1972 * RX and TX lists. 1973 */ 1974 static void 1975 re_stop(struct ifnet *ifp, int disable) 1976 { 1977 int i; 1978 struct rtk_softc *sc = ifp->if_softc; 1979 1980 callout_stop(&sc->rtk_tick_ch); 1981 1982 mii_down(&sc->mii); 1983 1984 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 1985 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1986 1987 if (sc->re_head != NULL) { 1988 m_freem(sc->re_head); 1989 sc->re_head = sc->re_tail = NULL; 1990 } 1991 1992 /* Free the TX list buffers. */ 1993 for (i = 0; i < RE_TX_QLEN; i++) { 1994 if (sc->re_ldata.re_txq[i].txq_mbuf != NULL) { 1995 bus_dmamap_unload(sc->sc_dmat, 1996 sc->re_ldata.re_txq[i].txq_dmamap); 1997 m_freem(sc->re_ldata.re_txq[i].txq_mbuf); 1998 sc->re_ldata.re_txq[i].txq_mbuf = NULL; 1999 } 2000 } 2001 2002 /* Free the RX list buffers. */ 2003 for (i = 0; i < RE_RX_DESC_CNT; i++) { 2004 if (sc->re_ldata.re_rxsoft[i].rxs_mbuf != NULL) { 2005 bus_dmamap_unload(sc->sc_dmat, 2006 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 2007 m_freem(sc->re_ldata.re_rxsoft[i].rxs_mbuf); 2008 sc->re_ldata.re_rxsoft[i].rxs_mbuf = NULL; 2009 } 2010 } 2011 2012 if (disable) 2013 re_disable(sc); 2014 2015 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2016 ifp->if_timer = 0; 2017 } 2018