1 /* $NetBSD: rtl8169.c,v 1.139 2013/05/10 14:55:08 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998-2003 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.139 2013/05/10 14:55:08 tsutsui Exp $"); 37 /* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */ 38 39 /* 40 * RealTek 8139C+/8169/8169S/8168/8110S PCI NIC driver 41 * 42 * Written by Bill Paul <wpaul@windriver.com> 43 * Senior Networking Software Engineer 44 * Wind River Systems 45 */ 46 47 /* 48 * This driver is designed to support RealTek's next generation of 49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 50 * six devices in this family: the RTL8139C+, the RTL8169, the RTL8169S, 51 * RTL8110S, the RTL8168 and the RTL8111. 52 * 53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 54 * with the older 8139 family, however it also supports a special 55 * C+ mode of operation that provides several new performance enhancing 56 * features. These include: 57 * 58 * o Descriptor based DMA mechanism. Each descriptor represents 59 * a single packet fragment. Data buffers may be aligned on 60 * any byte boundary. 61 * 62 * o 64-bit DMA 63 * 64 * o TCP/IP checksum offload for both RX and TX 65 * 66 * o High and normal priority transmit DMA rings 67 * 68 * o VLAN tag insertion and extraction 69 * 70 * o TCP large send (segmentation offload) 71 * 72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 73 * programming API is fairly straightforward. The RX filtering, EEPROM 74 * access and PHY access is the same as it is on the older 8139 series 75 * chips. 76 * 77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 78 * same programming API and feature set as the 8139C+ with the following 79 * differences and additions: 80 * 81 * o 1000Mbps mode 82 * 83 * o Jumbo frames 84 * 85 * o GMII and TBI ports/registers for interfacing with copper 86 * or fiber PHYs 87 * 88 * o RX and TX DMA rings can have up to 1024 descriptors 89 * (the 8139C+ allows a maximum of 64) 90 * 91 * o Slight differences in register layout from the 8139C+ 92 * 93 * The TX start and timer interrupt registers are at different locations 94 * on the 8169 than they are on the 8139C+. Also, the status word in the 95 * RX descriptor has a slightly different bit layout. The 8169 does not 96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 97 * copper gigE PHY. 98 * 99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 100 * (the 'S' stands for 'single-chip'). These devices have the same 101 * programming API as the older 8169, but also have some vendor-specific 102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 104 * 105 * This driver takes advantage of the RX and TX checksum offload and 106 * VLAN tag insertion/extraction features. It also implements TX 107 * interrupt moderation using the timer interrupt registers, which 108 * significantly reduces TX interrupt load. There is also support 109 * for jumbo frames, however the 8169/8169S/8110S can not transmit 110 * jumbo frames larger than 7.5K, so the max MTU possible with this 111 * driver is 7500 bytes. 112 */ 113 114 115 #include <sys/param.h> 116 #include <sys/endian.h> 117 #include <sys/systm.h> 118 #include <sys/sockio.h> 119 #include <sys/mbuf.h> 120 #include <sys/malloc.h> 121 #include <sys/kernel.h> 122 #include <sys/socket.h> 123 #include <sys/device.h> 124 125 #include <net/if.h> 126 #include <net/if_arp.h> 127 #include <net/if_dl.h> 128 #include <net/if_ether.h> 129 #include <net/if_media.h> 130 #include <net/if_vlanvar.h> 131 132 #include <netinet/in_systm.h> /* XXX for IP_MAXPACKET */ 133 #include <netinet/in.h> /* XXX for IP_MAXPACKET */ 134 #include <netinet/ip.h> /* XXX for IP_MAXPACKET */ 135 136 #include <net/bpf.h> 137 #include <sys/rnd.h> 138 139 #include <sys/bus.h> 140 141 #include <dev/mii/mii.h> 142 #include <dev/mii/miivar.h> 143 144 #include <dev/ic/rtl81x9reg.h> 145 #include <dev/ic/rtl81x9var.h> 146 147 #include <dev/ic/rtl8169var.h> 148 149 static inline void re_set_bufaddr(struct re_desc *, bus_addr_t); 150 151 static int re_newbuf(struct rtk_softc *, int, struct mbuf *); 152 static int re_rx_list_init(struct rtk_softc *); 153 static int re_tx_list_init(struct rtk_softc *); 154 static void re_rxeof(struct rtk_softc *); 155 static void re_txeof(struct rtk_softc *); 156 static void re_tick(void *); 157 static void re_start(struct ifnet *); 158 static int re_ioctl(struct ifnet *, u_long, void *); 159 static int re_init(struct ifnet *); 160 static void re_stop(struct ifnet *, int); 161 static void re_watchdog(struct ifnet *); 162 163 static int re_enable(struct rtk_softc *); 164 static void re_disable(struct rtk_softc *); 165 166 static int re_gmii_readreg(device_t, int, int); 167 static void re_gmii_writereg(device_t, int, int, int); 168 169 static int re_miibus_readreg(device_t, int, int); 170 static void re_miibus_writereg(device_t, int, int, int); 171 static void re_miibus_statchg(struct ifnet *); 172 173 static void re_reset(struct rtk_softc *); 174 175 static inline void 176 re_set_bufaddr(struct re_desc *d, bus_addr_t addr) 177 { 178 179 d->re_bufaddr_lo = htole32((uint32_t)addr); 180 if (sizeof(bus_addr_t) == sizeof(uint64_t)) 181 d->re_bufaddr_hi = htole32((uint64_t)addr >> 32); 182 else 183 d->re_bufaddr_hi = 0; 184 } 185 186 static int 187 re_gmii_readreg(device_t dev, int phy, int reg) 188 { 189 struct rtk_softc *sc = device_private(dev); 190 uint32_t rval; 191 int i; 192 193 if (phy != 7) 194 return 0; 195 196 /* Let the rgephy driver read the GMEDIASTAT register */ 197 198 if (reg == RTK_GMEDIASTAT) { 199 rval = CSR_READ_1(sc, RTK_GMEDIASTAT); 200 return rval; 201 } 202 203 CSR_WRITE_4(sc, RTK_PHYAR, reg << 16); 204 DELAY(1000); 205 206 for (i = 0; i < RTK_TIMEOUT; i++) { 207 rval = CSR_READ_4(sc, RTK_PHYAR); 208 if (rval & RTK_PHYAR_BUSY) 209 break; 210 DELAY(100); 211 } 212 213 if (i == RTK_TIMEOUT) { 214 printf("%s: PHY read failed\n", device_xname(sc->sc_dev)); 215 return 0; 216 } 217 218 return rval & RTK_PHYAR_PHYDATA; 219 } 220 221 static void 222 re_gmii_writereg(device_t dev, int phy, int reg, int data) 223 { 224 struct rtk_softc *sc = device_private(dev); 225 uint32_t rval; 226 int i; 227 228 CSR_WRITE_4(sc, RTK_PHYAR, (reg << 16) | 229 (data & RTK_PHYAR_PHYDATA) | RTK_PHYAR_BUSY); 230 DELAY(1000); 231 232 for (i = 0; i < RTK_TIMEOUT; i++) { 233 rval = CSR_READ_4(sc, RTK_PHYAR); 234 if (!(rval & RTK_PHYAR_BUSY)) 235 break; 236 DELAY(100); 237 } 238 239 if (i == RTK_TIMEOUT) { 240 printf("%s: PHY write reg %x <- %x failed\n", 241 device_xname(sc->sc_dev), reg, data); 242 } 243 } 244 245 static int 246 re_miibus_readreg(device_t dev, int phy, int reg) 247 { 248 struct rtk_softc *sc = device_private(dev); 249 uint16_t rval = 0; 250 uint16_t re8139_reg = 0; 251 int s; 252 253 s = splnet(); 254 255 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 256 rval = re_gmii_readreg(dev, phy, reg); 257 splx(s); 258 return rval; 259 } 260 261 /* Pretend the internal PHY is only at address 0 */ 262 if (phy) { 263 splx(s); 264 return 0; 265 } 266 switch (reg) { 267 case MII_BMCR: 268 re8139_reg = RTK_BMCR; 269 break; 270 case MII_BMSR: 271 re8139_reg = RTK_BMSR; 272 break; 273 case MII_ANAR: 274 re8139_reg = RTK_ANAR; 275 break; 276 case MII_ANER: 277 re8139_reg = RTK_ANER; 278 break; 279 case MII_ANLPAR: 280 re8139_reg = RTK_LPAR; 281 break; 282 case MII_PHYIDR1: 283 case MII_PHYIDR2: 284 splx(s); 285 return 0; 286 /* 287 * Allow the rlphy driver to read the media status 288 * register. If we have a link partner which does not 289 * support NWAY, this is the register which will tell 290 * us the results of parallel detection. 291 */ 292 case RTK_MEDIASTAT: 293 rval = CSR_READ_1(sc, RTK_MEDIASTAT); 294 splx(s); 295 return rval; 296 default: 297 printf("%s: bad phy register\n", device_xname(sc->sc_dev)); 298 splx(s); 299 return 0; 300 } 301 rval = CSR_READ_2(sc, re8139_reg); 302 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0 && re8139_reg == RTK_BMCR) { 303 /* 8139C+ has different bit layout. */ 304 rval &= ~(BMCR_LOOP | BMCR_ISO); 305 } 306 splx(s); 307 return rval; 308 } 309 310 static void 311 re_miibus_writereg(device_t dev, int phy, int reg, int data) 312 { 313 struct rtk_softc *sc = device_private(dev); 314 uint16_t re8139_reg = 0; 315 int s; 316 317 s = splnet(); 318 319 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 320 re_gmii_writereg(dev, phy, reg, data); 321 splx(s); 322 return; 323 } 324 325 /* Pretend the internal PHY is only at address 0 */ 326 if (phy) { 327 splx(s); 328 return; 329 } 330 switch (reg) { 331 case MII_BMCR: 332 re8139_reg = RTK_BMCR; 333 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) { 334 /* 8139C+ has different bit layout. */ 335 data &= ~(BMCR_LOOP | BMCR_ISO); 336 } 337 break; 338 case MII_BMSR: 339 re8139_reg = RTK_BMSR; 340 break; 341 case MII_ANAR: 342 re8139_reg = RTK_ANAR; 343 break; 344 case MII_ANER: 345 re8139_reg = RTK_ANER; 346 break; 347 case MII_ANLPAR: 348 re8139_reg = RTK_LPAR; 349 break; 350 case MII_PHYIDR1: 351 case MII_PHYIDR2: 352 splx(s); 353 return; 354 break; 355 default: 356 printf("%s: bad phy register\n", device_xname(sc->sc_dev)); 357 splx(s); 358 return; 359 } 360 CSR_WRITE_2(sc, re8139_reg, data); 361 splx(s); 362 return; 363 } 364 365 static void 366 re_miibus_statchg(struct ifnet *ifp) 367 { 368 369 return; 370 } 371 372 static void 373 re_reset(struct rtk_softc *sc) 374 { 375 int i; 376 377 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 378 379 for (i = 0; i < RTK_TIMEOUT; i++) { 380 DELAY(10); 381 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0) 382 break; 383 } 384 if (i == RTK_TIMEOUT) 385 printf("%s: reset never completed!\n", 386 device_xname(sc->sc_dev)); 387 388 /* 389 * NB: Realtek-supplied FreeBSD driver does this only for MACFG_3, 390 * but also says "Rtl8169s sigle chip detected". 391 */ 392 if ((sc->sc_quirk & RTKQ_MACLDPS) != 0) 393 CSR_WRITE_1(sc, RTK_LDPS, 1); 394 395 } 396 397 /* 398 * The following routine is designed to test for a defect on some 399 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 400 * lines connected to the bus, however for a 32-bit only card, they 401 * should be pulled high. The result of this defect is that the 402 * NIC will not work right if you plug it into a 64-bit slot: DMA 403 * operations will be done with 64-bit transfers, which will fail 404 * because the 64-bit data lines aren't connected. 405 * 406 * There's no way to work around this (short of talking a soldering 407 * iron to the board), however we can detect it. The method we use 408 * here is to put the NIC into digital loopback mode, set the receiver 409 * to promiscuous mode, and then try to send a frame. We then compare 410 * the frame data we sent to what was received. If the data matches, 411 * then the NIC is working correctly, otherwise we know the user has 412 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 413 * slot. In the latter case, there's no way the NIC can work correctly, 414 * so we print out a message on the console and abort the device attach. 415 */ 416 417 int 418 re_diag(struct rtk_softc *sc) 419 { 420 struct ifnet *ifp = &sc->ethercom.ec_if; 421 struct mbuf *m0; 422 struct ether_header *eh; 423 struct re_rxsoft *rxs; 424 struct re_desc *cur_rx; 425 bus_dmamap_t dmamap; 426 uint16_t status; 427 uint32_t rxstat; 428 int total_len, i, s, error = 0; 429 static const uint8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 430 static const uint8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 431 432 /* Allocate a single mbuf */ 433 434 MGETHDR(m0, M_DONTWAIT, MT_DATA); 435 if (m0 == NULL) 436 return ENOBUFS; 437 438 /* 439 * Initialize the NIC in test mode. This sets the chip up 440 * so that it can send and receive frames, but performs the 441 * following special functions: 442 * - Puts receiver in promiscuous mode 443 * - Enables digital loopback mode 444 * - Leaves interrupts turned off 445 */ 446 447 ifp->if_flags |= IFF_PROMISC; 448 sc->re_testmode = 1; 449 re_init(ifp); 450 re_stop(ifp, 0); 451 DELAY(100000); 452 re_init(ifp); 453 454 /* Put some data in the mbuf */ 455 456 eh = mtod(m0, struct ether_header *); 457 memcpy(eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN); 458 memcpy(eh->ether_shost, (char *)&src, ETHER_ADDR_LEN); 459 eh->ether_type = htons(ETHERTYPE_IP); 460 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 461 462 /* 463 * Queue the packet, start transmission. 464 */ 465 466 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF); 467 s = splnet(); 468 IF_ENQUEUE(&ifp->if_snd, m0); 469 re_start(ifp); 470 splx(s); 471 m0 = NULL; 472 473 /* Wait for it to propagate through the chip */ 474 475 DELAY(100000); 476 for (i = 0; i < RTK_TIMEOUT; i++) { 477 status = CSR_READ_2(sc, RTK_ISR); 478 if ((status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) == 479 (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) 480 break; 481 DELAY(10); 482 } 483 if (i == RTK_TIMEOUT) { 484 aprint_error_dev(sc->sc_dev, 485 "diagnostic failed, failed to receive packet " 486 "in loopback mode\n"); 487 error = EIO; 488 goto done; 489 } 490 491 /* 492 * The packet should have been dumped into the first 493 * entry in the RX DMA ring. Grab it from there. 494 */ 495 496 rxs = &sc->re_ldata.re_rxsoft[0]; 497 dmamap = rxs->rxs_dmamap; 498 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 499 BUS_DMASYNC_POSTREAD); 500 bus_dmamap_unload(sc->sc_dmat, dmamap); 501 502 m0 = rxs->rxs_mbuf; 503 rxs->rxs_mbuf = NULL; 504 eh = mtod(m0, struct ether_header *); 505 506 RE_RXDESCSYNC(sc, 0, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 507 cur_rx = &sc->re_ldata.re_rx_list[0]; 508 rxstat = le32toh(cur_rx->re_cmdstat); 509 total_len = rxstat & sc->re_rxlenmask; 510 511 if (total_len != ETHER_MIN_LEN) { 512 aprint_error_dev(sc->sc_dev, 513 "diagnostic failed, received short packet\n"); 514 error = EIO; 515 goto done; 516 } 517 518 /* Test that the received packet data matches what we sent. */ 519 520 if (memcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 521 memcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 522 ntohs(eh->ether_type) != ETHERTYPE_IP) { 523 aprint_error_dev(sc->sc_dev, "WARNING, DMA FAILURE!\n" 524 "expected TX data: %s/%s/0x%x\n" 525 "received RX data: %s/%s/0x%x\n" 526 "You may have a defective 32-bit NIC plugged " 527 "into a 64-bit PCI slot.\n" 528 "Please re-install the NIC in a 32-bit slot " 529 "for proper operation.\n" 530 "Read the re(4) man page for more details.\n" , 531 ether_sprintf(dst), ether_sprintf(src), ETHERTYPE_IP, 532 ether_sprintf(eh->ether_dhost), 533 ether_sprintf(eh->ether_shost), ntohs(eh->ether_type)); 534 error = EIO; 535 } 536 537 done: 538 /* Turn interface off, release resources */ 539 540 sc->re_testmode = 0; 541 ifp->if_flags &= ~IFF_PROMISC; 542 re_stop(ifp, 0); 543 if (m0 != NULL) 544 m_freem(m0); 545 546 return error; 547 } 548 549 550 /* 551 * Attach the interface. Allocate softc structures, do ifmedia 552 * setup and ethernet/BPF attach. 553 */ 554 void 555 re_attach(struct rtk_softc *sc) 556 { 557 uint8_t eaddr[ETHER_ADDR_LEN]; 558 struct ifnet *ifp; 559 int error = 0, i; 560 561 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 562 uint32_t hwrev; 563 564 /* Revision of 8169/8169S/8110s in bits 30..26, 23 */ 565 hwrev = CSR_READ_4(sc, RTK_TXCFG) & RTK_TXCFG_HWREV; 566 switch (hwrev) { 567 case RTK_HWREV_8169: 568 sc->sc_quirk |= RTKQ_8169NONS; 569 break; 570 case RTK_HWREV_8169S: 571 case RTK_HWREV_8110S: 572 case RTK_HWREV_8169_8110SB: 573 case RTK_HWREV_8169_8110SBL: 574 case RTK_HWREV_8169_8110SC: 575 sc->sc_quirk |= RTKQ_MACLDPS; 576 break; 577 case RTK_HWREV_8168_SPIN1: 578 case RTK_HWREV_8168_SPIN2: 579 case RTK_HWREV_8168_SPIN3: 580 sc->sc_quirk |= RTKQ_MACSTAT; 581 break; 582 case RTK_HWREV_8168C: 583 case RTK_HWREV_8168C_SPIN2: 584 case RTK_HWREV_8168CP: 585 case RTK_HWREV_8168D: 586 case RTK_HWREV_8168DP: 587 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 588 RTKQ_MACSTAT | RTKQ_CMDSTOP; 589 /* 590 * From FreeBSD driver: 591 * 592 * These (8168/8111) controllers support jumbo frame 593 * but it seems that enabling it requires touching 594 * additional magic registers. Depending on MAC 595 * revisions some controllers need to disable 596 * checksum offload. So disable jumbo frame until 597 * I have better idea what it really requires to 598 * make it support. 599 * RTL8168C/CP : supports up to 6KB jumbo frame. 600 * RTL8111C/CP : supports up to 9KB jumbo frame. 601 */ 602 sc->sc_quirk |= RTKQ_NOJUMBO; 603 break; 604 case RTK_HWREV_8168E: 605 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 606 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_PHYWAKE_PM | 607 RTKQ_NOJUMBO; 608 break; 609 case RTK_HWREV_8168E_VL: 610 case RTK_HWREV_8168F: 611 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 612 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO; 613 break; 614 case RTK_HWREV_8100E: 615 case RTK_HWREV_8100E_SPIN2: 616 case RTK_HWREV_8101E: 617 sc->sc_quirk |= RTKQ_NOJUMBO; 618 break; 619 case RTK_HWREV_8102E: 620 case RTK_HWREV_8102EL: 621 case RTK_HWREV_8103E: 622 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD | 623 RTKQ_MACSTAT | RTKQ_CMDSTOP | RTKQ_NOJUMBO; 624 break; 625 default: 626 aprint_normal_dev(sc->sc_dev, 627 "Unknown revision (0x%08x)\n", hwrev); 628 /* assume the latest features */ 629 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD; 630 sc->sc_quirk |= RTKQ_NOJUMBO; 631 } 632 633 /* Set RX length mask */ 634 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 635 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8169; 636 } else { 637 sc->sc_quirk |= RTKQ_NOJUMBO; 638 639 /* Set RX length mask */ 640 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 641 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8139; 642 } 643 644 /* Reset the adapter. */ 645 re_reset(sc); 646 647 /* 648 * RTL81x9 chips automatically read EEPROM to init MAC address, 649 * and some NAS override its MAC address per own configuration, 650 * so no need to explicitely read EEPROM and set ID registers. 651 */ 652 #ifdef RE_USE_EECMD 653 if ((sc->sc_quirk & RTKQ_NOEECMD) != 0) { 654 /* 655 * Get station address from ID registers. 656 */ 657 for (i = 0; i < ETHER_ADDR_LEN; i++) 658 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i); 659 } else { 660 uint16_t val; 661 int addr_len; 662 663 /* 664 * Get station address from the EEPROM. 665 */ 666 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 667 addr_len = RTK_EEADDR_LEN1; 668 else 669 addr_len = RTK_EEADDR_LEN0; 670 671 /* 672 * Get station address from the EEPROM. 673 */ 674 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 675 val = rtk_read_eeprom(sc, RTK_EE_EADDR0 + i, addr_len); 676 eaddr[(i * 2) + 0] = val & 0xff; 677 eaddr[(i * 2) + 1] = val >> 8; 678 } 679 } 680 #else 681 /* 682 * Get station address from ID registers. 683 */ 684 for (i = 0; i < ETHER_ADDR_LEN; i++) 685 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i); 686 #endif 687 688 /* Take PHY out of power down mode. */ 689 if ((sc->sc_quirk & RTKQ_PHYWAKE_PM) != 0) 690 CSR_WRITE_1(sc, RTK_PMCH, CSR_READ_1(sc, RTK_PMCH) | 0x80); 691 692 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 693 ether_sprintf(eaddr)); 694 695 if (sc->re_ldata.re_tx_desc_cnt > 696 PAGE_SIZE / sizeof(struct re_desc)) { 697 sc->re_ldata.re_tx_desc_cnt = 698 PAGE_SIZE / sizeof(struct re_desc); 699 } 700 701 aprint_verbose_dev(sc->sc_dev, "using %d tx descriptors\n", 702 sc->re_ldata.re_tx_desc_cnt); 703 KASSERT(RE_NEXT_TX_DESC(sc, RE_TX_DESC_CNT(sc) - 1) == 0); 704 705 /* Allocate DMA'able memory for the TX ring */ 706 if ((error = bus_dmamem_alloc(sc->sc_dmat, RE_TX_LIST_SZ(sc), 707 RE_RING_ALIGN, 0, &sc->re_ldata.re_tx_listseg, 1, 708 &sc->re_ldata.re_tx_listnseg, BUS_DMA_NOWAIT)) != 0) { 709 aprint_error_dev(sc->sc_dev, 710 "can't allocate tx listseg, error = %d\n", error); 711 goto fail_0; 712 } 713 714 /* Load the map for the TX ring. */ 715 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_tx_listseg, 716 sc->re_ldata.re_tx_listnseg, RE_TX_LIST_SZ(sc), 717 (void **)&sc->re_ldata.re_tx_list, 718 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) { 719 aprint_error_dev(sc->sc_dev, 720 "can't map tx list, error = %d\n", error); 721 goto fail_1; 722 } 723 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc)); 724 725 if ((error = bus_dmamap_create(sc->sc_dmat, RE_TX_LIST_SZ(sc), 1, 726 RE_TX_LIST_SZ(sc), 0, 0, 727 &sc->re_ldata.re_tx_list_map)) != 0) { 728 aprint_error_dev(sc->sc_dev, 729 "can't create tx list map, error = %d\n", error); 730 goto fail_2; 731 } 732 733 734 if ((error = bus_dmamap_load(sc->sc_dmat, 735 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list, 736 RE_TX_LIST_SZ(sc), NULL, BUS_DMA_NOWAIT)) != 0) { 737 aprint_error_dev(sc->sc_dev, 738 "can't load tx list, error = %d\n", error); 739 goto fail_3; 740 } 741 742 /* Create DMA maps for TX buffers */ 743 for (i = 0; i < RE_TX_QLEN; i++) { 744 error = bus_dmamap_create(sc->sc_dmat, 745 round_page(IP_MAXPACKET), 746 RE_TX_DESC_CNT(sc), RE_TDESC_CMD_FRAGLEN, 747 0, 0, &sc->re_ldata.re_txq[i].txq_dmamap); 748 if (error) { 749 aprint_error_dev(sc->sc_dev, 750 "can't create DMA map for TX\n"); 751 goto fail_4; 752 } 753 } 754 755 /* Allocate DMA'able memory for the RX ring */ 756 /* XXX see also a comment about RE_RX_DMAMEM_SZ in rtl81x9var.h */ 757 if ((error = bus_dmamem_alloc(sc->sc_dmat, 758 RE_RX_DMAMEM_SZ, RE_RING_ALIGN, 0, &sc->re_ldata.re_rx_listseg, 1, 759 &sc->re_ldata.re_rx_listnseg, BUS_DMA_NOWAIT)) != 0) { 760 aprint_error_dev(sc->sc_dev, 761 "can't allocate rx listseg, error = %d\n", error); 762 goto fail_4; 763 } 764 765 /* Load the map for the RX ring. */ 766 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_rx_listseg, 767 sc->re_ldata.re_rx_listnseg, RE_RX_DMAMEM_SZ, 768 (void **)&sc->re_ldata.re_rx_list, 769 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) { 770 aprint_error_dev(sc->sc_dev, 771 "can't map rx list, error = %d\n", error); 772 goto fail_5; 773 } 774 memset(sc->re_ldata.re_rx_list, 0, RE_RX_DMAMEM_SZ); 775 776 if ((error = bus_dmamap_create(sc->sc_dmat, 777 RE_RX_DMAMEM_SZ, 1, RE_RX_DMAMEM_SZ, 0, 0, 778 &sc->re_ldata.re_rx_list_map)) != 0) { 779 aprint_error_dev(sc->sc_dev, 780 "can't create rx list map, error = %d\n", error); 781 goto fail_6; 782 } 783 784 if ((error = bus_dmamap_load(sc->sc_dmat, 785 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list, 786 RE_RX_DMAMEM_SZ, NULL, BUS_DMA_NOWAIT)) != 0) { 787 aprint_error_dev(sc->sc_dev, 788 "can't load rx list, error = %d\n", error); 789 goto fail_7; 790 } 791 792 /* Create DMA maps for RX buffers */ 793 for (i = 0; i < RE_RX_DESC_CNT; i++) { 794 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 795 0, 0, &sc->re_ldata.re_rxsoft[i].rxs_dmamap); 796 if (error) { 797 aprint_error_dev(sc->sc_dev, 798 "can't create DMA map for RX\n"); 799 goto fail_8; 800 } 801 } 802 803 /* 804 * Record interface as attached. From here, we should not fail. 805 */ 806 sc->sc_flags |= RTK_ATTACHED; 807 808 ifp = &sc->ethercom.ec_if; 809 ifp->if_softc = sc; 810 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 811 ifp->if_mtu = ETHERMTU; 812 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 813 ifp->if_ioctl = re_ioctl; 814 sc->ethercom.ec_capabilities |= 815 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 816 ifp->if_start = re_start; 817 ifp->if_stop = re_stop; 818 819 /* 820 * IFCAP_CSUM_IPv4_Tx on re(4) is broken for small packets, 821 * so we have a workaround to handle the bug by padding 822 * such packets manually. 823 */ 824 ifp->if_capabilities |= 825 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 826 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 827 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 828 IFCAP_TSOv4; 829 830 /* 831 * XXX 832 * Still have no idea how to make TSO work on 8168C, 8168CP, 833 * 8102E, 8111C and 8111CP. 834 */ 835 if ((sc->sc_quirk & RTKQ_DESCV2) != 0) 836 ifp->if_capabilities &= ~IFCAP_TSOv4; 837 838 ifp->if_watchdog = re_watchdog; 839 ifp->if_init = re_init; 840 ifp->if_snd.ifq_maxlen = RE_IFQ_MAXLEN; 841 ifp->if_capenable = ifp->if_capabilities; 842 IFQ_SET_READY(&ifp->if_snd); 843 844 callout_init(&sc->rtk_tick_ch, 0); 845 846 /* Do MII setup */ 847 sc->mii.mii_ifp = ifp; 848 sc->mii.mii_readreg = re_miibus_readreg; 849 sc->mii.mii_writereg = re_miibus_writereg; 850 sc->mii.mii_statchg = re_miibus_statchg; 851 sc->ethercom.ec_mii = &sc->mii; 852 ifmedia_init(&sc->mii.mii_media, IFM_IMASK, ether_mediachange, 853 ether_mediastatus); 854 mii_attach(sc->sc_dev, &sc->mii, 0xffffffff, MII_PHY_ANY, 855 MII_OFFSET_ANY, 0); 856 ifmedia_set(&sc->mii.mii_media, IFM_ETHER | IFM_AUTO); 857 858 /* 859 * Call MI attach routine. 860 */ 861 if_attach(ifp); 862 ether_ifattach(ifp, eaddr); 863 864 rnd_attach_source(&sc->rnd_source, device_xname(sc->sc_dev), 865 RND_TYPE_NET, 0); 866 867 if (pmf_device_register(sc->sc_dev, NULL, NULL)) 868 pmf_class_network_register(sc->sc_dev, ifp); 869 else 870 aprint_error_dev(sc->sc_dev, 871 "couldn't establish power handler\n"); 872 873 return; 874 875 fail_8: 876 /* Destroy DMA maps for RX buffers. */ 877 for (i = 0; i < RE_RX_DESC_CNT; i++) 878 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL) 879 bus_dmamap_destroy(sc->sc_dmat, 880 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 881 882 /* Free DMA'able memory for the RX ring. */ 883 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 884 fail_7: 885 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 886 fail_6: 887 bus_dmamem_unmap(sc->sc_dmat, 888 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ); 889 fail_5: 890 bus_dmamem_free(sc->sc_dmat, 891 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg); 892 893 fail_4: 894 /* Destroy DMA maps for TX buffers. */ 895 for (i = 0; i < RE_TX_QLEN; i++) 896 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL) 897 bus_dmamap_destroy(sc->sc_dmat, 898 sc->re_ldata.re_txq[i].txq_dmamap); 899 900 /* Free DMA'able memory for the TX ring. */ 901 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 902 fail_3: 903 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 904 fail_2: 905 bus_dmamem_unmap(sc->sc_dmat, 906 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 907 fail_1: 908 bus_dmamem_free(sc->sc_dmat, 909 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg); 910 fail_0: 911 return; 912 } 913 914 915 /* 916 * re_activate: 917 * Handle device activation/deactivation requests. 918 */ 919 int 920 re_activate(device_t self, enum devact act) 921 { 922 struct rtk_softc *sc = device_private(self); 923 924 switch (act) { 925 case DVACT_DEACTIVATE: 926 if_deactivate(&sc->ethercom.ec_if); 927 return 0; 928 default: 929 return EOPNOTSUPP; 930 } 931 } 932 933 /* 934 * re_detach: 935 * Detach a rtk interface. 936 */ 937 int 938 re_detach(struct rtk_softc *sc) 939 { 940 struct ifnet *ifp = &sc->ethercom.ec_if; 941 int i; 942 943 /* 944 * Succeed now if there isn't any work to do. 945 */ 946 if ((sc->sc_flags & RTK_ATTACHED) == 0) 947 return 0; 948 949 /* Unhook our tick handler. */ 950 callout_stop(&sc->rtk_tick_ch); 951 952 /* Detach all PHYs. */ 953 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 954 955 /* Delete all remaining media. */ 956 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY); 957 958 rnd_detach_source(&sc->rnd_source); 959 ether_ifdetach(ifp); 960 if_detach(ifp); 961 962 /* Destroy DMA maps for RX buffers. */ 963 for (i = 0; i < RE_RX_DESC_CNT; i++) 964 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL) 965 bus_dmamap_destroy(sc->sc_dmat, 966 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 967 968 /* Free DMA'able memory for the RX ring. */ 969 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 970 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 971 bus_dmamem_unmap(sc->sc_dmat, 972 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ); 973 bus_dmamem_free(sc->sc_dmat, 974 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg); 975 976 /* Destroy DMA maps for TX buffers. */ 977 for (i = 0; i < RE_TX_QLEN; i++) 978 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL) 979 bus_dmamap_destroy(sc->sc_dmat, 980 sc->re_ldata.re_txq[i].txq_dmamap); 981 982 /* Free DMA'able memory for the TX ring. */ 983 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 984 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 985 bus_dmamem_unmap(sc->sc_dmat, 986 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 987 bus_dmamem_free(sc->sc_dmat, 988 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg); 989 990 pmf_device_deregister(sc->sc_dev); 991 992 /* we don't want to run again */ 993 sc->sc_flags &= ~RTK_ATTACHED; 994 995 return 0; 996 } 997 998 /* 999 * re_enable: 1000 * Enable the RTL81X9 chip. 1001 */ 1002 static int 1003 re_enable(struct rtk_softc *sc) 1004 { 1005 1006 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 1007 if ((*sc->sc_enable)(sc) != 0) { 1008 printf("%s: device enable failed\n", 1009 device_xname(sc->sc_dev)); 1010 return EIO; 1011 } 1012 sc->sc_flags |= RTK_ENABLED; 1013 } 1014 return 0; 1015 } 1016 1017 /* 1018 * re_disable: 1019 * Disable the RTL81X9 chip. 1020 */ 1021 static void 1022 re_disable(struct rtk_softc *sc) 1023 { 1024 1025 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 1026 (*sc->sc_disable)(sc); 1027 sc->sc_flags &= ~RTK_ENABLED; 1028 } 1029 } 1030 1031 static int 1032 re_newbuf(struct rtk_softc *sc, int idx, struct mbuf *m) 1033 { 1034 struct mbuf *n = NULL; 1035 bus_dmamap_t map; 1036 struct re_desc *d; 1037 struct re_rxsoft *rxs; 1038 uint32_t cmdstat; 1039 int error; 1040 1041 if (m == NULL) { 1042 MGETHDR(n, M_DONTWAIT, MT_DATA); 1043 if (n == NULL) 1044 return ENOBUFS; 1045 1046 MCLGET(n, M_DONTWAIT); 1047 if ((n->m_flags & M_EXT) == 0) { 1048 m_freem(n); 1049 return ENOBUFS; 1050 } 1051 m = n; 1052 } else 1053 m->m_data = m->m_ext.ext_buf; 1054 1055 /* 1056 * Initialize mbuf length fields and fixup 1057 * alignment so that the frame payload is 1058 * longword aligned. 1059 */ 1060 m->m_len = m->m_pkthdr.len = MCLBYTES - RE_ETHER_ALIGN; 1061 m->m_data += RE_ETHER_ALIGN; 1062 1063 rxs = &sc->re_ldata.re_rxsoft[idx]; 1064 map = rxs->rxs_dmamap; 1065 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1066 BUS_DMA_READ|BUS_DMA_NOWAIT); 1067 1068 if (error) 1069 goto out; 1070 1071 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1072 BUS_DMASYNC_PREREAD); 1073 1074 d = &sc->re_ldata.re_rx_list[idx]; 1075 #ifdef DIAGNOSTIC 1076 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1077 cmdstat = le32toh(d->re_cmdstat); 1078 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1079 if (cmdstat & RE_RDESC_STAT_OWN) { 1080 panic("%s: tried to map busy RX descriptor", 1081 device_xname(sc->sc_dev)); 1082 } 1083 #endif 1084 1085 rxs->rxs_mbuf = m; 1086 1087 d->re_vlanctl = 0; 1088 cmdstat = map->dm_segs[0].ds_len; 1089 if (idx == (RE_RX_DESC_CNT - 1)) 1090 cmdstat |= RE_RDESC_CMD_EOR; 1091 re_set_bufaddr(d, map->dm_segs[0].ds_addr); 1092 d->re_cmdstat = htole32(cmdstat); 1093 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1094 cmdstat |= RE_RDESC_CMD_OWN; 1095 d->re_cmdstat = htole32(cmdstat); 1096 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1097 1098 return 0; 1099 out: 1100 if (n != NULL) 1101 m_freem(n); 1102 return ENOMEM; 1103 } 1104 1105 static int 1106 re_tx_list_init(struct rtk_softc *sc) 1107 { 1108 int i; 1109 1110 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc)); 1111 for (i = 0; i < RE_TX_QLEN; i++) { 1112 sc->re_ldata.re_txq[i].txq_mbuf = NULL; 1113 } 1114 1115 bus_dmamap_sync(sc->sc_dmat, 1116 sc->re_ldata.re_tx_list_map, 0, 1117 sc->re_ldata.re_tx_list_map->dm_mapsize, 1118 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1119 sc->re_ldata.re_txq_prodidx = 0; 1120 sc->re_ldata.re_txq_considx = 0; 1121 sc->re_ldata.re_txq_free = RE_TX_QLEN; 1122 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT(sc); 1123 sc->re_ldata.re_tx_nextfree = 0; 1124 1125 return 0; 1126 } 1127 1128 static int 1129 re_rx_list_init(struct rtk_softc *sc) 1130 { 1131 int i; 1132 1133 memset(sc->re_ldata.re_rx_list, 0, RE_RX_LIST_SZ); 1134 1135 for (i = 0; i < RE_RX_DESC_CNT; i++) { 1136 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1137 return ENOBUFS; 1138 } 1139 1140 sc->re_ldata.re_rx_prodidx = 0; 1141 sc->re_head = sc->re_tail = NULL; 1142 1143 return 0; 1144 } 1145 1146 /* 1147 * RX handler for C+ and 8169. For the gigE chips, we support 1148 * the reception of jumbo frames that have been fragmented 1149 * across multiple 2K mbuf cluster buffers. 1150 */ 1151 static void 1152 re_rxeof(struct rtk_softc *sc) 1153 { 1154 struct mbuf *m; 1155 struct ifnet *ifp; 1156 int i, total_len; 1157 struct re_desc *cur_rx; 1158 struct re_rxsoft *rxs; 1159 uint32_t rxstat, rxvlan; 1160 1161 ifp = &sc->ethercom.ec_if; 1162 1163 for (i = sc->re_ldata.re_rx_prodidx;; i = RE_NEXT_RX_DESC(sc, i)) { 1164 cur_rx = &sc->re_ldata.re_rx_list[i]; 1165 RE_RXDESCSYNC(sc, i, 1166 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1167 rxstat = le32toh(cur_rx->re_cmdstat); 1168 rxvlan = le32toh(cur_rx->re_vlanctl); 1169 RE_RXDESCSYNC(sc, i, BUS_DMASYNC_PREREAD); 1170 if ((rxstat & RE_RDESC_STAT_OWN) != 0) { 1171 break; 1172 } 1173 total_len = rxstat & sc->re_rxlenmask; 1174 rxs = &sc->re_ldata.re_rxsoft[i]; 1175 m = rxs->rxs_mbuf; 1176 1177 /* Invalidate the RX mbuf and unload its map */ 1178 1179 bus_dmamap_sync(sc->sc_dmat, 1180 rxs->rxs_dmamap, 0, rxs->rxs_dmamap->dm_mapsize, 1181 BUS_DMASYNC_POSTREAD); 1182 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1183 1184 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1185 m->m_len = MCLBYTES - RE_ETHER_ALIGN; 1186 if (sc->re_head == NULL) 1187 sc->re_head = sc->re_tail = m; 1188 else { 1189 m->m_flags &= ~M_PKTHDR; 1190 sc->re_tail->m_next = m; 1191 sc->re_tail = m; 1192 } 1193 re_newbuf(sc, i, NULL); 1194 continue; 1195 } 1196 1197 /* 1198 * NOTE: for the 8139C+, the frame length field 1199 * is always 12 bits in size, but for the gigE chips, 1200 * it is 13 bits (since the max RX frame length is 16K). 1201 * Unfortunately, all 32 bits in the status word 1202 * were already used, so to make room for the extra 1203 * length bit, RealTek took out the 'frame alignment 1204 * error' bit and shifted the other status bits 1205 * over one slot. The OWN, EOR, FS and LS bits are 1206 * still in the same places. We have already extracted 1207 * the frame length and checked the OWN bit, so rather 1208 * than using an alternate bit mapping, we shift the 1209 * status bits one space to the right so we can evaluate 1210 * them using the 8169 status as though it was in the 1211 * same format as that of the 8139C+. 1212 */ 1213 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) 1214 rxstat >>= 1; 1215 1216 if (__predict_false((rxstat & RE_RDESC_STAT_RXERRSUM) != 0)) { 1217 #ifdef RE_DEBUG 1218 printf("%s: RX error (rxstat = 0x%08x)", 1219 device_xname(sc->sc_dev), rxstat); 1220 if (rxstat & RE_RDESC_STAT_FRALIGN) 1221 printf(", frame alignment error"); 1222 if (rxstat & RE_RDESC_STAT_BUFOFLOW) 1223 printf(", out of buffer space"); 1224 if (rxstat & RE_RDESC_STAT_FIFOOFLOW) 1225 printf(", FIFO overrun"); 1226 if (rxstat & RE_RDESC_STAT_GIANT) 1227 printf(", giant packet"); 1228 if (rxstat & RE_RDESC_STAT_RUNT) 1229 printf(", runt packet"); 1230 if (rxstat & RE_RDESC_STAT_CRCERR) 1231 printf(", CRC error"); 1232 printf("\n"); 1233 #endif 1234 ifp->if_ierrors++; 1235 /* 1236 * If this is part of a multi-fragment packet, 1237 * discard all the pieces. 1238 */ 1239 if (sc->re_head != NULL) { 1240 m_freem(sc->re_head); 1241 sc->re_head = sc->re_tail = NULL; 1242 } 1243 re_newbuf(sc, i, m); 1244 continue; 1245 } 1246 1247 /* 1248 * If allocating a replacement mbuf fails, 1249 * reload the current one. 1250 */ 1251 1252 if (__predict_false(re_newbuf(sc, i, NULL) != 0)) { 1253 ifp->if_ierrors++; 1254 if (sc->re_head != NULL) { 1255 m_freem(sc->re_head); 1256 sc->re_head = sc->re_tail = NULL; 1257 } 1258 re_newbuf(sc, i, m); 1259 continue; 1260 } 1261 1262 if (sc->re_head != NULL) { 1263 m->m_len = total_len % (MCLBYTES - RE_ETHER_ALIGN); 1264 /* 1265 * Special case: if there's 4 bytes or less 1266 * in this buffer, the mbuf can be discarded: 1267 * the last 4 bytes is the CRC, which we don't 1268 * care about anyway. 1269 */ 1270 if (m->m_len <= ETHER_CRC_LEN) { 1271 sc->re_tail->m_len -= 1272 (ETHER_CRC_LEN - m->m_len); 1273 m_freem(m); 1274 } else { 1275 m->m_len -= ETHER_CRC_LEN; 1276 m->m_flags &= ~M_PKTHDR; 1277 sc->re_tail->m_next = m; 1278 } 1279 m = sc->re_head; 1280 sc->re_head = sc->re_tail = NULL; 1281 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1282 } else 1283 m->m_pkthdr.len = m->m_len = 1284 (total_len - ETHER_CRC_LEN); 1285 1286 ifp->if_ipackets++; 1287 m->m_pkthdr.rcvif = ifp; 1288 1289 /* Do RX checksumming */ 1290 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) { 1291 /* Check IP header checksum */ 1292 if ((rxstat & RE_RDESC_STAT_PROTOID) != 0) { 1293 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1294 if (rxstat & RE_RDESC_STAT_IPSUMBAD) 1295 m->m_pkthdr.csum_flags |= 1296 M_CSUM_IPv4_BAD; 1297 1298 /* Check TCP/UDP checksum */ 1299 if (RE_TCPPKT(rxstat)) { 1300 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1301 if (rxstat & RE_RDESC_STAT_TCPSUMBAD) 1302 m->m_pkthdr.csum_flags |= 1303 M_CSUM_TCP_UDP_BAD; 1304 } else if (RE_UDPPKT(rxstat)) { 1305 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1306 if (rxstat & RE_RDESC_STAT_UDPSUMBAD) 1307 m->m_pkthdr.csum_flags |= 1308 M_CSUM_TCP_UDP_BAD; 1309 } 1310 } 1311 } else { 1312 /* Check IPv4 header checksum */ 1313 if ((rxvlan & RE_RDESC_VLANCTL_IPV4) != 0) { 1314 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1315 if (rxstat & RE_RDESC_STAT_IPSUMBAD) 1316 m->m_pkthdr.csum_flags |= 1317 M_CSUM_IPv4_BAD; 1318 1319 /* Check TCPv4/UDPv4 checksum */ 1320 if (RE_TCPPKT(rxstat)) { 1321 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1322 if (rxstat & RE_RDESC_STAT_TCPSUMBAD) 1323 m->m_pkthdr.csum_flags |= 1324 M_CSUM_TCP_UDP_BAD; 1325 } else if (RE_UDPPKT(rxstat)) { 1326 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1327 if (rxstat & RE_RDESC_STAT_UDPSUMBAD) 1328 m->m_pkthdr.csum_flags |= 1329 M_CSUM_TCP_UDP_BAD; 1330 } 1331 } 1332 /* XXX Check TCPv6/UDPv6 checksum? */ 1333 } 1334 1335 if (rxvlan & RE_RDESC_VLANCTL_TAG) { 1336 VLAN_INPUT_TAG(ifp, m, 1337 bswap16(rxvlan & RE_RDESC_VLANCTL_DATA), 1338 continue); 1339 } 1340 bpf_mtap(ifp, m); 1341 (*ifp->if_input)(ifp, m); 1342 } 1343 1344 sc->re_ldata.re_rx_prodidx = i; 1345 } 1346 1347 static void 1348 re_txeof(struct rtk_softc *sc) 1349 { 1350 struct ifnet *ifp; 1351 struct re_txq *txq; 1352 uint32_t txstat; 1353 int idx, descidx; 1354 1355 ifp = &sc->ethercom.ec_if; 1356 1357 for (idx = sc->re_ldata.re_txq_considx; 1358 sc->re_ldata.re_txq_free < RE_TX_QLEN; 1359 idx = RE_NEXT_TXQ(sc, idx), sc->re_ldata.re_txq_free++) { 1360 txq = &sc->re_ldata.re_txq[idx]; 1361 KASSERT(txq->txq_mbuf != NULL); 1362 1363 descidx = txq->txq_descidx; 1364 RE_TXDESCSYNC(sc, descidx, 1365 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1366 txstat = 1367 le32toh(sc->re_ldata.re_tx_list[descidx].re_cmdstat); 1368 RE_TXDESCSYNC(sc, descidx, BUS_DMASYNC_PREREAD); 1369 KASSERT((txstat & RE_TDESC_CMD_EOF) != 0); 1370 if (txstat & RE_TDESC_CMD_OWN) { 1371 break; 1372 } 1373 1374 sc->re_ldata.re_tx_free += txq->txq_nsegs; 1375 KASSERT(sc->re_ldata.re_tx_free <= RE_TX_DESC_CNT(sc)); 1376 bus_dmamap_sync(sc->sc_dmat, txq->txq_dmamap, 1377 0, txq->txq_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1378 bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap); 1379 m_freem(txq->txq_mbuf); 1380 txq->txq_mbuf = NULL; 1381 1382 if (txstat & (RE_TDESC_STAT_EXCESSCOL | RE_TDESC_STAT_COLCNT)) 1383 ifp->if_collisions++; 1384 if (txstat & RE_TDESC_STAT_TXERRSUM) 1385 ifp->if_oerrors++; 1386 else 1387 ifp->if_opackets++; 1388 } 1389 1390 sc->re_ldata.re_txq_considx = idx; 1391 1392 if (sc->re_ldata.re_txq_free > RE_NTXDESC_RSVD) 1393 ifp->if_flags &= ~IFF_OACTIVE; 1394 1395 /* 1396 * If not all descriptors have been released reaped yet, 1397 * reload the timer so that we will eventually get another 1398 * interrupt that will cause us to re-enter this routine. 1399 * This is done in case the transmitter has gone idle. 1400 */ 1401 if (sc->re_ldata.re_txq_free < RE_TX_QLEN) { 1402 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1403 if ((sc->sc_quirk & RTKQ_PCIE) != 0) { 1404 /* 1405 * Some chips will ignore a second TX request 1406 * issued while an existing transmission is in 1407 * progress. If the transmitter goes idle but 1408 * there are still packets waiting to be sent, 1409 * we need to restart the channel here to flush 1410 * them out. This only seems to be required with 1411 * the PCIe devices. 1412 */ 1413 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START); 1414 } 1415 } else 1416 ifp->if_timer = 0; 1417 } 1418 1419 static void 1420 re_tick(void *arg) 1421 { 1422 struct rtk_softc *sc = arg; 1423 int s; 1424 1425 /* XXX: just return for 8169S/8110S with rev 2 or newer phy */ 1426 s = splnet(); 1427 1428 mii_tick(&sc->mii); 1429 splx(s); 1430 1431 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1432 } 1433 1434 int 1435 re_intr(void *arg) 1436 { 1437 struct rtk_softc *sc = arg; 1438 struct ifnet *ifp; 1439 uint16_t status; 1440 int handled = 0; 1441 1442 if (!device_has_power(sc->sc_dev)) 1443 return 0; 1444 1445 ifp = &sc->ethercom.ec_if; 1446 1447 if ((ifp->if_flags & IFF_UP) == 0) 1448 return 0; 1449 1450 for (;;) { 1451 1452 status = CSR_READ_2(sc, RTK_ISR); 1453 /* If the card has gone away the read returns 0xffff. */ 1454 if (status == 0xffff) 1455 break; 1456 if (status) { 1457 handled = 1; 1458 CSR_WRITE_2(sc, RTK_ISR, status); 1459 } 1460 1461 if ((status & RTK_INTRS_CPLUS) == 0) 1462 break; 1463 1464 if (status & (RTK_ISR_RX_OK | RTK_ISR_RX_ERR)) 1465 re_rxeof(sc); 1466 1467 if (status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_TX_ERR | 1468 RTK_ISR_TX_DESC_UNAVAIL)) 1469 re_txeof(sc); 1470 1471 if (status & RTK_ISR_SYSTEM_ERR) { 1472 re_init(ifp); 1473 } 1474 1475 if (status & RTK_ISR_LINKCHG) { 1476 callout_stop(&sc->rtk_tick_ch); 1477 re_tick(sc); 1478 } 1479 } 1480 1481 if (handled && !IFQ_IS_EMPTY(&ifp->if_snd)) 1482 re_start(ifp); 1483 1484 rnd_add_uint32(&sc->rnd_source, status); 1485 1486 return handled; 1487 } 1488 1489 1490 1491 /* 1492 * Main transmit routine for C+ and gigE NICs. 1493 */ 1494 1495 static void 1496 re_start(struct ifnet *ifp) 1497 { 1498 struct rtk_softc *sc; 1499 struct mbuf *m; 1500 bus_dmamap_t map; 1501 struct re_txq *txq; 1502 struct re_desc *d; 1503 struct m_tag *mtag; 1504 uint32_t cmdstat, re_flags, vlanctl; 1505 int ofree, idx, error, nsegs, seg; 1506 int startdesc, curdesc, lastdesc; 1507 bool pad; 1508 1509 sc = ifp->if_softc; 1510 ofree = sc->re_ldata.re_txq_free; 1511 1512 for (idx = sc->re_ldata.re_txq_prodidx;; idx = RE_NEXT_TXQ(sc, idx)) { 1513 1514 IFQ_POLL(&ifp->if_snd, m); 1515 if (m == NULL) 1516 break; 1517 1518 if (sc->re_ldata.re_txq_free == 0 || 1519 sc->re_ldata.re_tx_free == 0) { 1520 /* no more free slots left */ 1521 ifp->if_flags |= IFF_OACTIVE; 1522 break; 1523 } 1524 1525 /* 1526 * Set up checksum offload. Note: checksum offload bits must 1527 * appear in all descriptors of a multi-descriptor transmit 1528 * attempt. (This is according to testing done with an 8169 1529 * chip. I'm not sure if this is a requirement or a bug.) 1530 */ 1531 1532 vlanctl = 0; 1533 if ((m->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0) { 1534 uint32_t segsz = m->m_pkthdr.segsz; 1535 1536 re_flags = RE_TDESC_CMD_LGSEND | 1537 (segsz << RE_TDESC_CMD_MSSVAL_SHIFT); 1538 } else { 1539 /* 1540 * set RE_TDESC_CMD_IPCSUM if any checksum offloading 1541 * is requested. otherwise, RE_TDESC_CMD_TCPCSUM/ 1542 * RE_TDESC_CMD_UDPCSUM doesn't make effects. 1543 */ 1544 re_flags = 0; 1545 if ((m->m_pkthdr.csum_flags & 1546 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1547 != 0) { 1548 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) { 1549 re_flags |= RE_TDESC_CMD_IPCSUM; 1550 if (m->m_pkthdr.csum_flags & 1551 M_CSUM_TCPv4) { 1552 re_flags |= 1553 RE_TDESC_CMD_TCPCSUM; 1554 } else if (m->m_pkthdr.csum_flags & 1555 M_CSUM_UDPv4) { 1556 re_flags |= 1557 RE_TDESC_CMD_UDPCSUM; 1558 } 1559 } else { 1560 vlanctl |= RE_TDESC_VLANCTL_IPCSUM; 1561 if (m->m_pkthdr.csum_flags & 1562 M_CSUM_TCPv4) { 1563 vlanctl |= 1564 RE_TDESC_VLANCTL_TCPCSUM; 1565 } else if (m->m_pkthdr.csum_flags & 1566 M_CSUM_UDPv4) { 1567 vlanctl |= 1568 RE_TDESC_VLANCTL_UDPCSUM; 1569 } 1570 } 1571 } 1572 } 1573 1574 txq = &sc->re_ldata.re_txq[idx]; 1575 map = txq->txq_dmamap; 1576 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1577 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1578 1579 if (__predict_false(error)) { 1580 /* XXX try to defrag if EFBIG? */ 1581 printf("%s: can't map mbuf (error %d)\n", 1582 device_xname(sc->sc_dev), error); 1583 1584 IFQ_DEQUEUE(&ifp->if_snd, m); 1585 m_freem(m); 1586 ifp->if_oerrors++; 1587 continue; 1588 } 1589 1590 nsegs = map->dm_nsegs; 1591 pad = false; 1592 if (__predict_false(m->m_pkthdr.len <= RE_IP4CSUMTX_PADLEN && 1593 (re_flags & RE_TDESC_CMD_IPCSUM) != 0 && 1594 (sc->sc_quirk & RTKQ_DESCV2) == 0)) { 1595 pad = true; 1596 nsegs++; 1597 } 1598 1599 if (nsegs > sc->re_ldata.re_tx_free) { 1600 /* 1601 * Not enough free descriptors to transmit this packet. 1602 */ 1603 ifp->if_flags |= IFF_OACTIVE; 1604 bus_dmamap_unload(sc->sc_dmat, map); 1605 break; 1606 } 1607 1608 IFQ_DEQUEUE(&ifp->if_snd, m); 1609 1610 /* 1611 * Make sure that the caches are synchronized before we 1612 * ask the chip to start DMA for the packet data. 1613 */ 1614 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1615 BUS_DMASYNC_PREWRITE); 1616 1617 /* 1618 * Set up hardware VLAN tagging. Note: vlan tag info must 1619 * appear in all descriptors of a multi-descriptor 1620 * transmission attempt. 1621 */ 1622 if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m)) != NULL) 1623 vlanctl |= bswap16(VLAN_TAG_VALUE(mtag)) | 1624 RE_TDESC_VLANCTL_TAG; 1625 1626 /* 1627 * Map the segment array into descriptors. 1628 * Note that we set the start-of-frame and 1629 * end-of-frame markers for either TX or RX, 1630 * but they really only have meaning in the TX case. 1631 * (In the RX case, it's the chip that tells us 1632 * where packets begin and end.) 1633 * We also keep track of the end of the ring 1634 * and set the end-of-ring bits as needed, 1635 * and we set the ownership bits in all except 1636 * the very first descriptor. (The caller will 1637 * set this descriptor later when it start 1638 * transmission or reception.) 1639 */ 1640 curdesc = startdesc = sc->re_ldata.re_tx_nextfree; 1641 lastdesc = -1; 1642 for (seg = 0; seg < map->dm_nsegs; 1643 seg++, curdesc = RE_NEXT_TX_DESC(sc, curdesc)) { 1644 d = &sc->re_ldata.re_tx_list[curdesc]; 1645 #ifdef DIAGNOSTIC 1646 RE_TXDESCSYNC(sc, curdesc, 1647 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1648 cmdstat = le32toh(d->re_cmdstat); 1649 RE_TXDESCSYNC(sc, curdesc, BUS_DMASYNC_PREREAD); 1650 if (cmdstat & RE_TDESC_STAT_OWN) { 1651 panic("%s: tried to map busy TX descriptor", 1652 device_xname(sc->sc_dev)); 1653 } 1654 #endif 1655 1656 d->re_vlanctl = htole32(vlanctl); 1657 re_set_bufaddr(d, map->dm_segs[seg].ds_addr); 1658 cmdstat = re_flags | map->dm_segs[seg].ds_len; 1659 if (seg == 0) 1660 cmdstat |= RE_TDESC_CMD_SOF; 1661 else 1662 cmdstat |= RE_TDESC_CMD_OWN; 1663 if (curdesc == (RE_TX_DESC_CNT(sc) - 1)) 1664 cmdstat |= RE_TDESC_CMD_EOR; 1665 if (seg == nsegs - 1) { 1666 cmdstat |= RE_TDESC_CMD_EOF; 1667 lastdesc = curdesc; 1668 } 1669 d->re_cmdstat = htole32(cmdstat); 1670 RE_TXDESCSYNC(sc, curdesc, 1671 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1672 } 1673 if (__predict_false(pad)) { 1674 d = &sc->re_ldata.re_tx_list[curdesc]; 1675 d->re_vlanctl = htole32(vlanctl); 1676 re_set_bufaddr(d, RE_TXPADDADDR(sc)); 1677 cmdstat = re_flags | 1678 RE_TDESC_CMD_OWN | RE_TDESC_CMD_EOF | 1679 (RE_IP4CSUMTX_PADLEN + 1 - m->m_pkthdr.len); 1680 if (curdesc == (RE_TX_DESC_CNT(sc) - 1)) 1681 cmdstat |= RE_TDESC_CMD_EOR; 1682 d->re_cmdstat = htole32(cmdstat); 1683 RE_TXDESCSYNC(sc, curdesc, 1684 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1685 lastdesc = curdesc; 1686 curdesc = RE_NEXT_TX_DESC(sc, curdesc); 1687 } 1688 KASSERT(lastdesc != -1); 1689 1690 /* Transfer ownership of packet to the chip. */ 1691 1692 sc->re_ldata.re_tx_list[startdesc].re_cmdstat |= 1693 htole32(RE_TDESC_CMD_OWN); 1694 RE_TXDESCSYNC(sc, startdesc, 1695 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1696 1697 /* update info of TX queue and descriptors */ 1698 txq->txq_mbuf = m; 1699 txq->txq_descidx = lastdesc; 1700 txq->txq_nsegs = nsegs; 1701 1702 sc->re_ldata.re_txq_free--; 1703 sc->re_ldata.re_tx_free -= nsegs; 1704 sc->re_ldata.re_tx_nextfree = curdesc; 1705 1706 /* 1707 * If there's a BPF listener, bounce a copy of this frame 1708 * to him. 1709 */ 1710 bpf_mtap(ifp, m); 1711 } 1712 1713 if (sc->re_ldata.re_txq_free < ofree) { 1714 /* 1715 * TX packets are enqueued. 1716 */ 1717 sc->re_ldata.re_txq_prodidx = idx; 1718 1719 /* 1720 * Start the transmitter to poll. 1721 * 1722 * RealTek put the TX poll request register in a different 1723 * location on the 8169 gigE chip. I don't know why. 1724 */ 1725 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) 1726 CSR_WRITE_1(sc, RTK_TXSTART, RTK_TXSTART_START); 1727 else 1728 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START); 1729 1730 /* 1731 * Use the countdown timer for interrupt moderation. 1732 * 'TX done' interrupts are disabled. Instead, we reset the 1733 * countdown timer, which will begin counting until it hits 1734 * the value in the TIMERINT register, and then trigger an 1735 * interrupt. Each time we write to the TIMERCNT register, 1736 * the timer count is reset to 0. 1737 */ 1738 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1739 1740 /* 1741 * Set a timeout in case the chip goes out to lunch. 1742 */ 1743 ifp->if_timer = 5; 1744 } 1745 } 1746 1747 static int 1748 re_init(struct ifnet *ifp) 1749 { 1750 struct rtk_softc *sc = ifp->if_softc; 1751 uint32_t rxcfg = 0; 1752 uint16_t cfg; 1753 int error; 1754 #ifdef RE_USE_EECMD 1755 const uint8_t *enaddr; 1756 uint32_t reg; 1757 #endif 1758 1759 if ((error = re_enable(sc)) != 0) 1760 goto out; 1761 1762 /* 1763 * Cancel pending I/O and free all RX/TX buffers. 1764 */ 1765 re_stop(ifp, 0); 1766 1767 re_reset(sc); 1768 1769 /* 1770 * Enable C+ RX and TX mode, as well as VLAN stripping and 1771 * RX checksum offload. We must configure the C+ register 1772 * before all others. 1773 */ 1774 cfg = RE_CPLUSCMD_PCI_MRW; 1775 1776 /* 1777 * XXX: For old 8169 set bit 14. 1778 * For 8169S/8110S and above, do not set bit 14. 1779 */ 1780 if ((sc->sc_quirk & RTKQ_8169NONS) != 0) 1781 cfg |= (0x1 << 14); 1782 1783 if ((sc->ethercom.ec_capenable & ETHERCAP_VLAN_HWTAGGING) != 0) 1784 cfg |= RE_CPLUSCMD_VLANSTRIP; 1785 if ((ifp->if_capenable & (IFCAP_CSUM_IPv4_Rx | 1786 IFCAP_CSUM_TCPv4_Rx | IFCAP_CSUM_UDPv4_Rx)) != 0) 1787 cfg |= RE_CPLUSCMD_RXCSUM_ENB; 1788 if ((sc->sc_quirk & RTKQ_MACSTAT) != 0) { 1789 cfg |= RE_CPLUSCMD_MACSTAT_DIS; 1790 cfg |= RE_CPLUSCMD_TXENB; 1791 } else 1792 cfg |= RE_CPLUSCMD_RXENB | RE_CPLUSCMD_TXENB; 1793 1794 CSR_WRITE_2(sc, RTK_CPLUS_CMD, cfg); 1795 1796 /* XXX: from Realtek-supplied Linux driver. Wholly undocumented. */ 1797 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) 1798 CSR_WRITE_2(sc, RTK_IM, 0x0000); 1799 1800 DELAY(10000); 1801 1802 #ifdef RE_USE_EECMD 1803 /* 1804 * Init our MAC address. Even though the chipset 1805 * documentation doesn't mention it, we need to enter "Config 1806 * register write enable" mode to modify the ID registers. 1807 */ 1808 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_WRITECFG); 1809 enaddr = CLLADDR(ifp->if_sadl); 1810 reg = enaddr[0] | (enaddr[1] << 8) | 1811 (enaddr[2] << 16) | (enaddr[3] << 24); 1812 CSR_WRITE_4(sc, RTK_IDR0, reg); 1813 reg = enaddr[4] | (enaddr[5] << 8); 1814 CSR_WRITE_4(sc, RTK_IDR4, reg); 1815 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 1816 #endif 1817 1818 /* 1819 * For C+ mode, initialize the RX descriptors and mbufs. 1820 */ 1821 re_rx_list_init(sc); 1822 re_tx_list_init(sc); 1823 1824 /* 1825 * Load the addresses of the RX and TX lists into the chip. 1826 */ 1827 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_HI, 1828 RE_ADDR_HI(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr)); 1829 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_LO, 1830 RE_ADDR_LO(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr)); 1831 1832 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_HI, 1833 RE_ADDR_HI(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr)); 1834 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_LO, 1835 RE_ADDR_LO(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr)); 1836 1837 /* 1838 * Enable transmit and receive. 1839 */ 1840 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1841 1842 /* 1843 * Set the initial TX and RX configuration. 1844 */ 1845 if (sc->re_testmode && (sc->sc_quirk & RTKQ_8169NONS) != 0) { 1846 /* test mode is needed only for old 8169 */ 1847 CSR_WRITE_4(sc, RTK_TXCFG, 1848 RE_TXCFG_CONFIG | RTK_LOOPTEST_ON); 1849 } else 1850 CSR_WRITE_4(sc, RTK_TXCFG, RE_TXCFG_CONFIG); 1851 1852 CSR_WRITE_1(sc, RTK_EARLY_TX_THRESH, 16); 1853 1854 CSR_WRITE_4(sc, RTK_RXCFG, RE_RXCFG_CONFIG); 1855 1856 /* Set the individual bit to receive frames for this host only. */ 1857 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 1858 rxcfg |= RTK_RXCFG_RX_INDIV; 1859 1860 /* If we want promiscuous mode, set the allframes bit. */ 1861 if (ifp->if_flags & IFF_PROMISC) 1862 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 1863 else 1864 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 1865 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1866 1867 /* 1868 * Set capture broadcast bit to capture broadcast frames. 1869 */ 1870 if (ifp->if_flags & IFF_BROADCAST) 1871 rxcfg |= RTK_RXCFG_RX_BROAD; 1872 else 1873 rxcfg &= ~RTK_RXCFG_RX_BROAD; 1874 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1875 1876 /* 1877 * Program the multicast filter, if necessary. 1878 */ 1879 rtk_setmulti(sc); 1880 1881 /* 1882 * Enable interrupts. 1883 */ 1884 if (sc->re_testmode) 1885 CSR_WRITE_2(sc, RTK_IMR, 0); 1886 else 1887 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS); 1888 1889 /* Start RX/TX process. */ 1890 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 1891 #ifdef notdef 1892 /* Enable receiver and transmitter. */ 1893 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1894 #endif 1895 1896 /* 1897 * Initialize the timer interrupt register so that 1898 * a timer interrupt will be generated once the timer 1899 * reaches a certain number of ticks. The timer is 1900 * reloaded on each transmit. This gives us TX interrupt 1901 * moderation, which dramatically improves TX frame rate. 1902 */ 1903 1904 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) 1905 CSR_WRITE_4(sc, RTK_TIMERINT, 0x400); 1906 else { 1907 CSR_WRITE_4(sc, RTK_TIMERINT_8169, 0x800); 1908 1909 /* 1910 * For 8169 gigE NICs, set the max allowed RX packet 1911 * size so we can receive jumbo frames. 1912 */ 1913 CSR_WRITE_2(sc, RTK_MAXRXPKTLEN, 16383); 1914 } 1915 1916 if (sc->re_testmode) 1917 return 0; 1918 1919 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD); 1920 1921 ifp->if_flags |= IFF_RUNNING; 1922 ifp->if_flags &= ~IFF_OACTIVE; 1923 1924 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1925 1926 out: 1927 if (error) { 1928 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1929 ifp->if_timer = 0; 1930 printf("%s: interface not running\n", 1931 device_xname(sc->sc_dev)); 1932 } 1933 1934 return error; 1935 } 1936 1937 static int 1938 re_ioctl(struct ifnet *ifp, u_long command, void *data) 1939 { 1940 struct rtk_softc *sc = ifp->if_softc; 1941 struct ifreq *ifr = data; 1942 int s, error = 0; 1943 1944 s = splnet(); 1945 1946 switch (command) { 1947 case SIOCSIFMTU: 1948 /* 1949 * Disable jumbo frames if it's not supported. 1950 */ 1951 if ((sc->sc_quirk & RTKQ_NOJUMBO) != 0 && 1952 ifr->ifr_mtu > ETHERMTU) { 1953 error = EINVAL; 1954 break; 1955 } 1956 1957 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO) 1958 error = EINVAL; 1959 else if ((error = ifioctl_common(ifp, command, data)) == 1960 ENETRESET) 1961 error = 0; 1962 break; 1963 default: 1964 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1965 break; 1966 1967 error = 0; 1968 1969 if (command == SIOCSIFCAP) 1970 error = (*ifp->if_init)(ifp); 1971 else if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1972 ; 1973 else if (ifp->if_flags & IFF_RUNNING) 1974 rtk_setmulti(sc); 1975 break; 1976 } 1977 1978 splx(s); 1979 1980 return error; 1981 } 1982 1983 static void 1984 re_watchdog(struct ifnet *ifp) 1985 { 1986 struct rtk_softc *sc; 1987 int s; 1988 1989 sc = ifp->if_softc; 1990 s = splnet(); 1991 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1992 ifp->if_oerrors++; 1993 1994 re_txeof(sc); 1995 re_rxeof(sc); 1996 1997 re_init(ifp); 1998 1999 splx(s); 2000 } 2001 2002 /* 2003 * Stop the adapter and free any mbufs allocated to the 2004 * RX and TX lists. 2005 */ 2006 static void 2007 re_stop(struct ifnet *ifp, int disable) 2008 { 2009 int i; 2010 struct rtk_softc *sc = ifp->if_softc; 2011 2012 callout_stop(&sc->rtk_tick_ch); 2013 2014 mii_down(&sc->mii); 2015 2016 if ((sc->sc_quirk & RTKQ_CMDSTOP) != 0) 2017 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_STOPREQ | RTK_CMD_TX_ENB | 2018 RTK_CMD_RX_ENB); 2019 else 2020 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 2021 DELAY(1000); 2022 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 2023 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF); 2024 2025 if (sc->re_head != NULL) { 2026 m_freem(sc->re_head); 2027 sc->re_head = sc->re_tail = NULL; 2028 } 2029 2030 /* Free the TX list buffers. */ 2031 for (i = 0; i < RE_TX_QLEN; i++) { 2032 if (sc->re_ldata.re_txq[i].txq_mbuf != NULL) { 2033 bus_dmamap_unload(sc->sc_dmat, 2034 sc->re_ldata.re_txq[i].txq_dmamap); 2035 m_freem(sc->re_ldata.re_txq[i].txq_mbuf); 2036 sc->re_ldata.re_txq[i].txq_mbuf = NULL; 2037 } 2038 } 2039 2040 /* Free the RX list buffers. */ 2041 for (i = 0; i < RE_RX_DESC_CNT; i++) { 2042 if (sc->re_ldata.re_rxsoft[i].rxs_mbuf != NULL) { 2043 bus_dmamap_unload(sc->sc_dmat, 2044 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 2045 m_freem(sc->re_ldata.re_rxsoft[i].rxs_mbuf); 2046 sc->re_ldata.re_rxsoft[i].rxs_mbuf = NULL; 2047 } 2048 } 2049 2050 if (disable) 2051 re_disable(sc); 2052 2053 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2054 ifp->if_timer = 0; 2055 } 2056