1 /* $NetBSD: rtl8169.c,v 1.107 2009/01/03 03:43:22 yamt Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998-2003 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.107 2009/01/03 03:43:22 yamt Exp $"); 37 /* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */ 38 39 /* 40 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 41 * 42 * Written by Bill Paul <wpaul@windriver.com> 43 * Senior Networking Software Engineer 44 * Wind River Systems 45 */ 46 47 /* 48 * This driver is designed to support RealTek's next generation of 49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 50 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 51 * and the RTL8110S. 52 * 53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 54 * with the older 8139 family, however it also supports a special 55 * C+ mode of operation that provides several new performance enhancing 56 * features. These include: 57 * 58 * o Descriptor based DMA mechanism. Each descriptor represents 59 * a single packet fragment. Data buffers may be aligned on 60 * any byte boundary. 61 * 62 * o 64-bit DMA 63 * 64 * o TCP/IP checksum offload for both RX and TX 65 * 66 * o High and normal priority transmit DMA rings 67 * 68 * o VLAN tag insertion and extraction 69 * 70 * o TCP large send (segmentation offload) 71 * 72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 73 * programming API is fairly straightforward. The RX filtering, EEPROM 74 * access and PHY access is the same as it is on the older 8139 series 75 * chips. 76 * 77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 78 * same programming API and feature set as the 8139C+ with the following 79 * differences and additions: 80 * 81 * o 1000Mbps mode 82 * 83 * o Jumbo frames 84 * 85 * o GMII and TBI ports/registers for interfacing with copper 86 * or fiber PHYs 87 * 88 * o RX and TX DMA rings can have up to 1024 descriptors 89 * (the 8139C+ allows a maximum of 64) 90 * 91 * o Slight differences in register layout from the 8139C+ 92 * 93 * The TX start and timer interrupt registers are at different locations 94 * on the 8169 than they are on the 8139C+. Also, the status word in the 95 * RX descriptor has a slightly different bit layout. The 8169 does not 96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 97 * copper gigE PHY. 98 * 99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 100 * (the 'S' stands for 'single-chip'). These devices have the same 101 * programming API as the older 8169, but also have some vendor-specific 102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 104 * 105 * This driver takes advantage of the RX and TX checksum offload and 106 * VLAN tag insertion/extraction features. It also implements TX 107 * interrupt moderation using the timer interrupt registers, which 108 * significantly reduces TX interrupt load. There is also support 109 * for jumbo frames, however the 8169/8169S/8110S can not transmit 110 * jumbo frames larger than 7.5K, so the max MTU possible with this 111 * driver is 7500 bytes. 112 */ 113 114 #include "bpfilter.h" 115 #include "vlan.h" 116 117 #include <sys/param.h> 118 #include <sys/endian.h> 119 #include <sys/systm.h> 120 #include <sys/sockio.h> 121 #include <sys/mbuf.h> 122 #include <sys/malloc.h> 123 #include <sys/kernel.h> 124 #include <sys/socket.h> 125 #include <sys/device.h> 126 127 #include <net/if.h> 128 #include <net/if_arp.h> 129 #include <net/if_dl.h> 130 #include <net/if_ether.h> 131 #include <net/if_media.h> 132 #include <net/if_vlanvar.h> 133 134 #include <netinet/in_systm.h> /* XXX for IP_MAXPACKET */ 135 #include <netinet/in.h> /* XXX for IP_MAXPACKET */ 136 #include <netinet/ip.h> /* XXX for IP_MAXPACKET */ 137 138 #if NBPFILTER > 0 139 #include <net/bpf.h> 140 #endif 141 142 #include <sys/bus.h> 143 144 #include <dev/mii/mii.h> 145 #include <dev/mii/miivar.h> 146 147 #include <dev/ic/rtl81x9reg.h> 148 #include <dev/ic/rtl81x9var.h> 149 150 #include <dev/ic/rtl8169var.h> 151 152 static inline void re_set_bufaddr(struct re_desc *, bus_addr_t); 153 154 static int re_newbuf(struct rtk_softc *, int, struct mbuf *); 155 static int re_rx_list_init(struct rtk_softc *); 156 static int re_tx_list_init(struct rtk_softc *); 157 static void re_rxeof(struct rtk_softc *); 158 static void re_txeof(struct rtk_softc *); 159 static void re_tick(void *); 160 static void re_start(struct ifnet *); 161 static int re_ioctl(struct ifnet *, u_long, void *); 162 static int re_init(struct ifnet *); 163 static void re_stop(struct ifnet *, int); 164 static void re_watchdog(struct ifnet *); 165 166 static int re_enable(struct rtk_softc *); 167 static void re_disable(struct rtk_softc *); 168 169 static int re_gmii_readreg(struct device *, int, int); 170 static void re_gmii_writereg(struct device *, int, int, int); 171 172 static int re_miibus_readreg(struct device *, int, int); 173 static void re_miibus_writereg(struct device *, int, int, int); 174 static void re_miibus_statchg(struct device *); 175 176 static void re_reset(struct rtk_softc *); 177 178 static inline void 179 re_set_bufaddr(struct re_desc *d, bus_addr_t addr) 180 { 181 182 d->re_bufaddr_lo = htole32((uint32_t)addr); 183 if (sizeof(bus_addr_t) == sizeof(uint64_t)) 184 d->re_bufaddr_hi = htole32((uint64_t)addr >> 32); 185 else 186 d->re_bufaddr_hi = 0; 187 } 188 189 static int 190 re_gmii_readreg(device_t dev, int phy, int reg) 191 { 192 struct rtk_softc *sc = device_private(dev); 193 uint32_t rval; 194 int i; 195 196 if (phy != 7) 197 return 0; 198 199 /* Let the rgephy driver read the GMEDIASTAT register */ 200 201 if (reg == RTK_GMEDIASTAT) { 202 rval = CSR_READ_1(sc, RTK_GMEDIASTAT); 203 return rval; 204 } 205 206 CSR_WRITE_4(sc, RTK_PHYAR, reg << 16); 207 DELAY(1000); 208 209 for (i = 0; i < RTK_TIMEOUT; i++) { 210 rval = CSR_READ_4(sc, RTK_PHYAR); 211 if (rval & RTK_PHYAR_BUSY) 212 break; 213 DELAY(100); 214 } 215 216 if (i == RTK_TIMEOUT) { 217 printf("%s: PHY read failed\n", device_xname(sc->sc_dev)); 218 return 0; 219 } 220 221 return rval & RTK_PHYAR_PHYDATA; 222 } 223 224 static void 225 re_gmii_writereg(device_t dev, int phy, int reg, int data) 226 { 227 struct rtk_softc *sc = device_private(dev); 228 uint32_t rval; 229 int i; 230 231 CSR_WRITE_4(sc, RTK_PHYAR, (reg << 16) | 232 (data & RTK_PHYAR_PHYDATA) | RTK_PHYAR_BUSY); 233 DELAY(1000); 234 235 for (i = 0; i < RTK_TIMEOUT; i++) { 236 rval = CSR_READ_4(sc, RTK_PHYAR); 237 if (!(rval & RTK_PHYAR_BUSY)) 238 break; 239 DELAY(100); 240 } 241 242 if (i == RTK_TIMEOUT) { 243 printf("%s: PHY write reg %x <- %x failed\n", 244 device_xname(sc->sc_dev), reg, data); 245 } 246 } 247 248 static int 249 re_miibus_readreg(device_t dev, int phy, int reg) 250 { 251 struct rtk_softc *sc = device_private(dev); 252 uint16_t rval = 0; 253 uint16_t re8139_reg = 0; 254 int s; 255 256 s = splnet(); 257 258 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 259 rval = re_gmii_readreg(dev, phy, reg); 260 splx(s); 261 return rval; 262 } 263 264 /* Pretend the internal PHY is only at address 0 */ 265 if (phy) { 266 splx(s); 267 return 0; 268 } 269 switch (reg) { 270 case MII_BMCR: 271 re8139_reg = RTK_BMCR; 272 break; 273 case MII_BMSR: 274 re8139_reg = RTK_BMSR; 275 break; 276 case MII_ANAR: 277 re8139_reg = RTK_ANAR; 278 break; 279 case MII_ANER: 280 re8139_reg = RTK_ANER; 281 break; 282 case MII_ANLPAR: 283 re8139_reg = RTK_LPAR; 284 break; 285 case MII_PHYIDR1: 286 case MII_PHYIDR2: 287 splx(s); 288 return 0; 289 /* 290 * Allow the rlphy driver to read the media status 291 * register. If we have a link partner which does not 292 * support NWAY, this is the register which will tell 293 * us the results of parallel detection. 294 */ 295 case RTK_MEDIASTAT: 296 rval = CSR_READ_1(sc, RTK_MEDIASTAT); 297 splx(s); 298 return rval; 299 default: 300 printf("%s: bad phy register\n", device_xname(sc->sc_dev)); 301 splx(s); 302 return 0; 303 } 304 rval = CSR_READ_2(sc, re8139_reg); 305 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0 && re8139_reg == RTK_BMCR) { 306 /* 8139C+ has different bit layout. */ 307 rval &= ~(BMCR_LOOP | BMCR_ISO); 308 } 309 splx(s); 310 return rval; 311 } 312 313 static void 314 re_miibus_writereg(device_t dev, int phy, int reg, int data) 315 { 316 struct rtk_softc *sc = device_private(dev); 317 uint16_t re8139_reg = 0; 318 int s; 319 320 s = splnet(); 321 322 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 323 re_gmii_writereg(dev, phy, reg, data); 324 splx(s); 325 return; 326 } 327 328 /* Pretend the internal PHY is only at address 0 */ 329 if (phy) { 330 splx(s); 331 return; 332 } 333 switch (reg) { 334 case MII_BMCR: 335 re8139_reg = RTK_BMCR; 336 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) { 337 /* 8139C+ has different bit layout. */ 338 data &= ~(BMCR_LOOP | BMCR_ISO); 339 } 340 break; 341 case MII_BMSR: 342 re8139_reg = RTK_BMSR; 343 break; 344 case MII_ANAR: 345 re8139_reg = RTK_ANAR; 346 break; 347 case MII_ANER: 348 re8139_reg = RTK_ANER; 349 break; 350 case MII_ANLPAR: 351 re8139_reg = RTK_LPAR; 352 break; 353 case MII_PHYIDR1: 354 case MII_PHYIDR2: 355 splx(s); 356 return; 357 break; 358 default: 359 printf("%s: bad phy register\n", device_xname(sc->sc_dev)); 360 splx(s); 361 return; 362 } 363 CSR_WRITE_2(sc, re8139_reg, data); 364 splx(s); 365 return; 366 } 367 368 static void 369 re_miibus_statchg(device_t dev) 370 { 371 372 return; 373 } 374 375 static void 376 re_reset(struct rtk_softc *sc) 377 { 378 int i; 379 380 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 381 382 for (i = 0; i < RTK_TIMEOUT; i++) { 383 DELAY(10); 384 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0) 385 break; 386 } 387 if (i == RTK_TIMEOUT) 388 printf("%s: reset never completed!\n", 389 device_xname(sc->sc_dev)); 390 391 /* 392 * NB: Realtek-supplied Linux driver does this only for 393 * MCFG_METHOD_2, which corresponds to sc->sc_rev == 3. 394 */ 395 if (1) /* XXX check softc flag for 8169s version */ 396 CSR_WRITE_1(sc, RTK_LDPS, 1); 397 398 } 399 400 /* 401 * The following routine is designed to test for a defect on some 402 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 403 * lines connected to the bus, however for a 32-bit only card, they 404 * should be pulled high. The result of this defect is that the 405 * NIC will not work right if you plug it into a 64-bit slot: DMA 406 * operations will be done with 64-bit transfers, which will fail 407 * because the 64-bit data lines aren't connected. 408 * 409 * There's no way to work around this (short of talking a soldering 410 * iron to the board), however we can detect it. The method we use 411 * here is to put the NIC into digital loopback mode, set the receiver 412 * to promiscuous mode, and then try to send a frame. We then compare 413 * the frame data we sent to what was received. If the data matches, 414 * then the NIC is working correctly, otherwise we know the user has 415 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 416 * slot. In the latter case, there's no way the NIC can work correctly, 417 * so we print out a message on the console and abort the device attach. 418 */ 419 420 int 421 re_diag(struct rtk_softc *sc) 422 { 423 struct ifnet *ifp = &sc->ethercom.ec_if; 424 struct mbuf *m0; 425 struct ether_header *eh; 426 struct re_rxsoft *rxs; 427 struct re_desc *cur_rx; 428 bus_dmamap_t dmamap; 429 uint16_t status; 430 uint32_t rxstat; 431 int total_len, i, s, error = 0; 432 static const uint8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 433 static const uint8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 434 435 /* Allocate a single mbuf */ 436 437 MGETHDR(m0, M_DONTWAIT, MT_DATA); 438 if (m0 == NULL) 439 return ENOBUFS; 440 441 /* 442 * Initialize the NIC in test mode. This sets the chip up 443 * so that it can send and receive frames, but performs the 444 * following special functions: 445 * - Puts receiver in promiscuous mode 446 * - Enables digital loopback mode 447 * - Leaves interrupts turned off 448 */ 449 450 ifp->if_flags |= IFF_PROMISC; 451 sc->re_testmode = 1; 452 re_init(ifp); 453 re_stop(ifp, 0); 454 DELAY(100000); 455 re_init(ifp); 456 457 /* Put some data in the mbuf */ 458 459 eh = mtod(m0, struct ether_header *); 460 memcpy(eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN); 461 memcpy(eh->ether_shost, (char *)&src, ETHER_ADDR_LEN); 462 eh->ether_type = htons(ETHERTYPE_IP); 463 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 464 465 /* 466 * Queue the packet, start transmission. 467 */ 468 469 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF); 470 s = splnet(); 471 IF_ENQUEUE(&ifp->if_snd, m0); 472 re_start(ifp); 473 splx(s); 474 m0 = NULL; 475 476 /* Wait for it to propagate through the chip */ 477 478 DELAY(100000); 479 for (i = 0; i < RTK_TIMEOUT; i++) { 480 status = CSR_READ_2(sc, RTK_ISR); 481 if ((status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) == 482 (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) 483 break; 484 DELAY(10); 485 } 486 if (i == RTK_TIMEOUT) { 487 aprint_error_dev(sc->sc_dev, 488 "diagnostic failed, failed to receive packet " 489 "in loopback mode\n"); 490 error = EIO; 491 goto done; 492 } 493 494 /* 495 * The packet should have been dumped into the first 496 * entry in the RX DMA ring. Grab it from there. 497 */ 498 499 rxs = &sc->re_ldata.re_rxsoft[0]; 500 dmamap = rxs->rxs_dmamap; 501 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 502 BUS_DMASYNC_POSTREAD); 503 bus_dmamap_unload(sc->sc_dmat, dmamap); 504 505 m0 = rxs->rxs_mbuf; 506 rxs->rxs_mbuf = NULL; 507 eh = mtod(m0, struct ether_header *); 508 509 RE_RXDESCSYNC(sc, 0, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 510 cur_rx = &sc->re_ldata.re_rx_list[0]; 511 rxstat = le32toh(cur_rx->re_cmdstat); 512 total_len = rxstat & sc->re_rxlenmask; 513 514 if (total_len != ETHER_MIN_LEN) { 515 aprint_error_dev(sc->sc_dev, 516 "diagnostic failed, received short packet\n"); 517 error = EIO; 518 goto done; 519 } 520 521 /* Test that the received packet data matches what we sent. */ 522 523 if (memcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 524 memcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 525 ntohs(eh->ether_type) != ETHERTYPE_IP) { 526 aprint_error_dev(sc->sc_dev, "WARNING, DMA FAILURE!\n" 527 "expected TX data: %s/%s/0x%x\n" 528 "received RX data: %s/%s/0x%x\n" 529 "You may have a defective 32-bit NIC plugged " 530 "into a 64-bit PCI slot.\n" 531 "Please re-install the NIC in a 32-bit slot " 532 "for proper operation.\n" 533 "Read the re(4) man page for more details.\n" , 534 ether_sprintf(dst), ether_sprintf(src), ETHERTYPE_IP, 535 ether_sprintf(eh->ether_dhost), 536 ether_sprintf(eh->ether_shost), ntohs(eh->ether_type)); 537 error = EIO; 538 } 539 540 done: 541 /* Turn interface off, release resources */ 542 543 sc->re_testmode = 0; 544 ifp->if_flags &= ~IFF_PROMISC; 545 re_stop(ifp, 0); 546 if (m0 != NULL) 547 m_freem(m0); 548 549 return error; 550 } 551 552 553 /* 554 * Attach the interface. Allocate softc structures, do ifmedia 555 * setup and ethernet/BPF attach. 556 */ 557 void 558 re_attach(struct rtk_softc *sc) 559 { 560 uint8_t eaddr[ETHER_ADDR_LEN]; 561 uint16_t val; 562 struct ifnet *ifp; 563 int error = 0, i, addr_len; 564 565 /* Reset the adapter. */ 566 re_reset(sc); 567 568 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 569 uint32_t hwrev; 570 571 /* Revision of 8169/8169S/8110s in bits 30..26, 23 */ 572 hwrev = CSR_READ_4(sc, RTK_TXCFG) & RTK_TXCFG_HWREV; 573 /* These rev numbers are taken from Realtek's driver */ 574 switch (hwrev) { 575 case RTK_HWREV_8169: 576 /* XXX not in the Realtek driver */ 577 sc->sc_rev = 1; 578 sc->sc_quirk |= RTKQ_8169NONS; 579 break; 580 case RTK_HWREV_8169S: 581 case RTK_HWREV_8110S: 582 sc->sc_rev = 3; 583 break; 584 case RTK_HWREV_8169_8110SB: 585 sc->sc_rev = 4; 586 break; 587 case RTK_HWREV_8169_8110SC: 588 sc->sc_rev = 5; 589 break; 590 case RTK_HWREV_8101E: 591 sc->sc_rev = 11; 592 break; 593 case RTK_HWREV_8168_SPIN1: 594 sc->sc_rev = 21; 595 break; 596 case RTK_HWREV_8168_SPIN2: 597 sc->sc_rev = 22; 598 break; 599 case RTK_HWREV_8168_SPIN3: 600 sc->sc_rev = 23; 601 break; 602 case RTK_HWREV_8168C: 603 case RTK_HWREV_8168C_SPIN2: 604 sc->sc_rev = 24; 605 break; 606 case RTK_HWREV_8102E: 607 case RTK_HWREV_8102EL: 608 sc->sc_rev = 25; 609 break; 610 case RTK_HWREV_8100E: 611 case RTK_HWREV_8100E_SPIN2: 612 /* XXX not in the Realtek driver */ 613 sc->sc_rev = 0; 614 break; 615 default: 616 aprint_normal_dev(sc->sc_dev, 617 "Unknown revision (0x%08x)\n", hwrev); 618 sc->sc_rev = 0; 619 } 620 621 /* Set RX length mask */ 622 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 623 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8169; 624 } else { 625 /* Set RX length mask */ 626 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 627 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8139; 628 } 629 630 if (sc->sc_rev == 24 || sc->sc_rev == 25) { 631 /* 632 * Get station address from ID registers. 633 */ 634 for (i = 0; i < ETHER_ADDR_LEN; i++) 635 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i); 636 } else { 637 /* 638 * Get station address from the EEPROM. 639 */ 640 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 641 addr_len = RTK_EEADDR_LEN1; 642 else 643 addr_len = RTK_EEADDR_LEN0; 644 645 /* 646 * Get station address from the EEPROM. 647 */ 648 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 649 val = rtk_read_eeprom(sc, RTK_EE_EADDR0 + i, addr_len); 650 eaddr[(i * 2) + 0] = val & 0xff; 651 eaddr[(i * 2) + 1] = val >> 8; 652 } 653 } 654 655 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 656 ether_sprintf(eaddr)); 657 658 if (sc->re_ldata.re_tx_desc_cnt > 659 PAGE_SIZE / sizeof(struct re_desc)) { 660 sc->re_ldata.re_tx_desc_cnt = 661 PAGE_SIZE / sizeof(struct re_desc); 662 } 663 664 aprint_verbose_dev(sc->sc_dev, "using %d tx descriptors\n", 665 sc->re_ldata.re_tx_desc_cnt); 666 KASSERT(RE_NEXT_TX_DESC(sc, RE_TX_DESC_CNT(sc) - 1) == 0); 667 668 /* Allocate DMA'able memory for the TX ring */ 669 if ((error = bus_dmamem_alloc(sc->sc_dmat, RE_TX_LIST_SZ(sc), 670 RE_RING_ALIGN, 0, &sc->re_ldata.re_tx_listseg, 1, 671 &sc->re_ldata.re_tx_listnseg, BUS_DMA_NOWAIT)) != 0) { 672 aprint_error_dev(sc->sc_dev, 673 "can't allocate tx listseg, error = %d\n", error); 674 goto fail_0; 675 } 676 677 /* Load the map for the TX ring. */ 678 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_tx_listseg, 679 sc->re_ldata.re_tx_listnseg, RE_TX_LIST_SZ(sc), 680 (void **)&sc->re_ldata.re_tx_list, 681 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) { 682 aprint_error_dev(sc->sc_dev, 683 "can't map tx list, error = %d\n", error); 684 goto fail_1; 685 } 686 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc)); 687 688 if ((error = bus_dmamap_create(sc->sc_dmat, RE_TX_LIST_SZ(sc), 1, 689 RE_TX_LIST_SZ(sc), 0, 0, 690 &sc->re_ldata.re_tx_list_map)) != 0) { 691 aprint_error_dev(sc->sc_dev, 692 "can't create tx list map, error = %d\n", error); 693 goto fail_2; 694 } 695 696 697 if ((error = bus_dmamap_load(sc->sc_dmat, 698 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list, 699 RE_TX_LIST_SZ(sc), NULL, BUS_DMA_NOWAIT)) != 0) { 700 aprint_error_dev(sc->sc_dev, 701 "can't load tx list, error = %d\n", error); 702 goto fail_3; 703 } 704 705 /* Create DMA maps for TX buffers */ 706 for (i = 0; i < RE_TX_QLEN; i++) { 707 error = bus_dmamap_create(sc->sc_dmat, 708 round_page(IP_MAXPACKET), 709 RE_TX_DESC_CNT(sc), RE_TDESC_CMD_FRAGLEN, 710 0, 0, &sc->re_ldata.re_txq[i].txq_dmamap); 711 if (error) { 712 aprint_error_dev(sc->sc_dev, 713 "can't create DMA map for TX\n"); 714 goto fail_4; 715 } 716 } 717 718 /* Allocate DMA'able memory for the RX ring */ 719 /* XXX see also a comment about RE_RX_DMAMEM_SZ in rtl81x9var.h */ 720 if ((error = bus_dmamem_alloc(sc->sc_dmat, 721 RE_RX_DMAMEM_SZ, RE_RING_ALIGN, 0, &sc->re_ldata.re_rx_listseg, 1, 722 &sc->re_ldata.re_rx_listnseg, BUS_DMA_NOWAIT)) != 0) { 723 aprint_error_dev(sc->sc_dev, 724 "can't allocate rx listseg, error = %d\n", error); 725 goto fail_4; 726 } 727 728 /* Load the map for the RX ring. */ 729 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_rx_listseg, 730 sc->re_ldata.re_rx_listnseg, RE_RX_DMAMEM_SZ, 731 (void **)&sc->re_ldata.re_rx_list, 732 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) { 733 aprint_error_dev(sc->sc_dev, 734 "can't map rx list, error = %d\n", error); 735 goto fail_5; 736 } 737 memset(sc->re_ldata.re_rx_list, 0, RE_RX_DMAMEM_SZ); 738 739 if ((error = bus_dmamap_create(sc->sc_dmat, 740 RE_RX_DMAMEM_SZ, 1, RE_RX_DMAMEM_SZ, 0, 0, 741 &sc->re_ldata.re_rx_list_map)) != 0) { 742 aprint_error_dev(sc->sc_dev, 743 "can't create rx list map, error = %d\n", error); 744 goto fail_6; 745 } 746 747 if ((error = bus_dmamap_load(sc->sc_dmat, 748 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list, 749 RE_RX_DMAMEM_SZ, NULL, BUS_DMA_NOWAIT)) != 0) { 750 aprint_error_dev(sc->sc_dev, 751 "can't load rx list, error = %d\n", error); 752 goto fail_7; 753 } 754 755 /* Create DMA maps for RX buffers */ 756 for (i = 0; i < RE_RX_DESC_CNT; i++) { 757 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 758 0, 0, &sc->re_ldata.re_rxsoft[i].rxs_dmamap); 759 if (error) { 760 aprint_error_dev(sc->sc_dev, 761 "can't create DMA map for RX\n"); 762 goto fail_8; 763 } 764 } 765 766 /* 767 * Record interface as attached. From here, we should not fail. 768 */ 769 sc->sc_flags |= RTK_ATTACHED; 770 771 ifp = &sc->ethercom.ec_if; 772 ifp->if_softc = sc; 773 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 774 ifp->if_mtu = ETHERMTU; 775 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 776 ifp->if_ioctl = re_ioctl; 777 sc->ethercom.ec_capabilities |= 778 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 779 ifp->if_start = re_start; 780 ifp->if_stop = re_stop; 781 782 /* 783 * IFCAP_CSUM_IPv4_Tx on re(4) is broken for small packets, 784 * so we have a workaround to handle the bug by padding 785 * such packets manually. 786 */ 787 ifp->if_capabilities |= 788 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 789 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 790 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 791 IFCAP_TSOv4; 792 ifp->if_watchdog = re_watchdog; 793 ifp->if_init = re_init; 794 ifp->if_snd.ifq_maxlen = RE_IFQ_MAXLEN; 795 ifp->if_capenable = ifp->if_capabilities; 796 IFQ_SET_READY(&ifp->if_snd); 797 798 callout_init(&sc->rtk_tick_ch, 0); 799 800 /* Do MII setup */ 801 sc->mii.mii_ifp = ifp; 802 sc->mii.mii_readreg = re_miibus_readreg; 803 sc->mii.mii_writereg = re_miibus_writereg; 804 sc->mii.mii_statchg = re_miibus_statchg; 805 sc->ethercom.ec_mii = &sc->mii; 806 ifmedia_init(&sc->mii.mii_media, IFM_IMASK, ether_mediachange, 807 ether_mediastatus); 808 mii_attach(sc->sc_dev, &sc->mii, 0xffffffff, MII_PHY_ANY, 809 MII_OFFSET_ANY, 0); 810 ifmedia_set(&sc->mii.mii_media, IFM_ETHER | IFM_AUTO); 811 812 /* 813 * Call MI attach routine. 814 */ 815 if_attach(ifp); 816 ether_ifattach(ifp, eaddr); 817 818 return; 819 820 fail_8: 821 /* Destroy DMA maps for RX buffers. */ 822 for (i = 0; i < RE_RX_DESC_CNT; i++) 823 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL) 824 bus_dmamap_destroy(sc->sc_dmat, 825 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 826 827 /* Free DMA'able memory for the RX ring. */ 828 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 829 fail_7: 830 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 831 fail_6: 832 bus_dmamem_unmap(sc->sc_dmat, 833 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ); 834 fail_5: 835 bus_dmamem_free(sc->sc_dmat, 836 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg); 837 838 fail_4: 839 /* Destroy DMA maps for TX buffers. */ 840 for (i = 0; i < RE_TX_QLEN; i++) 841 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL) 842 bus_dmamap_destroy(sc->sc_dmat, 843 sc->re_ldata.re_txq[i].txq_dmamap); 844 845 /* Free DMA'able memory for the TX ring. */ 846 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 847 fail_3: 848 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 849 fail_2: 850 bus_dmamem_unmap(sc->sc_dmat, 851 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 852 fail_1: 853 bus_dmamem_free(sc->sc_dmat, 854 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg); 855 fail_0: 856 return; 857 } 858 859 860 /* 861 * re_activate: 862 * Handle device activation/deactivation requests. 863 */ 864 int 865 re_activate(device_t self, enum devact act) 866 { 867 struct rtk_softc *sc = device_private(self); 868 int s, error = 0; 869 870 s = splnet(); 871 switch (act) { 872 case DVACT_ACTIVATE: 873 error = EOPNOTSUPP; 874 break; 875 case DVACT_DEACTIVATE: 876 mii_activate(&sc->mii, act, MII_PHY_ANY, MII_OFFSET_ANY); 877 if_deactivate(&sc->ethercom.ec_if); 878 break; 879 } 880 splx(s); 881 882 return error; 883 } 884 885 /* 886 * re_detach: 887 * Detach a rtk interface. 888 */ 889 int 890 re_detach(struct rtk_softc *sc) 891 { 892 struct ifnet *ifp = &sc->ethercom.ec_if; 893 int i; 894 895 /* 896 * Succeed now if there isn't any work to do. 897 */ 898 if ((sc->sc_flags & RTK_ATTACHED) == 0) 899 return 0; 900 901 /* Unhook our tick handler. */ 902 callout_stop(&sc->rtk_tick_ch); 903 904 /* Detach all PHYs. */ 905 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 906 907 /* Delete all remaining media. */ 908 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY); 909 910 ether_ifdetach(ifp); 911 if_detach(ifp); 912 913 /* Destroy DMA maps for RX buffers. */ 914 for (i = 0; i < RE_RX_DESC_CNT; i++) 915 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL) 916 bus_dmamap_destroy(sc->sc_dmat, 917 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 918 919 /* Free DMA'able memory for the RX ring. */ 920 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 921 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 922 bus_dmamem_unmap(sc->sc_dmat, 923 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ); 924 bus_dmamem_free(sc->sc_dmat, 925 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg); 926 927 /* Destroy DMA maps for TX buffers. */ 928 for (i = 0; i < RE_TX_QLEN; i++) 929 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL) 930 bus_dmamap_destroy(sc->sc_dmat, 931 sc->re_ldata.re_txq[i].txq_dmamap); 932 933 /* Free DMA'able memory for the TX ring. */ 934 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 935 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 936 bus_dmamem_unmap(sc->sc_dmat, 937 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 938 bus_dmamem_free(sc->sc_dmat, 939 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg); 940 941 return 0; 942 } 943 944 /* 945 * re_enable: 946 * Enable the RTL81X9 chip. 947 */ 948 static int 949 re_enable(struct rtk_softc *sc) 950 { 951 952 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 953 if ((*sc->sc_enable)(sc) != 0) { 954 printf("%s: device enable failed\n", 955 device_xname(sc->sc_dev)); 956 return EIO; 957 } 958 sc->sc_flags |= RTK_ENABLED; 959 } 960 return 0; 961 } 962 963 /* 964 * re_disable: 965 * Disable the RTL81X9 chip. 966 */ 967 static void 968 re_disable(struct rtk_softc *sc) 969 { 970 971 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 972 (*sc->sc_disable)(sc); 973 sc->sc_flags &= ~RTK_ENABLED; 974 } 975 } 976 977 static int 978 re_newbuf(struct rtk_softc *sc, int idx, struct mbuf *m) 979 { 980 struct mbuf *n = NULL; 981 bus_dmamap_t map; 982 struct re_desc *d; 983 struct re_rxsoft *rxs; 984 uint32_t cmdstat; 985 int error; 986 987 if (m == NULL) { 988 MGETHDR(n, M_DONTWAIT, MT_DATA); 989 if (n == NULL) 990 return ENOBUFS; 991 992 MCLGET(n, M_DONTWAIT); 993 if ((n->m_flags & M_EXT) == 0) { 994 m_freem(n); 995 return ENOBUFS; 996 } 997 m = n; 998 } else 999 m->m_data = m->m_ext.ext_buf; 1000 1001 /* 1002 * Initialize mbuf length fields and fixup 1003 * alignment so that the frame payload is 1004 * longword aligned. 1005 */ 1006 m->m_len = m->m_pkthdr.len = MCLBYTES - RE_ETHER_ALIGN; 1007 m->m_data += RE_ETHER_ALIGN; 1008 1009 rxs = &sc->re_ldata.re_rxsoft[idx]; 1010 map = rxs->rxs_dmamap; 1011 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1012 BUS_DMA_READ|BUS_DMA_NOWAIT); 1013 1014 if (error) 1015 goto out; 1016 1017 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1018 BUS_DMASYNC_PREREAD); 1019 1020 d = &sc->re_ldata.re_rx_list[idx]; 1021 #ifdef DIAGNOSTIC 1022 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1023 cmdstat = le32toh(d->re_cmdstat); 1024 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1025 if (cmdstat & RE_RDESC_STAT_OWN) { 1026 panic("%s: tried to map busy RX descriptor", 1027 device_xname(sc->sc_dev)); 1028 } 1029 #endif 1030 1031 rxs->rxs_mbuf = m; 1032 1033 d->re_vlanctl = 0; 1034 cmdstat = map->dm_segs[0].ds_len; 1035 if (idx == (RE_RX_DESC_CNT - 1)) 1036 cmdstat |= RE_RDESC_CMD_EOR; 1037 re_set_bufaddr(d, map->dm_segs[0].ds_addr); 1038 d->re_cmdstat = htole32(cmdstat); 1039 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1040 cmdstat |= RE_RDESC_CMD_OWN; 1041 d->re_cmdstat = htole32(cmdstat); 1042 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1043 1044 return 0; 1045 out: 1046 if (n != NULL) 1047 m_freem(n); 1048 return ENOMEM; 1049 } 1050 1051 static int 1052 re_tx_list_init(struct rtk_softc *sc) 1053 { 1054 int i; 1055 1056 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc)); 1057 for (i = 0; i < RE_TX_QLEN; i++) { 1058 sc->re_ldata.re_txq[i].txq_mbuf = NULL; 1059 } 1060 1061 bus_dmamap_sync(sc->sc_dmat, 1062 sc->re_ldata.re_tx_list_map, 0, 1063 sc->re_ldata.re_tx_list_map->dm_mapsize, 1064 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1065 sc->re_ldata.re_txq_prodidx = 0; 1066 sc->re_ldata.re_txq_considx = 0; 1067 sc->re_ldata.re_txq_free = RE_TX_QLEN; 1068 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT(sc); 1069 sc->re_ldata.re_tx_nextfree = 0; 1070 1071 return 0; 1072 } 1073 1074 static int 1075 re_rx_list_init(struct rtk_softc *sc) 1076 { 1077 int i; 1078 1079 memset(sc->re_ldata.re_rx_list, 0, RE_RX_LIST_SZ); 1080 1081 for (i = 0; i < RE_RX_DESC_CNT; i++) { 1082 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1083 return ENOBUFS; 1084 } 1085 1086 sc->re_ldata.re_rx_prodidx = 0; 1087 sc->re_head = sc->re_tail = NULL; 1088 1089 return 0; 1090 } 1091 1092 /* 1093 * RX handler for C+ and 8169. For the gigE chips, we support 1094 * the reception of jumbo frames that have been fragmented 1095 * across multiple 2K mbuf cluster buffers. 1096 */ 1097 static void 1098 re_rxeof(struct rtk_softc *sc) 1099 { 1100 struct mbuf *m; 1101 struct ifnet *ifp; 1102 int i, total_len; 1103 struct re_desc *cur_rx; 1104 struct re_rxsoft *rxs; 1105 uint32_t rxstat, rxvlan; 1106 1107 ifp = &sc->ethercom.ec_if; 1108 1109 for (i = sc->re_ldata.re_rx_prodidx;; i = RE_NEXT_RX_DESC(sc, i)) { 1110 cur_rx = &sc->re_ldata.re_rx_list[i]; 1111 RE_RXDESCSYNC(sc, i, 1112 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1113 rxstat = le32toh(cur_rx->re_cmdstat); 1114 rxvlan = le32toh(cur_rx->re_vlanctl); 1115 RE_RXDESCSYNC(sc, i, BUS_DMASYNC_PREREAD); 1116 if ((rxstat & RE_RDESC_STAT_OWN) != 0) { 1117 break; 1118 } 1119 total_len = rxstat & sc->re_rxlenmask; 1120 rxs = &sc->re_ldata.re_rxsoft[i]; 1121 m = rxs->rxs_mbuf; 1122 1123 /* Invalidate the RX mbuf and unload its map */ 1124 1125 bus_dmamap_sync(sc->sc_dmat, 1126 rxs->rxs_dmamap, 0, rxs->rxs_dmamap->dm_mapsize, 1127 BUS_DMASYNC_POSTREAD); 1128 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1129 1130 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1131 m->m_len = MCLBYTES - RE_ETHER_ALIGN; 1132 if (sc->re_head == NULL) 1133 sc->re_head = sc->re_tail = m; 1134 else { 1135 m->m_flags &= ~M_PKTHDR; 1136 sc->re_tail->m_next = m; 1137 sc->re_tail = m; 1138 } 1139 re_newbuf(sc, i, NULL); 1140 continue; 1141 } 1142 1143 /* 1144 * NOTE: for the 8139C+, the frame length field 1145 * is always 12 bits in size, but for the gigE chips, 1146 * it is 13 bits (since the max RX frame length is 16K). 1147 * Unfortunately, all 32 bits in the status word 1148 * were already used, so to make room for the extra 1149 * length bit, RealTek took out the 'frame alignment 1150 * error' bit and shifted the other status bits 1151 * over one slot. The OWN, EOR, FS and LS bits are 1152 * still in the same places. We have already extracted 1153 * the frame length and checked the OWN bit, so rather 1154 * than using an alternate bit mapping, we shift the 1155 * status bits one space to the right so we can evaluate 1156 * them using the 8169 status as though it was in the 1157 * same format as that of the 8139C+. 1158 */ 1159 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) 1160 rxstat >>= 1; 1161 1162 if (__predict_false((rxstat & RE_RDESC_STAT_RXERRSUM) != 0)) { 1163 #ifdef RE_DEBUG 1164 printf("%s: RX error (rxstat = 0x%08x)", 1165 device_xname(sc->sc_dev), rxstat); 1166 if (rxstat & RE_RDESC_STAT_FRALIGN) 1167 printf(", frame alignment error"); 1168 if (rxstat & RE_RDESC_STAT_BUFOFLOW) 1169 printf(", out of buffer space"); 1170 if (rxstat & RE_RDESC_STAT_FIFOOFLOW) 1171 printf(", FIFO overrun"); 1172 if (rxstat & RE_RDESC_STAT_GIANT) 1173 printf(", giant packet"); 1174 if (rxstat & RE_RDESC_STAT_RUNT) 1175 printf(", runt packet"); 1176 if (rxstat & RE_RDESC_STAT_CRCERR) 1177 printf(", CRC error"); 1178 printf("\n"); 1179 #endif 1180 ifp->if_ierrors++; 1181 /* 1182 * If this is part of a multi-fragment packet, 1183 * discard all the pieces. 1184 */ 1185 if (sc->re_head != NULL) { 1186 m_freem(sc->re_head); 1187 sc->re_head = sc->re_tail = NULL; 1188 } 1189 re_newbuf(sc, i, m); 1190 continue; 1191 } 1192 1193 /* 1194 * If allocating a replacement mbuf fails, 1195 * reload the current one. 1196 */ 1197 1198 if (__predict_false(re_newbuf(sc, i, NULL) != 0)) { 1199 ifp->if_ierrors++; 1200 if (sc->re_head != NULL) { 1201 m_freem(sc->re_head); 1202 sc->re_head = sc->re_tail = NULL; 1203 } 1204 re_newbuf(sc, i, m); 1205 continue; 1206 } 1207 1208 if (sc->re_head != NULL) { 1209 m->m_len = total_len % (MCLBYTES - RE_ETHER_ALIGN); 1210 /* 1211 * Special case: if there's 4 bytes or less 1212 * in this buffer, the mbuf can be discarded: 1213 * the last 4 bytes is the CRC, which we don't 1214 * care about anyway. 1215 */ 1216 if (m->m_len <= ETHER_CRC_LEN) { 1217 sc->re_tail->m_len -= 1218 (ETHER_CRC_LEN - m->m_len); 1219 m_freem(m); 1220 } else { 1221 m->m_len -= ETHER_CRC_LEN; 1222 m->m_flags &= ~M_PKTHDR; 1223 sc->re_tail->m_next = m; 1224 } 1225 m = sc->re_head; 1226 sc->re_head = sc->re_tail = NULL; 1227 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1228 } else 1229 m->m_pkthdr.len = m->m_len = 1230 (total_len - ETHER_CRC_LEN); 1231 1232 ifp->if_ipackets++; 1233 m->m_pkthdr.rcvif = ifp; 1234 1235 /* Do RX checksumming */ 1236 1237 /* Check IP header checksum */ 1238 if (rxstat & RE_RDESC_STAT_PROTOID) { 1239 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1240 if (rxstat & RE_RDESC_STAT_IPSUMBAD) 1241 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1242 } 1243 1244 /* Check TCP/UDP checksum */ 1245 if (RE_TCPPKT(rxstat)) { 1246 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1247 if (rxstat & RE_RDESC_STAT_TCPSUMBAD) 1248 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1249 } else if (RE_UDPPKT(rxstat)) { 1250 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1251 if (rxstat & RE_RDESC_STAT_UDPSUMBAD) 1252 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1253 } 1254 1255 if (rxvlan & RE_RDESC_VLANCTL_TAG) { 1256 VLAN_INPUT_TAG(ifp, m, 1257 bswap16(rxvlan & RE_RDESC_VLANCTL_DATA), 1258 continue); 1259 } 1260 #if NBPFILTER > 0 1261 if (ifp->if_bpf) 1262 bpf_mtap(ifp->if_bpf, m); 1263 #endif 1264 (*ifp->if_input)(ifp, m); 1265 } 1266 1267 sc->re_ldata.re_rx_prodidx = i; 1268 } 1269 1270 static void 1271 re_txeof(struct rtk_softc *sc) 1272 { 1273 struct ifnet *ifp; 1274 struct re_txq *txq; 1275 uint32_t txstat; 1276 int idx, descidx; 1277 1278 ifp = &sc->ethercom.ec_if; 1279 1280 for (idx = sc->re_ldata.re_txq_considx; 1281 sc->re_ldata.re_txq_free < RE_TX_QLEN; 1282 idx = RE_NEXT_TXQ(sc, idx), sc->re_ldata.re_txq_free++) { 1283 txq = &sc->re_ldata.re_txq[idx]; 1284 KASSERT(txq->txq_mbuf != NULL); 1285 1286 descidx = txq->txq_descidx; 1287 RE_TXDESCSYNC(sc, descidx, 1288 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1289 txstat = 1290 le32toh(sc->re_ldata.re_tx_list[descidx].re_cmdstat); 1291 RE_TXDESCSYNC(sc, descidx, BUS_DMASYNC_PREREAD); 1292 KASSERT((txstat & RE_TDESC_CMD_EOF) != 0); 1293 if (txstat & RE_TDESC_CMD_OWN) { 1294 break; 1295 } 1296 1297 sc->re_ldata.re_tx_free += txq->txq_nsegs; 1298 KASSERT(sc->re_ldata.re_tx_free <= RE_TX_DESC_CNT(sc)); 1299 bus_dmamap_sync(sc->sc_dmat, txq->txq_dmamap, 1300 0, txq->txq_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1301 bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap); 1302 m_freem(txq->txq_mbuf); 1303 txq->txq_mbuf = NULL; 1304 1305 if (txstat & (RE_TDESC_STAT_EXCESSCOL | RE_TDESC_STAT_COLCNT)) 1306 ifp->if_collisions++; 1307 if (txstat & RE_TDESC_STAT_TXERRSUM) 1308 ifp->if_oerrors++; 1309 else 1310 ifp->if_opackets++; 1311 } 1312 1313 sc->re_ldata.re_txq_considx = idx; 1314 1315 if (sc->re_ldata.re_txq_free > RE_NTXDESC_RSVD) 1316 ifp->if_flags &= ~IFF_OACTIVE; 1317 1318 /* 1319 * If not all descriptors have been released reaped yet, 1320 * reload the timer so that we will eventually get another 1321 * interrupt that will cause us to re-enter this routine. 1322 * This is done in case the transmitter has gone idle. 1323 */ 1324 if (sc->re_ldata.re_txq_free < RE_TX_QLEN) { 1325 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1326 if ((sc->sc_quirk & RTKQ_PCIE) != 0) { 1327 /* 1328 * Some chips will ignore a second TX request 1329 * issued while an existing transmission is in 1330 * progress. If the transmitter goes idle but 1331 * there are still packets waiting to be sent, 1332 * we need to restart the channel here to flush 1333 * them out. This only seems to be required with 1334 * the PCIe devices. 1335 */ 1336 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START); 1337 } 1338 } else 1339 ifp->if_timer = 0; 1340 } 1341 1342 static void 1343 re_tick(void *arg) 1344 { 1345 struct rtk_softc *sc = arg; 1346 int s; 1347 1348 /*XXX: just return for 8169S/8110S with rev 2 or newer phy */ 1349 s = splnet(); 1350 1351 mii_tick(&sc->mii); 1352 splx(s); 1353 1354 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1355 } 1356 1357 int 1358 re_intr(void *arg) 1359 { 1360 struct rtk_softc *sc = arg; 1361 struct ifnet *ifp; 1362 uint16_t status; 1363 int handled = 0; 1364 1365 if (!device_has_power(sc->sc_dev)) 1366 return 0; 1367 1368 ifp = &sc->ethercom.ec_if; 1369 1370 if ((ifp->if_flags & IFF_UP) == 0) 1371 return 0; 1372 1373 for (;;) { 1374 1375 status = CSR_READ_2(sc, RTK_ISR); 1376 /* If the card has gone away the read returns 0xffff. */ 1377 if (status == 0xffff) 1378 break; 1379 if (status) { 1380 handled = 1; 1381 CSR_WRITE_2(sc, RTK_ISR, status); 1382 } 1383 1384 if ((status & RTK_INTRS_CPLUS) == 0) 1385 break; 1386 1387 if (status & (RTK_ISR_RX_OK | RTK_ISR_RX_ERR)) 1388 re_rxeof(sc); 1389 1390 if (status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_TX_ERR | 1391 RTK_ISR_TX_DESC_UNAVAIL)) 1392 re_txeof(sc); 1393 1394 if (status & RTK_ISR_SYSTEM_ERR) { 1395 re_init(ifp); 1396 } 1397 1398 if (status & RTK_ISR_LINKCHG) { 1399 callout_stop(&sc->rtk_tick_ch); 1400 re_tick(sc); 1401 } 1402 } 1403 1404 if (handled && !IFQ_IS_EMPTY(&ifp->if_snd)) 1405 re_start(ifp); 1406 1407 return handled; 1408 } 1409 1410 1411 1412 /* 1413 * Main transmit routine for C+ and gigE NICs. 1414 */ 1415 1416 static void 1417 re_start(struct ifnet *ifp) 1418 { 1419 struct rtk_softc *sc; 1420 struct mbuf *m; 1421 bus_dmamap_t map; 1422 struct re_txq *txq; 1423 struct re_desc *d; 1424 struct m_tag *mtag; 1425 uint32_t cmdstat, re_flags, vlanctl; 1426 int ofree, idx, error, nsegs, seg; 1427 int startdesc, curdesc, lastdesc; 1428 bool pad; 1429 1430 sc = ifp->if_softc; 1431 ofree = sc->re_ldata.re_txq_free; 1432 1433 for (idx = sc->re_ldata.re_txq_prodidx;; idx = RE_NEXT_TXQ(sc, idx)) { 1434 1435 IFQ_POLL(&ifp->if_snd, m); 1436 if (m == NULL) 1437 break; 1438 1439 if (sc->re_ldata.re_txq_free == 0 || 1440 sc->re_ldata.re_tx_free == 0) { 1441 /* no more free slots left */ 1442 ifp->if_flags |= IFF_OACTIVE; 1443 break; 1444 } 1445 1446 /* 1447 * Set up checksum offload. Note: checksum offload bits must 1448 * appear in all descriptors of a multi-descriptor transmit 1449 * attempt. (This is according to testing done with an 8169 1450 * chip. I'm not sure if this is a requirement or a bug.) 1451 */ 1452 1453 if ((m->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0) { 1454 uint32_t segsz = m->m_pkthdr.segsz; 1455 1456 re_flags = RE_TDESC_CMD_LGSEND | 1457 (segsz << RE_TDESC_CMD_MSSVAL_SHIFT); 1458 } else { 1459 /* 1460 * set RE_TDESC_CMD_IPCSUM if any checksum offloading 1461 * is requested. otherwise, RE_TDESC_CMD_TCPCSUM/ 1462 * RE_TDESC_CMD_UDPCSUM doesn't make effects. 1463 */ 1464 re_flags = 0; 1465 if ((m->m_pkthdr.csum_flags & 1466 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1467 != 0) { 1468 re_flags |= RE_TDESC_CMD_IPCSUM; 1469 if (m->m_pkthdr.csum_flags & M_CSUM_TCPv4) { 1470 re_flags |= RE_TDESC_CMD_TCPCSUM; 1471 } else if (m->m_pkthdr.csum_flags & 1472 M_CSUM_UDPv4) { 1473 re_flags |= RE_TDESC_CMD_UDPCSUM; 1474 } 1475 } 1476 } 1477 1478 txq = &sc->re_ldata.re_txq[idx]; 1479 map = txq->txq_dmamap; 1480 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1481 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1482 1483 if (__predict_false(error)) { 1484 /* XXX try to defrag if EFBIG? */ 1485 printf("%s: can't map mbuf (error %d)\n", 1486 device_xname(sc->sc_dev), error); 1487 1488 IFQ_DEQUEUE(&ifp->if_snd, m); 1489 m_freem(m); 1490 ifp->if_oerrors++; 1491 continue; 1492 } 1493 1494 nsegs = map->dm_nsegs; 1495 pad = false; 1496 if (__predict_false(m->m_pkthdr.len <= RE_IP4CSUMTX_PADLEN && 1497 (re_flags & RE_TDESC_CMD_IPCSUM) != 0)) { 1498 pad = true; 1499 nsegs++; 1500 } 1501 1502 if (nsegs > sc->re_ldata.re_tx_free) { 1503 /* 1504 * Not enough free descriptors to transmit this packet. 1505 */ 1506 ifp->if_flags |= IFF_OACTIVE; 1507 bus_dmamap_unload(sc->sc_dmat, map); 1508 break; 1509 } 1510 1511 IFQ_DEQUEUE(&ifp->if_snd, m); 1512 1513 /* 1514 * Make sure that the caches are synchronized before we 1515 * ask the chip to start DMA for the packet data. 1516 */ 1517 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1518 BUS_DMASYNC_PREWRITE); 1519 1520 /* 1521 * Set up hardware VLAN tagging. Note: vlan tag info must 1522 * appear in all descriptors of a multi-descriptor 1523 * transmission attempt. 1524 */ 1525 vlanctl = 0; 1526 if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m)) != NULL) 1527 vlanctl = bswap16(VLAN_TAG_VALUE(mtag)) | 1528 RE_TDESC_VLANCTL_TAG; 1529 1530 /* 1531 * Map the segment array into descriptors. 1532 * Note that we set the start-of-frame and 1533 * end-of-frame markers for either TX or RX, 1534 * but they really only have meaning in the TX case. 1535 * (In the RX case, it's the chip that tells us 1536 * where packets begin and end.) 1537 * We also keep track of the end of the ring 1538 * and set the end-of-ring bits as needed, 1539 * and we set the ownership bits in all except 1540 * the very first descriptor. (The caller will 1541 * set this descriptor later when it start 1542 * transmission or reception.) 1543 */ 1544 curdesc = startdesc = sc->re_ldata.re_tx_nextfree; 1545 lastdesc = -1; 1546 for (seg = 0; seg < map->dm_nsegs; 1547 seg++, curdesc = RE_NEXT_TX_DESC(sc, curdesc)) { 1548 d = &sc->re_ldata.re_tx_list[curdesc]; 1549 #ifdef DIAGNOSTIC 1550 RE_TXDESCSYNC(sc, curdesc, 1551 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1552 cmdstat = le32toh(d->re_cmdstat); 1553 RE_TXDESCSYNC(sc, curdesc, BUS_DMASYNC_PREREAD); 1554 if (cmdstat & RE_TDESC_STAT_OWN) { 1555 panic("%s: tried to map busy TX descriptor", 1556 device_xname(sc->sc_dev)); 1557 } 1558 #endif 1559 1560 d->re_vlanctl = htole32(vlanctl); 1561 re_set_bufaddr(d, map->dm_segs[seg].ds_addr); 1562 cmdstat = re_flags | map->dm_segs[seg].ds_len; 1563 if (seg == 0) 1564 cmdstat |= RE_TDESC_CMD_SOF; 1565 else 1566 cmdstat |= RE_TDESC_CMD_OWN; 1567 if (curdesc == (RE_TX_DESC_CNT(sc) - 1)) 1568 cmdstat |= RE_TDESC_CMD_EOR; 1569 if (seg == nsegs - 1) { 1570 cmdstat |= RE_TDESC_CMD_EOF; 1571 lastdesc = curdesc; 1572 } 1573 d->re_cmdstat = htole32(cmdstat); 1574 RE_TXDESCSYNC(sc, curdesc, 1575 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1576 } 1577 if (__predict_false(pad)) { 1578 bus_addr_t paddaddr; 1579 1580 d = &sc->re_ldata.re_tx_list[curdesc]; 1581 d->re_vlanctl = htole32(vlanctl); 1582 paddaddr = RE_TXPADDADDR(sc); 1583 re_set_bufaddr(d, paddaddr); 1584 cmdstat = re_flags | 1585 RE_TDESC_CMD_OWN | RE_TDESC_CMD_EOF | 1586 (RE_IP4CSUMTX_PADLEN + 1 - m->m_pkthdr.len); 1587 if (curdesc == (RE_TX_DESC_CNT(sc) - 1)) 1588 cmdstat |= RE_TDESC_CMD_EOR; 1589 d->re_cmdstat = htole32(cmdstat); 1590 RE_TXDESCSYNC(sc, curdesc, 1591 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1592 lastdesc = curdesc; 1593 curdesc = RE_NEXT_TX_DESC(sc, curdesc); 1594 } 1595 KASSERT(lastdesc != -1); 1596 1597 /* Transfer ownership of packet to the chip. */ 1598 1599 sc->re_ldata.re_tx_list[startdesc].re_cmdstat |= 1600 htole32(RE_TDESC_CMD_OWN); 1601 RE_TXDESCSYNC(sc, startdesc, 1602 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1603 1604 /* update info of TX queue and descriptors */ 1605 txq->txq_mbuf = m; 1606 txq->txq_descidx = lastdesc; 1607 txq->txq_nsegs = nsegs; 1608 1609 sc->re_ldata.re_txq_free--; 1610 sc->re_ldata.re_tx_free -= nsegs; 1611 sc->re_ldata.re_tx_nextfree = curdesc; 1612 1613 #if NBPFILTER > 0 1614 /* 1615 * If there's a BPF listener, bounce a copy of this frame 1616 * to him. 1617 */ 1618 if (ifp->if_bpf) 1619 bpf_mtap(ifp->if_bpf, m); 1620 #endif 1621 } 1622 1623 if (sc->re_ldata.re_txq_free < ofree) { 1624 /* 1625 * TX packets are enqueued. 1626 */ 1627 sc->re_ldata.re_txq_prodidx = idx; 1628 1629 /* 1630 * Start the transmitter to poll. 1631 * 1632 * RealTek put the TX poll request register in a different 1633 * location on the 8169 gigE chip. I don't know why. 1634 */ 1635 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) 1636 CSR_WRITE_1(sc, RTK_TXSTART, RTK_TXSTART_START); 1637 else 1638 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START); 1639 1640 /* 1641 * Use the countdown timer for interrupt moderation. 1642 * 'TX done' interrupts are disabled. Instead, we reset the 1643 * countdown timer, which will begin counting until it hits 1644 * the value in the TIMERINT register, and then trigger an 1645 * interrupt. Each time we write to the TIMERCNT register, 1646 * the timer count is reset to 0. 1647 */ 1648 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1649 1650 /* 1651 * Set a timeout in case the chip goes out to lunch. 1652 */ 1653 ifp->if_timer = 5; 1654 } 1655 } 1656 1657 static int 1658 re_init(struct ifnet *ifp) 1659 { 1660 struct rtk_softc *sc = ifp->if_softc; 1661 const uint8_t *enaddr; 1662 uint32_t rxcfg = 0; 1663 uint32_t reg; 1664 int error; 1665 1666 if ((error = re_enable(sc)) != 0) 1667 goto out; 1668 1669 /* 1670 * Cancel pending I/O and free all RX/TX buffers. 1671 */ 1672 re_stop(ifp, 0); 1673 1674 re_reset(sc); 1675 1676 /* 1677 * Enable C+ RX and TX mode, as well as VLAN stripping and 1678 * RX checksum offload. We must configure the C+ register 1679 * before all others. 1680 */ 1681 reg = 0; 1682 1683 /* 1684 * XXX: Realtek docs say bits 0 and 1 are reserved, for 8169S/8110S. 1685 * FreeBSD drivers set these bits anyway (for 8139C+?). 1686 * So far, it works. 1687 */ 1688 1689 /* 1690 * XXX: For old 8169 set bit 14. 1691 * For 8169S/8110S and above, do not set bit 14. 1692 */ 1693 if ((sc->sc_quirk & RTKQ_8169NONS) != 0) 1694 reg |= (0x1 << 14) | RTK_CPLUSCMD_PCI_MRW; 1695 1696 if (1) {/* not for 8169S ? */ 1697 reg |= 1698 RTK_CPLUSCMD_VLANSTRIP | 1699 (ifp->if_capenable & 1700 (IFCAP_CSUM_IPv4_Rx | IFCAP_CSUM_TCPv4_Rx | 1701 IFCAP_CSUM_UDPv4_Rx) ? 1702 RTK_CPLUSCMD_RXCSUM_ENB : 0); 1703 } 1704 1705 CSR_WRITE_2(sc, RTK_CPLUS_CMD, 1706 reg | RTK_CPLUSCMD_RXENB | RTK_CPLUSCMD_TXENB); 1707 1708 /* XXX: from Realtek-supplied Linux driver. Wholly undocumented. */ 1709 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) 1710 CSR_WRITE_2(sc, RTK_IM, 0x0000); 1711 1712 DELAY(10000); 1713 1714 /* 1715 * Init our MAC address. Even though the chipset 1716 * documentation doesn't mention it, we need to enter "Config 1717 * register write enable" mode to modify the ID registers. 1718 */ 1719 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_WRITECFG); 1720 enaddr = CLLADDR(ifp->if_sadl); 1721 reg = enaddr[0] | (enaddr[1] << 8) | 1722 (enaddr[2] << 16) | (enaddr[3] << 24); 1723 CSR_WRITE_4(sc, RTK_IDR0, reg); 1724 reg = enaddr[4] | (enaddr[5] << 8); 1725 CSR_WRITE_4(sc, RTK_IDR4, reg); 1726 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 1727 1728 /* 1729 * For C+ mode, initialize the RX descriptors and mbufs. 1730 */ 1731 re_rx_list_init(sc); 1732 re_tx_list_init(sc); 1733 1734 /* 1735 * Load the addresses of the RX and TX lists into the chip. 1736 */ 1737 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_HI, 1738 RE_ADDR_HI(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr)); 1739 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_LO, 1740 RE_ADDR_LO(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr)); 1741 1742 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_HI, 1743 RE_ADDR_HI(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr)); 1744 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_LO, 1745 RE_ADDR_LO(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr)); 1746 1747 /* 1748 * Enable transmit and receive. 1749 */ 1750 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1751 1752 /* 1753 * Set the initial TX and RX configuration. 1754 */ 1755 if (sc->re_testmode && (sc->sc_quirk & RTKQ_8169NONS) != 0) { 1756 /* test mode is needed only for old 8169 */ 1757 CSR_WRITE_4(sc, RTK_TXCFG, 1758 RE_TXCFG_CONFIG | RTK_LOOPTEST_ON); 1759 } else 1760 CSR_WRITE_4(sc, RTK_TXCFG, RE_TXCFG_CONFIG); 1761 1762 CSR_WRITE_1(sc, RTK_EARLY_TX_THRESH, 16); 1763 1764 CSR_WRITE_4(sc, RTK_RXCFG, RE_RXCFG_CONFIG); 1765 1766 /* Set the individual bit to receive frames for this host only. */ 1767 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 1768 rxcfg |= RTK_RXCFG_RX_INDIV; 1769 1770 /* If we want promiscuous mode, set the allframes bit. */ 1771 if (ifp->if_flags & IFF_PROMISC) 1772 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 1773 else 1774 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 1775 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1776 1777 /* 1778 * Set capture broadcast bit to capture broadcast frames. 1779 */ 1780 if (ifp->if_flags & IFF_BROADCAST) 1781 rxcfg |= RTK_RXCFG_RX_BROAD; 1782 else 1783 rxcfg &= ~RTK_RXCFG_RX_BROAD; 1784 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1785 1786 /* 1787 * Program the multicast filter, if necessary. 1788 */ 1789 rtk_setmulti(sc); 1790 1791 /* 1792 * Enable interrupts. 1793 */ 1794 if (sc->re_testmode) 1795 CSR_WRITE_2(sc, RTK_IMR, 0); 1796 else 1797 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS); 1798 1799 /* Start RX/TX process. */ 1800 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 1801 #ifdef notdef 1802 /* Enable receiver and transmitter. */ 1803 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1804 #endif 1805 1806 /* 1807 * Initialize the timer interrupt register so that 1808 * a timer interrupt will be generated once the timer 1809 * reaches a certain number of ticks. The timer is 1810 * reloaded on each transmit. This gives us TX interrupt 1811 * moderation, which dramatically improves TX frame rate. 1812 */ 1813 1814 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) 1815 CSR_WRITE_4(sc, RTK_TIMERINT, 0x400); 1816 else { 1817 CSR_WRITE_4(sc, RTK_TIMERINT_8169, 0x800); 1818 1819 /* 1820 * For 8169 gigE NICs, set the max allowed RX packet 1821 * size so we can receive jumbo frames. 1822 */ 1823 CSR_WRITE_2(sc, RTK_MAXRXPKTLEN, 16383); 1824 } 1825 1826 if (sc->re_testmode) 1827 return 0; 1828 1829 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD); 1830 1831 ifp->if_flags |= IFF_RUNNING; 1832 ifp->if_flags &= ~IFF_OACTIVE; 1833 1834 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1835 1836 out: 1837 if (error) { 1838 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1839 ifp->if_timer = 0; 1840 printf("%s: interface not running\n", 1841 device_xname(sc->sc_dev)); 1842 } 1843 1844 return error; 1845 } 1846 1847 static int 1848 re_ioctl(struct ifnet *ifp, u_long command, void *data) 1849 { 1850 struct rtk_softc *sc = ifp->if_softc; 1851 struct ifreq *ifr = data; 1852 int s, error = 0; 1853 1854 s = splnet(); 1855 1856 switch (command) { 1857 case SIOCSIFMTU: 1858 /* 1859 * According to FreeBSD, 8102E/8102EL use a different DMA 1860 * descriptor format. 8168C/8111C requires touching additional 1861 * magic registers. Depending on MAC revisions some controllers 1862 * need to disable checksum offload. 1863 * 1864 * Disable jumbo frames for those parts. 1865 */ 1866 if ((sc->sc_rev == 24 || sc->sc_rev == 25) && 1867 ifr->ifr_mtu > ETHERMTU) { 1868 error = EINVAL; 1869 break; 1870 } 1871 1872 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO) 1873 error = EINVAL; 1874 else if ((error = ifioctl_common(ifp, command, data)) == 1875 ENETRESET) 1876 error = 0; 1877 break; 1878 default: 1879 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1880 break; 1881 1882 error = 0; 1883 1884 if (command == SIOCSIFCAP) 1885 error = (*ifp->if_init)(ifp); 1886 else if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1887 ; 1888 else if (ifp->if_flags & IFF_RUNNING) 1889 rtk_setmulti(sc); 1890 break; 1891 } 1892 1893 splx(s); 1894 1895 return error; 1896 } 1897 1898 static void 1899 re_watchdog(struct ifnet *ifp) 1900 { 1901 struct rtk_softc *sc; 1902 int s; 1903 1904 sc = ifp->if_softc; 1905 s = splnet(); 1906 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1907 ifp->if_oerrors++; 1908 1909 re_txeof(sc); 1910 re_rxeof(sc); 1911 1912 re_init(ifp); 1913 1914 splx(s); 1915 } 1916 1917 /* 1918 * Stop the adapter and free any mbufs allocated to the 1919 * RX and TX lists. 1920 */ 1921 static void 1922 re_stop(struct ifnet *ifp, int disable) 1923 { 1924 int i; 1925 struct rtk_softc *sc = ifp->if_softc; 1926 1927 callout_stop(&sc->rtk_tick_ch); 1928 1929 mii_down(&sc->mii); 1930 1931 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 1932 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1933 1934 if (sc->re_head != NULL) { 1935 m_freem(sc->re_head); 1936 sc->re_head = sc->re_tail = NULL; 1937 } 1938 1939 /* Free the TX list buffers. */ 1940 for (i = 0; i < RE_TX_QLEN; i++) { 1941 if (sc->re_ldata.re_txq[i].txq_mbuf != NULL) { 1942 bus_dmamap_unload(sc->sc_dmat, 1943 sc->re_ldata.re_txq[i].txq_dmamap); 1944 m_freem(sc->re_ldata.re_txq[i].txq_mbuf); 1945 sc->re_ldata.re_txq[i].txq_mbuf = NULL; 1946 } 1947 } 1948 1949 /* Free the RX list buffers. */ 1950 for (i = 0; i < RE_RX_DESC_CNT; i++) { 1951 if (sc->re_ldata.re_rxsoft[i].rxs_mbuf != NULL) { 1952 bus_dmamap_unload(sc->sc_dmat, 1953 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 1954 m_freem(sc->re_ldata.re_rxsoft[i].rxs_mbuf); 1955 sc->re_ldata.re_rxsoft[i].rxs_mbuf = NULL; 1956 } 1957 } 1958 1959 if (disable) 1960 re_disable(sc); 1961 1962 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1963 ifp->if_timer = 0; 1964 } 1965