1 /* $NetBSD: rtl8169.c,v 1.113 2009/03/28 22:16:08 tsutsui Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998-2003 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 __KERNEL_RCSID(0, "$NetBSD: rtl8169.c,v 1.113 2009/03/28 22:16:08 tsutsui Exp $"); 37 /* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */ 38 39 /* 40 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 41 * 42 * Written by Bill Paul <wpaul@windriver.com> 43 * Senior Networking Software Engineer 44 * Wind River Systems 45 */ 46 47 /* 48 * This driver is designed to support RealTek's next generation of 49 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 50 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 51 * and the RTL8110S. 52 * 53 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 54 * with the older 8139 family, however it also supports a special 55 * C+ mode of operation that provides several new performance enhancing 56 * features. These include: 57 * 58 * o Descriptor based DMA mechanism. Each descriptor represents 59 * a single packet fragment. Data buffers may be aligned on 60 * any byte boundary. 61 * 62 * o 64-bit DMA 63 * 64 * o TCP/IP checksum offload for both RX and TX 65 * 66 * o High and normal priority transmit DMA rings 67 * 68 * o VLAN tag insertion and extraction 69 * 70 * o TCP large send (segmentation offload) 71 * 72 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 73 * programming API is fairly straightforward. The RX filtering, EEPROM 74 * access and PHY access is the same as it is on the older 8139 series 75 * chips. 76 * 77 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 78 * same programming API and feature set as the 8139C+ with the following 79 * differences and additions: 80 * 81 * o 1000Mbps mode 82 * 83 * o Jumbo frames 84 * 85 * o GMII and TBI ports/registers for interfacing with copper 86 * or fiber PHYs 87 * 88 * o RX and TX DMA rings can have up to 1024 descriptors 89 * (the 8139C+ allows a maximum of 64) 90 * 91 * o Slight differences in register layout from the 8139C+ 92 * 93 * The TX start and timer interrupt registers are at different locations 94 * on the 8169 than they are on the 8139C+. Also, the status word in the 95 * RX descriptor has a slightly different bit layout. The 8169 does not 96 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 97 * copper gigE PHY. 98 * 99 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 100 * (the 'S' stands for 'single-chip'). These devices have the same 101 * programming API as the older 8169, but also have some vendor-specific 102 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 103 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 104 * 105 * This driver takes advantage of the RX and TX checksum offload and 106 * VLAN tag insertion/extraction features. It also implements TX 107 * interrupt moderation using the timer interrupt registers, which 108 * significantly reduces TX interrupt load. There is also support 109 * for jumbo frames, however the 8169/8169S/8110S can not transmit 110 * jumbo frames larger than 7.5K, so the max MTU possible with this 111 * driver is 7500 bytes. 112 */ 113 114 #include "bpfilter.h" 115 #include "vlan.h" 116 117 #include <sys/param.h> 118 #include <sys/endian.h> 119 #include <sys/systm.h> 120 #include <sys/sockio.h> 121 #include <sys/mbuf.h> 122 #include <sys/malloc.h> 123 #include <sys/kernel.h> 124 #include <sys/socket.h> 125 #include <sys/device.h> 126 127 #include <net/if.h> 128 #include <net/if_arp.h> 129 #include <net/if_dl.h> 130 #include <net/if_ether.h> 131 #include <net/if_media.h> 132 #include <net/if_vlanvar.h> 133 134 #include <netinet/in_systm.h> /* XXX for IP_MAXPACKET */ 135 #include <netinet/in.h> /* XXX for IP_MAXPACKET */ 136 #include <netinet/ip.h> /* XXX for IP_MAXPACKET */ 137 138 #if NBPFILTER > 0 139 #include <net/bpf.h> 140 #endif 141 142 #include <sys/bus.h> 143 144 #include <dev/mii/mii.h> 145 #include <dev/mii/miivar.h> 146 147 #include <dev/ic/rtl81x9reg.h> 148 #include <dev/ic/rtl81x9var.h> 149 150 #include <dev/ic/rtl8169var.h> 151 152 static inline void re_set_bufaddr(struct re_desc *, bus_addr_t); 153 154 static int re_newbuf(struct rtk_softc *, int, struct mbuf *); 155 static int re_rx_list_init(struct rtk_softc *); 156 static int re_tx_list_init(struct rtk_softc *); 157 static void re_rxeof(struct rtk_softc *); 158 static void re_txeof(struct rtk_softc *); 159 static void re_tick(void *); 160 static void re_start(struct ifnet *); 161 static int re_ioctl(struct ifnet *, u_long, void *); 162 static int re_init(struct ifnet *); 163 static void re_stop(struct ifnet *, int); 164 static void re_watchdog(struct ifnet *); 165 166 static int re_enable(struct rtk_softc *); 167 static void re_disable(struct rtk_softc *); 168 169 static int re_gmii_readreg(struct device *, int, int); 170 static void re_gmii_writereg(struct device *, int, int, int); 171 172 static int re_miibus_readreg(struct device *, int, int); 173 static void re_miibus_writereg(struct device *, int, int, int); 174 static void re_miibus_statchg(struct device *); 175 176 static void re_reset(struct rtk_softc *); 177 178 static inline void 179 re_set_bufaddr(struct re_desc *d, bus_addr_t addr) 180 { 181 182 d->re_bufaddr_lo = htole32((uint32_t)addr); 183 if (sizeof(bus_addr_t) == sizeof(uint64_t)) 184 d->re_bufaddr_hi = htole32((uint64_t)addr >> 32); 185 else 186 d->re_bufaddr_hi = 0; 187 } 188 189 static int 190 re_gmii_readreg(device_t dev, int phy, int reg) 191 { 192 struct rtk_softc *sc = device_private(dev); 193 uint32_t rval; 194 int i; 195 196 if (phy != 7) 197 return 0; 198 199 /* Let the rgephy driver read the GMEDIASTAT register */ 200 201 if (reg == RTK_GMEDIASTAT) { 202 rval = CSR_READ_1(sc, RTK_GMEDIASTAT); 203 return rval; 204 } 205 206 CSR_WRITE_4(sc, RTK_PHYAR, reg << 16); 207 DELAY(1000); 208 209 for (i = 0; i < RTK_TIMEOUT; i++) { 210 rval = CSR_READ_4(sc, RTK_PHYAR); 211 if (rval & RTK_PHYAR_BUSY) 212 break; 213 DELAY(100); 214 } 215 216 if (i == RTK_TIMEOUT) { 217 printf("%s: PHY read failed\n", device_xname(sc->sc_dev)); 218 return 0; 219 } 220 221 return rval & RTK_PHYAR_PHYDATA; 222 } 223 224 static void 225 re_gmii_writereg(device_t dev, int phy, int reg, int data) 226 { 227 struct rtk_softc *sc = device_private(dev); 228 uint32_t rval; 229 int i; 230 231 CSR_WRITE_4(sc, RTK_PHYAR, (reg << 16) | 232 (data & RTK_PHYAR_PHYDATA) | RTK_PHYAR_BUSY); 233 DELAY(1000); 234 235 for (i = 0; i < RTK_TIMEOUT; i++) { 236 rval = CSR_READ_4(sc, RTK_PHYAR); 237 if (!(rval & RTK_PHYAR_BUSY)) 238 break; 239 DELAY(100); 240 } 241 242 if (i == RTK_TIMEOUT) { 243 printf("%s: PHY write reg %x <- %x failed\n", 244 device_xname(sc->sc_dev), reg, data); 245 } 246 } 247 248 static int 249 re_miibus_readreg(device_t dev, int phy, int reg) 250 { 251 struct rtk_softc *sc = device_private(dev); 252 uint16_t rval = 0; 253 uint16_t re8139_reg = 0; 254 int s; 255 256 s = splnet(); 257 258 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 259 rval = re_gmii_readreg(dev, phy, reg); 260 splx(s); 261 return rval; 262 } 263 264 /* Pretend the internal PHY is only at address 0 */ 265 if (phy) { 266 splx(s); 267 return 0; 268 } 269 switch (reg) { 270 case MII_BMCR: 271 re8139_reg = RTK_BMCR; 272 break; 273 case MII_BMSR: 274 re8139_reg = RTK_BMSR; 275 break; 276 case MII_ANAR: 277 re8139_reg = RTK_ANAR; 278 break; 279 case MII_ANER: 280 re8139_reg = RTK_ANER; 281 break; 282 case MII_ANLPAR: 283 re8139_reg = RTK_LPAR; 284 break; 285 case MII_PHYIDR1: 286 case MII_PHYIDR2: 287 splx(s); 288 return 0; 289 /* 290 * Allow the rlphy driver to read the media status 291 * register. If we have a link partner which does not 292 * support NWAY, this is the register which will tell 293 * us the results of parallel detection. 294 */ 295 case RTK_MEDIASTAT: 296 rval = CSR_READ_1(sc, RTK_MEDIASTAT); 297 splx(s); 298 return rval; 299 default: 300 printf("%s: bad phy register\n", device_xname(sc->sc_dev)); 301 splx(s); 302 return 0; 303 } 304 rval = CSR_READ_2(sc, re8139_reg); 305 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0 && re8139_reg == RTK_BMCR) { 306 /* 8139C+ has different bit layout. */ 307 rval &= ~(BMCR_LOOP | BMCR_ISO); 308 } 309 splx(s); 310 return rval; 311 } 312 313 static void 314 re_miibus_writereg(device_t dev, int phy, int reg, int data) 315 { 316 struct rtk_softc *sc = device_private(dev); 317 uint16_t re8139_reg = 0; 318 int s; 319 320 s = splnet(); 321 322 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 323 re_gmii_writereg(dev, phy, reg, data); 324 splx(s); 325 return; 326 } 327 328 /* Pretend the internal PHY is only at address 0 */ 329 if (phy) { 330 splx(s); 331 return; 332 } 333 switch (reg) { 334 case MII_BMCR: 335 re8139_reg = RTK_BMCR; 336 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) { 337 /* 8139C+ has different bit layout. */ 338 data &= ~(BMCR_LOOP | BMCR_ISO); 339 } 340 break; 341 case MII_BMSR: 342 re8139_reg = RTK_BMSR; 343 break; 344 case MII_ANAR: 345 re8139_reg = RTK_ANAR; 346 break; 347 case MII_ANER: 348 re8139_reg = RTK_ANER; 349 break; 350 case MII_ANLPAR: 351 re8139_reg = RTK_LPAR; 352 break; 353 case MII_PHYIDR1: 354 case MII_PHYIDR2: 355 splx(s); 356 return; 357 break; 358 default: 359 printf("%s: bad phy register\n", device_xname(sc->sc_dev)); 360 splx(s); 361 return; 362 } 363 CSR_WRITE_2(sc, re8139_reg, data); 364 splx(s); 365 return; 366 } 367 368 static void 369 re_miibus_statchg(device_t dev) 370 { 371 372 return; 373 } 374 375 static void 376 re_reset(struct rtk_softc *sc) 377 { 378 int i; 379 380 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 381 382 for (i = 0; i < RTK_TIMEOUT; i++) { 383 DELAY(10); 384 if ((CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET) == 0) 385 break; 386 } 387 if (i == RTK_TIMEOUT) 388 printf("%s: reset never completed!\n", 389 device_xname(sc->sc_dev)); 390 391 /* 392 * NB: Realtek-supplied FreeBSD driver does this only for MACFG_3, 393 * but also says "Rtl8169s sigle chip detected". 394 */ 395 if ((sc->sc_quirk & RTKQ_MACLDPS) != 0) 396 CSR_WRITE_1(sc, RTK_LDPS, 1); 397 398 } 399 400 /* 401 * The following routine is designed to test for a defect on some 402 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 403 * lines connected to the bus, however for a 32-bit only card, they 404 * should be pulled high. The result of this defect is that the 405 * NIC will not work right if you plug it into a 64-bit slot: DMA 406 * operations will be done with 64-bit transfers, which will fail 407 * because the 64-bit data lines aren't connected. 408 * 409 * There's no way to work around this (short of talking a soldering 410 * iron to the board), however we can detect it. The method we use 411 * here is to put the NIC into digital loopback mode, set the receiver 412 * to promiscuous mode, and then try to send a frame. We then compare 413 * the frame data we sent to what was received. If the data matches, 414 * then the NIC is working correctly, otherwise we know the user has 415 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 416 * slot. In the latter case, there's no way the NIC can work correctly, 417 * so we print out a message on the console and abort the device attach. 418 */ 419 420 int 421 re_diag(struct rtk_softc *sc) 422 { 423 struct ifnet *ifp = &sc->ethercom.ec_if; 424 struct mbuf *m0; 425 struct ether_header *eh; 426 struct re_rxsoft *rxs; 427 struct re_desc *cur_rx; 428 bus_dmamap_t dmamap; 429 uint16_t status; 430 uint32_t rxstat; 431 int total_len, i, s, error = 0; 432 static const uint8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 433 static const uint8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 434 435 /* Allocate a single mbuf */ 436 437 MGETHDR(m0, M_DONTWAIT, MT_DATA); 438 if (m0 == NULL) 439 return ENOBUFS; 440 441 /* 442 * Initialize the NIC in test mode. This sets the chip up 443 * so that it can send and receive frames, but performs the 444 * following special functions: 445 * - Puts receiver in promiscuous mode 446 * - Enables digital loopback mode 447 * - Leaves interrupts turned off 448 */ 449 450 ifp->if_flags |= IFF_PROMISC; 451 sc->re_testmode = 1; 452 re_init(ifp); 453 re_stop(ifp, 0); 454 DELAY(100000); 455 re_init(ifp); 456 457 /* Put some data in the mbuf */ 458 459 eh = mtod(m0, struct ether_header *); 460 memcpy(eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN); 461 memcpy(eh->ether_shost, (char *)&src, ETHER_ADDR_LEN); 462 eh->ether_type = htons(ETHERTYPE_IP); 463 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 464 465 /* 466 * Queue the packet, start transmission. 467 */ 468 469 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF); 470 s = splnet(); 471 IF_ENQUEUE(&ifp->if_snd, m0); 472 re_start(ifp); 473 splx(s); 474 m0 = NULL; 475 476 /* Wait for it to propagate through the chip */ 477 478 DELAY(100000); 479 for (i = 0; i < RTK_TIMEOUT; i++) { 480 status = CSR_READ_2(sc, RTK_ISR); 481 if ((status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) == 482 (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) 483 break; 484 DELAY(10); 485 } 486 if (i == RTK_TIMEOUT) { 487 aprint_error_dev(sc->sc_dev, 488 "diagnostic failed, failed to receive packet " 489 "in loopback mode\n"); 490 error = EIO; 491 goto done; 492 } 493 494 /* 495 * The packet should have been dumped into the first 496 * entry in the RX DMA ring. Grab it from there. 497 */ 498 499 rxs = &sc->re_ldata.re_rxsoft[0]; 500 dmamap = rxs->rxs_dmamap; 501 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 502 BUS_DMASYNC_POSTREAD); 503 bus_dmamap_unload(sc->sc_dmat, dmamap); 504 505 m0 = rxs->rxs_mbuf; 506 rxs->rxs_mbuf = NULL; 507 eh = mtod(m0, struct ether_header *); 508 509 RE_RXDESCSYNC(sc, 0, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 510 cur_rx = &sc->re_ldata.re_rx_list[0]; 511 rxstat = le32toh(cur_rx->re_cmdstat); 512 total_len = rxstat & sc->re_rxlenmask; 513 514 if (total_len != ETHER_MIN_LEN) { 515 aprint_error_dev(sc->sc_dev, 516 "diagnostic failed, received short packet\n"); 517 error = EIO; 518 goto done; 519 } 520 521 /* Test that the received packet data matches what we sent. */ 522 523 if (memcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 524 memcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 525 ntohs(eh->ether_type) != ETHERTYPE_IP) { 526 aprint_error_dev(sc->sc_dev, "WARNING, DMA FAILURE!\n" 527 "expected TX data: %s/%s/0x%x\n" 528 "received RX data: %s/%s/0x%x\n" 529 "You may have a defective 32-bit NIC plugged " 530 "into a 64-bit PCI slot.\n" 531 "Please re-install the NIC in a 32-bit slot " 532 "for proper operation.\n" 533 "Read the re(4) man page for more details.\n" , 534 ether_sprintf(dst), ether_sprintf(src), ETHERTYPE_IP, 535 ether_sprintf(eh->ether_dhost), 536 ether_sprintf(eh->ether_shost), ntohs(eh->ether_type)); 537 error = EIO; 538 } 539 540 done: 541 /* Turn interface off, release resources */ 542 543 sc->re_testmode = 0; 544 ifp->if_flags &= ~IFF_PROMISC; 545 re_stop(ifp, 0); 546 if (m0 != NULL) 547 m_freem(m0); 548 549 return error; 550 } 551 552 553 /* 554 * Attach the interface. Allocate softc structures, do ifmedia 555 * setup and ethernet/BPF attach. 556 */ 557 void 558 re_attach(struct rtk_softc *sc) 559 { 560 uint8_t eaddr[ETHER_ADDR_LEN]; 561 uint16_t val; 562 struct ifnet *ifp; 563 int error = 0, i, addr_len; 564 565 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) { 566 uint32_t hwrev; 567 568 /* Revision of 8169/8169S/8110s in bits 30..26, 23 */ 569 hwrev = CSR_READ_4(sc, RTK_TXCFG) & RTK_TXCFG_HWREV; 570 /* These rev numbers are taken from Realtek's driver */ 571 switch (hwrev) { 572 case RTK_HWREV_8169: 573 /* XXX not in the Realtek driver */ 574 sc->sc_rev = 1; 575 sc->sc_quirk |= RTKQ_8169NONS; 576 break; 577 case RTK_HWREV_8169S: 578 case RTK_HWREV_8110S: 579 sc->sc_rev = 3; 580 sc->sc_quirk |= RTKQ_MACLDPS; 581 break; 582 case RTK_HWREV_8169_8110SB: 583 sc->sc_rev = 4; 584 sc->sc_quirk |= RTKQ_MACLDPS; 585 break; 586 case RTK_HWREV_8169_8110SC: 587 sc->sc_rev = 5; 588 sc->sc_quirk |= RTKQ_MACLDPS; 589 break; 590 case RTK_HWREV_8101E: 591 sc->sc_rev = 11; 592 sc->sc_quirk |= RTKQ_NOJUMBO; 593 break; 594 case RTK_HWREV_8168_SPIN1: 595 sc->sc_rev = 21; 596 break; 597 case RTK_HWREV_8168_SPIN2: 598 sc->sc_rev = 22; 599 break; 600 case RTK_HWREV_8168_SPIN3: 601 sc->sc_rev = 23; 602 break; 603 case RTK_HWREV_8168C: 604 case RTK_HWREV_8168C_SPIN2: 605 sc->sc_rev = 24; 606 sc->sc_quirk |= RTKQ_DESCV2 | RTKQ_NOEECMD; 607 /* 608 * From FreeBSD driver: 609 * 610 * These (8168/8111) controllers support jumbo frame 611 * but it seems that enabling it requires touching 612 * additional magic registers. Depending on MAC 613 * revisions some controllers need to disable 614 * checksum offload. So disable jumbo frame until 615 * I have better idea what it really requires to 616 * make it support. 617 * RTL8168C/CP : supports up to 6KB jumbo frame. 618 * RTL8111C/CP : supports up to 9KB jumbo frame. 619 */ 620 sc->sc_quirk |= RTKQ_NOJUMBO; 621 break; 622 case RTK_HWREV_8102E: 623 case RTK_HWREV_8102EL: 624 sc->sc_rev = 25; 625 sc->sc_quirk |= 626 RTKQ_DESCV2 | RTKQ_NOEECMD | RTKQ_NOJUMBO; 627 break; 628 case RTK_HWREV_8100E: 629 case RTK_HWREV_8100E_SPIN2: 630 /* XXX not in the Realtek driver */ 631 sc->sc_rev = 0; 632 sc->sc_quirk |= RTKQ_NOJUMBO; 633 break; 634 default: 635 aprint_normal_dev(sc->sc_dev, 636 "Unknown revision (0x%08x)\n", hwrev); 637 sc->sc_rev = 0; 638 } 639 640 /* Set RX length mask */ 641 sc->re_rxlenmask = RE_RDESC_STAT_GFRAGLEN; 642 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8169; 643 } else { 644 sc->sc_quirk |= RTKQ_NOJUMBO; 645 646 /* Set RX length mask */ 647 sc->re_rxlenmask = RE_RDESC_STAT_FRAGLEN; 648 sc->re_ldata.re_tx_desc_cnt = RE_TX_DESC_CNT_8139; 649 } 650 651 /* Reset the adapter. */ 652 re_reset(sc); 653 654 if ((sc->sc_quirk & RTKQ_NOEECMD) != 0) { 655 /* 656 * Get station address from ID registers. 657 */ 658 for (i = 0; i < ETHER_ADDR_LEN; i++) 659 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i); 660 } else { 661 /* 662 * Get station address from the EEPROM. 663 */ 664 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 665 addr_len = RTK_EEADDR_LEN1; 666 else 667 addr_len = RTK_EEADDR_LEN0; 668 669 /* 670 * Get station address from the EEPROM. 671 */ 672 for (i = 0; i < ETHER_ADDR_LEN / 2; i++) { 673 val = rtk_read_eeprom(sc, RTK_EE_EADDR0 + i, addr_len); 674 eaddr[(i * 2) + 0] = val & 0xff; 675 eaddr[(i * 2) + 1] = val >> 8; 676 } 677 } 678 679 aprint_normal_dev(sc->sc_dev, "Ethernet address %s\n", 680 ether_sprintf(eaddr)); 681 682 if (sc->re_ldata.re_tx_desc_cnt > 683 PAGE_SIZE / sizeof(struct re_desc)) { 684 sc->re_ldata.re_tx_desc_cnt = 685 PAGE_SIZE / sizeof(struct re_desc); 686 } 687 688 aprint_verbose_dev(sc->sc_dev, "using %d tx descriptors\n", 689 sc->re_ldata.re_tx_desc_cnt); 690 KASSERT(RE_NEXT_TX_DESC(sc, RE_TX_DESC_CNT(sc) - 1) == 0); 691 692 /* Allocate DMA'able memory for the TX ring */ 693 if ((error = bus_dmamem_alloc(sc->sc_dmat, RE_TX_LIST_SZ(sc), 694 RE_RING_ALIGN, 0, &sc->re_ldata.re_tx_listseg, 1, 695 &sc->re_ldata.re_tx_listnseg, BUS_DMA_NOWAIT)) != 0) { 696 aprint_error_dev(sc->sc_dev, 697 "can't allocate tx listseg, error = %d\n", error); 698 goto fail_0; 699 } 700 701 /* Load the map for the TX ring. */ 702 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_tx_listseg, 703 sc->re_ldata.re_tx_listnseg, RE_TX_LIST_SZ(sc), 704 (void **)&sc->re_ldata.re_tx_list, 705 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) { 706 aprint_error_dev(sc->sc_dev, 707 "can't map tx list, error = %d\n", error); 708 goto fail_1; 709 } 710 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc)); 711 712 if ((error = bus_dmamap_create(sc->sc_dmat, RE_TX_LIST_SZ(sc), 1, 713 RE_TX_LIST_SZ(sc), 0, 0, 714 &sc->re_ldata.re_tx_list_map)) != 0) { 715 aprint_error_dev(sc->sc_dev, 716 "can't create tx list map, error = %d\n", error); 717 goto fail_2; 718 } 719 720 721 if ((error = bus_dmamap_load(sc->sc_dmat, 722 sc->re_ldata.re_tx_list_map, sc->re_ldata.re_tx_list, 723 RE_TX_LIST_SZ(sc), NULL, BUS_DMA_NOWAIT)) != 0) { 724 aprint_error_dev(sc->sc_dev, 725 "can't load tx list, error = %d\n", error); 726 goto fail_3; 727 } 728 729 /* Create DMA maps for TX buffers */ 730 for (i = 0; i < RE_TX_QLEN; i++) { 731 error = bus_dmamap_create(sc->sc_dmat, 732 round_page(IP_MAXPACKET), 733 RE_TX_DESC_CNT(sc), RE_TDESC_CMD_FRAGLEN, 734 0, 0, &sc->re_ldata.re_txq[i].txq_dmamap); 735 if (error) { 736 aprint_error_dev(sc->sc_dev, 737 "can't create DMA map for TX\n"); 738 goto fail_4; 739 } 740 } 741 742 /* Allocate DMA'able memory for the RX ring */ 743 /* XXX see also a comment about RE_RX_DMAMEM_SZ in rtl81x9var.h */ 744 if ((error = bus_dmamem_alloc(sc->sc_dmat, 745 RE_RX_DMAMEM_SZ, RE_RING_ALIGN, 0, &sc->re_ldata.re_rx_listseg, 1, 746 &sc->re_ldata.re_rx_listnseg, BUS_DMA_NOWAIT)) != 0) { 747 aprint_error_dev(sc->sc_dev, 748 "can't allocate rx listseg, error = %d\n", error); 749 goto fail_4; 750 } 751 752 /* Load the map for the RX ring. */ 753 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->re_ldata.re_rx_listseg, 754 sc->re_ldata.re_rx_listnseg, RE_RX_DMAMEM_SZ, 755 (void **)&sc->re_ldata.re_rx_list, 756 BUS_DMA_COHERENT | BUS_DMA_NOWAIT)) != 0) { 757 aprint_error_dev(sc->sc_dev, 758 "can't map rx list, error = %d\n", error); 759 goto fail_5; 760 } 761 memset(sc->re_ldata.re_rx_list, 0, RE_RX_DMAMEM_SZ); 762 763 if ((error = bus_dmamap_create(sc->sc_dmat, 764 RE_RX_DMAMEM_SZ, 1, RE_RX_DMAMEM_SZ, 0, 0, 765 &sc->re_ldata.re_rx_list_map)) != 0) { 766 aprint_error_dev(sc->sc_dev, 767 "can't create rx list map, error = %d\n", error); 768 goto fail_6; 769 } 770 771 if ((error = bus_dmamap_load(sc->sc_dmat, 772 sc->re_ldata.re_rx_list_map, sc->re_ldata.re_rx_list, 773 RE_RX_DMAMEM_SZ, NULL, BUS_DMA_NOWAIT)) != 0) { 774 aprint_error_dev(sc->sc_dev, 775 "can't load rx list, error = %d\n", error); 776 goto fail_7; 777 } 778 779 /* Create DMA maps for RX buffers */ 780 for (i = 0; i < RE_RX_DESC_CNT; i++) { 781 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 782 0, 0, &sc->re_ldata.re_rxsoft[i].rxs_dmamap); 783 if (error) { 784 aprint_error_dev(sc->sc_dev, 785 "can't create DMA map for RX\n"); 786 goto fail_8; 787 } 788 } 789 790 /* 791 * Record interface as attached. From here, we should not fail. 792 */ 793 sc->sc_flags |= RTK_ATTACHED; 794 795 ifp = &sc->ethercom.ec_if; 796 ifp->if_softc = sc; 797 strlcpy(ifp->if_xname, device_xname(sc->sc_dev), IFNAMSIZ); 798 ifp->if_mtu = ETHERMTU; 799 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 800 ifp->if_ioctl = re_ioctl; 801 sc->ethercom.ec_capabilities |= 802 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 803 ifp->if_start = re_start; 804 ifp->if_stop = re_stop; 805 806 /* 807 * IFCAP_CSUM_IPv4_Tx on re(4) is broken for small packets, 808 * so we have a workaround to handle the bug by padding 809 * such packets manually. 810 */ 811 ifp->if_capabilities |= 812 IFCAP_CSUM_IPv4_Tx | IFCAP_CSUM_IPv4_Rx | 813 IFCAP_CSUM_TCPv4_Tx | IFCAP_CSUM_TCPv4_Rx | 814 IFCAP_CSUM_UDPv4_Tx | IFCAP_CSUM_UDPv4_Rx | 815 IFCAP_TSOv4; 816 817 /* 818 * XXX 819 * Still have no idea how to make TSO work on 8168C, 8168CP, 820 * 8102E, 8111C and 8111CP. 821 */ 822 if ((sc->sc_quirk & RTKQ_DESCV2) != 0) 823 ifp->if_capabilities &= ~IFCAP_TSOv4; 824 825 ifp->if_watchdog = re_watchdog; 826 ifp->if_init = re_init; 827 ifp->if_snd.ifq_maxlen = RE_IFQ_MAXLEN; 828 ifp->if_capenable = ifp->if_capabilities; 829 IFQ_SET_READY(&ifp->if_snd); 830 831 callout_init(&sc->rtk_tick_ch, 0); 832 833 /* Do MII setup */ 834 sc->mii.mii_ifp = ifp; 835 sc->mii.mii_readreg = re_miibus_readreg; 836 sc->mii.mii_writereg = re_miibus_writereg; 837 sc->mii.mii_statchg = re_miibus_statchg; 838 sc->ethercom.ec_mii = &sc->mii; 839 ifmedia_init(&sc->mii.mii_media, IFM_IMASK, ether_mediachange, 840 ether_mediastatus); 841 mii_attach(sc->sc_dev, &sc->mii, 0xffffffff, MII_PHY_ANY, 842 MII_OFFSET_ANY, 0); 843 ifmedia_set(&sc->mii.mii_media, IFM_ETHER | IFM_AUTO); 844 845 /* 846 * Call MI attach routine. 847 */ 848 if_attach(ifp); 849 ether_ifattach(ifp, eaddr); 850 851 return; 852 853 fail_8: 854 /* Destroy DMA maps for RX buffers. */ 855 for (i = 0; i < RE_RX_DESC_CNT; i++) 856 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL) 857 bus_dmamap_destroy(sc->sc_dmat, 858 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 859 860 /* Free DMA'able memory for the RX ring. */ 861 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 862 fail_7: 863 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 864 fail_6: 865 bus_dmamem_unmap(sc->sc_dmat, 866 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ); 867 fail_5: 868 bus_dmamem_free(sc->sc_dmat, 869 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg); 870 871 fail_4: 872 /* Destroy DMA maps for TX buffers. */ 873 for (i = 0; i < RE_TX_QLEN; i++) 874 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL) 875 bus_dmamap_destroy(sc->sc_dmat, 876 sc->re_ldata.re_txq[i].txq_dmamap); 877 878 /* Free DMA'able memory for the TX ring. */ 879 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 880 fail_3: 881 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 882 fail_2: 883 bus_dmamem_unmap(sc->sc_dmat, 884 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 885 fail_1: 886 bus_dmamem_free(sc->sc_dmat, 887 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg); 888 fail_0: 889 return; 890 } 891 892 893 /* 894 * re_activate: 895 * Handle device activation/deactivation requests. 896 */ 897 int 898 re_activate(device_t self, enum devact act) 899 { 900 struct rtk_softc *sc = device_private(self); 901 int s, error = 0; 902 903 s = splnet(); 904 switch (act) { 905 case DVACT_ACTIVATE: 906 error = EOPNOTSUPP; 907 break; 908 case DVACT_DEACTIVATE: 909 mii_activate(&sc->mii, act, MII_PHY_ANY, MII_OFFSET_ANY); 910 if_deactivate(&sc->ethercom.ec_if); 911 break; 912 } 913 splx(s); 914 915 return error; 916 } 917 918 /* 919 * re_detach: 920 * Detach a rtk interface. 921 */ 922 int 923 re_detach(struct rtk_softc *sc) 924 { 925 struct ifnet *ifp = &sc->ethercom.ec_if; 926 int i; 927 928 /* 929 * Succeed now if there isn't any work to do. 930 */ 931 if ((sc->sc_flags & RTK_ATTACHED) == 0) 932 return 0; 933 934 /* Unhook our tick handler. */ 935 callout_stop(&sc->rtk_tick_ch); 936 937 /* Detach all PHYs. */ 938 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 939 940 /* Delete all remaining media. */ 941 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY); 942 943 ether_ifdetach(ifp); 944 if_detach(ifp); 945 946 /* Destroy DMA maps for RX buffers. */ 947 for (i = 0; i < RE_RX_DESC_CNT; i++) 948 if (sc->re_ldata.re_rxsoft[i].rxs_dmamap != NULL) 949 bus_dmamap_destroy(sc->sc_dmat, 950 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 951 952 /* Free DMA'able memory for the RX ring. */ 953 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 954 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_rx_list_map); 955 bus_dmamem_unmap(sc->sc_dmat, 956 (void *)sc->re_ldata.re_rx_list, RE_RX_DMAMEM_SZ); 957 bus_dmamem_free(sc->sc_dmat, 958 &sc->re_ldata.re_rx_listseg, sc->re_ldata.re_rx_listnseg); 959 960 /* Destroy DMA maps for TX buffers. */ 961 for (i = 0; i < RE_TX_QLEN; i++) 962 if (sc->re_ldata.re_txq[i].txq_dmamap != NULL) 963 bus_dmamap_destroy(sc->sc_dmat, 964 sc->re_ldata.re_txq[i].txq_dmamap); 965 966 /* Free DMA'able memory for the TX ring. */ 967 bus_dmamap_unload(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 968 bus_dmamap_destroy(sc->sc_dmat, sc->re_ldata.re_tx_list_map); 969 bus_dmamem_unmap(sc->sc_dmat, 970 (void *)sc->re_ldata.re_tx_list, RE_TX_LIST_SZ(sc)); 971 bus_dmamem_free(sc->sc_dmat, 972 &sc->re_ldata.re_tx_listseg, sc->re_ldata.re_tx_listnseg); 973 974 return 0; 975 } 976 977 /* 978 * re_enable: 979 * Enable the RTL81X9 chip. 980 */ 981 static int 982 re_enable(struct rtk_softc *sc) 983 { 984 985 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 986 if ((*sc->sc_enable)(sc) != 0) { 987 printf("%s: device enable failed\n", 988 device_xname(sc->sc_dev)); 989 return EIO; 990 } 991 sc->sc_flags |= RTK_ENABLED; 992 } 993 return 0; 994 } 995 996 /* 997 * re_disable: 998 * Disable the RTL81X9 chip. 999 */ 1000 static void 1001 re_disable(struct rtk_softc *sc) 1002 { 1003 1004 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 1005 (*sc->sc_disable)(sc); 1006 sc->sc_flags &= ~RTK_ENABLED; 1007 } 1008 } 1009 1010 static int 1011 re_newbuf(struct rtk_softc *sc, int idx, struct mbuf *m) 1012 { 1013 struct mbuf *n = NULL; 1014 bus_dmamap_t map; 1015 struct re_desc *d; 1016 struct re_rxsoft *rxs; 1017 uint32_t cmdstat; 1018 int error; 1019 1020 if (m == NULL) { 1021 MGETHDR(n, M_DONTWAIT, MT_DATA); 1022 if (n == NULL) 1023 return ENOBUFS; 1024 1025 MCLGET(n, M_DONTWAIT); 1026 if ((n->m_flags & M_EXT) == 0) { 1027 m_freem(n); 1028 return ENOBUFS; 1029 } 1030 m = n; 1031 } else 1032 m->m_data = m->m_ext.ext_buf; 1033 1034 /* 1035 * Initialize mbuf length fields and fixup 1036 * alignment so that the frame payload is 1037 * longword aligned. 1038 */ 1039 m->m_len = m->m_pkthdr.len = MCLBYTES - RE_ETHER_ALIGN; 1040 m->m_data += RE_ETHER_ALIGN; 1041 1042 rxs = &sc->re_ldata.re_rxsoft[idx]; 1043 map = rxs->rxs_dmamap; 1044 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1045 BUS_DMA_READ|BUS_DMA_NOWAIT); 1046 1047 if (error) 1048 goto out; 1049 1050 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1051 BUS_DMASYNC_PREREAD); 1052 1053 d = &sc->re_ldata.re_rx_list[idx]; 1054 #ifdef DIAGNOSTIC 1055 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1056 cmdstat = le32toh(d->re_cmdstat); 1057 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD); 1058 if (cmdstat & RE_RDESC_STAT_OWN) { 1059 panic("%s: tried to map busy RX descriptor", 1060 device_xname(sc->sc_dev)); 1061 } 1062 #endif 1063 1064 rxs->rxs_mbuf = m; 1065 1066 d->re_vlanctl = 0; 1067 cmdstat = map->dm_segs[0].ds_len; 1068 if (idx == (RE_RX_DESC_CNT - 1)) 1069 cmdstat |= RE_RDESC_CMD_EOR; 1070 re_set_bufaddr(d, map->dm_segs[0].ds_addr); 1071 d->re_cmdstat = htole32(cmdstat); 1072 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1073 cmdstat |= RE_RDESC_CMD_OWN; 1074 d->re_cmdstat = htole32(cmdstat); 1075 RE_RXDESCSYNC(sc, idx, BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1076 1077 return 0; 1078 out: 1079 if (n != NULL) 1080 m_freem(n); 1081 return ENOMEM; 1082 } 1083 1084 static int 1085 re_tx_list_init(struct rtk_softc *sc) 1086 { 1087 int i; 1088 1089 memset(sc->re_ldata.re_tx_list, 0, RE_TX_LIST_SZ(sc)); 1090 for (i = 0; i < RE_TX_QLEN; i++) { 1091 sc->re_ldata.re_txq[i].txq_mbuf = NULL; 1092 } 1093 1094 bus_dmamap_sync(sc->sc_dmat, 1095 sc->re_ldata.re_tx_list_map, 0, 1096 sc->re_ldata.re_tx_list_map->dm_mapsize, 1097 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1098 sc->re_ldata.re_txq_prodidx = 0; 1099 sc->re_ldata.re_txq_considx = 0; 1100 sc->re_ldata.re_txq_free = RE_TX_QLEN; 1101 sc->re_ldata.re_tx_free = RE_TX_DESC_CNT(sc); 1102 sc->re_ldata.re_tx_nextfree = 0; 1103 1104 return 0; 1105 } 1106 1107 static int 1108 re_rx_list_init(struct rtk_softc *sc) 1109 { 1110 int i; 1111 1112 memset(sc->re_ldata.re_rx_list, 0, RE_RX_LIST_SZ); 1113 1114 for (i = 0; i < RE_RX_DESC_CNT; i++) { 1115 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1116 return ENOBUFS; 1117 } 1118 1119 sc->re_ldata.re_rx_prodidx = 0; 1120 sc->re_head = sc->re_tail = NULL; 1121 1122 return 0; 1123 } 1124 1125 /* 1126 * RX handler for C+ and 8169. For the gigE chips, we support 1127 * the reception of jumbo frames that have been fragmented 1128 * across multiple 2K mbuf cluster buffers. 1129 */ 1130 static void 1131 re_rxeof(struct rtk_softc *sc) 1132 { 1133 struct mbuf *m; 1134 struct ifnet *ifp; 1135 int i, total_len; 1136 struct re_desc *cur_rx; 1137 struct re_rxsoft *rxs; 1138 uint32_t rxstat, rxvlan; 1139 1140 ifp = &sc->ethercom.ec_if; 1141 1142 for (i = sc->re_ldata.re_rx_prodidx;; i = RE_NEXT_RX_DESC(sc, i)) { 1143 cur_rx = &sc->re_ldata.re_rx_list[i]; 1144 RE_RXDESCSYNC(sc, i, 1145 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1146 rxstat = le32toh(cur_rx->re_cmdstat); 1147 rxvlan = le32toh(cur_rx->re_vlanctl); 1148 RE_RXDESCSYNC(sc, i, BUS_DMASYNC_PREREAD); 1149 if ((rxstat & RE_RDESC_STAT_OWN) != 0) { 1150 break; 1151 } 1152 total_len = rxstat & sc->re_rxlenmask; 1153 rxs = &sc->re_ldata.re_rxsoft[i]; 1154 m = rxs->rxs_mbuf; 1155 1156 /* Invalidate the RX mbuf and unload its map */ 1157 1158 bus_dmamap_sync(sc->sc_dmat, 1159 rxs->rxs_dmamap, 0, rxs->rxs_dmamap->dm_mapsize, 1160 BUS_DMASYNC_POSTREAD); 1161 bus_dmamap_unload(sc->sc_dmat, rxs->rxs_dmamap); 1162 1163 if ((rxstat & RE_RDESC_STAT_EOF) == 0) { 1164 m->m_len = MCLBYTES - RE_ETHER_ALIGN; 1165 if (sc->re_head == NULL) 1166 sc->re_head = sc->re_tail = m; 1167 else { 1168 m->m_flags &= ~M_PKTHDR; 1169 sc->re_tail->m_next = m; 1170 sc->re_tail = m; 1171 } 1172 re_newbuf(sc, i, NULL); 1173 continue; 1174 } 1175 1176 /* 1177 * NOTE: for the 8139C+, the frame length field 1178 * is always 12 bits in size, but for the gigE chips, 1179 * it is 13 bits (since the max RX frame length is 16K). 1180 * Unfortunately, all 32 bits in the status word 1181 * were already used, so to make room for the extra 1182 * length bit, RealTek took out the 'frame alignment 1183 * error' bit and shifted the other status bits 1184 * over one slot. The OWN, EOR, FS and LS bits are 1185 * still in the same places. We have already extracted 1186 * the frame length and checked the OWN bit, so rather 1187 * than using an alternate bit mapping, we shift the 1188 * status bits one space to the right so we can evaluate 1189 * them using the 8169 status as though it was in the 1190 * same format as that of the 8139C+. 1191 */ 1192 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) 1193 rxstat >>= 1; 1194 1195 if (__predict_false((rxstat & RE_RDESC_STAT_RXERRSUM) != 0)) { 1196 #ifdef RE_DEBUG 1197 printf("%s: RX error (rxstat = 0x%08x)", 1198 device_xname(sc->sc_dev), rxstat); 1199 if (rxstat & RE_RDESC_STAT_FRALIGN) 1200 printf(", frame alignment error"); 1201 if (rxstat & RE_RDESC_STAT_BUFOFLOW) 1202 printf(", out of buffer space"); 1203 if (rxstat & RE_RDESC_STAT_FIFOOFLOW) 1204 printf(", FIFO overrun"); 1205 if (rxstat & RE_RDESC_STAT_GIANT) 1206 printf(", giant packet"); 1207 if (rxstat & RE_RDESC_STAT_RUNT) 1208 printf(", runt packet"); 1209 if (rxstat & RE_RDESC_STAT_CRCERR) 1210 printf(", CRC error"); 1211 printf("\n"); 1212 #endif 1213 ifp->if_ierrors++; 1214 /* 1215 * If this is part of a multi-fragment packet, 1216 * discard all the pieces. 1217 */ 1218 if (sc->re_head != NULL) { 1219 m_freem(sc->re_head); 1220 sc->re_head = sc->re_tail = NULL; 1221 } 1222 re_newbuf(sc, i, m); 1223 continue; 1224 } 1225 1226 /* 1227 * If allocating a replacement mbuf fails, 1228 * reload the current one. 1229 */ 1230 1231 if (__predict_false(re_newbuf(sc, i, NULL) != 0)) { 1232 ifp->if_ierrors++; 1233 if (sc->re_head != NULL) { 1234 m_freem(sc->re_head); 1235 sc->re_head = sc->re_tail = NULL; 1236 } 1237 re_newbuf(sc, i, m); 1238 continue; 1239 } 1240 1241 if (sc->re_head != NULL) { 1242 m->m_len = total_len % (MCLBYTES - RE_ETHER_ALIGN); 1243 /* 1244 * Special case: if there's 4 bytes or less 1245 * in this buffer, the mbuf can be discarded: 1246 * the last 4 bytes is the CRC, which we don't 1247 * care about anyway. 1248 */ 1249 if (m->m_len <= ETHER_CRC_LEN) { 1250 sc->re_tail->m_len -= 1251 (ETHER_CRC_LEN - m->m_len); 1252 m_freem(m); 1253 } else { 1254 m->m_len -= ETHER_CRC_LEN; 1255 m->m_flags &= ~M_PKTHDR; 1256 sc->re_tail->m_next = m; 1257 } 1258 m = sc->re_head; 1259 sc->re_head = sc->re_tail = NULL; 1260 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1261 } else 1262 m->m_pkthdr.len = m->m_len = 1263 (total_len - ETHER_CRC_LEN); 1264 1265 ifp->if_ipackets++; 1266 m->m_pkthdr.rcvif = ifp; 1267 1268 /* Do RX checksumming */ 1269 1270 /* Check IP header checksum */ 1271 if ((rxstat & RE_RDESC_STAT_PROTOID) != 0 && 1272 ((sc->sc_quirk & RTKQ_DESCV2) == 0 || 1273 (rxvlan & RE_RDESC_VLANCTL_IPV4) != 0)) { 1274 m->m_pkthdr.csum_flags |= M_CSUM_IPv4; 1275 if (rxstat & RE_RDESC_STAT_IPSUMBAD) 1276 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1277 } 1278 1279 /* Check TCP/UDP checksum */ 1280 if (RE_TCPPKT(rxstat)) { 1281 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1282 if (rxstat & RE_RDESC_STAT_TCPSUMBAD) 1283 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1284 } else if (RE_UDPPKT(rxstat)) { 1285 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1286 if (rxstat & RE_RDESC_STAT_UDPSUMBAD) 1287 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1288 } 1289 1290 if (rxvlan & RE_RDESC_VLANCTL_TAG) { 1291 VLAN_INPUT_TAG(ifp, m, 1292 bswap16(rxvlan & RE_RDESC_VLANCTL_DATA), 1293 continue); 1294 } 1295 #if NBPFILTER > 0 1296 if (ifp->if_bpf) 1297 bpf_mtap(ifp->if_bpf, m); 1298 #endif 1299 (*ifp->if_input)(ifp, m); 1300 } 1301 1302 sc->re_ldata.re_rx_prodidx = i; 1303 } 1304 1305 static void 1306 re_txeof(struct rtk_softc *sc) 1307 { 1308 struct ifnet *ifp; 1309 struct re_txq *txq; 1310 uint32_t txstat; 1311 int idx, descidx; 1312 1313 ifp = &sc->ethercom.ec_if; 1314 1315 for (idx = sc->re_ldata.re_txq_considx; 1316 sc->re_ldata.re_txq_free < RE_TX_QLEN; 1317 idx = RE_NEXT_TXQ(sc, idx), sc->re_ldata.re_txq_free++) { 1318 txq = &sc->re_ldata.re_txq[idx]; 1319 KASSERT(txq->txq_mbuf != NULL); 1320 1321 descidx = txq->txq_descidx; 1322 RE_TXDESCSYNC(sc, descidx, 1323 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1324 txstat = 1325 le32toh(sc->re_ldata.re_tx_list[descidx].re_cmdstat); 1326 RE_TXDESCSYNC(sc, descidx, BUS_DMASYNC_PREREAD); 1327 KASSERT((txstat & RE_TDESC_CMD_EOF) != 0); 1328 if (txstat & RE_TDESC_CMD_OWN) { 1329 break; 1330 } 1331 1332 sc->re_ldata.re_tx_free += txq->txq_nsegs; 1333 KASSERT(sc->re_ldata.re_tx_free <= RE_TX_DESC_CNT(sc)); 1334 bus_dmamap_sync(sc->sc_dmat, txq->txq_dmamap, 1335 0, txq->txq_dmamap->dm_mapsize, BUS_DMASYNC_POSTWRITE); 1336 bus_dmamap_unload(sc->sc_dmat, txq->txq_dmamap); 1337 m_freem(txq->txq_mbuf); 1338 txq->txq_mbuf = NULL; 1339 1340 if (txstat & (RE_TDESC_STAT_EXCESSCOL | RE_TDESC_STAT_COLCNT)) 1341 ifp->if_collisions++; 1342 if (txstat & RE_TDESC_STAT_TXERRSUM) 1343 ifp->if_oerrors++; 1344 else 1345 ifp->if_opackets++; 1346 } 1347 1348 sc->re_ldata.re_txq_considx = idx; 1349 1350 if (sc->re_ldata.re_txq_free > RE_NTXDESC_RSVD) 1351 ifp->if_flags &= ~IFF_OACTIVE; 1352 1353 /* 1354 * If not all descriptors have been released reaped yet, 1355 * reload the timer so that we will eventually get another 1356 * interrupt that will cause us to re-enter this routine. 1357 * This is done in case the transmitter has gone idle. 1358 */ 1359 if (sc->re_ldata.re_txq_free < RE_TX_QLEN) { 1360 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1361 if ((sc->sc_quirk & RTKQ_PCIE) != 0) { 1362 /* 1363 * Some chips will ignore a second TX request 1364 * issued while an existing transmission is in 1365 * progress. If the transmitter goes idle but 1366 * there are still packets waiting to be sent, 1367 * we need to restart the channel here to flush 1368 * them out. This only seems to be required with 1369 * the PCIe devices. 1370 */ 1371 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START); 1372 } 1373 } else 1374 ifp->if_timer = 0; 1375 } 1376 1377 static void 1378 re_tick(void *arg) 1379 { 1380 struct rtk_softc *sc = arg; 1381 int s; 1382 1383 /*XXX: just return for 8169S/8110S with rev 2 or newer phy */ 1384 s = splnet(); 1385 1386 mii_tick(&sc->mii); 1387 splx(s); 1388 1389 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1390 } 1391 1392 int 1393 re_intr(void *arg) 1394 { 1395 struct rtk_softc *sc = arg; 1396 struct ifnet *ifp; 1397 uint16_t status; 1398 int handled = 0; 1399 1400 if (!device_has_power(sc->sc_dev)) 1401 return 0; 1402 1403 ifp = &sc->ethercom.ec_if; 1404 1405 if ((ifp->if_flags & IFF_UP) == 0) 1406 return 0; 1407 1408 for (;;) { 1409 1410 status = CSR_READ_2(sc, RTK_ISR); 1411 /* If the card has gone away the read returns 0xffff. */ 1412 if (status == 0xffff) 1413 break; 1414 if (status) { 1415 handled = 1; 1416 CSR_WRITE_2(sc, RTK_ISR, status); 1417 } 1418 1419 if ((status & RTK_INTRS_CPLUS) == 0) 1420 break; 1421 1422 if (status & (RTK_ISR_RX_OK | RTK_ISR_RX_ERR)) 1423 re_rxeof(sc); 1424 1425 if (status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_TX_ERR | 1426 RTK_ISR_TX_DESC_UNAVAIL)) 1427 re_txeof(sc); 1428 1429 if (status & RTK_ISR_SYSTEM_ERR) { 1430 re_init(ifp); 1431 } 1432 1433 if (status & RTK_ISR_LINKCHG) { 1434 callout_stop(&sc->rtk_tick_ch); 1435 re_tick(sc); 1436 } 1437 } 1438 1439 if (handled && !IFQ_IS_EMPTY(&ifp->if_snd)) 1440 re_start(ifp); 1441 1442 return handled; 1443 } 1444 1445 1446 1447 /* 1448 * Main transmit routine for C+ and gigE NICs. 1449 */ 1450 1451 static void 1452 re_start(struct ifnet *ifp) 1453 { 1454 struct rtk_softc *sc; 1455 struct mbuf *m; 1456 bus_dmamap_t map; 1457 struct re_txq *txq; 1458 struct re_desc *d; 1459 struct m_tag *mtag; 1460 uint32_t cmdstat, re_flags, vlanctl; 1461 int ofree, idx, error, nsegs, seg; 1462 int startdesc, curdesc, lastdesc; 1463 bool pad; 1464 1465 sc = ifp->if_softc; 1466 ofree = sc->re_ldata.re_txq_free; 1467 1468 for (idx = sc->re_ldata.re_txq_prodidx;; idx = RE_NEXT_TXQ(sc, idx)) { 1469 1470 IFQ_POLL(&ifp->if_snd, m); 1471 if (m == NULL) 1472 break; 1473 1474 if (sc->re_ldata.re_txq_free == 0 || 1475 sc->re_ldata.re_tx_free == 0) { 1476 /* no more free slots left */ 1477 ifp->if_flags |= IFF_OACTIVE; 1478 break; 1479 } 1480 1481 /* 1482 * Set up checksum offload. Note: checksum offload bits must 1483 * appear in all descriptors of a multi-descriptor transmit 1484 * attempt. (This is according to testing done with an 8169 1485 * chip. I'm not sure if this is a requirement or a bug.) 1486 */ 1487 1488 vlanctl = 0; 1489 if ((m->m_pkthdr.csum_flags & M_CSUM_TSOv4) != 0) { 1490 uint32_t segsz = m->m_pkthdr.segsz; 1491 1492 re_flags = RE_TDESC_CMD_LGSEND | 1493 (segsz << RE_TDESC_CMD_MSSVAL_SHIFT); 1494 } else { 1495 /* 1496 * set RE_TDESC_CMD_IPCSUM if any checksum offloading 1497 * is requested. otherwise, RE_TDESC_CMD_TCPCSUM/ 1498 * RE_TDESC_CMD_UDPCSUM doesn't make effects. 1499 */ 1500 re_flags = 0; 1501 if ((m->m_pkthdr.csum_flags & 1502 (M_CSUM_IPv4 | M_CSUM_TCPv4 | M_CSUM_UDPv4)) 1503 != 0) { 1504 if ((sc->sc_quirk & RTKQ_DESCV2) == 0) { 1505 re_flags |= RE_TDESC_CMD_IPCSUM; 1506 if (m->m_pkthdr.csum_flags & 1507 M_CSUM_TCPv4) { 1508 re_flags |= 1509 RE_TDESC_CMD_TCPCSUM; 1510 } else if (m->m_pkthdr.csum_flags & 1511 M_CSUM_UDPv4) { 1512 re_flags |= 1513 RE_TDESC_CMD_UDPCSUM; 1514 } 1515 } else { 1516 vlanctl |= RE_TDESC_VLANCTL_IPCSUM; 1517 if (m->m_pkthdr.csum_flags & 1518 M_CSUM_TCPv4) { 1519 vlanctl |= 1520 RE_TDESC_VLANCTL_TCPCSUM; 1521 } else if (m->m_pkthdr.csum_flags & 1522 M_CSUM_UDPv4) { 1523 vlanctl |= 1524 RE_TDESC_VLANCTL_UDPCSUM; 1525 } 1526 } 1527 } 1528 } 1529 1530 txq = &sc->re_ldata.re_txq[idx]; 1531 map = txq->txq_dmamap; 1532 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, 1533 BUS_DMA_WRITE|BUS_DMA_NOWAIT); 1534 1535 if (__predict_false(error)) { 1536 /* XXX try to defrag if EFBIG? */ 1537 printf("%s: can't map mbuf (error %d)\n", 1538 device_xname(sc->sc_dev), error); 1539 1540 IFQ_DEQUEUE(&ifp->if_snd, m); 1541 m_freem(m); 1542 ifp->if_oerrors++; 1543 continue; 1544 } 1545 1546 nsegs = map->dm_nsegs; 1547 pad = false; 1548 if (__predict_false(m->m_pkthdr.len <= RE_IP4CSUMTX_PADLEN && 1549 (re_flags & RE_TDESC_CMD_IPCSUM) != 0 && 1550 (sc->sc_quirk & RTKQ_DESCV2) == 0)) { 1551 pad = true; 1552 nsegs++; 1553 } 1554 1555 if (nsegs > sc->re_ldata.re_tx_free) { 1556 /* 1557 * Not enough free descriptors to transmit this packet. 1558 */ 1559 ifp->if_flags |= IFF_OACTIVE; 1560 bus_dmamap_unload(sc->sc_dmat, map); 1561 break; 1562 } 1563 1564 IFQ_DEQUEUE(&ifp->if_snd, m); 1565 1566 /* 1567 * Make sure that the caches are synchronized before we 1568 * ask the chip to start DMA for the packet data. 1569 */ 1570 bus_dmamap_sync(sc->sc_dmat, map, 0, map->dm_mapsize, 1571 BUS_DMASYNC_PREWRITE); 1572 1573 /* 1574 * Set up hardware VLAN tagging. Note: vlan tag info must 1575 * appear in all descriptors of a multi-descriptor 1576 * transmission attempt. 1577 */ 1578 if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m)) != NULL) 1579 vlanctl |= bswap16(VLAN_TAG_VALUE(mtag)) | 1580 RE_TDESC_VLANCTL_TAG; 1581 1582 /* 1583 * Map the segment array into descriptors. 1584 * Note that we set the start-of-frame and 1585 * end-of-frame markers for either TX or RX, 1586 * but they really only have meaning in the TX case. 1587 * (In the RX case, it's the chip that tells us 1588 * where packets begin and end.) 1589 * We also keep track of the end of the ring 1590 * and set the end-of-ring bits as needed, 1591 * and we set the ownership bits in all except 1592 * the very first descriptor. (The caller will 1593 * set this descriptor later when it start 1594 * transmission or reception.) 1595 */ 1596 curdesc = startdesc = sc->re_ldata.re_tx_nextfree; 1597 lastdesc = -1; 1598 for (seg = 0; seg < map->dm_nsegs; 1599 seg++, curdesc = RE_NEXT_TX_DESC(sc, curdesc)) { 1600 d = &sc->re_ldata.re_tx_list[curdesc]; 1601 #ifdef DIAGNOSTIC 1602 RE_TXDESCSYNC(sc, curdesc, 1603 BUS_DMASYNC_POSTREAD|BUS_DMASYNC_POSTWRITE); 1604 cmdstat = le32toh(d->re_cmdstat); 1605 RE_TXDESCSYNC(sc, curdesc, BUS_DMASYNC_PREREAD); 1606 if (cmdstat & RE_TDESC_STAT_OWN) { 1607 panic("%s: tried to map busy TX descriptor", 1608 device_xname(sc->sc_dev)); 1609 } 1610 #endif 1611 1612 d->re_vlanctl = htole32(vlanctl); 1613 re_set_bufaddr(d, map->dm_segs[seg].ds_addr); 1614 cmdstat = re_flags | map->dm_segs[seg].ds_len; 1615 if (seg == 0) 1616 cmdstat |= RE_TDESC_CMD_SOF; 1617 else 1618 cmdstat |= RE_TDESC_CMD_OWN; 1619 if (curdesc == (RE_TX_DESC_CNT(sc) - 1)) 1620 cmdstat |= RE_TDESC_CMD_EOR; 1621 if (seg == nsegs - 1) { 1622 cmdstat |= RE_TDESC_CMD_EOF; 1623 lastdesc = curdesc; 1624 } 1625 d->re_cmdstat = htole32(cmdstat); 1626 RE_TXDESCSYNC(sc, curdesc, 1627 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1628 } 1629 if (__predict_false(pad)) { 1630 bus_addr_t paddaddr; 1631 1632 d = &sc->re_ldata.re_tx_list[curdesc]; 1633 d->re_vlanctl = htole32(vlanctl); 1634 paddaddr = RE_TXPADDADDR(sc); 1635 re_set_bufaddr(d, paddaddr); 1636 cmdstat = re_flags | 1637 RE_TDESC_CMD_OWN | RE_TDESC_CMD_EOF | 1638 (RE_IP4CSUMTX_PADLEN + 1 - m->m_pkthdr.len); 1639 if (curdesc == (RE_TX_DESC_CNT(sc) - 1)) 1640 cmdstat |= RE_TDESC_CMD_EOR; 1641 d->re_cmdstat = htole32(cmdstat); 1642 RE_TXDESCSYNC(sc, curdesc, 1643 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1644 lastdesc = curdesc; 1645 curdesc = RE_NEXT_TX_DESC(sc, curdesc); 1646 } 1647 KASSERT(lastdesc != -1); 1648 1649 /* Transfer ownership of packet to the chip. */ 1650 1651 sc->re_ldata.re_tx_list[startdesc].re_cmdstat |= 1652 htole32(RE_TDESC_CMD_OWN); 1653 RE_TXDESCSYNC(sc, startdesc, 1654 BUS_DMASYNC_PREREAD|BUS_DMASYNC_PREWRITE); 1655 1656 /* update info of TX queue and descriptors */ 1657 txq->txq_mbuf = m; 1658 txq->txq_descidx = lastdesc; 1659 txq->txq_nsegs = nsegs; 1660 1661 sc->re_ldata.re_txq_free--; 1662 sc->re_ldata.re_tx_free -= nsegs; 1663 sc->re_ldata.re_tx_nextfree = curdesc; 1664 1665 #if NBPFILTER > 0 1666 /* 1667 * If there's a BPF listener, bounce a copy of this frame 1668 * to him. 1669 */ 1670 if (ifp->if_bpf) 1671 bpf_mtap(ifp->if_bpf, m); 1672 #endif 1673 } 1674 1675 if (sc->re_ldata.re_txq_free < ofree) { 1676 /* 1677 * TX packets are enqueued. 1678 */ 1679 sc->re_ldata.re_txq_prodidx = idx; 1680 1681 /* 1682 * Start the transmitter to poll. 1683 * 1684 * RealTek put the TX poll request register in a different 1685 * location on the 8169 gigE chip. I don't know why. 1686 */ 1687 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) 1688 CSR_WRITE_1(sc, RTK_TXSTART, RTK_TXSTART_START); 1689 else 1690 CSR_WRITE_1(sc, RTK_GTXSTART, RTK_TXSTART_START); 1691 1692 /* 1693 * Use the countdown timer for interrupt moderation. 1694 * 'TX done' interrupts are disabled. Instead, we reset the 1695 * countdown timer, which will begin counting until it hits 1696 * the value in the TIMERINT register, and then trigger an 1697 * interrupt. Each time we write to the TIMERCNT register, 1698 * the timer count is reset to 0. 1699 */ 1700 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1701 1702 /* 1703 * Set a timeout in case the chip goes out to lunch. 1704 */ 1705 ifp->if_timer = 5; 1706 } 1707 } 1708 1709 static int 1710 re_init(struct ifnet *ifp) 1711 { 1712 struct rtk_softc *sc = ifp->if_softc; 1713 const uint8_t *enaddr; 1714 uint32_t rxcfg = 0; 1715 uint32_t reg; 1716 int error; 1717 1718 if ((error = re_enable(sc)) != 0) 1719 goto out; 1720 1721 /* 1722 * Cancel pending I/O and free all RX/TX buffers. 1723 */ 1724 re_stop(ifp, 0); 1725 1726 re_reset(sc); 1727 1728 /* 1729 * Enable C+ RX and TX mode, as well as VLAN stripping and 1730 * RX checksum offload. We must configure the C+ register 1731 * before all others. 1732 */ 1733 reg = 0; 1734 1735 /* 1736 * XXX: Realtek docs say bits 0 and 1 are reserved, for 8169S/8110S. 1737 * FreeBSD drivers set these bits anyway (for 8139C+?). 1738 * So far, it works. 1739 */ 1740 1741 /* 1742 * XXX: For old 8169 set bit 14. 1743 * For 8169S/8110S and above, do not set bit 14. 1744 */ 1745 if ((sc->sc_quirk & RTKQ_8169NONS) != 0) 1746 reg |= (0x1 << 14) | RTK_CPLUSCMD_PCI_MRW; 1747 1748 if (1) {/* not for 8169S ? */ 1749 reg |= 1750 RTK_CPLUSCMD_VLANSTRIP | 1751 (ifp->if_capenable & 1752 (IFCAP_CSUM_IPv4_Rx | IFCAP_CSUM_TCPv4_Rx | 1753 IFCAP_CSUM_UDPv4_Rx) ? 1754 RTK_CPLUSCMD_RXCSUM_ENB : 0); 1755 } 1756 1757 CSR_WRITE_2(sc, RTK_CPLUS_CMD, 1758 reg | RTK_CPLUSCMD_RXENB | RTK_CPLUSCMD_TXENB); 1759 1760 /* XXX: from Realtek-supplied Linux driver. Wholly undocumented. */ 1761 if ((sc->sc_quirk & RTKQ_8139CPLUS) == 0) 1762 CSR_WRITE_2(sc, RTK_IM, 0x0000); 1763 1764 DELAY(10000); 1765 1766 /* 1767 * Init our MAC address. Even though the chipset 1768 * documentation doesn't mention it, we need to enter "Config 1769 * register write enable" mode to modify the ID registers. 1770 */ 1771 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_WRITECFG); 1772 enaddr = CLLADDR(ifp->if_sadl); 1773 reg = enaddr[0] | (enaddr[1] << 8) | 1774 (enaddr[2] << 16) | (enaddr[3] << 24); 1775 CSR_WRITE_4(sc, RTK_IDR0, reg); 1776 reg = enaddr[4] | (enaddr[5] << 8); 1777 CSR_WRITE_4(sc, RTK_IDR4, reg); 1778 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 1779 1780 /* 1781 * For C+ mode, initialize the RX descriptors and mbufs. 1782 */ 1783 re_rx_list_init(sc); 1784 re_tx_list_init(sc); 1785 1786 /* 1787 * Load the addresses of the RX and TX lists into the chip. 1788 */ 1789 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_HI, 1790 RE_ADDR_HI(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr)); 1791 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_LO, 1792 RE_ADDR_LO(sc->re_ldata.re_rx_list_map->dm_segs[0].ds_addr)); 1793 1794 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_HI, 1795 RE_ADDR_HI(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr)); 1796 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_LO, 1797 RE_ADDR_LO(sc->re_ldata.re_tx_list_map->dm_segs[0].ds_addr)); 1798 1799 /* 1800 * Enable transmit and receive. 1801 */ 1802 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1803 1804 /* 1805 * Set the initial TX and RX configuration. 1806 */ 1807 if (sc->re_testmode && (sc->sc_quirk & RTKQ_8169NONS) != 0) { 1808 /* test mode is needed only for old 8169 */ 1809 CSR_WRITE_4(sc, RTK_TXCFG, 1810 RE_TXCFG_CONFIG | RTK_LOOPTEST_ON); 1811 } else 1812 CSR_WRITE_4(sc, RTK_TXCFG, RE_TXCFG_CONFIG); 1813 1814 CSR_WRITE_1(sc, RTK_EARLY_TX_THRESH, 16); 1815 1816 CSR_WRITE_4(sc, RTK_RXCFG, RE_RXCFG_CONFIG); 1817 1818 /* Set the individual bit to receive frames for this host only. */ 1819 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 1820 rxcfg |= RTK_RXCFG_RX_INDIV; 1821 1822 /* If we want promiscuous mode, set the allframes bit. */ 1823 if (ifp->if_flags & IFF_PROMISC) 1824 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 1825 else 1826 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 1827 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1828 1829 /* 1830 * Set capture broadcast bit to capture broadcast frames. 1831 */ 1832 if (ifp->if_flags & IFF_BROADCAST) 1833 rxcfg |= RTK_RXCFG_RX_BROAD; 1834 else 1835 rxcfg &= ~RTK_RXCFG_RX_BROAD; 1836 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1837 1838 /* 1839 * Program the multicast filter, if necessary. 1840 */ 1841 rtk_setmulti(sc); 1842 1843 /* 1844 * Enable interrupts. 1845 */ 1846 if (sc->re_testmode) 1847 CSR_WRITE_2(sc, RTK_IMR, 0); 1848 else 1849 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS); 1850 1851 /* Start RX/TX process. */ 1852 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 1853 #ifdef notdef 1854 /* Enable receiver and transmitter. */ 1855 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1856 #endif 1857 1858 /* 1859 * Initialize the timer interrupt register so that 1860 * a timer interrupt will be generated once the timer 1861 * reaches a certain number of ticks. The timer is 1862 * reloaded on each transmit. This gives us TX interrupt 1863 * moderation, which dramatically improves TX frame rate. 1864 */ 1865 1866 if ((sc->sc_quirk & RTKQ_8139CPLUS) != 0) 1867 CSR_WRITE_4(sc, RTK_TIMERINT, 0x400); 1868 else { 1869 CSR_WRITE_4(sc, RTK_TIMERINT_8169, 0x800); 1870 1871 /* 1872 * For 8169 gigE NICs, set the max allowed RX packet 1873 * size so we can receive jumbo frames. 1874 */ 1875 CSR_WRITE_2(sc, RTK_MAXRXPKTLEN, 16383); 1876 } 1877 1878 if (sc->re_testmode) 1879 return 0; 1880 1881 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD); 1882 1883 ifp->if_flags |= IFF_RUNNING; 1884 ifp->if_flags &= ~IFF_OACTIVE; 1885 1886 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1887 1888 out: 1889 if (error) { 1890 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1891 ifp->if_timer = 0; 1892 printf("%s: interface not running\n", 1893 device_xname(sc->sc_dev)); 1894 } 1895 1896 return error; 1897 } 1898 1899 static int 1900 re_ioctl(struct ifnet *ifp, u_long command, void *data) 1901 { 1902 struct rtk_softc *sc = ifp->if_softc; 1903 struct ifreq *ifr = data; 1904 int s, error = 0; 1905 1906 s = splnet(); 1907 1908 switch (command) { 1909 case SIOCSIFMTU: 1910 /* 1911 * Disable jumbo frames if it's not supported. 1912 */ 1913 if ((sc->sc_quirk & RTKQ_NOJUMBO) != 0 && 1914 ifr->ifr_mtu > ETHERMTU) { 1915 error = EINVAL; 1916 break; 1917 } 1918 1919 if (ifr->ifr_mtu < ETHERMIN || ifr->ifr_mtu > ETHERMTU_JUMBO) 1920 error = EINVAL; 1921 else if ((error = ifioctl_common(ifp, command, data)) == 1922 ENETRESET) 1923 error = 0; 1924 break; 1925 default: 1926 if ((error = ether_ioctl(ifp, command, data)) != ENETRESET) 1927 break; 1928 1929 error = 0; 1930 1931 if (command == SIOCSIFCAP) 1932 error = (*ifp->if_init)(ifp); 1933 else if (command != SIOCADDMULTI && command != SIOCDELMULTI) 1934 ; 1935 else if (ifp->if_flags & IFF_RUNNING) 1936 rtk_setmulti(sc); 1937 break; 1938 } 1939 1940 splx(s); 1941 1942 return error; 1943 } 1944 1945 static void 1946 re_watchdog(struct ifnet *ifp) 1947 { 1948 struct rtk_softc *sc; 1949 int s; 1950 1951 sc = ifp->if_softc; 1952 s = splnet(); 1953 printf("%s: watchdog timeout\n", device_xname(sc->sc_dev)); 1954 ifp->if_oerrors++; 1955 1956 re_txeof(sc); 1957 re_rxeof(sc); 1958 1959 re_init(ifp); 1960 1961 splx(s); 1962 } 1963 1964 /* 1965 * Stop the adapter and free any mbufs allocated to the 1966 * RX and TX lists. 1967 */ 1968 static void 1969 re_stop(struct ifnet *ifp, int disable) 1970 { 1971 int i; 1972 struct rtk_softc *sc = ifp->if_softc; 1973 1974 callout_stop(&sc->rtk_tick_ch); 1975 1976 mii_down(&sc->mii); 1977 1978 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 1979 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1980 1981 if (sc->re_head != NULL) { 1982 m_freem(sc->re_head); 1983 sc->re_head = sc->re_tail = NULL; 1984 } 1985 1986 /* Free the TX list buffers. */ 1987 for (i = 0; i < RE_TX_QLEN; i++) { 1988 if (sc->re_ldata.re_txq[i].txq_mbuf != NULL) { 1989 bus_dmamap_unload(sc->sc_dmat, 1990 sc->re_ldata.re_txq[i].txq_dmamap); 1991 m_freem(sc->re_ldata.re_txq[i].txq_mbuf); 1992 sc->re_ldata.re_txq[i].txq_mbuf = NULL; 1993 } 1994 } 1995 1996 /* Free the RX list buffers. */ 1997 for (i = 0; i < RE_RX_DESC_CNT; i++) { 1998 if (sc->re_ldata.re_rxsoft[i].rxs_mbuf != NULL) { 1999 bus_dmamap_unload(sc->sc_dmat, 2000 sc->re_ldata.re_rxsoft[i].rxs_dmamap); 2001 m_freem(sc->re_ldata.re_rxsoft[i].rxs_mbuf); 2002 sc->re_ldata.re_rxsoft[i].rxs_mbuf = NULL; 2003 } 2004 } 2005 2006 if (disable) 2007 re_disable(sc); 2008 2009 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2010 ifp->if_timer = 0; 2011 } 2012