1 /* $NetBSD: rtl8169.c,v 1.9 2005/02/20 15:56:03 jdolecek Exp $ */ 2 3 /* 4 * Copyright (c) 1997, 1998-2003 5 * Bill Paul <wpaul@windriver.com>. All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. All advertising materials mentioning features or use of this software 16 * must display the following acknowledgement: 17 * This product includes software developed by Bill Paul. 18 * 4. Neither the name of the author nor the names of any co-contributors 19 * may be used to endorse or promote products derived from this software 20 * without specific prior written permission. 21 * 22 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 23 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 24 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 25 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 26 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 27 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 28 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 29 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 30 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 31 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 32 * THE POSSIBILITY OF SUCH DAMAGE. 33 */ 34 35 #include <sys/cdefs.h> 36 /* $FreeBSD: /repoman/r/ncvs/src/sys/dev/re/if_re.c,v 1.20 2004/04/11 20:34:08 ru Exp $ */ 37 38 /* 39 * RealTek 8139C+/8169/8169S/8110S PCI NIC driver 40 * 41 * Written by Bill Paul <wpaul@windriver.com> 42 * Senior Networking Software Engineer 43 * Wind River Systems 44 */ 45 46 /* 47 * This driver is designed to support RealTek's next generation of 48 * 10/100 and 10/100/1000 PCI ethernet controllers. There are currently 49 * four devices in this family: the RTL8139C+, the RTL8169, the RTL8169S 50 * and the RTL8110S. 51 * 52 * The 8139C+ is a 10/100 ethernet chip. It is backwards compatible 53 * with the older 8139 family, however it also supports a special 54 * C+ mode of operation that provides several new performance enhancing 55 * features. These include: 56 * 57 * o Descriptor based DMA mechanism. Each descriptor represents 58 * a single packet fragment. Data buffers may be aligned on 59 * any byte boundary. 60 * 61 * o 64-bit DMA 62 * 63 * o TCP/IP checksum offload for both RX and TX 64 * 65 * o High and normal priority transmit DMA rings 66 * 67 * o VLAN tag insertion and extraction 68 * 69 * o TCP large send (segmentation offload) 70 * 71 * Like the 8139, the 8139C+ also has a built-in 10/100 PHY. The C+ 72 * programming API is fairly straightforward. The RX filtering, EEPROM 73 * access and PHY access is the same as it is on the older 8139 series 74 * chips. 75 * 76 * The 8169 is a 64-bit 10/100/1000 gigabit ethernet MAC. It has almost the 77 * same programming API and feature set as the 8139C+ with the following 78 * differences and additions: 79 * 80 * o 1000Mbps mode 81 * 82 * o Jumbo frames 83 * 84 * o GMII and TBI ports/registers for interfacing with copper 85 * or fiber PHYs 86 * 87 * o RX and TX DMA rings can have up to 1024 descriptors 88 * (the 8139C+ allows a maximum of 64) 89 * 90 * o Slight differences in register layout from the 8139C+ 91 * 92 * The TX start and timer interrupt registers are at different locations 93 * on the 8169 than they are on the 8139C+. Also, the status word in the 94 * RX descriptor has a slightly different bit layout. The 8169 does not 95 * have a built-in PHY. Most reference boards use a Marvell 88E1000 'Alaska' 96 * copper gigE PHY. 97 * 98 * The 8169S/8110S 10/100/1000 devices have built-in copper gigE PHYs 99 * (the 'S' stands for 'single-chip'). These devices have the same 100 * programming API as the older 8169, but also have some vendor-specific 101 * registers for the on-board PHY. The 8110S is a LAN-on-motherboard 102 * part designed to be pin-compatible with the RealTek 8100 10/100 chip. 103 * 104 * This driver takes advantage of the RX and TX checksum offload and 105 * VLAN tag insertion/extraction features. It also implements TX 106 * interrupt moderation using the timer interrupt registers, which 107 * significantly reduces TX interrupt load. There is also support 108 * for jumbo frames, however the 8169/8169S/8110S can not transmit 109 * jumbo frames larger than 7.5K, so the max MTU possible with this 110 * driver is 7500 bytes. 111 */ 112 113 #include "bpfilter.h" 114 #include "vlan.h" 115 116 #include <sys/param.h> 117 #include <sys/endian.h> 118 #include <sys/systm.h> 119 #include <sys/sockio.h> 120 #include <sys/mbuf.h> 121 #include <sys/malloc.h> 122 #include <sys/kernel.h> 123 #include <sys/socket.h> 124 #include <sys/device.h> 125 126 #include <net/if.h> 127 #include <net/if_arp.h> 128 #include <net/if_dl.h> 129 #include <net/if_ether.h> 130 #include <net/if_media.h> 131 #include <net/if_vlanvar.h> 132 133 #if NBPFILTER > 0 134 #include <net/bpf.h> 135 #endif 136 137 #include <machine/bus.h> 138 139 #include <dev/mii/mii.h> 140 #include <dev/mii/miivar.h> 141 142 #include <dev/pci/pcireg.h> 143 #include <dev/pci/pcivar.h> 144 #include <dev/pci/pcidevs.h> 145 146 /* 147 * Default to using PIO access for this driver. 148 */ 149 #define RE_USEIOSPACE 150 151 #include <dev/ic/rtl81x9reg.h> 152 #include <dev/ic/rtl81x9var.h> 153 154 #include <dev/ic/rtl8169var.h> 155 156 157 static int re_encap(struct rtk_softc *, struct mbuf *, int *); 158 159 static int re_newbuf(struct rtk_softc *, int, struct mbuf *); 160 static int re_rx_list_init(struct rtk_softc *); 161 static int re_tx_list_init(struct rtk_softc *); 162 static void re_rxeof(struct rtk_softc *); 163 static void re_txeof(struct rtk_softc *); 164 static void re_tick(void *); 165 static void re_start(struct ifnet *); 166 static int re_ioctl(struct ifnet *, u_long, caddr_t); 167 static int re_init(struct ifnet *); 168 static void re_stop(struct ifnet *, int); 169 static void re_watchdog(struct ifnet *); 170 171 static void re_shutdown(void *); 172 static int re_enable(struct rtk_softc *); 173 static void re_disable(struct rtk_softc *); 174 static void re_power(int, void *); 175 176 static int re_ifmedia_upd(struct ifnet *); 177 static void re_ifmedia_sts(struct ifnet *, struct ifmediareq *); 178 179 static int re_gmii_readreg(struct device *, int, int); 180 static void re_gmii_writereg(struct device *, int, int, int); 181 182 static int re_miibus_readreg(struct device *, int, int); 183 static void re_miibus_writereg(struct device *, int, int, int); 184 static void re_miibus_statchg(struct device *); 185 186 static void re_reset(struct rtk_softc *); 187 188 189 #ifdef RE_USEIOSPACE 190 #define RTK_RES SYS_RES_IOPORT 191 #define RTK_RID RTK_PCI_LOIO 192 #else 193 #define RTK_RES SYS_RES_MEMORY 194 #define RTK_RID RTK_PCI_LOMEM 195 #endif 196 197 #define EE_SET(x) \ 198 CSR_WRITE_1(sc, RTK_EECMD, \ 199 CSR_READ_1(sc, RTK_EECMD) | x) 200 201 #define EE_CLR(x) \ 202 CSR_WRITE_1(sc, RTK_EECMD, \ 203 CSR_READ_1(sc, RTK_EECMD) & ~x) 204 205 static int 206 re_gmii_readreg(struct device *self, int phy, int reg) 207 { 208 struct rtk_softc *sc = (void *)self; 209 u_int32_t rval; 210 int i; 211 212 if (phy != 7) 213 return 0; 214 215 /* Let the rgephy driver read the GMEDIASTAT register */ 216 217 if (reg == RTK_GMEDIASTAT) { 218 rval = CSR_READ_1(sc, RTK_GMEDIASTAT); 219 return rval; 220 } 221 222 CSR_WRITE_4(sc, RTK_PHYAR, reg << 16); 223 DELAY(1000); 224 225 for (i = 0; i < RTK_TIMEOUT; i++) { 226 rval = CSR_READ_4(sc, RTK_PHYAR); 227 if (rval & RTK_PHYAR_BUSY) 228 break; 229 DELAY(100); 230 } 231 232 if (i == RTK_TIMEOUT) { 233 aprint_error("%s: PHY read failed\n", sc->sc_dev.dv_xname); 234 return 0; 235 } 236 237 return rval & RTK_PHYAR_PHYDATA; 238 } 239 240 static void 241 re_gmii_writereg(struct device *dev, int phy, int reg, int data) 242 { 243 struct rtk_softc *sc = (void *)dev; 244 u_int32_t rval; 245 int i; 246 247 CSR_WRITE_4(sc, RTK_PHYAR, (reg << 16) | 248 (data & RTK_PHYAR_PHYDATA) | RTK_PHYAR_BUSY); 249 DELAY(1000); 250 251 for (i = 0; i < RTK_TIMEOUT; i++) { 252 rval = CSR_READ_4(sc, RTK_PHYAR); 253 if (!(rval & RTK_PHYAR_BUSY)) 254 break; 255 DELAY(100); 256 } 257 258 if (i == RTK_TIMEOUT) { 259 aprint_error("%s: PHY write reg %x <- %x failed\n", 260 sc->sc_dev.dv_xname, reg, data); 261 return; 262 } 263 264 return; 265 } 266 267 static int 268 re_miibus_readreg(struct device *dev, int phy, int reg) 269 { 270 struct rtk_softc *sc = (void *)dev; 271 u_int16_t rval = 0; 272 u_int16_t re8139_reg = 0; 273 int s; 274 275 s = splnet(); 276 277 if (sc->rtk_type == RTK_8169) { 278 rval = re_gmii_readreg(dev, phy, reg); 279 splx(s); 280 return rval; 281 } 282 283 /* Pretend the internal PHY is only at address 0 */ 284 if (phy) { 285 splx(s); 286 return 0; 287 } 288 switch (reg) { 289 case MII_BMCR: 290 re8139_reg = RTK_BMCR; 291 break; 292 case MII_BMSR: 293 re8139_reg = RTK_BMSR; 294 break; 295 case MII_ANAR: 296 re8139_reg = RTK_ANAR; 297 break; 298 case MII_ANER: 299 re8139_reg = RTK_ANER; 300 break; 301 case MII_ANLPAR: 302 re8139_reg = RTK_LPAR; 303 break; 304 case MII_PHYIDR1: 305 case MII_PHYIDR2: 306 splx(s); 307 return 0; 308 /* 309 * Allow the rlphy driver to read the media status 310 * register. If we have a link partner which does not 311 * support NWAY, this is the register which will tell 312 * us the results of parallel detection. 313 */ 314 case RTK_MEDIASTAT: 315 rval = CSR_READ_1(sc, RTK_MEDIASTAT); 316 splx(s); 317 return rval; 318 default: 319 aprint_error("%s: bad phy register\n", sc->sc_dev.dv_xname); 320 splx(s); 321 return 0; 322 } 323 rval = CSR_READ_2(sc, re8139_reg); 324 splx(s); 325 return rval; 326 } 327 328 static void 329 re_miibus_writereg(struct device *dev, int phy, int reg, int data) 330 { 331 struct rtk_softc *sc = (void *)dev; 332 u_int16_t re8139_reg = 0; 333 int s; 334 335 s = splnet(); 336 337 if (sc->rtk_type == RTK_8169) { 338 re_gmii_writereg(dev, phy, reg, data); 339 splx(s); 340 return; 341 } 342 343 /* Pretend the internal PHY is only at address 0 */ 344 if (phy) { 345 splx(s); 346 return; 347 } 348 switch (reg) { 349 case MII_BMCR: 350 re8139_reg = RTK_BMCR; 351 break; 352 case MII_BMSR: 353 re8139_reg = RTK_BMSR; 354 break; 355 case MII_ANAR: 356 re8139_reg = RTK_ANAR; 357 break; 358 case MII_ANER: 359 re8139_reg = RTK_ANER; 360 break; 361 case MII_ANLPAR: 362 re8139_reg = RTK_LPAR; 363 break; 364 case MII_PHYIDR1: 365 case MII_PHYIDR2: 366 splx(s); 367 return; 368 break; 369 default: 370 aprint_error("%s: bad phy register\n", sc->sc_dev.dv_xname); 371 splx(s); 372 return; 373 } 374 CSR_WRITE_2(sc, re8139_reg, data); 375 splx(s); 376 return; 377 } 378 379 static void 380 re_miibus_statchg(struct device *dev) 381 { 382 383 return; 384 } 385 386 static void 387 re_reset(struct rtk_softc *sc) 388 { 389 register int i; 390 391 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_RESET); 392 393 for (i = 0; i < RTK_TIMEOUT; i++) { 394 DELAY(10); 395 if (!(CSR_READ_1(sc, RTK_COMMAND) & RTK_CMD_RESET)) 396 break; 397 } 398 if (i == RTK_TIMEOUT) 399 aprint_error("%s: reset never completed!\n", 400 sc->sc_dev.dv_xname); 401 402 /* 403 * NB: Realtek-supplied Linux driver does this only for 404 * MCFG_METHOD_2, which corresponds to sc->sc_rev == 2. 405 */ 406 if (1) /* XXX check softc flag for 8169s version */ 407 CSR_WRITE_1(sc, 0x82, 1); 408 409 return; 410 } 411 412 /* 413 * The following routine is designed to test for a defect on some 414 * 32-bit 8169 cards. Some of these NICs have the REQ64# and ACK64# 415 * lines connected to the bus, however for a 32-bit only card, they 416 * should be pulled high. The result of this defect is that the 417 * NIC will not work right if you plug it into a 64-bit slot: DMA 418 * operations will be done with 64-bit transfers, which will fail 419 * because the 64-bit data lines aren't connected. 420 * 421 * There's no way to work around this (short of talking a soldering 422 * iron to the board), however we can detect it. The method we use 423 * here is to put the NIC into digital loopback mode, set the receiver 424 * to promiscuous mode, and then try to send a frame. We then compare 425 * the frame data we sent to what was received. If the data matches, 426 * then the NIC is working correctly, otherwise we know the user has 427 * a defective NIC which has been mistakenly plugged into a 64-bit PCI 428 * slot. In the latter case, there's no way the NIC can work correctly, 429 * so we print out a message on the console and abort the device attach. 430 */ 431 432 int 433 re_diag(struct rtk_softc *sc) 434 { 435 struct ifnet *ifp = &sc->ethercom.ec_if; 436 struct mbuf *m0; 437 struct ether_header *eh; 438 struct rtk_desc *cur_rx; 439 bus_dmamap_t dmamap; 440 u_int16_t status; 441 u_int32_t rxstat; 442 int total_len, i, s, error = 0; 443 u_int8_t dst[] = { 0x00, 'h', 'e', 'l', 'l', 'o' }; 444 u_int8_t src[] = { 0x00, 'w', 'o', 'r', 'l', 'd' }; 445 446 /* Allocate a single mbuf */ 447 448 MGETHDR(m0, M_DONTWAIT, MT_DATA); 449 if (m0 == NULL) 450 return ENOBUFS; 451 452 /* 453 * Initialize the NIC in test mode. This sets the chip up 454 * so that it can send and receive frames, but performs the 455 * following special functions: 456 * - Puts receiver in promiscuous mode 457 * - Enables digital loopback mode 458 * - Leaves interrupts turned off 459 */ 460 461 ifp->if_flags |= IFF_PROMISC; 462 sc->rtk_testmode = 1; 463 re_init(ifp); 464 re_stop(ifp, 0); 465 DELAY(100000); 466 re_init(ifp); 467 468 /* Put some data in the mbuf */ 469 470 eh = mtod(m0, struct ether_header *); 471 bcopy((char *)&dst, eh->ether_dhost, ETHER_ADDR_LEN); 472 bcopy((char *)&src, eh->ether_shost, ETHER_ADDR_LEN); 473 eh->ether_type = htons(ETHERTYPE_IP); 474 m0->m_pkthdr.len = m0->m_len = ETHER_MIN_LEN - ETHER_CRC_LEN; 475 476 /* 477 * Queue the packet, start transmission. 478 */ 479 480 CSR_WRITE_2(sc, RTK_ISR, 0xFFFF); 481 s = splnet(); 482 IF_ENQUEUE(&ifp->if_snd, m0); 483 re_start(ifp); 484 splx(s); 485 m0 = NULL; 486 487 /* Wait for it to propagate through the chip */ 488 489 DELAY(100000); 490 for (i = 0; i < RTK_TIMEOUT; i++) { 491 status = CSR_READ_2(sc, RTK_ISR); 492 if ((status & (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) == 493 (RTK_ISR_TIMEOUT_EXPIRED | RTK_ISR_RX_OK)) 494 break; 495 DELAY(10); 496 } 497 if (i == RTK_TIMEOUT) { 498 aprint_error("%s: diagnostic failed, failed to receive packet " 499 "in loopback mode\n", sc->sc_dev.dv_xname); 500 error = EIO; 501 goto done; 502 } 503 504 /* 505 * The packet should have been dumped into the first 506 * entry in the RX DMA ring. Grab it from there. 507 */ 508 509 dmamap = sc->rtk_ldata.rtk_rx_list_map; 510 bus_dmamap_sync(sc->sc_dmat, 511 dmamap, 0, dmamap->dm_mapsize, BUS_DMASYNC_POSTREAD); 512 dmamap = sc->rtk_ldata.rtk_rx_dmamap[0]; 513 bus_dmamap_sync(sc->sc_dmat, dmamap, 0, dmamap->dm_mapsize, 514 BUS_DMASYNC_POSTWRITE); 515 bus_dmamap_unload(sc->sc_dmat, 516 sc->rtk_ldata.rtk_rx_dmamap[0]); 517 518 m0 = sc->rtk_ldata.rtk_rx_mbuf[0]; 519 sc->rtk_ldata.rtk_rx_mbuf[0] = NULL; 520 eh = mtod(m0, struct ether_header *); 521 522 cur_rx = &sc->rtk_ldata.rtk_rx_list[0]; 523 total_len = RTK_RXBYTES(cur_rx); 524 rxstat = le32toh(cur_rx->rtk_cmdstat); 525 526 if (total_len != ETHER_MIN_LEN) { 527 aprint_error("%s: diagnostic failed, received short packet\n", 528 sc->sc_dev.dv_xname); 529 error = EIO; 530 goto done; 531 } 532 533 /* Test that the received packet data matches what we sent. */ 534 535 if (bcmp((char *)&eh->ether_dhost, (char *)&dst, ETHER_ADDR_LEN) || 536 bcmp((char *)&eh->ether_shost, (char *)&src, ETHER_ADDR_LEN) || 537 ntohs(eh->ether_type) != ETHERTYPE_IP) { 538 aprint_error("%s: WARNING, DMA FAILURE!\n", 539 sc->sc_dev.dv_xname); 540 aprint_error("%s: expected TX data: %s", 541 sc->sc_dev.dv_xname, ether_sprintf(dst)); 542 aprint_error("/%s/0x%x\n", ether_sprintf(src), ETHERTYPE_IP); 543 aprint_error("%s: received RX data: %s", 544 sc->sc_dev.dv_xname, 545 ether_sprintf(eh->ether_dhost)); 546 aprint_error("/%s/0x%x\n", ether_sprintf(eh->ether_shost), 547 ntohs(eh->ether_type)); 548 aprint_error("%s: You may have a defective 32-bit NIC plugged " 549 "into a 64-bit PCI slot.\n", sc->sc_dev.dv_xname); 550 aprint_error("%s: Please re-install the NIC in a 32-bit slot " 551 "for proper operation.\n", sc->sc_dev.dv_xname); 552 aprint_error("%s: Read the re(4) man page for more details.\n", 553 sc->sc_dev.dv_xname); 554 error = EIO; 555 } 556 557 done: 558 /* Turn interface off, release resources */ 559 560 sc->rtk_testmode = 0; 561 ifp->if_flags &= ~IFF_PROMISC; 562 re_stop(ifp, 0); 563 if (m0 != NULL) 564 m_freem(m0); 565 566 return error; 567 } 568 569 570 /* 571 * Attach the interface. Allocate softc structures, do ifmedia 572 * setup and ethernet/BPF attach. 573 */ 574 void 575 re_attach(struct rtk_softc *sc) 576 { 577 u_char eaddr[ETHER_ADDR_LEN]; 578 u_int16_t val; 579 struct ifnet *ifp; 580 int error = 0, i, addr_len; 581 582 583 /* XXX JRS: bus-attach-independent code begins approximately here */ 584 585 /* Reset the adapter. */ 586 re_reset(sc); 587 588 if (sc->rtk_type == RTK_8169) { 589 uint32_t hwrev; 590 591 /* Revision of 8169/8169S/8110s in bits 30..26, 23 */ 592 hwrev = CSR_READ_4(sc, RTK_TXCFG) & 0x7c800000; 593 if (hwrev == (0x1 << 28)) { 594 sc->sc_rev = 4; 595 } else if (hwrev == (0x1 << 26)) { 596 sc->sc_rev = 3; 597 } else if (hwrev == (0x1 << 23)) { 598 sc->sc_rev = 2; 599 } else 600 sc->sc_rev = 1; 601 602 /* Set RX length mask */ 603 604 sc->rtk_rxlenmask = RTK_RDESC_STAT_GFRAGLEN; 605 606 /* Force station address autoload from the EEPROM */ 607 608 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_AUTOLOAD); 609 for (i = 0; i < RTK_TIMEOUT; i++) { 610 if (!(CSR_READ_1(sc, RTK_EECMD) & RTK_EEMODE_AUTOLOAD)) 611 break; 612 DELAY(100); 613 } 614 if (i == RTK_TIMEOUT) 615 aprint_error("%s: eeprom autoload timed out\n", 616 sc->sc_dev.dv_xname); 617 618 for (i = 0; i < ETHER_ADDR_LEN; i++) 619 eaddr[i] = CSR_READ_1(sc, RTK_IDR0 + i); 620 } else { 621 622 /* Set RX length mask */ 623 624 sc->rtk_rxlenmask = RTK_RDESC_STAT_FRAGLEN; 625 626 if (rtk_read_eeprom(sc, RTK_EE_ID, RTK_EEADDR_LEN1) == 0x8129) 627 addr_len = RTK_EEADDR_LEN1; 628 else 629 addr_len = RTK_EEADDR_LEN0; 630 631 /* 632 * Get station address from the EEPROM. 633 */ 634 for (i = 0; i < 3; i++) { 635 val = rtk_read_eeprom(sc, RTK_EE_EADDR0 + i, addr_len); 636 eaddr[(i * 2) + 0] = val & 0xff; 637 eaddr[(i * 2) + 1] = val >> 8; 638 } 639 } 640 641 aprint_normal("%s: Ethernet address %s\n", 642 sc->sc_dev.dv_xname, ether_sprintf(eaddr)); 643 644 645 /* Allocate DMA'able memory for the TX ring */ 646 if ((error = bus_dmamem_alloc(sc->sc_dmat, RTK_TX_LIST_SZ, 647 RTK_ETHER_ALIGN, 0, &sc->rtk_ldata.rtk_tx_listseg, 648 1, &sc->rtk_ldata.rtk_tx_listnseg, BUS_DMA_NOWAIT)) != 0) { 649 aprint_error("%s: can't allocate tx listseg, error = %d\n", 650 sc->sc_dev.dv_xname, error); 651 goto fail_0; 652 } 653 654 /* Load the map for the TX ring. */ 655 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->rtk_ldata.rtk_tx_listseg, 656 sc->rtk_ldata.rtk_tx_listnseg, RTK_TX_LIST_SZ, 657 (caddr_t *)&sc->rtk_ldata.rtk_tx_list, 658 BUS_DMA_NOWAIT)) != 0) { 659 aprint_error("%s: can't map tx list, error = %d\n", 660 sc->sc_dev.dv_xname, error); 661 goto fail_1; 662 } 663 memset(sc->rtk_ldata.rtk_tx_list, 0, RTK_TX_LIST_SZ); 664 665 if ((error = bus_dmamap_create(sc->sc_dmat, RTK_TX_LIST_SZ, 1, 666 RTK_TX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 667 &sc->rtk_ldata.rtk_tx_list_map)) != 0) { 668 aprint_error("%s: can't create tx list map, error = %d\n", 669 sc->sc_dev.dv_xname, error); 670 goto fail_2; 671 } 672 673 674 if ((error = bus_dmamap_load(sc->sc_dmat, 675 sc->rtk_ldata.rtk_tx_list_map, sc->rtk_ldata.rtk_tx_list, 676 RTK_TX_LIST_SZ, NULL, BUS_DMA_NOWAIT)) != 0) { 677 aprint_error("%s: can't load tx list, error = %d\n", 678 sc->sc_dev.dv_xname, error); 679 goto fail_3; 680 } 681 682 /* Create DMA maps for TX buffers */ 683 for (i = 0; i < RTK_TX_DESC_CNT; i++) { 684 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES * RTK_NTXSEGS, 685 RTK_NTXSEGS, MCLBYTES, 0, BUS_DMA_ALLOCNOW, 686 &sc->rtk_ldata.rtk_tx_dmamap[i]); 687 if (error) { 688 aprint_error("%s: can't create DMA map for TX\n", 689 sc->sc_dev.dv_xname); 690 goto fail_4; 691 } 692 } 693 694 /* Allocate DMA'able memory for the RX ring */ 695 if ((error = bus_dmamem_alloc(sc->sc_dmat, RTK_RX_LIST_SZ, 696 RTK_RING_ALIGN, 0, &sc->rtk_ldata.rtk_rx_listseg, 1, 697 &sc->rtk_ldata.rtk_rx_listnseg, BUS_DMA_NOWAIT)) != 0) { 698 aprint_error("%s: can't allocate rx listseg, error = %d\n", 699 sc->sc_dev.dv_xname, error); 700 goto fail_4; 701 } 702 703 /* Load the map for the RX ring. */ 704 if ((error = bus_dmamem_map(sc->sc_dmat, &sc->rtk_ldata.rtk_rx_listseg, 705 sc->rtk_ldata.rtk_rx_listnseg, RTK_RX_LIST_SZ, 706 (caddr_t *)&sc->rtk_ldata.rtk_rx_list, 707 BUS_DMA_NOWAIT)) != 0) { 708 aprint_error("%s: can't map rx list, error = %d\n", 709 sc->sc_dev.dv_xname, error); 710 goto fail_5; 711 } 712 memset(sc->rtk_ldata.rtk_rx_list, 0, RTK_TX_LIST_SZ); 713 714 if ((error = bus_dmamap_create(sc->sc_dmat, RTK_RX_LIST_SZ, 1, 715 RTK_RX_LIST_SZ, 0, BUS_DMA_ALLOCNOW, 716 &sc->rtk_ldata.rtk_rx_list_map)) != 0) { 717 aprint_error("%s: can't create rx list map, error = %d\n", 718 sc->sc_dev.dv_xname, error); 719 goto fail_6; 720 } 721 722 if ((error = bus_dmamap_load(sc->sc_dmat, 723 sc->rtk_ldata.rtk_rx_list_map, sc->rtk_ldata.rtk_rx_list, 724 RTK_RX_LIST_SZ, NULL, BUS_DMA_NOWAIT)) != 0) { 725 aprint_error("%s: can't load rx list, error = %d\n", 726 sc->sc_dev.dv_xname, error); 727 goto fail_7; 728 } 729 730 /* Create DMA maps for RX buffers */ 731 for (i = 0; i < RTK_RX_DESC_CNT; i++) { 732 error = bus_dmamap_create(sc->sc_dmat, MCLBYTES, 1, MCLBYTES, 733 0, BUS_DMA_ALLOCNOW, &sc->rtk_ldata.rtk_rx_dmamap[i]); 734 if (error) { 735 aprint_error("%s: can't create DMA map for RX\n", 736 sc->sc_dev.dv_xname); 737 goto fail_8; 738 } 739 } 740 741 /* 742 * Record interface as attached. From here, we should not fail. 743 */ 744 sc->sc_flags |= RTK_ATTACHED; 745 746 ifp = &sc->ethercom.ec_if; 747 ifp->if_softc = sc; 748 strcpy(ifp->if_xname, sc->sc_dev.dv_xname); 749 ifp->if_mtu = ETHERMTU; 750 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 751 ifp->if_ioctl = re_ioctl; 752 sc->ethercom.ec_capabilities |= 753 ETHERCAP_VLAN_MTU | ETHERCAP_VLAN_HWTAGGING; 754 ifp->if_start = re_start; 755 ifp->if_stop = re_stop; 756 ifp->if_capabilities |= 757 IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4; 758 ifp->if_watchdog = re_watchdog; 759 ifp->if_init = re_init; 760 if (sc->rtk_type == RTK_8169) 761 ifp->if_baudrate = 1000000000; 762 else 763 ifp->if_baudrate = 100000000; 764 ifp->if_snd.ifq_maxlen = RTK_IFQ_MAXLEN; 765 ifp->if_capenable = ifp->if_capabilities; 766 IFQ_SET_READY(&ifp->if_snd); 767 768 callout_init(&sc->rtk_tick_ch); 769 770 /* Do MII setup */ 771 sc->mii.mii_ifp = ifp; 772 sc->mii.mii_readreg = re_miibus_readreg; 773 sc->mii.mii_writereg = re_miibus_writereg; 774 sc->mii.mii_statchg = re_miibus_statchg; 775 ifmedia_init(&sc->mii.mii_media, IFM_IMASK, re_ifmedia_upd, 776 re_ifmedia_sts); 777 mii_attach(&sc->sc_dev, &sc->mii, 0xffffffff, MII_PHY_ANY, 778 MII_OFFSET_ANY, 0); 779 ifmedia_set(&sc->mii.mii_media, IFM_ETHER | IFM_AUTO); 780 781 /* 782 * Call MI attach routine. 783 */ 784 if_attach(ifp); 785 ether_ifattach(ifp, eaddr); 786 787 788 /* 789 * Make sure the interface is shutdown during reboot. 790 */ 791 sc->sc_sdhook = shutdownhook_establish(re_shutdown, sc); 792 if (sc->sc_sdhook == NULL) 793 aprint_error("%s: WARNING: unable to establish shutdown hook\n", 794 sc->sc_dev.dv_xname); 795 /* 796 * Add a suspend hook to make sure we come back up after a 797 * resume. 798 */ 799 sc->sc_powerhook = powerhook_establish(re_power, sc); 800 if (sc->sc_powerhook == NULL) 801 aprint_error("%s: WARNING: unable to establish power hook\n", 802 sc->sc_dev.dv_xname); 803 804 805 return; 806 807 fail_8: 808 /* Destroy DMA maps for RX buffers. */ 809 for (i = 0; i < RTK_RX_DESC_CNT; i++) 810 if (sc->rtk_ldata.rtk_rx_dmamap[i] != NULL) 811 bus_dmamap_destroy(sc->sc_dmat, 812 sc->rtk_ldata.rtk_rx_dmamap[i]); 813 814 /* Free DMA'able memory for the RX ring. */ 815 bus_dmamap_unload(sc->sc_dmat, sc->rtk_ldata.rtk_rx_list_map); 816 fail_7: 817 bus_dmamap_destroy(sc->sc_dmat, sc->rtk_ldata.rtk_rx_list_map); 818 fail_6: 819 bus_dmamem_unmap(sc->sc_dmat, 820 (caddr_t)sc->rtk_ldata.rtk_rx_list, RTK_RX_LIST_SZ); 821 fail_5: 822 bus_dmamem_free(sc->sc_dmat, 823 &sc->rtk_ldata.rtk_rx_listseg, sc->rtk_ldata.rtk_rx_listnseg); 824 825 fail_4: 826 /* Destroy DMA maps for TX buffers. */ 827 for (i = 0; i < RTK_TX_DESC_CNT; i++) 828 if (sc->rtk_ldata.rtk_tx_dmamap[i] != NULL) 829 bus_dmamap_destroy(sc->sc_dmat, 830 sc->rtk_ldata.rtk_tx_dmamap[i]); 831 832 /* Free DMA'able memory for the TX ring. */ 833 bus_dmamap_unload(sc->sc_dmat, sc->rtk_ldata.rtk_tx_list_map); 834 fail_3: 835 bus_dmamap_destroy(sc->sc_dmat, sc->rtk_ldata.rtk_tx_list_map); 836 fail_2: 837 bus_dmamem_unmap(sc->sc_dmat, 838 (caddr_t)sc->rtk_ldata.rtk_tx_list, RTK_TX_LIST_SZ); 839 fail_1: 840 bus_dmamem_free(sc->sc_dmat, 841 &sc->rtk_ldata.rtk_tx_listseg, sc->rtk_ldata.rtk_tx_listnseg); 842 fail_0: 843 return; 844 } 845 846 847 /* 848 * re_activate: 849 * Handle device activation/deactivation requests. 850 */ 851 int 852 re_activate(struct device *self, enum devact act) 853 { 854 struct rtk_softc *sc = (void *) self; 855 int s, error = 0; 856 857 s = splnet(); 858 switch (act) { 859 case DVACT_ACTIVATE: 860 error = EOPNOTSUPP; 861 break; 862 case DVACT_DEACTIVATE: 863 mii_activate(&sc->mii, act, MII_PHY_ANY, MII_OFFSET_ANY); 864 if_deactivate(&sc->ethercom.ec_if); 865 break; 866 } 867 splx(s); 868 869 return error; 870 } 871 872 /* 873 * re_detach: 874 * Detach a rtk interface. 875 */ 876 int 877 re_detach(struct rtk_softc *sc) 878 { 879 struct ifnet *ifp = &sc->ethercom.ec_if; 880 int i; 881 882 /* 883 * Succeed now if there isn't any work to do. 884 */ 885 if ((sc->sc_flags & RTK_ATTACHED) == 0) 886 return 0; 887 888 /* Unhook our tick handler. */ 889 callout_stop(&sc->rtk_tick_ch); 890 891 /* Detach all PHYs. */ 892 mii_detach(&sc->mii, MII_PHY_ANY, MII_OFFSET_ANY); 893 894 /* Delete all remaining media. */ 895 ifmedia_delete_instance(&sc->mii.mii_media, IFM_INST_ANY); 896 897 ether_ifdetach(ifp); 898 if_detach(ifp); 899 900 /* XXX undo re_allocmem() */ 901 902 /* Destroy DMA maps for RX buffers. */ 903 for (i = 0; i < RTK_RX_DESC_CNT; i++) 904 if (sc->rtk_ldata.rtk_rx_dmamap[i] != NULL) 905 bus_dmamap_destroy(sc->sc_dmat, 906 sc->rtk_ldata.rtk_rx_dmamap[i]); 907 908 /* Free DMA'able memory for the RX ring. */ 909 bus_dmamap_unload(sc->sc_dmat, sc->rtk_ldata.rtk_rx_list_map); 910 bus_dmamap_destroy(sc->sc_dmat, sc->rtk_ldata.rtk_rx_list_map); 911 bus_dmamem_unmap(sc->sc_dmat, 912 (caddr_t)sc->rtk_ldata.rtk_rx_list, RTK_RX_LIST_SZ); 913 bus_dmamem_free(sc->sc_dmat, 914 &sc->rtk_ldata.rtk_rx_listseg, sc->rtk_ldata.rtk_rx_listnseg); 915 916 /* Destroy DMA maps for TX buffers. */ 917 for (i = 0; i < RTK_TX_DESC_CNT; i++) 918 if (sc->rtk_ldata.rtk_tx_dmamap[i] != NULL) 919 bus_dmamap_destroy(sc->sc_dmat, 920 sc->rtk_ldata.rtk_tx_dmamap[i]); 921 922 /* Free DMA'able memory for the TX ring. */ 923 bus_dmamap_unload(sc->sc_dmat, sc->rtk_ldata.rtk_tx_list_map); 924 bus_dmamap_destroy(sc->sc_dmat, sc->rtk_ldata.rtk_tx_list_map); 925 bus_dmamem_unmap(sc->sc_dmat, 926 (caddr_t)sc->rtk_ldata.rtk_tx_list, RTK_TX_LIST_SZ); 927 bus_dmamem_free(sc->sc_dmat, 928 &sc->rtk_ldata.rtk_tx_listseg, sc->rtk_ldata.rtk_tx_listnseg); 929 930 931 shutdownhook_disestablish(sc->sc_sdhook); 932 powerhook_disestablish(sc->sc_powerhook); 933 934 return 0; 935 } 936 937 /* 938 * re_enable: 939 * Enable the RTL81X9 chip. 940 */ 941 static int 942 re_enable(struct rtk_softc *sc) 943 { 944 if (RTK_IS_ENABLED(sc) == 0 && sc->sc_enable != NULL) { 945 if ((*sc->sc_enable)(sc) != 0) { 946 aprint_error("%s: device enable failed\n", 947 sc->sc_dev.dv_xname); 948 return EIO; 949 } 950 sc->sc_flags |= RTK_ENABLED; 951 } 952 return 0; 953 } 954 955 /* 956 * re_disable: 957 * Disable the RTL81X9 chip. 958 */ 959 static void 960 re_disable(struct rtk_softc *sc) 961 { 962 963 if (RTK_IS_ENABLED(sc) && sc->sc_disable != NULL) { 964 (*sc->sc_disable)(sc); 965 sc->sc_flags &= ~RTK_ENABLED; 966 } 967 } 968 969 /* 970 * re_power: 971 * Power management (suspend/resume) hook. 972 */ 973 void 974 re_power(int why, void *arg) 975 { 976 struct rtk_softc *sc = (void *) arg; 977 struct ifnet *ifp = &sc->ethercom.ec_if; 978 int s; 979 980 s = splnet(); 981 switch (why) { 982 case PWR_SUSPEND: 983 case PWR_STANDBY: 984 re_stop(ifp, 0); 985 if (sc->sc_power != NULL) 986 (*sc->sc_power)(sc, why); 987 break; 988 case PWR_RESUME: 989 if (ifp->if_flags & IFF_UP) { 990 if (sc->sc_power != NULL) 991 (*sc->sc_power)(sc, why); 992 re_init(ifp); 993 } 994 break; 995 case PWR_SOFTSUSPEND: 996 case PWR_SOFTSTANDBY: 997 case PWR_SOFTRESUME: 998 break; 999 } 1000 splx(s); 1001 } 1002 1003 1004 static int 1005 re_newbuf(struct rtk_softc *sc, int idx, struct mbuf *m) 1006 { 1007 struct mbuf *n = NULL; 1008 bus_dmamap_t map; 1009 struct rtk_desc *d; 1010 u_int32_t cmdstat; 1011 int error; 1012 1013 if (m == NULL) { 1014 MGETHDR(n, M_DONTWAIT, MT_DATA); 1015 if (n == NULL) 1016 return ENOBUFS; 1017 m = n; 1018 1019 MCLGET(m, M_DONTWAIT); 1020 if (!(m->m_flags & M_EXT)) { 1021 m_freem(m); 1022 return ENOBUFS; 1023 } 1024 } else 1025 m->m_data = m->m_ext.ext_buf; 1026 1027 /* 1028 * Initialize mbuf length fields and fixup 1029 * alignment so that the frame payload is 1030 * longword aligned. 1031 */ 1032 m->m_len = m->m_pkthdr.len = MCLBYTES; 1033 m_adj(m, RTK_ETHER_ALIGN); 1034 1035 map = sc->rtk_ldata.rtk_rx_dmamap[idx]; 1036 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, m, BUS_DMA_NOWAIT); 1037 1038 if (error) 1039 goto out; 1040 1041 d = &sc->rtk_ldata.rtk_rx_list[idx]; 1042 if (le32toh(d->rtk_cmdstat) & RTK_RDESC_STAT_OWN) 1043 goto out; 1044 1045 cmdstat = map->dm_segs[0].ds_len; 1046 d->rtk_bufaddr_lo = htole32(RTK_ADDR_LO(map->dm_segs[0].ds_addr)); 1047 d->rtk_bufaddr_hi = htole32(RTK_ADDR_HI(map->dm_segs[0].ds_addr)); 1048 cmdstat |= RTK_TDESC_CMD_SOF; 1049 if (idx == (RTK_RX_DESC_CNT - 1)) 1050 cmdstat |= RTK_TDESC_CMD_EOR; 1051 d->rtk_cmdstat = htole32(cmdstat); 1052 1053 d->rtk_cmdstat |= htole32(RTK_TDESC_CMD_EOF); 1054 1055 1056 sc->rtk_ldata.rtk_rx_list[idx].rtk_cmdstat |= 1057 htole32(RTK_RDESC_CMD_OWN); 1058 sc->rtk_ldata.rtk_rx_mbuf[idx] = m; 1059 1060 bus_dmamap_sync(sc->sc_dmat, sc->rtk_ldata.rtk_rx_dmamap[idx], 0, 1061 sc->rtk_ldata.rtk_rx_dmamap[idx]->dm_mapsize, 1062 BUS_DMASYNC_PREREAD); 1063 1064 return 0; 1065 out: 1066 if (n != NULL) 1067 m_freem(n); 1068 return ENOMEM; 1069 } 1070 1071 static int 1072 re_tx_list_init(struct rtk_softc *sc) 1073 { 1074 memset((char *)sc->rtk_ldata.rtk_tx_list, 0, RTK_TX_LIST_SZ); 1075 memset((char *)&sc->rtk_ldata.rtk_tx_mbuf, 0, 1076 (RTK_TX_DESC_CNT * sizeof(struct mbuf *))); 1077 1078 bus_dmamap_sync(sc->sc_dmat, 1079 sc->rtk_ldata.rtk_tx_list_map, 0, 1080 sc->rtk_ldata.rtk_tx_list_map->dm_mapsize, BUS_DMASYNC_PREWRITE); 1081 sc->rtk_ldata.rtk_tx_prodidx = 0; 1082 sc->rtk_ldata.rtk_tx_considx = 0; 1083 sc->rtk_ldata.rtk_tx_free = RTK_TX_DESC_CNT; 1084 1085 return 0; 1086 } 1087 1088 static int 1089 re_rx_list_init(struct rtk_softc *sc) 1090 { 1091 int i; 1092 1093 memset((char *)sc->rtk_ldata.rtk_rx_list, 0, RTK_RX_LIST_SZ); 1094 memset((char *)&sc->rtk_ldata.rtk_rx_mbuf, 0, 1095 (RTK_RX_DESC_CNT * sizeof(struct mbuf *))); 1096 1097 for (i = 0; i < RTK_RX_DESC_CNT; i++) { 1098 if (re_newbuf(sc, i, NULL) == ENOBUFS) 1099 return ENOBUFS; 1100 } 1101 1102 /* Flush the RX descriptors */ 1103 1104 bus_dmamap_sync(sc->sc_dmat, 1105 sc->rtk_ldata.rtk_rx_list_map, 1106 0, sc->rtk_ldata.rtk_rx_list_map->dm_mapsize, 1107 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1108 1109 sc->rtk_ldata.rtk_rx_prodidx = 0; 1110 sc->rtk_head = sc->rtk_tail = NULL; 1111 1112 return 0; 1113 } 1114 1115 /* 1116 * RX handler for C+ and 8169. For the gigE chips, we support 1117 * the reception of jumbo frames that have been fragmented 1118 * across multiple 2K mbuf cluster buffers. 1119 */ 1120 static void 1121 re_rxeof(struct rtk_softc *sc) 1122 { 1123 struct mbuf *m; 1124 struct ifnet *ifp; 1125 int i, total_len; 1126 struct rtk_desc *cur_rx; 1127 u_int32_t rxstat, rxvlan; 1128 1129 ifp = &sc->ethercom.ec_if; 1130 i = sc->rtk_ldata.rtk_rx_prodidx; 1131 1132 /* Invalidate the descriptor memory */ 1133 1134 bus_dmamap_sync(sc->sc_dmat, 1135 sc->rtk_ldata.rtk_rx_list_map, 1136 0, sc->rtk_ldata.rtk_rx_list_map->dm_mapsize, 1137 BUS_DMASYNC_POSTREAD); 1138 1139 while (!RTK_OWN(&sc->rtk_ldata.rtk_rx_list[i])) { 1140 1141 cur_rx = &sc->rtk_ldata.rtk_rx_list[i]; 1142 m = sc->rtk_ldata.rtk_rx_mbuf[i]; 1143 total_len = RTK_RXBYTES(cur_rx); 1144 rxstat = le32toh(cur_rx->rtk_cmdstat); 1145 rxvlan = le32toh(cur_rx->rtk_vlanctl); 1146 1147 /* Invalidate the RX mbuf and unload its map */ 1148 1149 bus_dmamap_sync(sc->sc_dmat, 1150 sc->rtk_ldata.rtk_rx_dmamap[i], 1151 0, sc->rtk_ldata.rtk_rx_dmamap[i]->dm_mapsize, 1152 BUS_DMASYNC_POSTWRITE); 1153 bus_dmamap_unload(sc->sc_dmat, 1154 sc->rtk_ldata.rtk_rx_dmamap[i]); 1155 1156 if (!(rxstat & RTK_RDESC_STAT_EOF)) { 1157 m->m_len = MCLBYTES - RTK_ETHER_ALIGN; 1158 if (sc->rtk_head == NULL) 1159 sc->rtk_head = sc->rtk_tail = m; 1160 else { 1161 m->m_flags &= ~M_PKTHDR; 1162 sc->rtk_tail->m_next = m; 1163 sc->rtk_tail = m; 1164 } 1165 re_newbuf(sc, i, NULL); 1166 RTK_DESC_INC(i); 1167 continue; 1168 } 1169 1170 /* 1171 * NOTE: for the 8139C+, the frame length field 1172 * is always 12 bits in size, but for the gigE chips, 1173 * it is 13 bits (since the max RX frame length is 16K). 1174 * Unfortunately, all 32 bits in the status word 1175 * were already used, so to make room for the extra 1176 * length bit, RealTek took out the 'frame alignment 1177 * error' bit and shifted the other status bits 1178 * over one slot. The OWN, EOR, FS and LS bits are 1179 * still in the same places. We have already extracted 1180 * the frame length and checked the OWN bit, so rather 1181 * than using an alternate bit mapping, we shift the 1182 * status bits one space to the right so we can evaluate 1183 * them using the 8169 status as though it was in the 1184 * same format as that of the 8139C+. 1185 */ 1186 if (sc->rtk_type == RTK_8169) 1187 rxstat >>= 1; 1188 1189 if (rxstat & RTK_RDESC_STAT_RXERRSUM) { 1190 ifp->if_ierrors++; 1191 /* 1192 * If this is part of a multi-fragment packet, 1193 * discard all the pieces. 1194 */ 1195 if (sc->rtk_head != NULL) { 1196 m_freem(sc->rtk_head); 1197 sc->rtk_head = sc->rtk_tail = NULL; 1198 } 1199 re_newbuf(sc, i, m); 1200 RTK_DESC_INC(i); 1201 continue; 1202 } 1203 1204 /* 1205 * If allocating a replacement mbuf fails, 1206 * reload the current one. 1207 */ 1208 1209 if (re_newbuf(sc, i, NULL)) { 1210 ifp->if_ierrors++; 1211 if (sc->rtk_head != NULL) { 1212 m_freem(sc->rtk_head); 1213 sc->rtk_head = sc->rtk_tail = NULL; 1214 } 1215 re_newbuf(sc, i, m); 1216 RTK_DESC_INC(i); 1217 continue; 1218 } 1219 1220 RTK_DESC_INC(i); 1221 1222 if (sc->rtk_head != NULL) { 1223 m->m_len = total_len % (MCLBYTES - RTK_ETHER_ALIGN); 1224 /* 1225 * Special case: if there's 4 bytes or less 1226 * in this buffer, the mbuf can be discarded: 1227 * the last 4 bytes is the CRC, which we don't 1228 * care about anyway. 1229 */ 1230 if (m->m_len <= ETHER_CRC_LEN) { 1231 sc->rtk_tail->m_len -= 1232 (ETHER_CRC_LEN - m->m_len); 1233 m_freem(m); 1234 } else { 1235 m->m_len -= ETHER_CRC_LEN; 1236 m->m_flags &= ~M_PKTHDR; 1237 sc->rtk_tail->m_next = m; 1238 } 1239 m = sc->rtk_head; 1240 sc->rtk_head = sc->rtk_tail = NULL; 1241 m->m_pkthdr.len = total_len - ETHER_CRC_LEN; 1242 } else 1243 m->m_pkthdr.len = m->m_len = 1244 (total_len - ETHER_CRC_LEN); 1245 1246 ifp->if_ipackets++; 1247 m->m_pkthdr.rcvif = ifp; 1248 1249 /* Do RX checksumming if enabled */ 1250 1251 if (ifp->if_capenable & IFCAP_CSUM_IPv4) { 1252 1253 /* Check IP header checksum */ 1254 if (rxstat & RTK_RDESC_STAT_PROTOID) 1255 m->m_pkthdr.csum_flags |= M_CSUM_IPv4;; 1256 if (rxstat & RTK_RDESC_STAT_IPSUMBAD) 1257 m->m_pkthdr.csum_flags |= M_CSUM_IPv4_BAD; 1258 } 1259 1260 /* Check TCP/UDP checksum */ 1261 if (RTK_TCPPKT(rxstat) && 1262 (ifp->if_capenable & IFCAP_CSUM_TCPv4)) { 1263 m->m_pkthdr.csum_flags |= M_CSUM_TCPv4; 1264 if (rxstat & RTK_RDESC_STAT_TCPSUMBAD) 1265 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1266 } 1267 if (RTK_UDPPKT(rxstat) && 1268 (ifp->if_capenable & IFCAP_CSUM_UDPv4)) { 1269 m->m_pkthdr.csum_flags |= M_CSUM_UDPv4; 1270 if (rxstat & RTK_RDESC_STAT_UDPSUMBAD) 1271 m->m_pkthdr.csum_flags |= M_CSUM_TCP_UDP_BAD; 1272 } 1273 1274 if (rxvlan & RTK_RDESC_VLANCTL_TAG) { 1275 VLAN_INPUT_TAG(ifp, m, 1276 be16toh(rxvlan & RTK_RDESC_VLANCTL_DATA), 1277 continue); 1278 } 1279 #if NBPFILTER > 0 1280 if (ifp->if_bpf) 1281 bpf_mtap(ifp->if_bpf, m); 1282 #endif 1283 (*ifp->if_input)(ifp, m); 1284 } 1285 1286 /* Flush the RX DMA ring */ 1287 1288 bus_dmamap_sync(sc->sc_dmat, 1289 sc->rtk_ldata.rtk_rx_list_map, 1290 0, sc->rtk_ldata.rtk_rx_list_map->dm_mapsize, 1291 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1292 1293 sc->rtk_ldata.rtk_rx_prodidx = i; 1294 1295 return; 1296 } 1297 1298 static void 1299 re_txeof(struct rtk_softc *sc) 1300 { 1301 struct ifnet *ifp; 1302 u_int32_t txstat; 1303 int idx; 1304 1305 ifp = &sc->ethercom.ec_if; 1306 idx = sc->rtk_ldata.rtk_tx_considx; 1307 1308 /* Invalidate the TX descriptor list */ 1309 1310 bus_dmamap_sync(sc->sc_dmat, 1311 sc->rtk_ldata.rtk_tx_list_map, 1312 0, sc->rtk_ldata.rtk_tx_list_map->dm_mapsize, 1313 BUS_DMASYNC_POSTREAD); 1314 1315 while (idx != sc->rtk_ldata.rtk_tx_prodidx) { 1316 1317 txstat = le32toh(sc->rtk_ldata.rtk_tx_list[idx].rtk_cmdstat); 1318 if (txstat & RTK_TDESC_CMD_OWN) 1319 break; 1320 1321 /* 1322 * We only stash mbufs in the last descriptor 1323 * in a fragment chain, which also happens to 1324 * be the only place where the TX status bits 1325 * are valid. 1326 */ 1327 1328 if (txstat & RTK_TDESC_CMD_EOF) { 1329 m_freem(sc->rtk_ldata.rtk_tx_mbuf[idx]); 1330 sc->rtk_ldata.rtk_tx_mbuf[idx] = NULL; 1331 bus_dmamap_unload(sc->sc_dmat, 1332 sc->rtk_ldata.rtk_tx_dmamap[idx]); 1333 if (txstat & (RTK_TDESC_STAT_EXCESSCOL | 1334 RTK_TDESC_STAT_COLCNT)) 1335 ifp->if_collisions++; 1336 if (txstat & RTK_TDESC_STAT_TXERRSUM) 1337 ifp->if_oerrors++; 1338 else 1339 ifp->if_opackets++; 1340 } 1341 sc->rtk_ldata.rtk_tx_free++; 1342 RTK_DESC_INC(idx); 1343 } 1344 1345 /* No changes made to the TX ring, so no flush needed */ 1346 1347 if (idx != sc->rtk_ldata.rtk_tx_considx) { 1348 sc->rtk_ldata.rtk_tx_considx = idx; 1349 ifp->if_flags &= ~IFF_OACTIVE; 1350 ifp->if_timer = 0; 1351 } 1352 1353 /* 1354 * If not all descriptors have been released reaped yet, 1355 * reload the timer so that we will eventually get another 1356 * interrupt that will cause us to re-enter this routine. 1357 * This is done in case the transmitter has gone idle. 1358 */ 1359 if (sc->rtk_ldata.rtk_tx_free != RTK_TX_DESC_CNT) 1360 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1361 1362 return; 1363 } 1364 1365 /* 1366 * Stop all chip I/O so that the kernel's probe routines don't 1367 * get confused by errant DMAs when rebooting. 1368 */ 1369 static void 1370 re_shutdown(void *vsc) 1371 1372 { 1373 struct rtk_softc *sc = (struct rtk_softc *)vsc; 1374 1375 re_stop(&sc->ethercom.ec_if, 0); 1376 } 1377 1378 1379 static void 1380 re_tick(void *xsc) 1381 { 1382 struct rtk_softc *sc = xsc; 1383 int s; 1384 1385 /*XXX: just return for 8169S/8110S with rev 2 or newer phy */ 1386 s = splnet(); 1387 1388 mii_tick(&sc->mii); 1389 splx(s); 1390 1391 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1392 } 1393 1394 #ifdef DEVICE_POLLING 1395 static void 1396 re_poll(struct ifnet *ifp, enum poll_cmd cmd, int count) 1397 { 1398 struct rtk_softc *sc = ifp->if_softc; 1399 1400 RTK_LOCK(sc); 1401 if (!(ifp->if_capenable & IFCAP_POLLING)) { 1402 ether_poll_deregister(ifp); 1403 cmd = POLL_DEREGISTER; 1404 } 1405 if (cmd == POLL_DEREGISTER) { /* final call, enable interrupts */ 1406 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS); 1407 goto done; 1408 } 1409 1410 sc->rxcycles = count; 1411 re_rxeof(sc); 1412 re_txeof(sc); 1413 1414 if (ifp->if_snd.ifq_head != NULL) 1415 (*ifp->if_start)(ifp); 1416 1417 if (cmd == POLL_AND_CHECK_STATUS) { /* also check status register */ 1418 u_int16_t status; 1419 1420 status = CSR_READ_2(sc, RTK_ISR); 1421 if (status == 0xffff) 1422 goto done; 1423 if (status) 1424 CSR_WRITE_2(sc, RTK_ISR, status); 1425 1426 /* 1427 * XXX check behaviour on receiver stalls. 1428 */ 1429 1430 if (status & RTK_ISR_SYSTEM_ERR) { 1431 re_reset(sc); 1432 re_init(sc); 1433 } 1434 } 1435 done: 1436 RTK_UNLOCK(sc); 1437 } 1438 #endif /* DEVICE_POLLING */ 1439 1440 int 1441 re_intr(void *arg) 1442 { 1443 struct rtk_softc *sc = arg; 1444 struct ifnet *ifp; 1445 u_int16_t status; 1446 int handled = 0; 1447 1448 ifp = &sc->ethercom.ec_if; 1449 1450 if (!(ifp->if_flags & IFF_UP)) 1451 return 0; 1452 1453 #ifdef DEVICE_POLLING 1454 if (ifp->if_flags & IFF_POLLING) 1455 goto done; 1456 if ((ifp->if_capenable & IFCAP_POLLING) && 1457 ether_poll_register(re_poll, ifp)) { /* ok, disable interrupts */ 1458 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1459 re_poll(ifp, 0, 1); 1460 goto done; 1461 } 1462 #endif /* DEVICE_POLLING */ 1463 1464 for (;;) { 1465 1466 status = CSR_READ_2(sc, RTK_ISR); 1467 /* If the card has gone away the read returns 0xffff. */ 1468 if (status == 0xffff) 1469 break; 1470 if (status) { 1471 handled = 1; 1472 CSR_WRITE_2(sc, RTK_ISR, status); 1473 } 1474 1475 if ((status & RTK_INTRS_CPLUS) == 0) 1476 break; 1477 1478 if ((status & RTK_ISR_RX_OK) || 1479 (status & RTK_ISR_RX_ERR)) 1480 re_rxeof(sc); 1481 1482 if ((status & RTK_ISR_TIMEOUT_EXPIRED) || 1483 (status & RTK_ISR_TX_ERR) || 1484 (status & RTK_ISR_TX_DESC_UNAVAIL)) 1485 re_txeof(sc); 1486 1487 if (status & RTK_ISR_SYSTEM_ERR) { 1488 re_reset(sc); 1489 re_init(ifp); 1490 } 1491 1492 if (status & RTK_ISR_LINKCHG) { 1493 callout_stop(&sc->rtk_tick_ch); 1494 re_tick(sc); 1495 } 1496 } 1497 1498 if (ifp->if_flags & IFF_UP) /* kludge for interrupt during re_init() */ 1499 if (ifp->if_snd.ifq_head != NULL) 1500 (*ifp->if_start)(ifp); 1501 1502 #ifdef DEVICE_POLLING 1503 done: 1504 #endif 1505 1506 return handled; 1507 } 1508 1509 static int 1510 re_encap(struct rtk_softc *sc, struct mbuf *m_head, int *idx) 1511 { 1512 bus_dmamap_t map; 1513 int error, i, curidx; 1514 struct m_tag *mtag; 1515 struct rtk_desc *d; 1516 u_int32_t cmdstat, rtk_flags; 1517 1518 if (sc->rtk_ldata.rtk_tx_free <= 4) 1519 return EFBIG; 1520 1521 /* 1522 * Set up checksum offload. Note: checksum offload bits must 1523 * appear in all descriptors of a multi-descriptor transmit 1524 * attempt. (This is according to testing done with an 8169 1525 * chip. I'm not sure if this is a requirement or a bug.) 1526 */ 1527 1528 rtk_flags = 0; 1529 1530 if (m_head->m_pkthdr.csum_flags & M_CSUM_IPv4) 1531 rtk_flags |= RTK_TDESC_CMD_IPCSUM; 1532 if (m_head->m_pkthdr.csum_flags & M_CSUM_TCPv4) 1533 rtk_flags |= RTK_TDESC_CMD_TCPCSUM; 1534 if (m_head->m_pkthdr.csum_flags & M_CSUM_UDPv4) 1535 rtk_flags |= RTK_TDESC_CMD_UDPCSUM; 1536 1537 map = sc->rtk_ldata.rtk_tx_dmamap[*idx]; 1538 error = bus_dmamap_load_mbuf(sc->sc_dmat, map, 1539 m_head, BUS_DMA_NOWAIT); 1540 1541 if (error) { 1542 aprint_error("%s: can't map mbuf (error %d)\n", 1543 sc->sc_dev.dv_xname, error); 1544 return ENOBUFS; 1545 } 1546 1547 if (map->dm_nsegs > sc->rtk_ldata.rtk_tx_free - 4) 1548 return ENOBUFS; 1549 /* 1550 * Map the segment array into descriptors. Note that we set the 1551 * start-of-frame and end-of-frame markers for either TX or RX, but 1552 * they really only have meaning in the TX case. (In the RX case, 1553 * it's the chip that tells us where packets begin and end.) 1554 * We also keep track of the end of the ring and set the 1555 * end-of-ring bits as needed, and we set the ownership bits 1556 * in all except the very first descriptor. (The caller will 1557 * set this descriptor later when it start transmission or 1558 * reception.) 1559 */ 1560 i = 0; 1561 curidx = *idx; 1562 while (1) { 1563 d = &sc->rtk_ldata.rtk_tx_list[curidx]; 1564 if (le32toh(d->rtk_cmdstat) & RTK_RDESC_STAT_OWN) 1565 return ENOBUFS; 1566 1567 cmdstat = map->dm_segs[i].ds_len; 1568 d->rtk_bufaddr_lo = 1569 htole32(RTK_ADDR_LO(map->dm_segs[i].ds_addr)); 1570 d->rtk_bufaddr_hi = 1571 htole32(RTK_ADDR_HI(map->dm_segs[i].ds_addr)); 1572 if (i == 0) 1573 cmdstat |= RTK_TDESC_CMD_SOF; 1574 else 1575 cmdstat |= RTK_TDESC_CMD_OWN; 1576 if (curidx == (RTK_RX_DESC_CNT - 1)) 1577 cmdstat |= RTK_TDESC_CMD_EOR; 1578 d->rtk_cmdstat = htole32(cmdstat | rtk_flags); 1579 i++; 1580 if (i == map->dm_nsegs) 1581 break; 1582 RTK_DESC_INC(curidx); 1583 } 1584 1585 d->rtk_cmdstat |= htole32(RTK_TDESC_CMD_EOF); 1586 1587 /* 1588 * Insure that the map for this transmission 1589 * is placed at the array index of the last descriptor 1590 * in this chain. 1591 */ 1592 sc->rtk_ldata.rtk_tx_dmamap[*idx] = 1593 sc->rtk_ldata.rtk_tx_dmamap[curidx]; 1594 sc->rtk_ldata.rtk_tx_dmamap[curidx] = map; 1595 sc->rtk_ldata.rtk_tx_mbuf[curidx] = m_head; 1596 sc->rtk_ldata.rtk_tx_free -= map->dm_nsegs; 1597 1598 /* 1599 * Set up hardware VLAN tagging. Note: vlan tag info must 1600 * appear in the first descriptor of a multi-descriptor 1601 * transmission attempt. 1602 */ 1603 1604 if ((mtag = VLAN_OUTPUT_TAG(&sc->ethercom, m_head)) != NULL) { 1605 sc->rtk_ldata.rtk_tx_list[*idx].rtk_vlanctl = 1606 htole32(htons(VLAN_TAG_VALUE(mtag)) | 1607 RTK_TDESC_VLANCTL_TAG); 1608 } 1609 1610 /* Transfer ownership of packet to the chip. */ 1611 1612 sc->rtk_ldata.rtk_tx_list[curidx].rtk_cmdstat |= 1613 htole32(RTK_TDESC_CMD_OWN); 1614 if (*idx != curidx) 1615 sc->rtk_ldata.rtk_tx_list[*idx].rtk_cmdstat |= 1616 htole32(RTK_TDESC_CMD_OWN); 1617 1618 RTK_DESC_INC(curidx); 1619 *idx = curidx; 1620 1621 return 0; 1622 } 1623 1624 /* 1625 * Main transmit routine for C+ and gigE NICs. 1626 */ 1627 1628 static void 1629 re_start(struct ifnet *ifp) 1630 { 1631 struct rtk_softc *sc; 1632 struct mbuf *m_head = NULL; 1633 int idx; 1634 1635 sc = ifp->if_softc; 1636 1637 idx = sc->rtk_ldata.rtk_tx_prodidx; 1638 while (sc->rtk_ldata.rtk_tx_mbuf[idx] == NULL) { 1639 IF_DEQUEUE(&ifp->if_snd, m_head); 1640 if (m_head == NULL) 1641 break; 1642 1643 if (re_encap(sc, m_head, &idx)) { 1644 IF_PREPEND(&ifp->if_snd, m_head); 1645 ifp->if_flags |= IFF_OACTIVE; 1646 break; 1647 } 1648 #if NBPFILTER > 0 1649 /* 1650 * If there's a BPF listener, bounce a copy of this frame 1651 * to him. 1652 */ 1653 if (ifp->if_bpf) 1654 bpf_mtap(ifp->if_bpf, m_head); 1655 #endif 1656 } 1657 1658 /* Flush the TX descriptors */ 1659 1660 bus_dmamap_sync(sc->sc_dmat, 1661 sc->rtk_ldata.rtk_tx_list_map, 1662 0, sc->rtk_ldata.rtk_tx_list_map->dm_mapsize, 1663 BUS_DMASYNC_PREWRITE | BUS_DMASYNC_PREREAD); 1664 1665 sc->rtk_ldata.rtk_tx_prodidx = idx; 1666 1667 /* 1668 * RealTek put the TX poll request register in a different 1669 * location on the 8169 gigE chip. I don't know why. 1670 */ 1671 1672 if (sc->rtk_type == RTK_8169) 1673 CSR_WRITE_2(sc, RTK_GTXSTART, RTK_TXSTART_START); 1674 else 1675 CSR_WRITE_2(sc, RTK_TXSTART, RTK_TXSTART_START); 1676 1677 /* 1678 * Use the countdown timer for interrupt moderation. 1679 * 'TX done' interrupts are disabled. Instead, we reset the 1680 * countdown timer, which will begin counting until it hits 1681 * the value in the TIMERINT register, and then trigger an 1682 * interrupt. Each time we write to the TIMERCNT register, 1683 * the timer count is reset to 0. 1684 */ 1685 CSR_WRITE_4(sc, RTK_TIMERCNT, 1); 1686 1687 /* 1688 * Set a timeout in case the chip goes out to lunch. 1689 */ 1690 ifp->if_timer = 5; 1691 1692 return; 1693 } 1694 1695 static int 1696 re_init(struct ifnet *ifp) 1697 { 1698 struct rtk_softc *sc = ifp->if_softc; 1699 u_int32_t rxcfg = 0; 1700 u_int32_t reg; 1701 int error; 1702 1703 if ((error = re_enable(sc)) != 0) 1704 goto out; 1705 1706 /* 1707 * Cancel pending I/O and free all RX/TX buffers. 1708 */ 1709 re_stop(ifp, 0); 1710 1711 /* 1712 * Enable C+ RX and TX mode, as well as VLAN stripping and 1713 * RX checksum offload. We must configure the C+ register 1714 * before all others. 1715 */ 1716 reg = 0; 1717 1718 /* 1719 * XXX: Realtek docs say bits 0 and 1 are reserved, for 8169S/8110S. 1720 * FreeBSD drivers set these bits anyway (for 8139C+?). 1721 * So far, it works. 1722 */ 1723 1724 /* 1725 * XXX: For 8169 and 8196S revs below 2, set bit 14. 1726 * For 8169S/8110S rev 2 and above, do not set bit 14. 1727 */ 1728 if (sc->rtk_type == RTK_8169 && sc->sc_rev == 1) 1729 reg |= (0x1 << 14) | RTK_CPLUSCMD_PCI_MRW;; 1730 1731 if (1) {/* not for 8169S ? */ 1732 reg |= RTK_CPLUSCMD_VLANSTRIP | 1733 (ifp->if_capenable & 1734 (IFCAP_CSUM_IPv4 | IFCAP_CSUM_TCPv4 | IFCAP_CSUM_UDPv4) ? 1735 RTK_CPLUSCMD_RXCSUM_ENB : 0); 1736 } 1737 1738 CSR_WRITE_2(sc, RTK_CPLUS_CMD, 1739 reg | RTK_CPLUSCMD_RXENB | RTK_CPLUSCMD_TXENB); 1740 1741 /* XXX: from Realtek-supplied Linux driver. Wholly undocumented. */ 1742 if (sc->rtk_type == RTK_8169) 1743 CSR_WRITE_2(sc, RTK_CPLUS_CMD+0x2, 0x0000); 1744 1745 DELAY(10000); 1746 1747 /* 1748 * Init our MAC address. Even though the chipset 1749 * documentation doesn't mention it, we need to enter "Config 1750 * register write enable" mode to modify the ID registers. 1751 */ 1752 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_WRITECFG); 1753 memcpy(®, LLADDR(ifp->if_sadl), 4); 1754 CSR_WRITE_STREAM_4(sc, RTK_IDR0, reg); 1755 reg = 0; 1756 memcpy(®, LLADDR(ifp->if_sadl) + 4, 4); 1757 CSR_WRITE_STREAM_4(sc, RTK_IDR4, reg); 1758 CSR_WRITE_1(sc, RTK_EECMD, RTK_EEMODE_OFF); 1759 1760 /* 1761 * For C+ mode, initialize the RX descriptors and mbufs. 1762 */ 1763 re_rx_list_init(sc); 1764 re_tx_list_init(sc); 1765 1766 /* 1767 * Enable transmit and receive. 1768 */ 1769 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1770 1771 /* 1772 * Set the initial TX and RX configuration. 1773 */ 1774 if (sc->rtk_testmode) { 1775 if (sc->rtk_type == RTK_8169) 1776 CSR_WRITE_4(sc, RTK_TXCFG, 1777 RTK_TXCFG_CONFIG | RTK_LOOPTEST_ON); 1778 else 1779 CSR_WRITE_4(sc, RTK_TXCFG, 1780 RTK_TXCFG_CONFIG | RTK_LOOPTEST_ON_CPLUS); 1781 } else 1782 CSR_WRITE_4(sc, RTK_TXCFG, RTK_TXCFG_CONFIG); 1783 CSR_WRITE_4(sc, RTK_RXCFG, RTK_RXCFG_CONFIG); 1784 1785 /* Set the individual bit to receive frames for this host only. */ 1786 rxcfg = CSR_READ_4(sc, RTK_RXCFG); 1787 rxcfg |= RTK_RXCFG_RX_INDIV; 1788 1789 /* If we want promiscuous mode, set the allframes bit. */ 1790 if (ifp->if_flags & IFF_PROMISC) 1791 rxcfg |= RTK_RXCFG_RX_ALLPHYS; 1792 else 1793 rxcfg &= ~RTK_RXCFG_RX_ALLPHYS; 1794 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1795 1796 /* 1797 * Set capture broadcast bit to capture broadcast frames. 1798 */ 1799 if (ifp->if_flags & IFF_BROADCAST) 1800 rxcfg |= RTK_RXCFG_RX_BROAD; 1801 else 1802 rxcfg &= ~RTK_RXCFG_RX_BROAD; 1803 CSR_WRITE_4(sc, RTK_RXCFG, rxcfg); 1804 1805 /* 1806 * Program the multicast filter, if necessary. 1807 */ 1808 rtk_setmulti(sc); 1809 1810 #ifdef DEVICE_POLLING 1811 /* 1812 * Disable interrupts if we are polling. 1813 */ 1814 if (ifp->if_flags & IFF_POLLING) 1815 CSR_WRITE_2(sc, RTK_IMR, 0); 1816 else /* otherwise ... */ 1817 #endif /* DEVICE_POLLING */ 1818 /* 1819 * Enable interrupts. 1820 */ 1821 if (sc->rtk_testmode) 1822 CSR_WRITE_2(sc, RTK_IMR, 0); 1823 else 1824 CSR_WRITE_2(sc, RTK_IMR, RTK_INTRS_CPLUS); 1825 1826 /* Start RX/TX process. */ 1827 CSR_WRITE_4(sc, RTK_MISSEDPKT, 0); 1828 #ifdef notdef 1829 /* Enable receiver and transmitter. */ 1830 CSR_WRITE_1(sc, RTK_COMMAND, RTK_CMD_TX_ENB | RTK_CMD_RX_ENB); 1831 #endif 1832 /* 1833 * Load the addresses of the RX and TX lists into the chip. 1834 */ 1835 1836 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_HI, 1837 RTK_ADDR_HI(sc->rtk_ldata.rtk_rx_listseg.ds_addr)); 1838 CSR_WRITE_4(sc, RTK_RXLIST_ADDR_LO, 1839 RTK_ADDR_LO(sc->rtk_ldata.rtk_rx_listseg.ds_addr)); 1840 1841 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_HI, 1842 RTK_ADDR_HI(sc->rtk_ldata.rtk_tx_listseg.ds_addr)); 1843 CSR_WRITE_4(sc, RTK_TXLIST_ADDR_LO, 1844 RTK_ADDR_LO(sc->rtk_ldata.rtk_tx_listseg.ds_addr)); 1845 1846 CSR_WRITE_1(sc, RTK_EARLY_TX_THRESH, 16); 1847 1848 /* 1849 * Initialize the timer interrupt register so that 1850 * a timer interrupt will be generated once the timer 1851 * reaches a certain number of ticks. The timer is 1852 * reloaded on each transmit. This gives us TX interrupt 1853 * moderation, which dramatically improves TX frame rate. 1854 */ 1855 1856 if (sc->rtk_type == RTK_8169) 1857 CSR_WRITE_4(sc, RTK_TIMERINT_8169, 0x800); 1858 else 1859 CSR_WRITE_4(sc, RTK_TIMERINT, 0x400); 1860 1861 /* 1862 * For 8169 gigE NICs, set the max allowed RX packet 1863 * size so we can receive jumbo frames. 1864 */ 1865 if (sc->rtk_type == RTK_8169) 1866 CSR_WRITE_2(sc, RTK_MAXRXPKTLEN, 16383); 1867 1868 if (sc->rtk_testmode) 1869 return 0; 1870 1871 mii_mediachg(&sc->mii); 1872 1873 CSR_WRITE_1(sc, RTK_CFG1, RTK_CFG1_DRVLOAD | RTK_CFG1_FULLDUPLEX); 1874 1875 ifp->if_flags |= IFF_RUNNING; 1876 ifp->if_flags &= ~IFF_OACTIVE; 1877 1878 callout_reset(&sc->rtk_tick_ch, hz, re_tick, sc); 1879 1880 out: 1881 if (error) { 1882 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1883 ifp->if_timer = 0; 1884 aprint_error("%s: interface not running\n", 1885 sc->sc_dev.dv_xname); 1886 } 1887 1888 return error; 1889 1890 } 1891 1892 /* 1893 * Set media options. 1894 */ 1895 static int 1896 re_ifmedia_upd(struct ifnet *ifp) 1897 { 1898 struct rtk_softc *sc; 1899 1900 sc = ifp->if_softc; 1901 1902 return mii_mediachg(&sc->mii); 1903 } 1904 1905 /* 1906 * Report current media status. 1907 */ 1908 static void 1909 re_ifmedia_sts(struct ifnet *ifp, struct ifmediareq *ifmr) 1910 { 1911 struct rtk_softc *sc; 1912 1913 sc = ifp->if_softc; 1914 1915 mii_pollstat(&sc->mii); 1916 ifmr->ifm_active = sc->mii.mii_media_active; 1917 ifmr->ifm_status = sc->mii.mii_media_status; 1918 1919 return; 1920 } 1921 1922 static int 1923 re_ioctl(struct ifnet *ifp, u_long command, caddr_t data) 1924 { 1925 struct rtk_softc *sc = ifp->if_softc; 1926 struct ifreq *ifr = (struct ifreq *) data; 1927 int s, error = 0; 1928 1929 s = splnet(); 1930 1931 switch (command) { 1932 case SIOCSIFMTU: 1933 if (ifr->ifr_mtu > RTK_JUMBO_MTU) 1934 error = EINVAL; 1935 ifp->if_mtu = ifr->ifr_mtu; 1936 break; 1937 case SIOCGIFMEDIA: 1938 case SIOCSIFMEDIA: 1939 error = ifmedia_ioctl(ifp, ifr, &sc->mii.mii_media, command); 1940 break; 1941 default: 1942 error = ether_ioctl(ifp, command, data); 1943 if (error == ENETRESET) { 1944 if (ifp->if_flags & IFF_RUNNING) 1945 rtk_setmulti(sc); 1946 error = 0; 1947 } 1948 break; 1949 } 1950 1951 splx(s); 1952 1953 return error; 1954 } 1955 1956 static void 1957 re_watchdog(struct ifnet *ifp) 1958 { 1959 struct rtk_softc *sc; 1960 int s; 1961 1962 sc = ifp->if_softc; 1963 s = splnet(); 1964 aprint_error("%s: watchdog timeout\n", sc->sc_dev.dv_xname); 1965 ifp->if_oerrors++; 1966 1967 re_txeof(sc); 1968 re_rxeof(sc); 1969 1970 re_init(ifp); 1971 1972 splx(s); 1973 } 1974 1975 /* 1976 * Stop the adapter and free any mbufs allocated to the 1977 * RX and TX lists. 1978 */ 1979 static void 1980 re_stop(struct ifnet *ifp, int disable) 1981 { 1982 register int i; 1983 struct rtk_softc *sc = ifp->if_softc; 1984 1985 callout_stop(&sc->rtk_tick_ch); 1986 1987 #ifdef DEVICE_POLLING 1988 ether_poll_deregister(ifp); 1989 #endif /* DEVICE_POLLING */ 1990 1991 mii_down(&sc->mii); 1992 1993 CSR_WRITE_1(sc, RTK_COMMAND, 0x00); 1994 CSR_WRITE_2(sc, RTK_IMR, 0x0000); 1995 1996 if (sc->rtk_head != NULL) { 1997 m_freem(sc->rtk_head); 1998 sc->rtk_head = sc->rtk_tail = NULL; 1999 } 2000 2001 /* Free the TX list buffers. */ 2002 for (i = 0; i < RTK_TX_DESC_CNT; i++) { 2003 if (sc->rtk_ldata.rtk_tx_mbuf[i] != NULL) { 2004 bus_dmamap_unload(sc->sc_dmat, 2005 sc->rtk_ldata.rtk_tx_dmamap[i]); 2006 m_freem(sc->rtk_ldata.rtk_tx_mbuf[i]); 2007 sc->rtk_ldata.rtk_tx_mbuf[i] = NULL; 2008 } 2009 } 2010 2011 /* Free the RX list buffers. */ 2012 for (i = 0; i < RTK_RX_DESC_CNT; i++) { 2013 if (sc->rtk_ldata.rtk_rx_mbuf[i] != NULL) { 2014 bus_dmamap_unload(sc->sc_dmat, 2015 sc->rtk_ldata.rtk_rx_dmamap[i]); 2016 m_freem(sc->rtk_ldata.rtk_rx_mbuf[i]); 2017 sc->rtk_ldata.rtk_rx_mbuf[i] = NULL; 2018 } 2019 } 2020 2021 if (disable) 2022 re_disable(sc); 2023 2024 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 2025 ifp->if_timer = 0; 2026 2027 return; 2028 } 2029