1 /* $NetBSD: rt2860reg.h,v 1.1 2012/05/30 14:30:35 nonaka Exp $ */ 2 /* $OpenBSD: rt2860reg.h,v 1.30 2010/05/10 18:17:10 damien Exp $ */ 3 4 /*- 5 * Copyright (c) 2007 6 * Damien Bergamini <damien.bergamini@free.fr> 7 * 8 * Permission to use, copy, modify, and distribute this software for any 9 * purpose with or without fee is hereby granted, provided that the above 10 * copyright notice and this permission notice appear in all copies. 11 * 12 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES 13 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF 14 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR 15 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES 16 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN 17 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF 18 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. 19 */ 20 21 /* PCI registers */ 22 #define RT2860_PCI_CFG 0x0000 23 #define RT2860_PCI_EECTRL 0x0004 24 #define RT2860_PCI_MCUCTRL 0x0008 25 #define RT2860_PCI_SYSCTRL 0x000c 26 #define RT2860_PCIE_JTAG 0x0010 27 28 #define RT3090_AUX_CTRL 0x010c 29 30 #define RT3070_OPT_14 0x0114 31 32 /* SCH/DMA registers */ 33 #define RT2860_INT_STATUS 0x0200 34 #define RT2860_INT_MASK 0x0204 35 #define RT2860_WPDMA_GLO_CFG 0x0208 36 #define RT2860_WPDMA_RST_IDX 0x020c 37 #define RT2860_DELAY_INT_CFG 0x0210 38 #define RT2860_WMM_AIFSN_CFG 0x0214 39 #define RT2860_WMM_CWMIN_CFG 0x0218 40 #define RT2860_WMM_CWMAX_CFG 0x021c 41 #define RT2860_WMM_TXOP0_CFG 0x0220 42 #define RT2860_WMM_TXOP1_CFG 0x0224 43 #define RT2860_GPIO_CTRL 0x0228 44 #define RT2860_MCU_CMD_REG 0x022c 45 #define RT2860_TX_BASE_PTR(qid) (0x0230 + (qid) * 16) 46 #define RT2860_TX_MAX_CNT(qid) (0x0234 + (qid) * 16) 47 #define RT2860_TX_CTX_IDX(qid) (0x0238 + (qid) * 16) 48 #define RT2860_TX_DTX_IDX(qid) (0x023c + (qid) * 16) 49 #define RT2860_RX_BASE_PTR 0x0290 50 #define RT2860_RX_MAX_CNT 0x0294 51 #define RT2860_RX_CALC_IDX 0x0298 52 #define RT2860_FS_DRX_IDX 0x029c 53 #define RT2860_USB_DMA_CFG 0x02a0 /* RT2870 only */ 54 #define RT2860_US_CYC_CNT 0x02a4 55 56 /* PBF registers */ 57 #define RT2860_SYS_CTRL 0x0400 58 #define RT2860_HOST_CMD 0x0404 59 #define RT2860_PBF_CFG 0x0408 60 #define RT2860_MAX_PCNT 0x040c 61 #define RT2860_BUF_CTRL 0x0410 62 #define RT2860_MCU_INT_STA 0x0414 63 #define RT2860_MCU_INT_ENA 0x0418 64 #define RT2860_TXQ_IO(qid) (0x041c + (qid) * 4) 65 #define RT2860_RX0Q_IO 0x0424 66 #define RT2860_BCN_OFFSET0 0x042c 67 #define RT2860_BCN_OFFSET1 0x0430 68 #define RT2860_TXRXQ_STA 0x0434 69 #define RT2860_TXRXQ_PCNT 0x0438 70 #define RT2860_PBF_DBG 0x043c 71 #define RT2860_CAP_CTRL 0x0440 72 73 /* RT3070 registers */ 74 #define RT3070_RF_CSR_CFG 0x0500 75 #define RT3070_EFUSE_CTRL 0x0580 76 #define RT3070_EFUSE_DATA0 0x0590 77 #define RT3070_EFUSE_DATA1 0x0594 78 #define RT3070_EFUSE_DATA2 0x0598 79 #define RT3070_EFUSE_DATA3 0x059c 80 #define RT3090_OSC_CTRL 0x05a4 81 #define RT3070_LDO_CFG0 0x05d4 82 #define RT3070_GPIO_SWITCH 0x05dc 83 84 /* MAC registers */ 85 #define RT2860_ASIC_VER_ID 0x1000 86 #define RT2860_MAC_SYS_CTRL 0x1004 87 #define RT2860_MAC_ADDR_DW0 0x1008 88 #define RT2860_MAC_ADDR_DW1 0x100c 89 #define RT2860_MAC_BSSID_DW0 0x1010 90 #define RT2860_MAC_BSSID_DW1 0x1014 91 #define RT2860_MAX_LEN_CFG 0x1018 92 #define RT2860_BBP_CSR_CFG 0x101c 93 #define RT2860_RF_CSR_CFG0 0x1020 94 #define RT2860_RF_CSR_CFG1 0x1024 95 #define RT2860_RF_CSR_CFG2 0x1028 96 #define RT2860_LED_CFG 0x102c 97 98 /* undocumented registers */ 99 #define RT2860_DEBUG 0x10f4 100 101 /* MAC Timing control registers */ 102 #define RT2860_XIFS_TIME_CFG 0x1100 103 #define RT2860_BKOFF_SLOT_CFG 0x1104 104 #define RT2860_NAV_TIME_CFG 0x1108 105 #define RT2860_CH_TIME_CFG 0x110c 106 #define RT2860_PBF_LIFE_TIMER 0x1110 107 #define RT2860_BCN_TIME_CFG 0x1114 108 #define RT2860_TBTT_SYNC_CFG 0x1118 109 #define RT2860_TSF_TIMER_DW0 0x111c 110 #define RT2860_TSF_TIMER_DW1 0x1120 111 #define RT2860_TBTT_TIMER 0x1124 112 #define RT2860_INT_TIMER_CFG 0x1128 113 #define RT2860_INT_TIMER_EN 0x112c 114 #define RT2860_CH_IDLE_TIME 0x1130 115 116 /* MAC Power Save configuration registers */ 117 #define RT2860_MAC_STATUS_REG 0x1200 118 #define RT2860_PWR_PIN_CFG 0x1204 119 #define RT2860_AUTO_WAKEUP_CFG 0x1208 120 121 /* MAC TX configuration registers */ 122 #define RT2860_EDCA_AC_CFG(aci) (0x1300 + (aci) * 4) 123 #define RT2860_EDCA_TID_AC_MAP 0x1310 124 #define RT2860_TX_PWR_CFG(ridx) (0x1314 + (ridx) * 4) 125 #define RT2860_TX_PIN_CFG 0x1328 126 #define RT2860_TX_BAND_CFG 0x132c 127 #define RT2860_TX_SW_CFG0 0x1330 128 #define RT2860_TX_SW_CFG1 0x1334 129 #define RT2860_TX_SW_CFG2 0x1338 130 #define RT2860_TXOP_THRES_CFG 0x133c 131 #define RT2860_TXOP_CTRL_CFG 0x1340 132 #define RT2860_TX_RTS_CFG 0x1344 133 #define RT2860_TX_TIMEOUT_CFG 0x1348 134 #define RT2860_TX_RTY_CFG 0x134c 135 #define RT2860_TX_LINK_CFG 0x1350 136 #define RT2860_HT_FBK_CFG0 0x1354 137 #define RT2860_HT_FBK_CFG1 0x1358 138 #define RT2860_LG_FBK_CFG0 0x135c 139 #define RT2860_LG_FBK_CFG1 0x1360 140 #define RT2860_CCK_PROT_CFG 0x1364 141 #define RT2860_OFDM_PROT_CFG 0x1368 142 #define RT2860_MM20_PROT_CFG 0x136c 143 #define RT2860_MM40_PROT_CFG 0x1370 144 #define RT2860_GF20_PROT_CFG 0x1374 145 #define RT2860_GF40_PROT_CFG 0x1378 146 #define RT2860_EXP_CTS_TIME 0x137c 147 #define RT2860_EXP_ACK_TIME 0x1380 148 149 /* MAC RX configuration registers */ 150 #define RT2860_RX_FILTR_CFG 0x1400 151 #define RT2860_AUTO_RSP_CFG 0x1404 152 #define RT2860_LEGACY_BASIC_RATE 0x1408 153 #define RT2860_HT_BASIC_RATE 0x140c 154 #define RT2860_HT_CTRL_CFG 0x1410 155 #define RT2860_SIFS_COST_CFG 0x1414 156 #define RT2860_RX_PARSER_CFG 0x1418 157 158 /* MAC Security configuration registers */ 159 #define RT2860_TX_SEC_CNT0 0x1500 160 #define RT2860_RX_SEC_CNT0 0x1504 161 #define RT2860_CCMP_FC_MUTE 0x1508 162 163 /* MAC HCCA/PSMP configuration registers */ 164 #define RT2860_TXOP_HLDR_ADDR0 0x1600 165 #define RT2860_TXOP_HLDR_ADDR1 0x1604 166 #define RT2860_TXOP_HLDR_ET 0x1608 167 #define RT2860_QOS_CFPOLL_RA_DW0 0x160c 168 #define RT2860_QOS_CFPOLL_A1_DW1 0x1610 169 #define RT2860_QOS_CFPOLL_QC 0x1614 170 171 /* MAC Statistics Counters */ 172 #define RT2860_RX_STA_CNT0 0x1700 173 #define RT2860_RX_STA_CNT1 0x1704 174 #define RT2860_RX_STA_CNT2 0x1708 175 #define RT2860_TX_STA_CNT0 0x170c 176 #define RT2860_TX_STA_CNT1 0x1710 177 #define RT2860_TX_STA_CNT2 0x1714 178 #define RT2860_TX_STAT_FIFO 0x1718 179 180 /* RX WCID search table */ 181 #define RT2860_WCID_ENTRY(wcid) (0x1800 + (wcid) * 8) 182 183 #define RT2860_FW_BASE 0x2000 184 #define RT2870_FW_BASE 0x3000 185 186 /* Pair-wise key table */ 187 #define RT2860_PKEY(wcid) (0x4000 + (wcid) * 32) 188 189 /* IV/EIV table */ 190 #define RT2860_IVEIV(wcid) (0x6000 + (wcid) * 8) 191 192 /* WCID attribute table */ 193 #define RT2860_WCID_ATTR(wcid) (0x6800 + (wcid) * 4) 194 195 /* Shared Key Table */ 196 #define RT2860_SKEY(vap, kidx) (0x6c00 + (vap) * 128 + (kidx) * 32) 197 198 /* Shared Key Mode */ 199 #define RT2860_SKEY_MODE_0_7 0x7000 200 #define RT2860_SKEY_MODE_8_15 0x7004 201 #define RT2860_SKEY_MODE_16_23 0x7008 202 #define RT2860_SKEY_MODE_24_31 0x700c 203 204 /* Shared Memory between MCU and host */ 205 #define RT2860_H2M_MAILBOX 0x7010 206 #define RT2860_H2M_MAILBOX_CID 0x7014 207 #define RT2860_H2M_MAILBOX_STATUS 0x701c 208 #define RT2860_H2M_BBPAGENT 0x7028 209 #define RT2860_BCN_BASE(vap) (0x7800 + (vap) * 512) 210 211 212 /* possible flags for RT2860_PCI_CFG */ 213 #define RT2860_PCI_CFG_USB (1 << 17) 214 #define RT2860_PCI_CFG_PCI (1 << 16) 215 216 /* possible flags for register RT2860_PCI_EECTRL */ 217 #define RT2860_C (1 << 0) 218 #define RT2860_S (1 << 1) 219 #define RT2860_D (1 << 2) 220 #define RT2860_SHIFT_D 2 221 #define RT2860_Q (1 << 3) 222 #define RT2860_SHIFT_Q 3 223 224 /* possible flags for registers INT_STATUS/INT_MASK */ 225 #define RT2860_TX_COHERENT (1 << 17) 226 #define RT2860_RX_COHERENT (1 << 16) 227 #define RT2860_MAC_INT_4 (1 << 15) 228 #define RT2860_MAC_INT_3 (1 << 14) 229 #define RT2860_MAC_INT_2 (1 << 13) 230 #define RT2860_MAC_INT_1 (1 << 12) 231 #define RT2860_MAC_INT_0 (1 << 11) 232 #define RT2860_TX_RX_COHERENT (1 << 10) 233 #define RT2860_MCU_CMD_INT (1 << 9) 234 #define RT2860_TX_DONE_INT5 (1 << 8) 235 #define RT2860_TX_DONE_INT4 (1 << 7) 236 #define RT2860_TX_DONE_INT3 (1 << 6) 237 #define RT2860_TX_DONE_INT2 (1 << 5) 238 #define RT2860_TX_DONE_INT1 (1 << 4) 239 #define RT2860_TX_DONE_INT0 (1 << 3) 240 #define RT2860_RX_DONE_INT (1 << 2) 241 #define RT2860_TX_DLY_INT (1 << 1) 242 #define RT2860_RX_DLY_INT (1 << 0) 243 244 /* possible flags for register WPDMA_GLO_CFG */ 245 #define RT2860_HDR_SEG_LEN_SHIFT 8 246 #define RT2860_BIG_ENDIAN (1 << 7) 247 #define RT2860_TX_WB_DDONE (1 << 6) 248 #define RT2860_WPDMA_BT_SIZE_SHIFT 4 249 #define RT2860_WPDMA_BT_SIZE16 0 250 #define RT2860_WPDMA_BT_SIZE32 1 251 #define RT2860_WPDMA_BT_SIZE64 2 252 #define RT2860_WPDMA_BT_SIZE128 3 253 #define RT2860_RX_DMA_BUSY (1 << 3) 254 #define RT2860_RX_DMA_EN (1 << 2) 255 #define RT2860_TX_DMA_BUSY (1 << 1) 256 #define RT2860_TX_DMA_EN (1 << 0) 257 258 /* possible flags for register DELAY_INT_CFG */ 259 #define RT2860_TXDLY_INT_EN (1 << 31) 260 #define RT2860_TXMAX_PINT_SHIFT 24 261 #define RT2860_TXMAX_PTIME_SHIFT 16 262 #define RT2860_RXDLY_INT_EN (1 << 15) 263 #define RT2860_RXMAX_PINT_SHIFT 8 264 #define RT2860_RXMAX_PTIME_SHIFT 0 265 266 /* possible flags for register GPIO_CTRL */ 267 #define RT2860_GPIO_D_SHIFT 8 268 #define RT2860_GPIO_O_SHIFT 0 269 270 /* possible flags for register USB_DMA_CFG */ 271 #define RT2860_USB_TX_BUSY (1 << 31) 272 #define RT2860_USB_RX_BUSY (1 << 30) 273 #define RT2860_USB_EPOUT_VLD_SHIFT 24 274 #define RT2860_USB_TX_EN (1 << 23) 275 #define RT2860_USB_RX_EN (1 << 22) 276 #define RT2860_USB_RX_AGG_EN (1 << 21) 277 #define RT2860_USB_TXOP_HALT (1 << 20) 278 #define RT2860_USB_TX_CLEAR (1 << 19) 279 #define RT2860_USB_PHY_WD_EN (1 << 16) 280 #define RT2860_USB_PHY_MAN_RST (1 << 15) 281 #define RT2860_USB_RX_AGG_LMT(x) ((x) << 8) /* in unit of 1KB */ 282 #define RT2860_USB_RX_AGG_TO(x) ((x) & 0xff) /* in unit of 33ns */ 283 284 /* possible flags for register US_CYC_CNT */ 285 #define RT2860_TEST_EN (1 << 24) 286 #define RT2860_TEST_SEL_SHIFT 16 287 #define RT2860_BT_MODE_EN (1 << 8) 288 #define RT2860_US_CYC_CNT_SHIFT 0 289 290 /* possible flags for register SYS_CTRL */ 291 #define RT2860_HST_PM_SEL (1 << 16) 292 #define RT2860_CAP_MODE (1 << 14) 293 #define RT2860_PME_OEN (1 << 13) 294 #define RT2860_CLKSELECT (1 << 12) 295 #define RT2860_PBF_CLK_EN (1 << 11) 296 #define RT2860_MAC_CLK_EN (1 << 10) 297 #define RT2860_DMA_CLK_EN (1 << 9) 298 #define RT2860_MCU_READY (1 << 7) 299 #define RT2860_ASY_RESET (1 << 4) 300 #define RT2860_PBF_RESET (1 << 3) 301 #define RT2860_MAC_RESET (1 << 2) 302 #define RT2860_DMA_RESET (1 << 1) 303 #define RT2860_MCU_RESET (1 << 0) 304 305 /* possible values for register HOST_CMD */ 306 #define RT2860_MCU_CMD_SLEEP 0x30 307 #define RT2860_MCU_CMD_WAKEUP 0x31 308 #define RT2860_MCU_CMD_LEDS 0x50 309 #define RT2860_MCU_CMD_LED_RSSI 0x51 310 #define RT2860_MCU_CMD_LED1 0x52 311 #define RT2860_MCU_CMD_LED2 0x53 312 #define RT2860_MCU_CMD_LED3 0x54 313 #define RT2860_MCU_CMD_RFRESET 0x72 314 #define RT2860_MCU_CMD_ANTSEL 0x73 315 #define RT2860_MCU_CMD_BBP 0x80 316 #define RT2860_MCU_CMD_PSLEVEL 0x83 317 318 /* possible flags for register PBF_CFG */ 319 #define RT2860_TX1Q_NUM_SHIFT 21 320 #define RT2860_TX2Q_NUM_SHIFT 16 321 #define RT2860_NULL0_MODE (1 << 15) 322 #define RT2860_NULL1_MODE (1 << 14) 323 #define RT2860_RX_DROP_MODE (1 << 13) 324 #define RT2860_TX0Q_MANUAL (1 << 12) 325 #define RT2860_TX1Q_MANUAL (1 << 11) 326 #define RT2860_TX2Q_MANUAL (1 << 10) 327 #define RT2860_RX0Q_MANUAL (1 << 9) 328 #define RT2860_HCCA_EN (1 << 8) 329 #define RT2860_TX0Q_EN (1 << 4) 330 #define RT2860_TX1Q_EN (1 << 3) 331 #define RT2860_TX2Q_EN (1 << 2) 332 #define RT2860_RX0Q_EN (1 << 1) 333 334 /* possible flags for register BUF_CTRL */ 335 #define RT2860_WRITE_TXQ(qid) (1 << (11 - (qid))) 336 #define RT2860_NULL0_KICK (1 << 7) 337 #define RT2860_NULL1_KICK (1 << 6) 338 #define RT2860_BUF_RESET (1 << 5) 339 #define RT2860_READ_TXQ(qid) (1 << (3 - (qid)) 340 #define RT2860_READ_RX0Q (1 << 0) 341 342 /* possible flags for registers MCU_INT_STA/MCU_INT_ENA */ 343 #define RT2860_MCU_MAC_INT_8 (1 << 24) 344 #define RT2860_MCU_MAC_INT_7 (1 << 23) 345 #define RT2860_MCU_MAC_INT_6 (1 << 22) 346 #define RT2860_MCU_MAC_INT_4 (1 << 20) 347 #define RT2860_MCU_MAC_INT_3 (1 << 19) 348 #define RT2860_MCU_MAC_INT_2 (1 << 18) 349 #define RT2860_MCU_MAC_INT_1 (1 << 17) 350 #define RT2860_MCU_MAC_INT_0 (1 << 16) 351 #define RT2860_DTX0_INT (1 << 11) 352 #define RT2860_DTX1_INT (1 << 10) 353 #define RT2860_DTX2_INT (1 << 9) 354 #define RT2860_DRX0_INT (1 << 8) 355 #define RT2860_HCMD_INT (1 << 7) 356 #define RT2860_N0TX_INT (1 << 6) 357 #define RT2860_N1TX_INT (1 << 5) 358 #define RT2860_BCNTX_INT (1 << 4) 359 #define RT2860_MTX0_INT (1 << 3) 360 #define RT2860_MTX1_INT (1 << 2) 361 #define RT2860_MTX2_INT (1 << 1) 362 #define RT2860_MRX0_INT (1 << 0) 363 364 /* possible flags for register TXRXQ_PCNT */ 365 #define RT2860_RX0Q_PCNT_MASK 0xff000000 366 #define RT2860_TX2Q_PCNT_MASK 0x00ff0000 367 #define RT2860_TX1Q_PCNT_MASK 0x0000ff00 368 #define RT2860_TX0Q_PCNT_MASK 0x000000ff 369 370 /* possible flags for register CAP_CTRL */ 371 #define RT2860_CAP_ADC_FEQ (1 << 31) 372 #define RT2860_CAP_START (1 << 30) 373 #define RT2860_MAN_TRIG (1 << 29) 374 #define RT2860_TRIG_OFFSET_SHIFT 16 375 #define RT2860_START_ADDR_SHIFT 0 376 377 /* possible flags for register RF_CSR_CFG */ 378 #define RT3070_RF_KICK (1 << 17) 379 #define RT3070_RF_WRITE (1 << 16) 380 381 /* possible flags for register EFUSE_CTRL */ 382 #define RT3070_SEL_EFUSE (1 << 31) 383 #define RT3070_EFSROM_KICK (1 << 30) 384 #define RT3070_EFSROM_AIN_MASK 0x03ff0000 385 #define RT3070_EFSROM_AIN_SHIFT 16 386 #define RT3070_EFSROM_MODE_MASK 0x000000c0 387 #define RT3070_EFUSE_AOUT_MASK 0x0000003f 388 389 /* possible flags for register MAC_SYS_CTRL */ 390 #define RT2860_RX_TS_EN (1 << 7) 391 #define RT2860_WLAN_HALT_EN (1 << 6) 392 #define RT2860_PBF_LOOP_EN (1 << 5) 393 #define RT2860_CONT_TX_TEST (1 << 4) 394 #define RT2860_MAC_RX_EN (1 << 3) 395 #define RT2860_MAC_TX_EN (1 << 2) 396 #define RT2860_BBP_HRST (1 << 1) 397 #define RT2860_MAC_SRST (1 << 0) 398 399 /* possible flags for register MAC_BSSID_DW1 */ 400 #define RT2860_MULTI_BCN_NUM_SHIFT 18 401 #define RT2860_MULTI_BSSID_MODE_SHIFT 16 402 403 /* possible flags for register MAX_LEN_CFG */ 404 #define RT2860_MIN_MPDU_LEN_SHIFT 16 405 #define RT2860_MAX_PSDU_LEN_SHIFT 12 406 #define RT2860_MAX_PSDU_LEN8K 0 407 #define RT2860_MAX_PSDU_LEN16K 1 408 #define RT2860_MAX_PSDU_LEN32K 2 409 #define RT2860_MAX_PSDU_LEN64K 3 410 #define RT2860_MAX_MPDU_LEN_SHIFT 0 411 412 /* possible flags for registers BBP_CSR_CFG/H2M_BBPAGENT */ 413 #define RT2860_BBP_RW_PARALLEL (1 << 19) 414 #define RT2860_BBP_PAR_DUR_112_5 (1 << 18) 415 #define RT2860_BBP_CSR_KICK (1 << 17) 416 #define RT2860_BBP_CSR_READ (1 << 16) 417 #define RT2860_BBP_ADDR_SHIFT 8 418 #define RT2860_BBP_DATA_SHIFT 0 419 420 /* possible flags for register RF_CSR_CFG0 */ 421 #define RT2860_RF_REG_CTRL (1 << 31) 422 #define RT2860_RF_LE_SEL1 (1 << 30) 423 #define RT2860_RF_LE_STBY (1 << 29) 424 #define RT2860_RF_REG_WIDTH_SHIFT 24 425 #define RT2860_RF_REG_0_SHIFT 0 426 427 /* possible flags for register RF_CSR_CFG1 */ 428 #define RT2860_RF_DUR_5 (1 << 24) 429 #define RT2860_RF_REG_1_SHIFT 0 430 431 /* possible flags for register LED_CFG */ 432 #define RT2860_LED_POL (1 << 30) 433 #define RT2860_Y_LED_MODE_SHIFT 28 434 #define RT2860_G_LED_MODE_SHIFT 26 435 #define RT2860_R_LED_MODE_SHIFT 24 436 #define RT2860_LED_MODE_OFF 0 437 #define RT2860_LED_MODE_BLINK_TX 1 438 #define RT2860_LED_MODE_SLOW_BLINK 2 439 #define RT2860_LED_MODE_ON 3 440 #define RT2860_SLOW_BLK_TIME_SHIFT 16 441 #define RT2860_LED_OFF_TIME_SHIFT 8 442 #define RT2860_LED_ON_TIME_SHIFT 0 443 444 /* possible flags for register XIFS_TIME_CFG */ 445 #define RT2860_BB_RXEND_EN (1 << 29) 446 #define RT2860_EIFS_TIME_SHIFT 20 447 #define RT2860_OFDM_XIFS_TIME_SHIFT 16 448 #define RT2860_OFDM_SIFS_TIME_SHIFT 8 449 #define RT2860_CCK_SIFS_TIME_SHIFT 0 450 451 /* possible flags for register BKOFF_SLOT_CFG */ 452 #define RT2860_CC_DELAY_TIME_SHIFT 8 453 #define RT2860_SLOT_TIME 0 454 455 /* possible flags for register NAV_TIME_CFG */ 456 #define RT2860_NAV_UPD (1 << 31) 457 #define RT2860_NAV_UPD_VAL_SHIFT 16 458 #define RT2860_NAV_CLR_EN (1 << 15) 459 #define RT2860_NAV_TIMER_SHIFT 0 460 461 /* possible flags for register CH_TIME_CFG */ 462 #define RT2860_EIFS_AS_CH_BUSY (1 << 4) 463 #define RT2860_NAV_AS_CH_BUSY (1 << 3) 464 #define RT2860_RX_AS_CH_BUSY (1 << 2) 465 #define RT2860_TX_AS_CH_BUSY (1 << 1) 466 #define RT2860_CH_STA_TIMER_EN (1 << 0) 467 468 /* possible values for register BCN_TIME_CFG */ 469 #define RT2860_TSF_INS_COMP_SHIFT 24 470 #define RT2860_BCN_TX_EN (1 << 20) 471 #define RT2860_TBTT_TIMER_EN (1 << 19) 472 #define RT2860_TSF_SYNC_MODE_SHIFT 17 473 #define RT2860_TSF_SYNC_MODE_DIS 0 474 #define RT2860_TSF_SYNC_MODE_STA 1 475 #define RT2860_TSF_SYNC_MODE_IBSS 2 476 #define RT2860_TSF_SYNC_MODE_HOSTAP 3 477 #define RT2860_TSF_TIMER_EN (1 << 16) 478 #define RT2860_BCN_INTVAL_SHIFT 0 479 480 /* possible flags for register TBTT_SYNC_CFG */ 481 #define RT2860_BCN_CWMIN_SHIFT 20 482 #define RT2860_BCN_AIFSN_SHIFT 16 483 #define RT2860_BCN_EXP_WIN_SHIFT 8 484 #define RT2860_TBTT_ADJUST_SHIFT 0 485 486 /* possible flags for register INT_TIMER_CFG */ 487 #define RT2860_GP_TIMER_SHIFT 16 488 #define RT2860_PRE_TBTT_TIMER_SHIFT 0 489 490 /* possible flags for register INT_TIMER_EN */ 491 #define RT2860_GP_TIMER_EN (1 << 1) 492 #define RT2860_PRE_TBTT_INT_EN (1 << 0) 493 494 /* possible flags for register MAC_STATUS_REG */ 495 #define RT2860_RX_STATUS_BUSY (1 << 1) 496 #define RT2860_TX_STATUS_BUSY (1 << 0) 497 498 /* possible flags for register PWR_PIN_CFG */ 499 #define RT2860_IO_ADDA_PD (1 << 3) 500 #define RT2860_IO_PLL_PD (1 << 2) 501 #define RT2860_IO_RA_PE (1 << 1) 502 #define RT2860_IO_RF_PE (1 << 0) 503 504 /* possible flags for register AUTO_WAKEUP_CFG */ 505 #define RT2860_AUTO_WAKEUP_EN (1 << 15) 506 #define RT2860_SLEEP_TBTT_NUM_SHIFT 8 507 #define RT2860_WAKEUP_LEAD_TIME_SHIFT 0 508 509 /* possible flags for register TX_PIN_CFG */ 510 #define RT3593_LNA_PE_G2_POL (1 << 31) 511 #define RT3593_LNA_PE_A2_POL (1 << 30) 512 #define RT3593_LNA_PE_G2_EN (1 << 29) 513 #define RT3593_LNA_PE_A2_EN (1 << 28) 514 #define RT3593_LNA_PE2_EN (RT3593_LNA_PE_A2_EN | RT3593_LNA_PE_G2_EN) 515 #define RT3593_PA_PE_G2_POL (1 << 27) 516 #define RT3593_PA_PE_A2_POL (1 << 26) 517 #define RT3593_PA_PE_G2_EN (1 << 25) 518 #define RT3593_PA_PE_A2_EN (1 << 24) 519 #define RT2860_TRSW_POL (1 << 19) 520 #define RT2860_TRSW_EN (1 << 18) 521 #define RT2860_RFTR_POL (1 << 17) 522 #define RT2860_RFTR_EN (1 << 16) 523 #define RT2860_LNA_PE_G1_POL (1 << 15) 524 #define RT2860_LNA_PE_A1_POL (1 << 14) 525 #define RT2860_LNA_PE_G0_POL (1 << 13) 526 #define RT2860_LNA_PE_A0_POL (1 << 12) 527 #define RT2860_LNA_PE_G1_EN (1 << 11) 528 #define RT2860_LNA_PE_A1_EN (1 << 10) 529 #define RT2860_LNA_PE1_EN (RT2860_LNA_PE_A1_EN | RT2860_LNA_PE_G1_EN) 530 #define RT2860_LNA_PE_G0_EN (1 << 9) 531 #define RT2860_LNA_PE_A0_EN (1 << 8) 532 #define RT2860_LNA_PE0_EN (RT2860_LNA_PE_A0_EN | RT2860_LNA_PE_G0_EN) 533 #define RT2860_PA_PE_G1_POL (1 << 7) 534 #define RT2860_PA_PE_A1_POL (1 << 6) 535 #define RT2860_PA_PE_G0_POL (1 << 5) 536 #define RT2860_PA_PE_A0_POL (1 << 4) 537 #define RT2860_PA_PE_G1_EN (1 << 3) 538 #define RT2860_PA_PE_A1_EN (1 << 2) 539 #define RT2860_PA_PE_G0_EN (1 << 1) 540 #define RT2860_PA_PE_A0_EN (1 << 0) 541 542 /* possible flags for register TX_BAND_CFG */ 543 #define RT2860_5G_BAND_SEL_N (1 << 2) 544 #define RT2860_5G_BAND_SEL_P (1 << 1) 545 #define RT2860_TX_BAND_SEL (1 << 0) 546 547 /* possible flags for register TX_SW_CFG0 */ 548 #define RT2860_DLY_RFTR_EN_SHIFT 24 549 #define RT2860_DLY_TRSW_EN_SHIFT 16 550 #define RT2860_DLY_PAPE_EN_SHIFT 8 551 #define RT2860_DLY_TXPE_EN_SHIFT 0 552 553 /* possible flags for register TX_SW_CFG1 */ 554 #define RT2860_DLY_RFTR_DIS_SHIFT 16 555 #define RT2860_DLY_TRSW_DIS_SHIFT 8 556 #define RT2860_DLY_PAPE_DIS SHIFT 0 557 558 /* possible flags for register TX_SW_CFG2 */ 559 #define RT2860_DLY_LNA_EN_SHIFT 24 560 #define RT2860_DLY_LNA_DIS_SHIFT 16 561 #define RT2860_DLY_DAC_EN_SHIFT 8 562 #define RT2860_DLY_DAC_DIS_SHIFT 0 563 564 /* possible flags for register TXOP_THRES_CFG */ 565 #define RT2860_TXOP_REM_THRES_SHIFT 24 566 #define RT2860_CF_END_THRES_SHIFT 16 567 #define RT2860_RDG_IN_THRES 8 568 #define RT2860_RDG_OUT_THRES 0 569 570 /* possible flags for register TXOP_CTRL_CFG */ 571 #define RT2860_EXT_CW_MIN_SHIFT 16 572 #define RT2860_EXT_CCA_DLY_SHIFT 8 573 #define RT2860_EXT_CCA_EN (1 << 7) 574 #define RT2860_LSIG_TXOP_EN (1 << 6) 575 #define RT2860_TXOP_TRUN_EN_MIMOPS (1 << 4) 576 #define RT2860_TXOP_TRUN_EN_TXOP (1 << 3) 577 #define RT2860_TXOP_TRUN_EN_RATE (1 << 2) 578 #define RT2860_TXOP_TRUN_EN_AC (1 << 1) 579 #define RT2860_TXOP_TRUN_EN_TIMEOUT (1 << 0) 580 581 /* possible flags for register TX_RTS_CFG */ 582 #define RT2860_RTS_FBK_EN (1 << 24) 583 #define RT2860_RTS_THRES_SHIFT 8 584 #define RT2860_RTS_RTY_LIMIT_SHIFT 0 585 586 /* possible flags for register TX_TIMEOUT_CFG */ 587 #define RT2860_TXOP_TIMEOUT_SHIFT 16 588 #define RT2860_RX_ACK_TIMEOUT_SHIFT 8 589 #define RT2860_MPDU_LIFE_TIME_SHIFT 4 590 591 /* possible flags for register TX_RTY_CFG */ 592 #define RT2860_TX_AUTOFB_EN (1 << 30) 593 #define RT2860_AGG_RTY_MODE_TIMER (1 << 29) 594 #define RT2860_NAG_RTY_MODE_TIMER (1 << 28) 595 #define RT2860_LONG_RTY_THRES_SHIFT 16 596 #define RT2860_LONG_RTY_LIMIT_SHIFT 8 597 #define RT2860_SHORT_RTY_LIMIT_SHIFT 0 598 599 /* possible flags for register TX_LINK_CFG */ 600 #define RT2860_REMOTE_MFS_SHIFT 24 601 #define RT2860_REMOTE_MFB_SHIFT 16 602 #define RT2860_TX_CFACK_EN (1 << 12) 603 #define RT2860_TX_RDG_EN (1 << 11) 604 #define RT2860_TX_MRQ_EN (1 << 10) 605 #define RT2860_REMOTE_UMFS_EN (1 << 9) 606 #define RT2860_TX_MFB_EN (1 << 8) 607 #define RT2860_REMOTE_MFB_LT_SHIFT 0 608 609 /* possible flags for registers *_PROT_CFG */ 610 #define RT2860_RTSTH_EN (1 << 26) 611 #define RT2860_TXOP_ALLOW_GF40 (1 << 25) 612 #define RT2860_TXOP_ALLOW_GF20 (1 << 24) 613 #define RT2860_TXOP_ALLOW_MM40 (1 << 23) 614 #define RT2860_TXOP_ALLOW_MM20 (1 << 22) 615 #define RT2860_TXOP_ALLOW_OFDM (1 << 21) 616 #define RT2860_TXOP_ALLOW_CCK (1 << 20) 617 #define RT2860_TXOP_ALLOW_ALL (0x3f << 20) 618 #define RT2860_PROT_NAV_SHORT (1 << 18) 619 #define RT2860_PROT_NAV_LONG (2 << 18) 620 #define RT2860_PROT_CTRL_RTS_CTS (1 << 16) 621 #define RT2860_PROT_CTRL_CTS (2 << 16) 622 623 /* possible flags for registers EXP_{CTS,ACK}_TIME */ 624 #define RT2860_EXP_OFDM_TIME_SHIFT 16 625 #define RT2860_EXP_CCK_TIME_SHIFT 0 626 627 /* possible flags for register RX_FILTR_CFG */ 628 #define RT2860_DROP_CTRL_RSV (1 << 16) 629 #define RT2860_DROP_BAR (1 << 15) 630 #define RT2860_DROP_BA (1 << 14) 631 #define RT2860_DROP_PSPOLL (1 << 13) 632 #define RT2860_DROP_RTS (1 << 12) 633 #define RT2860_DROP_CTS (1 << 11) 634 #define RT2860_DROP_ACK (1 << 10) 635 #define RT2860_DROP_CFEND (1 << 9) 636 #define RT2860_DROP_CFACK (1 << 8) 637 #define RT2860_DROP_DUPL (1 << 7) 638 #define RT2860_DROP_BC (1 << 6) 639 #define RT2860_DROP_MC (1 << 5) 640 #define RT2860_DROP_VER_ERR (1 << 4) 641 #define RT2860_DROP_NOT_MYBSS (1 << 3) 642 #define RT2860_DROP_UC_NOME (1 << 2) 643 #define RT2860_DROP_PHY_ERR (1 << 1) 644 #define RT2860_DROP_CRC_ERR (1 << 0) 645 646 /* possible flags for register AUTO_RSP_CFG */ 647 #define RT2860_CTRL_PWR_BIT (1 << 7) 648 #define RT2860_BAC_ACK_POLICY (1 << 6) 649 #define RT2860_CCK_SHORT_EN (1 << 4) 650 #define RT2860_CTS_40M_REF_EN (1 << 3) 651 #define RT2860_CTS_40M_MODE_EN (1 << 2) 652 #define RT2860_BAC_ACKPOLICY_EN (1 << 1) 653 #define RT2860_AUTO_RSP_EN (1 << 0) 654 655 /* possible flags for register SIFS_COST_CFG */ 656 #define RT2860_OFDM_SIFS_COST_SHIFT 8 657 #define RT2860_CCK_SIFS_COST_SHIFT 0 658 659 /* possible flags for register TXOP_HLDR_ET */ 660 #define RT2860_TXOP_ETM1_EN (1 << 25) 661 #define RT2860_TXOP_ETM0_EN (1 << 24) 662 #define RT2860_TXOP_ETM_THRES_SHIFT 16 663 #define RT2860_TXOP_ETO_EN (1 << 8) 664 #define RT2860_TXOP_ETO_THRES_SHIFT 1 665 #define RT2860_PER_RX_RST_EN (1 << 0) 666 667 /* possible flags for register TX_STAT_FIFO */ 668 #define RT2860_TXQ_MCS_SHIFT 16 669 #define RT2860_TXQ_WCID_SHIFT 8 670 #define RT2860_TXQ_ACKREQ (1 << 7) 671 #define RT2860_TXQ_AGG (1 << 6) 672 #define RT2860_TXQ_OK (1 << 5) 673 #define RT2860_TXQ_PID_SHIFT 1 674 #define RT2860_TXQ_VLD (1 << 0) 675 676 /* possible flags for register WCID_ATTR */ 677 #define RT2860_MODE_NOSEC 0 678 #define RT2860_MODE_WEP40 1 679 #define RT2860_MODE_WEP104 2 680 #define RT2860_MODE_TKIP 3 681 #define RT2860_MODE_AES_CCMP 4 682 #define RT2860_MODE_CKIP40 5 683 #define RT2860_MODE_CKIP104 6 684 #define RT2860_MODE_CKIP128 7 685 #define RT2860_RX_PKEY_EN (1 << 0) 686 687 /* possible flags for register H2M_MAILBOX */ 688 #define RT2860_H2M_BUSY (1 << 24) 689 #define RT2860_TOKEN_NO_INTR 0xff 690 691 692 /* possible flags for MCU command RT2860_MCU_CMD_LEDS */ 693 #define RT2860_LED_RADIO (1 << 13) 694 #define RT2860_LED_LINK_2GHZ (1 << 14) 695 #define RT2860_LED_LINK_5GHZ (1 << 15) 696 697 698 /* possible flags for RT3020 RF register 1 */ 699 #define RT3070_RF_BLOCK (1 << 0) 700 #define RT3070_RX0_PD (1 << 2) 701 #define RT3070_TX0_PD (1 << 3) 702 #define RT3070_RX1_PD (1 << 4) 703 #define RT3070_TX1_PD (1 << 5) 704 #define RT3070_RX2_PD (1 << 6) 705 #define RT3070_TX2_PD (1 << 7) 706 707 /* possible flags for RT3020 RF register 7 */ 708 #define RT3070_TUNE (1 << 0) 709 710 /* possible flags for RT3020 RF register 15 */ 711 #define RT3070_TX_LO2 (1 << 3) 712 713 /* possible flags for RT3020 RF register 17 */ 714 #define RT3070_TX_LO1 (1 << 3) 715 716 /* possible flags for RT3020 RF register 20 */ 717 #define RT3070_RX_LO1 (1 << 3) 718 719 /* possible flags for RT3020 RF register 21 */ 720 #define RT3070_RX_LO2 (1 << 3) 721 #define RT3070_RX_CTB (1 << 7) 722 723 /* possible flags for RT3020 RF register 22 */ 724 #define RT3070_BB_LOOPBACK (1 << 0) 725 726 /* possible flags for RT3053 RF register 1 */ 727 #define RT3593_VCO (1 << 0) 728 729 /* possible flags for RT3053 RF register 2 */ 730 #define RT3593_RESCAL (1 << 7) 731 732 /* possible flags for RT3053 RF register 3 */ 733 #define RT3593_VCOCAL (1 << 7) 734 735 /* possible flags for RT3053 RF register 6 */ 736 #define RT3593_VCO_IC (1 << 6) 737 738 /* possible flags for RT3053 RF register 20 */ 739 #define RT3593_LDO_PLL_VC_MASK 0x0e 740 #define RT3593_LDO_RF_VC_MASK 0xe0 741 742 /* possible flags for RT3053 RF register 22 */ 743 #define RT3593_CP_IC_MASK 0xe0 744 #define RT3593_CP_IC_SHIFT 5 745 746 /* possible flags for RT3053 RF register 46 */ 747 #define RT3593_RX_CTB (1 << 5) 748 749 #define RT3090_DEF_LNA 10 750 751 /* RT2860 TX descriptor */ 752 struct rt2860_txd { 753 uint32_t sdp0; /* Segment Data Pointer 0 */ 754 uint16_t sdl1; /* Segment Data Length 1 */ 755 #define RT2860_TX_BURST (1 << 15) 756 #define RT2860_TX_LS1 (1 << 14) /* SDP1 is the last segment */ 757 758 uint16_t sdl0; /* Segment Data Length 0 */ 759 #define RT2860_TX_DDONE (1 << 15) 760 #define RT2860_TX_LS0 (1 << 14) /* SDP0 is the last segment */ 761 762 uint32_t sdp1; /* Segment Data Pointer 1 */ 763 uint8_t reserved[3]; 764 uint8_t flags; 765 #define RT2860_TX_QSEL_SHIFT 1 766 #define RT2860_TX_QSEL_MGMT (0 << 1) 767 #define RT2860_TX_QSEL_HCCA (1 << 1) 768 #define RT2860_TX_QSEL_EDCA (2 << 1) 769 #define RT2860_TX_WIV (1 << 0) 770 } __packed; 771 772 /* RT2870 TX descriptor */ 773 struct rt2870_txd { 774 uint16_t len; 775 uint8_t pad; 776 uint8_t flags; 777 } __packed; 778 779 /* TX Wireless Information */ 780 struct rt2860_txwi { 781 uint8_t flags; 782 #define RT2860_TX_MPDU_DSITY_SHIFT 5 783 #define RT2860_TX_AMPDU (1 << 4) 784 #define RT2860_TX_TS (1 << 3) 785 #define RT2860_TX_CFACK (1 << 2) 786 #define RT2860_TX_MMPS (1 << 1) 787 #define RT2860_TX_FRAG (1 << 0) 788 789 uint8_t txop; 790 #define RT2860_TX_TXOP_HT 0 791 #define RT2860_TX_TXOP_PIFS 1 792 #define RT2860_TX_TXOP_SIFS 2 793 #define RT2860_TX_TXOP_BACKOFF 3 794 795 uint16_t phy; 796 #define RT2860_PHY_MODE 0xc000 797 #define RT2860_PHY_CCK (0 << 14) 798 #define RT2860_PHY_OFDM (1 << 14) 799 #define RT2860_PHY_HT (2 << 14) 800 #define RT2860_PHY_HT_GF (3 << 14) 801 #define RT2860_PHY_SGI (1 << 8) 802 #define RT2860_PHY_BW40 (1 << 7) 803 #define RT2860_PHY_MCS 0x7f 804 #define RT2860_PHY_SHPRE (1 << 3) 805 806 uint8_t xflags; 807 #define RT2860_TX_BAWINSIZE_SHIFT 2 808 #define RT2860_TX_NSEQ (1 << 1) 809 #define RT2860_TX_ACK (1 << 0) 810 811 uint8_t wcid; /* Wireless Client ID */ 812 uint16_t len; 813 #define RT2860_TX_PID_SHIFT 12 814 815 uint32_t iv; 816 uint32_t eiv; 817 } __packed; 818 819 /* RT2860 RX descriptor */ 820 struct rt2860_rxd { 821 uint32_t sdp0; 822 uint16_t sdl1; /* unused */ 823 uint16_t sdl0; 824 #define RT2860_RX_DDONE (1 << 15) 825 #define RT2860_RX_LS0 (1 << 14) 826 827 uint32_t sdp1; /* unused */ 828 uint32_t flags; 829 #define RT2860_RX_DEC (1 << 16) 830 #define RT2860_RX_AMPDU (1 << 15) 831 #define RT2860_RX_L2PAD (1 << 14) 832 #define RT2860_RX_RSSI (1 << 13) 833 #define RT2860_RX_HTC (1 << 12) 834 #define RT2860_RX_AMSDU (1 << 11) 835 #define RT2860_RX_MICERR (1 << 10) 836 #define RT2860_RX_ICVERR (1 << 9) 837 #define RT2860_RX_CRCERR (1 << 8) 838 #define RT2860_RX_MYBSS (1 << 7) 839 #define RT2860_RX_BC (1 << 6) 840 #define RT2860_RX_MC (1 << 5) 841 #define RT2860_RX_UC2ME (1 << 4) 842 #define RT2860_RX_FRAG (1 << 3) 843 #define RT2860_RX_NULL (1 << 2) 844 #define RT2860_RX_DATA (1 << 1) 845 #define RT2860_RX_BA (1 << 0) 846 } __packed; 847 848 /* RT2870 RX descriptor */ 849 struct rt2870_rxd { 850 /* single 32-bit field */ 851 uint32_t flags; 852 } __packed; 853 854 /* RX Wireless Information */ 855 struct rt2860_rxwi { 856 uint8_t wcid; 857 uint8_t keyidx; 858 #define RT2860_RX_UDF_SHIFT 5 859 #define RT2860_RX_BSS_IDX_SHIFT 2 860 861 uint16_t len; 862 #define RT2860_RX_TID_SHIFT 12 863 864 uint16_t seq; 865 uint16_t phy; 866 uint8_t rssi[3]; 867 uint8_t reserved1; 868 uint8_t snr[2]; 869 uint16_t reserved2; 870 } __packed; 871 872 873 /* first DMA segment contains TXWI + 802.11 header + 32-bit padding */ 874 #define RT2860_TXWI_DMASZ \ 875 (sizeof (struct rt2860_txwi) + \ 876 sizeof (struct ieee80211_htframe) + \ 877 sizeof (uint16_t)) 878 879 #define RT2860_RF1 0 880 #define RT2860_RF2 2 881 #define RT2860_RF3 1 882 #define RT2860_RF4 3 883 884 #define RT2860_RF_2820 1 /* 2T3R */ 885 #define RT2860_RF_2850 2 /* dual-band 2T3R */ 886 #define RT2860_RF_2720 3 /* 1T2R */ 887 #define RT2860_RF_2750 4 /* dual-band 1T2R */ 888 #define RT3070_RF_3020 5 /* 1T1R */ 889 #define RT3070_RF_2020 6 /* b/g */ 890 #define RT3070_RF_3021 7 /* 1T2R */ 891 #define RT3070_RF_3022 8 /* 2T2R */ 892 #define RT3070_RF_3052 9 /* dual-band 2T2R */ 893 #define RT3070_RF_3320 11 /* 1T1R */ 894 #define RT3070_RF_3053 13 /* dual-band 3T3R */ 895 896 /* USB commands for RT2870 only */ 897 #define RT2870_RESET 1 898 #define RT2870_WRITE_2 2 899 #define RT2870_WRITE_REGION_1 6 900 #define RT2870_READ_REGION_1 7 901 #define RT2870_EEPROM_READ 9 902 903 #define RT2860_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ 904 905 #define RT2860_EEPROM_VERSION 0x01 906 #define RT2860_EEPROM_MAC01 0x02 907 #define RT2860_EEPROM_MAC23 0x03 908 #define RT2860_EEPROM_MAC45 0x04 909 #define RT2860_EEPROM_PCIE_PSLEVEL 0x11 910 #define RT2860_EEPROM_REV 0x12 911 #define RT2860_EEPROM_ANTENNA 0x1a 912 #define RT2860_EEPROM_CONFIG 0x1b 913 #define RT2860_EEPROM_COUNTRY 0x1c 914 #define RT2860_EEPROM_FREQ_LEDS 0x1d 915 #define RT2860_EEPROM_LED1 0x1e 916 #define RT2860_EEPROM_LED2 0x1f 917 #define RT2860_EEPROM_LED3 0x20 918 #define RT2860_EEPROM_LNA 0x22 919 #define RT2860_EEPROM_RSSI1_2GHZ 0x23 920 #define RT2860_EEPROM_RSSI2_2GHZ 0x24 921 #define RT2860_EEPROM_RSSI1_5GHZ 0x25 922 #define RT2860_EEPROM_RSSI2_5GHZ 0x26 923 #define RT2860_EEPROM_DELTAPWR 0x28 924 #define RT2860_EEPROM_PWR2GHZ_BASE1 0x29 925 #define RT2860_EEPROM_PWR2GHZ_BASE2 0x30 926 #define RT2860_EEPROM_TSSI1_2GHZ 0x37 927 #define RT2860_EEPROM_TSSI2_2GHZ 0x38 928 #define RT2860_EEPROM_TSSI3_2GHZ 0x39 929 #define RT2860_EEPROM_TSSI4_2GHZ 0x3a 930 #define RT2860_EEPROM_TSSI5_2GHZ 0x3b 931 #define RT2860_EEPROM_PWR5GHZ_BASE1 0x3c 932 #define RT2860_EEPROM_PWR5GHZ_BASE2 0x53 933 #define RT2860_EEPROM_TSSI1_5GHZ 0x6a 934 #define RT2860_EEPROM_TSSI2_5GHZ 0x6b 935 #define RT2860_EEPROM_TSSI3_5GHZ 0x6c 936 #define RT2860_EEPROM_TSSI4_5GHZ 0x6d 937 #define RT2860_EEPROM_TSSI5_5GHZ 0x6e 938 #define RT2860_EEPROM_RPWR 0x6f 939 #define RT2860_EEPROM_BBP_BASE 0x78 940 #define RT3071_EEPROM_RF_BASE 0x82 941 942 #define RT2860_RIDX_CCK1 0 943 #define RT2860_RIDX_CCK11 3 944 #define RT2860_RIDX_OFDM6 4 945 #define RT2860_RIDX_MAX 11 946 static const struct rt2860_rate { 947 uint8_t rate; 948 uint8_t mcs; 949 enum ieee80211_phytype phy; 950 uint8_t ctl_ridx; 951 uint16_t sp_ack_dur; 952 uint16_t lp_ack_dur; 953 } rt2860_rates[] = { 954 { 2, 0, IEEE80211_T_DS, 0, 314, 314 }, 955 { 4, 1, IEEE80211_T_DS, 1, 258, 162 }, 956 { 11, 2, IEEE80211_T_DS, 2, 223, 127 }, 957 { 22, 3, IEEE80211_T_DS, 3, 213, 117 }, 958 { 12, 0, IEEE80211_T_OFDM, 4, 60, 60 }, 959 { 18, 1, IEEE80211_T_OFDM, 4, 52, 52 }, 960 { 24, 2, IEEE80211_T_OFDM, 6, 48, 48 }, 961 { 36, 3, IEEE80211_T_OFDM, 6, 44, 44 }, 962 { 48, 4, IEEE80211_T_OFDM, 8, 44, 44 }, 963 { 72, 5, IEEE80211_T_OFDM, 8, 40, 40 }, 964 { 96, 6, IEEE80211_T_OFDM, 8, 40, 40 }, 965 { 108, 7, IEEE80211_T_OFDM, 8, 40, 40 } 966 }; 967 968 /* 969 * Control and status registers access macros. 970 */ 971 #define RAL_READ(sc, reg) \ 972 bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) 973 974 #define RAL_WRITE(sc, reg, val) \ 975 bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) 976 977 #define RAL_BARRIER_WRITE(sc) \ 978 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, 0x1800, \ 979 BUS_SPACE_BARRIER_WRITE) 980 981 #define RAL_BARRIER_READ_WRITE(sc) \ 982 bus_space_barrier((sc)->sc_st, (sc)->sc_sh, 0, 0x1800, \ 983 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 984 985 #define RAL_WRITE_REGION_1(sc, offset, datap, count) \ 986 bus_space_write_region_1((sc)->sc_st, (sc)->sc_sh, (offset), \ 987 (datap), (count)) 988 989 #define RAL_SET_REGION_4(sc, offset, val, count) \ 990 bus_space_set_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ 991 (val), (count)) 992 993 /* 994 * EEPROM access macro. 995 */ 996 #define RT2860_EEPROM_CTL(sc, val) do { \ 997 RAL_WRITE((sc), RT2860_PCI_EECTRL, (val)); \ 998 RAL_BARRIER_READ_WRITE((sc)); \ 999 DELAY(RT2860_EEPROM_DELAY); \ 1000 } while (/* CONSTCOND */0) 1001 1002 /* 1003 * Default values for MAC registers; values taken from the reference driver. 1004 */ 1005 #define RT2860_DEF_MAC \ 1006 { RT2860_BCN_OFFSET0, 0xf8f0e8e0 }, \ 1007 { RT2860_LEGACY_BASIC_RATE, 0x0000013f }, \ 1008 { RT2860_HT_BASIC_RATE, 0x00008003 }, \ 1009 { RT2860_MAC_SYS_CTRL, 0x00000000 }, \ 1010 { RT2860_BKOFF_SLOT_CFG, 0x00000209 }, \ 1011 { RT2860_TX_SW_CFG0, 0x00000000 }, \ 1012 { RT2860_TX_SW_CFG1, 0x00080606 }, \ 1013 { RT2860_TX_LINK_CFG, 0x00001020 }, \ 1014 { RT2860_TX_TIMEOUT_CFG, 0x000a2090 }, \ 1015 { RT2860_LED_CFG, 0x7f031e46 }, \ 1016 { RT2860_WMM_AIFSN_CFG, 0x00002273 }, \ 1017 { RT2860_WMM_CWMIN_CFG, 0x00002344 }, \ 1018 { RT2860_WMM_CWMAX_CFG, 0x000034aa }, \ 1019 { RT2860_MAX_PCNT, 0x1f3fbf9f }, \ 1020 { RT2860_TX_RTY_CFG, 0x47d01f0f }, \ 1021 { RT2860_AUTO_RSP_CFG, 0x00000013 }, \ 1022 { RT2860_CCK_PROT_CFG, 0x05740003 }, \ 1023 { RT2860_OFDM_PROT_CFG, 0x05740003 }, \ 1024 { RT2860_GF20_PROT_CFG, 0x01744004 }, \ 1025 { RT2860_GF40_PROT_CFG, 0x03f44084 }, \ 1026 { RT2860_MM20_PROT_CFG, 0x01744004 }, \ 1027 { RT2860_MM40_PROT_CFG, 0x03f54084 }, \ 1028 { RT2860_TXOP_CTRL_CFG, 0x0000583f }, \ 1029 { RT2860_TXOP_HLDR_ET, 0x00000002 }, \ 1030 { RT2860_TX_RTS_CFG, 0x00092b20 }, \ 1031 { RT2860_EXP_ACK_TIME, 0x002400ca }, \ 1032 { RT2860_XIFS_TIME_CFG, 0x33a41010 }, \ 1033 { RT2860_PWR_PIN_CFG, 0x00000003 } 1034 1035 /* XXX only a few registers differ from above, try to merge? */ 1036 #define RT2870_DEF_MAC \ 1037 { RT2860_BCN_OFFSET0, 0xf8f0e8e0 }, \ 1038 { RT2860_LEGACY_BASIC_RATE, 0x0000013f }, \ 1039 { RT2860_HT_BASIC_RATE, 0x00008003 }, \ 1040 { RT2860_MAC_SYS_CTRL, 0x00000000 }, \ 1041 { RT2860_BKOFF_SLOT_CFG, 0x00000209 }, \ 1042 { RT2860_TX_SW_CFG0, 0x00000000 }, \ 1043 { RT2860_TX_SW_CFG1, 0x00080606 }, \ 1044 { RT2860_TX_LINK_CFG, 0x00001020 }, \ 1045 { RT2860_TX_TIMEOUT_CFG, 0x000a2090 }, \ 1046 { RT2860_LED_CFG, 0x7f031e46 }, \ 1047 { RT2860_WMM_AIFSN_CFG, 0x00002273 }, \ 1048 { RT2860_WMM_CWMIN_CFG, 0x00002344 }, \ 1049 { RT2860_WMM_CWMAX_CFG, 0x000034aa }, \ 1050 { RT2860_MAX_PCNT, 0x1f3fbf9f }, \ 1051 { RT2860_TX_RTY_CFG, 0x47d01f0f }, \ 1052 { RT2860_AUTO_RSP_CFG, 0x00000013 }, \ 1053 { RT2860_CCK_PROT_CFG, 0x05740003 }, \ 1054 { RT2860_OFDM_PROT_CFG, 0x05740003 }, \ 1055 { RT2860_PBF_CFG, 0x00f40006 }, \ 1056 { RT2860_WPDMA_GLO_CFG, 0x00000030 }, \ 1057 { RT2860_GF20_PROT_CFG, 0x01744004 }, \ 1058 { RT2860_GF40_PROT_CFG, 0x03f44084 }, \ 1059 { RT2860_MM20_PROT_CFG, 0x01744004 }, \ 1060 { RT2860_MM40_PROT_CFG, 0x03f44084 }, \ 1061 { RT2860_TXOP_CTRL_CFG, 0x0000583f }, \ 1062 { RT2860_TXOP_HLDR_ET, 0x00000002 }, \ 1063 { RT2860_TX_RTS_CFG, 0x00092b20 }, \ 1064 { RT2860_EXP_ACK_TIME, 0x002400ca }, \ 1065 { RT2860_XIFS_TIME_CFG, 0x33a41010 }, \ 1066 { RT2860_PWR_PIN_CFG, 0x00000003 } 1067 1068 /* 1069 * Default values for BBP registers; values taken from the reference driver. 1070 */ 1071 #define RT2860_DEF_BBP \ 1072 { 65, 0x2c }, \ 1073 { 66, 0x38 }, \ 1074 { 69, 0x12 }, \ 1075 { 70, 0x0a }, \ 1076 { 73, 0x10 }, \ 1077 { 81, 0x37 }, \ 1078 { 82, 0x62 }, \ 1079 { 83, 0x6a }, \ 1080 { 84, 0x99 }, \ 1081 { 86, 0x00 }, \ 1082 { 91, 0x04 }, \ 1083 { 92, 0x00 }, \ 1084 { 103, 0x00 }, \ 1085 { 105, 0x05 }, \ 1086 { 106, 0x35 } 1087 1088 /* 1089 * Default settings for RF registers; values derived from the reference driver. 1090 */ 1091 #define RT2860_RF2850 \ 1092 { 1, 0x100bb3, 0x1301e1, 0x05a014, 0x001402 }, \ 1093 { 2, 0x100bb3, 0x1301e1, 0x05a014, 0x001407 }, \ 1094 { 3, 0x100bb3, 0x1301e2, 0x05a014, 0x001402 }, \ 1095 { 4, 0x100bb3, 0x1301e2, 0x05a014, 0x001407 }, \ 1096 { 5, 0x100bb3, 0x1301e3, 0x05a014, 0x001402 }, \ 1097 { 6, 0x100bb3, 0x1301e3, 0x05a014, 0x001407 }, \ 1098 { 7, 0x100bb3, 0x1301e4, 0x05a014, 0x001402 }, \ 1099 { 8, 0x100bb3, 0x1301e4, 0x05a014, 0x001407 }, \ 1100 { 9, 0x100bb3, 0x1301e5, 0x05a014, 0x001402 }, \ 1101 { 10, 0x100bb3, 0x1301e5, 0x05a014, 0x001407 }, \ 1102 { 11, 0x100bb3, 0x1301e6, 0x05a014, 0x001402 }, \ 1103 { 12, 0x100bb3, 0x1301e6, 0x05a014, 0x001407 }, \ 1104 { 13, 0x100bb3, 0x1301e7, 0x05a014, 0x001402 }, \ 1105 { 14, 0x100bb3, 0x1301e8, 0x05a014, 0x001404 }, \ 1106 { 36, 0x100bb3, 0x130266, 0x056014, 0x001408 }, \ 1107 { 38, 0x100bb3, 0x130267, 0x056014, 0x001404 }, \ 1108 { 40, 0x100bb2, 0x1301a0, 0x056014, 0x001400 }, \ 1109 { 44, 0x100bb2, 0x1301a0, 0x056014, 0x001408 }, \ 1110 { 46, 0x100bb2, 0x1301a1, 0x056014, 0x001402 }, \ 1111 { 48, 0x100bb2, 0x1301a1, 0x056014, 0x001406 }, \ 1112 { 52, 0x100bb2, 0x1301a2, 0x056014, 0x001404 }, \ 1113 { 54, 0x100bb2, 0x1301a2, 0x056014, 0x001408 }, \ 1114 { 56, 0x100bb2, 0x1301a3, 0x056014, 0x001402 }, \ 1115 { 60, 0x100bb2, 0x1301a4, 0x056014, 0x001400 }, \ 1116 { 62, 0x100bb2, 0x1301a4, 0x056014, 0x001404 }, \ 1117 { 64, 0x100bb2, 0x1301a4, 0x056014, 0x001408 }, \ 1118 { 100, 0x100bb2, 0x1301ac, 0x05e014, 0x001400 }, \ 1119 { 102, 0x100bb2, 0x1701ac, 0x15e014, 0x001404 }, \ 1120 { 104, 0x100bb2, 0x1701ac, 0x15e014, 0x001408 }, \ 1121 { 108, 0x100bb3, 0x17028c, 0x15e014, 0x001404 }, \ 1122 { 110, 0x100bb3, 0x13028d, 0x05e014, 0x001400 }, \ 1123 { 112, 0x100bb3, 0x13028d, 0x05e014, 0x001406 }, \ 1124 { 116, 0x100bb3, 0x13028e, 0x05e014, 0x001408 }, \ 1125 { 118, 0x100bb3, 0x13028f, 0x05e014, 0x001404 }, \ 1126 { 120, 0x100bb1, 0x1300e0, 0x05e014, 0x001400 }, \ 1127 { 124, 0x100bb1, 0x1300e0, 0x05e014, 0x001404 }, \ 1128 { 126, 0x100bb1, 0x1300e0, 0x05e014, 0x001406 }, \ 1129 { 128, 0x100bb1, 0x1300e0, 0x05e014, 0x001408 }, \ 1130 { 132, 0x100bb1, 0x1300e1, 0x05e014, 0x001402 }, \ 1131 { 134, 0x100bb1, 0x1300e1, 0x05e014, 0x001404 }, \ 1132 { 136, 0x100bb1, 0x1300e1, 0x05e014, 0x001406 }, \ 1133 { 140, 0x100bb1, 0x1300e2, 0x05e014, 0x001400 }, \ 1134 { 149, 0x100bb1, 0x1300e2, 0x05e014, 0x001409 }, \ 1135 { 151, 0x100bb1, 0x1300e3, 0x05e014, 0x001401 }, \ 1136 { 153, 0x100bb1, 0x1300e3, 0x05e014, 0x001403 }, \ 1137 { 157, 0x100bb1, 0x1300e3, 0x05e014, 0x001407 }, \ 1138 { 159, 0x100bb1, 0x1300e3, 0x05e014, 0x001409 }, \ 1139 { 161, 0x100bb1, 0x1300e4, 0x05e014, 0x001401 }, \ 1140 { 165, 0x100bb1, 0x1300e4, 0x05e014, 0x001405 }, \ 1141 { 167, 0x100bb1, 0x1300f4, 0x05e014, 0x001407 }, \ 1142 { 169, 0x100bb1, 0x1300f4, 0x05e014, 0x001409 }, \ 1143 { 171, 0x100bb1, 0x1300f5, 0x05e014, 0x001401 }, \ 1144 { 173, 0x100bb1, 0x1300f5, 0x05e014, 0x001403 } 1145 1146 #define RT3070_RF3052 \ 1147 { 0xf1, 2, 2 }, \ 1148 { 0xf1, 2, 7 }, \ 1149 { 0xf2, 2, 2 }, \ 1150 { 0xf2, 2, 7 }, \ 1151 { 0xf3, 2, 2 }, \ 1152 { 0xf3, 2, 7 }, \ 1153 { 0xf4, 2, 2 }, \ 1154 { 0xf4, 2, 7 }, \ 1155 { 0xf5, 2, 2 }, \ 1156 { 0xf5, 2, 7 }, \ 1157 { 0xf6, 2, 2 }, \ 1158 { 0xf6, 2, 7 }, \ 1159 { 0xf7, 2, 2 }, \ 1160 { 0xf8, 2, 4 }, \ 1161 { 0x56, 0, 4 }, \ 1162 { 0x56, 0, 6 }, \ 1163 { 0x56, 0, 8 }, \ 1164 { 0x57, 0, 0 }, \ 1165 { 0x57, 0, 2 }, \ 1166 { 0x57, 0, 4 }, \ 1167 { 0x57, 0, 8 }, \ 1168 { 0x57, 0, 10 }, \ 1169 { 0x58, 0, 0 }, \ 1170 { 0x58, 0, 4 }, \ 1171 { 0x58, 0, 6 }, \ 1172 { 0x58, 0, 8 }, \ 1173 { 0x5b, 0, 8 }, \ 1174 { 0x5b, 0, 10 }, \ 1175 { 0x5c, 0, 0 }, \ 1176 { 0x5c, 0, 4 }, \ 1177 { 0x5c, 0, 6 }, \ 1178 { 0x5c, 0, 8 }, \ 1179 { 0x5d, 0, 0 }, \ 1180 { 0x5d, 0, 2 }, \ 1181 { 0x5d, 0, 4 }, \ 1182 { 0x5d, 0, 8 }, \ 1183 { 0x5d, 0, 10 }, \ 1184 { 0x5e, 0, 0 }, \ 1185 { 0x5e, 0, 4 }, \ 1186 { 0x5e, 0, 6 }, \ 1187 { 0x5e, 0, 8 }, \ 1188 { 0x5f, 0, 0 }, \ 1189 { 0x5f, 0, 9 }, \ 1190 { 0x5f, 0, 11 }, \ 1191 { 0x60, 0, 1 }, \ 1192 { 0x60, 0, 5 }, \ 1193 { 0x60, 0, 7 }, \ 1194 { 0x60, 0, 9 }, \ 1195 { 0x61, 0, 1 }, \ 1196 { 0x61, 0, 3 }, \ 1197 { 0x61, 0, 5 }, \ 1198 { 0x61, 0, 7 }, \ 1199 { 0x61, 0, 9 } 1200 1201 #define RT3070_DEF_RF \ 1202 { 4, 0x40 }, \ 1203 { 5, 0x03 }, \ 1204 { 6, 0x02 }, \ 1205 { 7, 0x70 }, \ 1206 { 9, 0x0f }, \ 1207 { 10, 0x41 }, \ 1208 { 11, 0x21 }, \ 1209 { 12, 0x7b }, \ 1210 { 14, 0x90 }, \ 1211 { 15, 0x58 }, \ 1212 { 16, 0xb3 }, \ 1213 { 17, 0x92 }, \ 1214 { 18, 0x2c }, \ 1215 { 19, 0x02 }, \ 1216 { 20, 0xba }, \ 1217 { 21, 0xdb }, \ 1218 { 24, 0x16 }, \ 1219 { 25, 0x01 }, \ 1220 { 29, 0x1f } 1221 1222 #define RT3572_DEF_RF \ 1223 { 0, 0x70 }, \ 1224 { 1, 0x81 }, \ 1225 { 2, 0xf1 }, \ 1226 { 3, 0x02 }, \ 1227 { 4, 0x4c }, \ 1228 { 5, 0x05 }, \ 1229 { 6, 0x4a }, \ 1230 { 7, 0xd8 }, \ 1231 { 9, 0xc3 }, \ 1232 { 10, 0xf1 }, \ 1233 { 11, 0xb9 }, \ 1234 { 12, 0x70 }, \ 1235 { 13, 0x65 }, \ 1236 { 14, 0xa0 }, \ 1237 { 15, 0x53 }, \ 1238 { 16, 0x4c }, \ 1239 { 17, 0x23 }, \ 1240 { 18, 0xac }, \ 1241 { 19, 0x93 }, \ 1242 { 20, 0xb3 }, \ 1243 { 21, 0xd0 }, \ 1244 { 22, 0x00 }, \ 1245 { 23, 0x3c }, \ 1246 { 24, 0x16 }, \ 1247 { 25, 0x15 }, \ 1248 { 26, 0x85 }, \ 1249 { 27, 0x00 }, \ 1250 { 28, 0x00 }, \ 1251 { 29, 0x9b }, \ 1252 { 30, 0x09 }, \ 1253 { 31, 0x10 } 1254